HX8347 - Adafruit

HX8347-G(T)240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver6.27 Frame control register (PAGE0 -29h~R2Ch)DATA SHEET Preliminary V01R/WDNCRB7RB6 RB5 RB4 RB3 RB2 RB1 RB0W1I/P_RTN3I/P_RTN2I/P_RTN1I/P_RTN0N/P_RTN3N/P_RTN2N/P_RTN1N/P_RTN0R 1I/P_RTN3I/P_RTN2I/P_RTN1I/P_RTN0N/P_RTN3N/P_RTN_2N/P_RTN1N/P_RTN0Figure 6.41: Frame control 1 register (PAGE0 -29h)R/WDNCRB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0W1* *R 1 * *R/WWI/P_DIV1I/P_DIV1I/P_DIV0I/P_DIV0* ** *N/P_DIV1N/P_DIV1Figure 6.42: Frame control 2 register (PAGE0 -2Ah)DNC1R 1R/WWRB7N/P_DUM7N/P_DUM7N/P_DIV0N/P_DIV0RB6 RB5 RB4 RB3 RB2 RB1 RB0N/P_DUM6N/P_DUM5N/P_DUM4N/P_DUM3N/P_DUM2N/P_DUM1N/P_DUM0N/P_DUM6N/P_DUM5N/P_DUM4N/P_DUM3N/P_DUM2N/P_DUM1Figure 6.43: Frame control 3 register (PAGE0 -2Bh)DNC1R 1RB7I/PI_DUM7I/PI_DUM7N/P_DUM0RB6 RB5 RB4 RB3 RB2 RB1 RB0I/PI_DUM6I/PI_DUM5I/PI_DUM4I/PI_DUM3I/PI_DUM2I/PI_DUM1I/PI_DUM0I/PI_DUM6I/PI_DUM5I/PI_DUM4I/PI_DUM3I/PI_DUM2I/PI_DUM1Figure 6.44: Frame control 4 register (PAGE0 -2Ch)N/P_DIV[1:0]: Specify the division ratio of internal clocks in Normal / Partial mode forinternal operation. When used internal clock for the display operation, framefrequency can be adjusted with the N/P_RTN[3:0] bits (1H period clock cycle),N/P_DIV[1:0], and N/P_DUM[7:0] bits.I/PI_DIV[1:0]: Specify the division ratio of internal clocks in Idle (8-color) / Partial Idlemode for internal operation. When used internal clock for the display operation, framefrequency can be adjusted with the I/PI_RTN[3:0] bits(1H period clock cycle),I/PI_DIV[1:0], and I/PI_DUM[7:0] bits.I/PI_DUM0DIV1 DIV0 Division Ratio Internal Display Operation Clock Frequency0 0 1 fosc / 10 1 2 fosc / 21 0 4 fosc / 41 1 8 fosc / 8Note: fosc = R-C oscillation frequencyHimax ConfidentialFor Go-tek OnlyThis information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosedin whole or in part without prior written permission of Himax.-P.146-October, 2009