iAPX 286 Operating System Writers Guide 1983

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TASK MANAGEMENTTASK XTSS TSS TSS TSSFLAGS FLAGS FLAGS FLAGSNT~l NT~l NT~l NT~lBACK LINKL/ BACK LINK L/ BACK LINK L/BACK LINKCURRENTLYBEXECUTINGETASKFHARDWARE-SCHEDULED TASKS0 ------------------------------------------------------SOFTWARE-SCHEDULED TASKSRE\TSS TSS TSSFLAGS FLAGS FLAGSNT~O NT~O NT~OBACK LINKCURRENTSOFTWARE-SCHEDULEDTASK*BACKLINK-:e-.r-BACK LINKTSS TSS TSSFLAGS FLAGS FLAGSNT~l NT~l NT~lBACK LINKL/ BACK LINK ~BACK LINKCURRENTLYEXECUTINGATASKF HARDWARE-SCHEDULED TASKST ------------------------------------------------------E SOFTWARE-SCHEDULED TASKSRTASK X\TSS TSS TSS TSSFLAGS FLAGS FLAGS FLAGSNT~O NT~O NT~O NT~OBACK LINKBACK LINK.rBACK LINK~CURRENT - - -.r-SOFTWARE-SCHEDULEDTASK.r-BACK LINKFigure 4·4. Changing Scheduling Mode121960-574-8 121960-001
TASK MANAGEMENTexample, when an application calls the operating system to request receipt of a message from anothertask, the operating system determines whether a message is waiting for delivery. If no message iswaiting, then the operating system must switch the task from RUNNING state to WAITING state.Later when another task calls the operating system to send a message to the waiting task, the operatingsystem must change the task from WAITING state to READY state. In cases such as these, theoperating system plays a bookkeeping role, simply keeping track of which tasks are waiting and associatingevents with the correct waiting tasks.The operating system plays a much more significant role, however, when it determines which of theready tasks to dispatch (the transition from READY state to RUNNING state) or when to preemptthe task that is executing (the transition from RUNNING state to READY state). These decisionsaffect the overall performance of the system, both throughput and response to external events.POLICIES AND MECHANISMSBecause of the difficulty of establishing an effective policy for dispatching and preemption decisions,it is desirable to clearly separate mechanisms from policies. The only control an operating system canexercise over tasks is deciding which task to execute and how long to let it run before changing toanother task. The scheduling mechanisms must exert such control in a manner that the policies canadjust. For example, to control how long a task executes, the scheduler implements a mechanism forpreempting the task after a certain time period has elapsed. The mechanism consists of an intervaltimer (such as Intel's 8254 Programmable Interval Timer) that interrupts the executing task periodicallyso that the operating system can determine whether the task has yet exceeded the time-sliceallocated to it. The length of the time-slice is a variable that the policy layer can control. The policylayer sets the length of the time-slice to reflect the importance of the task.The separation of policy and mechanism applies as well to deciding which task to execute next. Forexample, the scheduling mechanism associates a priority number with each task. When changing tasksit always chooses the task with highest priority. The priority, however, is a variable, and the policylayer determines its value.For the policy layer to make reasonable decisions about scheduling, the mechanism layer may need tocollect statistics about the run-time behavior of tasks, for example:• Elapsed time in the system• Total of actual time serviced by processor• Running average of actual length of time-slice(Note that interrupt-scheduled tasks subtract from the time allocated to software-scheduled tasks.)The privilege levels of the <strong>iAPX</strong> <strong>286</strong> architecture can support the separation between mechanisms andpolicies. The mechanisms belong to the kernel of the operating system, and as such they should be welltested, highly reliable, and not subject to frequent change; in other words, they are good candidatesfor PL O. Policies, on the other hand, are subject to frequent change and, as a result, are less reliable.Running scheduling policies at PL I ensures that errors cannot corrupt kernel procedures.4-9 121960-001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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Page 42 and 43: USING HARDWARE PROTECTION FEATURESo
Page 44 and 45: USING HARDWARE PROTECTION FEATURESL
Page 46 and 47: USING HARDWARE PROTECTION FEATUREST
Page 48 and 49: USING HARDWARE PROTECTION FEATURESE
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Page 52 and 53: IntelUSING HARDWARE PROTECTION FEAT
Page 54 and 55: IntelU~ING HARDWARE PROTECTION FEAT
Page 56 and 57: lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
Page 59 and 60: CHAPTER 3REAL MEMORY MANAGEMENTIn d
Page 61 and 62: REAL MEMORY MANAGEMENTIALLOCATEGATE
Page 63 and 64: interREAL MEMORY MANAGEMENTBEFOREAF
Page 65 and 66: REAL MEMORY MANAGEMENTGLOBAL DESCRI
Page 67 and 68: REAL MEMORY MANAGEMENTTable 3-1. Ac
Page 69 and 70: REAL MEMORY MANAGEMENTBEFOREI "FREE
Page 71 and 72: REAL MEMORY MANAGEMENTBEFOREI "FREE
Page 73 and 74: REAL MEMORY MANAGEMENTPL/M-286 COMP
Page 79: REAL MEMORY MANAGEMENTPL/M-286 COMP
Page 82 and 83: IIIIIIIIIIIIIIIIIIIIII
Page 84 and 85: II I telTASK MANAGEMENTCPUTASK REGI
Page 86 and 87: TASK MANAGEMENTIf the proc~sser, wh
Page 88 and 89: TASK MANAGEMENTUsually, termination
Page 92 and 93: TASK MANAGEMENTSCHEDULING POLICIEST
Page 94 and 95: TASK MANAGEMENTThe example in figur
Page 96 and 97: TASK MANAGEMENTREADY QUEUESBY PRIOR
Page 98 and 99: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Page 101 and 102: CHAPTER 5DATA SHARING, ALIASING, AN
Page 103 and 104: DATA SHARING, ALIASING, AND SYNCHRO
Page 105 and 106: interDATA SHARING, ALIASING, AND SV
Page 117: DATA SHARING, ALIASING, AND SYNCHRO
Page 121 and 122: CHAPTER 6SIGNALS AND INTERRUPTSInte
Page 123 and 124: interSIGNALS AND INTERRUPTSlOTGOTTS
Page 125 and 126: SIGNALS AND INTERRUPTSTable 6-1. In
Page 127 and 128: SIGNALS AND INTERRUPTSSend interrup
Page 129 and 130: SIGNALS AND INTERRUPTSprocedure suc
Page 131: Handling Exception Conditions 7
Page 134 and 135: HANDLING EXCEPTION CONDITIONSError
Page 136 and 137: HANDLING EXCEPTION CONDITIONSAn exc
Page 138 and 139: HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
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CHAPTER 11BINDING AND LOADINGBindin
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BINDING AND LOADINGNamingThe names
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BINDING AND LOADING$ COMPACT (NUCLE
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interBINDING AND LOADINGsystem-IDiA
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BIND.ING AND LOADINGConverting a Pr
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BINDING AND LOADINGThe OMF of each
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interBINDING AND LOADINGsystem-IDiA
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOADI.NGPL/M-286 COMPIL
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BINDING AND LOADINGPL/M-286 COMPILE
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOAD.INGPL/M-286 COMPIL
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interBINDING AND LOADINGPL/M-286 CO
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BINDING AND LOADINGPL/M-286 COMPILE
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Numerics Processor Extension 12
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NUMERICS PROCESSOR EXTENSIONMath Pr
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interNUMERICS PROCESSOR EXTENSION
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Extended Protection13
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EXTENDED PROTECTIONIndirect NamingT
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EXTENDED PROTECTIONanother procedur
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Glossary
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GLOSSARYbootloadable module: a modu
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GLOSSARYexception: a processor-dete
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GLOSSARYintersegment reference: a r
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GLOSSARYoutward call: the attempt t
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GLOSSARYscheduling state: one of se
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GLOSSARYvirtual address: an address
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INDEXES register, 2-17, 2-18, 2-21,
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INDEXpresent bit, 2-2, 2-3, 2-9, 5-
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interu.s. SALES OFFICESALAIWIA IlEQ
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interu.s. DISTRIBUTORSNEW YORK (C"n
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intJINTEL INTERNATIONAL SALES OFFIC
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