iAPX 286 Operating System Writers Guide 1983

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REAL MEMORY MANAGEMENT"FREE"STARTLINKED LIST OFAVAILABLE SEGMENTSNULLSIZENEXTPRIOR"FREE"NULL"USED"ALLOCATEDSEGMENTFIRST AVAILABLEBOUNDARY TAG ---!:Cj"U~S~E2D':':r121960·18Figure 3-3. Example Memory-Management Data StructuresThe memory manager maintains physical-address pointers to the first segment in the available segmentlist and to the last. It also maintains a "current available" pointer that corresponds to Knuth's "rovingpointer."This example also makes some assumptions about the placement of descriptors in the GDT. Figure3-6 illustrates these assumptions:• The memory manager frequently needs to create temporary descriptors for such purposes as readingand updating the boundary tags and link fields. For its own convenience, the memory managerreserves GDT slots for these temporary descriptors. This example identifies the slots as SLOT_A,SLOLB, and SLOLe.• Adjacent slots in the GDT contain all the descriptors to information for one task. This way, given aselector for one task descriptor, simple addition or subtraction yields selectors for other descriptorsfor the same task.3-4 121960·001
interREAL MEMORY MANAGEMENTBEFOREAFTERI "USED" I I "USED" IL "USED" JLI "USED" L ...J "FREE" .1"USED" ...JSTARTSEGMENTTO BEFREEDI "USED"I "FREE"STARTILSIZENEXTPRIORSIZENEXTPRIORI "FREE" I I "FREE" ...J 121960-56Figure 3-4. Using Boundary Tags3-5 121960-001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
Page 11 and 12: TABLE OF CONTENTSCHAPTER 9PageVIRTU
Page 13 and 14: TABLE OF CONTENTSLIST OF FIGURESFig
Page 15: Introduction to Protected 1Multitas
Page 18 and 19: INTRODUCTION TO PROTECTED MULTITASK
Page 20 and 21: inter INTRODUCTION TO PROTECTED MUL
Page 22 and 23: 111'eI INTRODUCTION TO PROTECTED MU
Page 29: Using Hardware2Protection Features
Page 32 and 33: USING HARDWARE PROTECTION,FEATURESs
Page 34 and 35: interUSING HARDWARE PROTECTION FEAT
Page 36 and 37: USING HARDWARE PROTECTION FEATURES(
Page 38 and 39: USING HARDWARE PROTECTION FEATURES
Page 40 and 41: USING HARDWARE PROTECTION FEATUREST
Page 42 and 43: USING HARDWARE PROTECTION FEATURESo
Page 44 and 45: USING HARDWARE PROTECTION FEATURESL
Page 46 and 47: USING HARDWARE PROTECTION FEATUREST
Page 48 and 49: USING HARDWARE PROTECTION FEATURESE
Page 50 and 51: inl:el~USING HARDWARE PROTECTION FE
Page 52 and 53: IntelUSING HARDWARE PROTECTION FEAT
Page 54 and 55: IntelU~ING HARDWARE PROTECTION FEAT
Page 56 and 57: lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
Page 59 and 60: CHAPTER 3REAL MEMORY MANAGEMENTIn d
Page 61: REAL MEMORY MANAGEMENTIALLOCATEGATE
Page 65 and 66: REAL MEMORY MANAGEMENTGLOBAL DESCRI
Page 67 and 68: REAL MEMORY MANAGEMENTTable 3-1. Ac
Page 69 and 70: REAL MEMORY MANAGEMENTBEFOREI "FREE
Page 71 and 72: REAL MEMORY MANAGEMENTBEFOREI "FREE
Page 73 and 74: REAL MEMORY MANAGEMENTPL/M-286 COMP
Page 79: REAL MEMORY MANAGEMENTPL/M-286 COMP
Page 82 and 83: IIIIIIIIIIIIIIIIIIIIII
Page 84 and 85: II I telTASK MANAGEMENTCPUTASK REGI
Page 86 and 87: TASK MANAGEMENTIf the proc~sser, wh
Page 88 and 89: TASK MANAGEMENTUsually, termination
Page 90 and 91: TASK MANAGEMENTTASK XTSS TSS TSS TS
Page 92 and 93: TASK MANAGEMENTSCHEDULING POLICIEST
Page 94 and 95: TASK MANAGEMENTThe example in figur
Page 96 and 97: TASK MANAGEMENTREADY QUEUESBY PRIOR
Page 98 and 99: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Page 101 and 102: CHAPTER 5DATA SHARING, ALIASING, AN
Page 103 and 104: DATA SHARING, ALIASING, AND SYNCHRO
Page 105 and 106: interDATA SHARING, ALIASING, AND SV
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DATA SHARING, ALIASING, AND SYNCHRO
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CHAPTER 6SIGNALS AND INTERRUPTSInte
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interSIGNALS AND INTERRUPTSlOTGOTTS
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SIGNALS AND INTERRUPTSTable 6-1. In
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SIGNALS AND INTERRUPTSSend interrup
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SIGNALS AND INTERRUPTSprocedure suc
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Handling Exception Conditions 7
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HANDLING EXCEPTION CONDITIONSError
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HANDLING EXCEPTION CONDITIONSAn exc
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HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
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CHAPTER 11BINDING AND LOADINGBindin
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BINDING AND LOADINGNamingThe names
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BINDING AND LOADING$ COMPACT (NUCLE
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interBINDING AND LOADINGsystem-IDiA
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BIND.ING AND LOADINGConverting a Pr
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BINDING AND LOADINGThe OMF of each
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interBINDING AND LOADINGsystem-IDiA
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOADI.NGPL/M-286 COMPIL
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BINDING AND LOADINGPL/M-286 COMPILE
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOAD.INGPL/M-286 COMPIL
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interBINDING AND LOADINGPL/M-286 CO
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BINDING AND LOADINGPL/M-286 COMPILE
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Numerics Processor Extension 12
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NUMERICS PROCESSOR EXTENSIONMath Pr
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interNUMERICS PROCESSOR EXTENSION
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Extended Protection13
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EXTENDED PROTECTIONIndirect NamingT
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EXTENDED PROTECTIONanother procedur
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Glossary
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GLOSSARYbootloadable module: a modu
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GLOSSARYexception: a processor-dete
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GLOSSARYintersegment reference: a r
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GLOSSARYoutward call: the attempt t
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GLOSSARYscheduling state: one of se
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GLOSSARYvirtual address: an address
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INDEXES register, 2-17, 2-18, 2-21,
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INDEXpresent bit, 2-2, 2-3, 2-9, 5-
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interu.s. SALES OFFICESALAIWIA IlEQ
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interu.s. DISTRIBUTORSNEW YORK (C"n
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intJINTEL INTERNATIONAL SALES OFFIC
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iAPX 286 Operating System Writers Guide 1983

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