iAPX 286 Operating System Writers Guide 1983

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GLOSSARYvirtual address: an address that consists of a selector and an offset value. The selector chooses adescriptor for a segment; the offset provides an index into the selected segment.virtual address space: The set of all possible virtual addresses that a 'task can access, as defined by theGDT and the task's LDT. The maximum possible virtual address space for one task is one gigabyte.virtual memory: a style of memory management that permits the virtual address space to exceed thephysical address space of RAM. With the help of processor features, the operating system simulatesthe virtual address space by using secondary storage to hold the overflow from RAM.word count: a field of a gate descriptor that specifies the number of words of parameters to be copiedfrom the calling procedure's stack to the stack of the called procedure.writable segment: a data segment that can be written to. A writable segment is identified by a Booleanin its descriptor.XOS (Example Operating System): an imaginary operating system, portions of which are used in thisbook as examples.Glossary-12 121960-001
INDEX8089 I/O processor, 8-18254 Programmable Interval Timer (PIT), 4-5,4-9,4-138259A Programmable Interrupt Controller(PIC), 4-6, 6-1, 6-6, 7-680287 Numerics Processor Extension (NPX),1-7,7-4,7-5,7-8, Chapter 12access rights (field of descriptor), 2-21, 2-22,9-2, 11-5, 11-10, 13-1, 13-2, 13-4accessed bit, 2-7, 5-3, 9-1, 9-4, 9-5, 9-7, 10-2ADC, 7-8addressing mechanism, 2-1ADJUST$RPL, 2-16, 13~2alias, 2-17 thru 2-22, 3-2,4-10,4-12, Chapter 5,6-5,8-2,9-3,9-7, 10-3, 11-2, 11-9, 13-5ARPL, 2-16, 13-2 thru 13-4ASM286, 3-6, 4-13, 11-4, 13-2ASSUME, 11-4asynchronous execution, 1-6back link (of TSS), 4-1 thru 4-4, 4-7, 4-13, 7-5,7-6, 10-2, 11-10base address, 2-4, 2-15, 4-1, 5-3, 9-3,9-5, 10-3,11-3, 11-10, 11-11binding, 1-8, 2-8, 2-9, Chapter 11Binder, see iAPX 286 Binderbootloadable, see module, bootloadableBOUND,7-4bound check exception, 7-4boundary tags, 3-2, 3-5, 3-6, 9-3breakpoint, 2-17, 7-3buffer, 2-18, 3-1, 3-10, 5-10, 8-1, 8-3, 8-5, 8-7,9-2,9-4Builder, see iAPX 286 System BuilderBUSY/ pin, 12-2, 12-3busy task, 4-3, 4-4, 7-7CALL, 2-7, 2-9, 2-10, 4-2 thru 4-4, 4-13, 4-17,6-1,6-2,6-4,6-6,7-5 thru 7-7, 11-3carry flag (CF), 7-8CLI, 4-6, 4-7, 5-6, 6-2, 8-2CL TS, 12-2, 12-4CMPS, 7-7combine type, 11-4COMPACT, 11-4, 11-5compaction, 3-10 .compiler control statements, 11-4conforming segment, 2-5, 6-2, 6-7, 6-8critical section, 5-5 thru 5-7, 12-4CS register, 4-4,6-9,7-5 thru 7-7, 9-1,9-6, 9-7,10-1, 11-3, 11-9, 12-5current privilege level (CPL), 2-11, 2-16, 4-6,5-6,6-2,6-7,6-8,8-2, 10-1, 10-2, 13-3deadlock, 5-7, 5-10debugger, 2-17, 7-3,11-3,11-10deletionof segment, 2-20,5-2,5-3,8-3,9-5, 13-1of descriptor, 13-5DESCRP section, 11-11, 11-12descriptor, 2-2,2-12, 11-6, 11-9data segment, 2-2, 2-3, 2-6, 2-14, 2-15, 2~18,7-7,9-3 thru 9-5, 9-7dynamic creation, 3-1, 3-2executable segment, 2-2, 2-4, 2-6,2-7,2-14,2-15,2-17,6-7,7-7,9-7gate, 2-2, 2-7 thru 2-11, 2-15, 6-2,7-6,9-1,9-2, 10-2, 11-3, 11-9system segment, 2-2, 2-5descriptor privilege level (DPL), 2-3, 2-6, 2-9,2-11,2-15,2-20,2-21,4-3,5-7,6-7,6-8,8-2,8-5, 8-7descriptor table, 2-2, 2-12, 2-15see also global descriptor table, localdescriptor table, interrupt descriptor tableDESNAM section, 11-11device drivers, 5-17, 8-1, 8-2, 8-4, 8-7, 9-2, 9-4,11-2, 11-4DI register, 7-7DISABLE, 6·2, 6-4, 7-1dispatching, 4-9, 4-13, 5-7,9-5, 11-4divide error exception, 6-7, 7-3double fault, 7-5, 9-2, 9-4DPL, see descriptor privilege levelDS register, 2-17, 2-18, 2-21, 4-12, 7-5 thru 7-7,9-1, 9-6, 9-7, 10-1dynamic system, 1-7 thru 1-10,2-2,2-3,2-12,2-18 thru 2-20,2-22,3-1,4-4,5-7,6-5, 11-8effective privilege level, 2-16EM (emulation mode) flag, 7-4, 7-8, 12-1 thru12-3emulation, 7-8, 12-1, 12-4ENABLE,6-2ENTER,7-6ENTRY, 11-6EPROM,10-3ERROR/ pin, 7-8, 12-1 thru 12-3, 12-5error code, 7-1, 7-2, 7-5 thru 7-7, 7-9, 9-2, 9-3,12-5Index-1121960·001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESo
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USING HARDWARE PROTECTION FEATURESL
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESE
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inl:el~USING HARDWARE PROTECTION FE
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IntelUSING HARDWARE PROTECTION FEAT
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IntelU~ING HARDWARE PROTECTION FEAT
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lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
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CHAPTER 3REAL MEMORY MANAGEMENTIn d
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REAL MEMORY MANAGEMENTIALLOCATEGATE
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interREAL MEMORY MANAGEMENTBEFOREAF
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REAL MEMORY MANAGEMENTGLOBAL DESCRI
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REAL MEMORY MANAGEMENTTable 3-1. Ac
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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IIIIIIIIIIIIIIIIIIIIII
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II I telTASK MANAGEMENTCPUTASK REGI
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TASK MANAGEMENTIf the proc~sser, wh
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TASK MANAGEMENTUsually, termination
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TASK MANAGEMENTTASK XTSS TSS TSS TS
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TASK MANAGEMENTSCHEDULING POLICIEST
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TASK MANAGEMENTThe example in figur
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TASK MANAGEMENTREADY QUEUESBY PRIOR
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
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CHAPTER 5DATA SHARING, ALIASING, AN
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DATA SHARING, ALIASING, AND SYNCHRO
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interDATA SHARING, ALIASING, AND SV
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CHAPTER 6SIGNALS AND INTERRUPTSInte
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interSIGNALS AND INTERRUPTSlOTGOTTS
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SIGNALS AND INTERRUPTSTable 6-1. In
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SIGNALS AND INTERRUPTSSend interrup
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SIGNALS AND INTERRUPTSprocedure suc
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Handling Exception Conditions 7
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HANDLING EXCEPTION CONDITIONSError
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HANDLING EXCEPTION CONDITIONSAn exc
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HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
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CHAPTER 11BINDING AND LOADINGBindin
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BINDING AND LOADINGNamingThe names
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BINDING AND LOADING$ COMPACT (NUCLE
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Page 189 and 190: BIND.ING AND LOADINGConverting a Pr
Page 191 and 192: BINDING AND LOADINGThe OMF of each
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Page 195 and 196: BINDING AND LOADINGPL/M-2B6 COMPILE
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Page 207 and 208: BINDING AND LOADINGPL/M-286 COMPILE
Page 209: Numerics Processor Extension 12
Page 212 and 213: NUMERICS PROCESSOR EXTENSIONMath Pr
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Page 217: Extended Protection13
Page 220 and 221: EXTENDED PROTECTIONIndirect NamingT
Page 222 and 223: EXTENDED PROTECTIONanother procedur
Page 225: Glossary
Page 228 and 229: GLOSSARYbootloadable module: a modu
Page 230 and 231: GLOSSARYexception: a processor-dete
Page 232 and 233: GLOSSARYintersegment reference: a r
Page 234 and 235: GLOSSARYoutward call: the attempt t
Page 236 and 237: GLOSSARYscheduling state: one of se
Page 240 and 241: INDEXES register, 2-17, 2-18, 2-21,
Page 242 and 243: INDEXpresent bit, 2-2, 2-3, 2-9, 5-
Page 245 and 246: interu.s. SALES OFFICESALAIWIA IlEQ
Page 247 and 248: interu.s. DISTRIBUTORSNEW YORK (C"n
Page 249 and 250: intJINTEL INTERNATIONAL SALES OFFIC
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