iAPX 286 Operating System Writers Guide 1983

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GLOSSARYintersegment reference: a reference to a location in a segment other than the segment containing thereference.intrasegment reference: a reference to a location in the same segment as the segment containing thereference.interlevel reference: an intersegment reference to a segment that has a different privilege level thanthat of the segment containing the reference.intertask transfer: a transfer of control flow to a task other that the current task.I/O-mapped I/O: a style of I/O interface in which I/O devices respond to addresses in an addressspace that is distinct from the memory address space. Special I/O instructions (IN, INS, OUT, OUTS)trigger I/O operations. The 80286 uses the M/IO pin to distinguish memory addresses from I/Oaddresses.I/O privilege level (IOPL): a two-bit item in the flag register of the 80286 that controls the currenttask's right to execute the I/O-related instructions IN, INS, OUT, OUTS, CLI, ST!, LOCK. A proceduremay not execute any of these instructions if CPL> 10PL.I/O subsystem: the portion of an operating system that deals with filing and I/O.IP (instruction pointer): an 80286 register that contains the offset of the instruction to be executedwithin the current code segment.kernel: that portion of an operating system that implements the most primitive of its functions.LDT register: an 80286 register that stores the selector, base address, and limit of the current LOT.limit: the field of a descriptor that defines the offset of the last byte of the segment.linkable module: an object module created by iAPX 286 translators, by the Binder, or by the Builderthat can serve as input to either the Builder or the Binder. A linkable module requires further processingbefore it can be executed.linking: the process of combining segments from one or more input modules and resolving referencesbetween modules. The Binder provides linking services for iAPX 286 program development.loadable module: an executable object module (usually created by the Builder or the Binder) that hasa format suitable for processing by a loader running under control of an operating system.loader: the task or procedures of an operating system that places an object module in RAM and preparesit for execution by the operating system and the processor.load-time: at the time a.task is loaded.local descriptor table (LDT): the descriptor table that contains descriptors that are (generally) privateto a given .task. Each task may have an LOT. A task can use only descriptors that are in its LOT or inthe GOT. The LOT protects tasks from one another.logical segment: the representation of a segment used by translators and program development utilitiesprior to the time when the segment is actually placed in physical memory.Glossary-6 121960·001
GLOSSARYmachine status word (MSW): an 80286 register that includes the TS, EM, MP, and PE Booleans.These items are global to the system and are not a part of the task state.mailbox: a software mechanism for sending messages between tasks. The mechanism consists of twoqueues: one a queue of undelivered messages, the other a queue of tasks waiting for messages. Messagesare delivered in FIFO order.memory management: the set of operating system functions that deal with the l111ocation of RAM totasks.memory-mapped I/O: a style of I/O interface in which I/O devices respond to specific addresses inthe memory address space. I/O operations are triggered by standard instructions that read from, andwrite to, memory locations.message: a unit of intertask communication.module: a compilation unit or a combination of compilation units.MP (math present) flag: a Boolean in the MSW that indicates whether a processor extension (such asthe 80287 Numerics Processor Extension) is present.mutual exclusion: preventing two critical sections from executing concurrently.multiprocessing: using more than one CPU to execute a multitasking system.multitasking: the capability to support more than one task either simultaneously (by using more thanone CPU) or virtually simultaneously (by multiplexing one CPU among several tasks).nested task (NT) flag: a Boolean in the flag word that indicates the existence of a back link field inthe TSS to a previous TSS.non-maskable interrupt (NMI): an external interrupt presented to the NMI pin of the 80286 that theprocessor does not ignore, even when IF is reset.not-present segment: a segment whose descriptor has the present bit reset. In a virtual-memory system,this condition normally indicates that the segment has been evicted from RAM to make space for othersegments.nucleus: see kernel.nullify: assign a null value to.numerics processor extension (NPX): the 80287 processor which cooperates with the 80286 CPU toextend its processing power in mathematical applications.object module format (OM F): a standard for the structure of object code files.OF (overflow) flag: an arithmetic flag that indicates when a signed operation produces a positive numberthat is too large or a negative number that is too small to fit in the destination operand.offset: the address of a location within a segment, expressed as a quantity to be added to the baseaddress of the segment.Glossary-7 121960·001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESo
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USING HARDWARE PROTECTION FEATURESL
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESE
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inl:el~USING HARDWARE PROTECTION FE
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IntelUSING HARDWARE PROTECTION FEAT
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IntelU~ING HARDWARE PROTECTION FEAT
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lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
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CHAPTER 3REAL MEMORY MANAGEMENTIn d
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REAL MEMORY MANAGEMENTIALLOCATEGATE
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interREAL MEMORY MANAGEMENTBEFOREAF
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REAL MEMORY MANAGEMENTGLOBAL DESCRI
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REAL MEMORY MANAGEMENTTable 3-1. Ac
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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IIIIIIIIIIIIIIIIIIIIII
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II I telTASK MANAGEMENTCPUTASK REGI
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TASK MANAGEMENTIf the proc~sser, wh
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TASK MANAGEMENTUsually, termination
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TASK MANAGEMENTTASK XTSS TSS TSS TS
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TASK MANAGEMENTSCHEDULING POLICIEST
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TASK MANAGEMENTThe example in figur
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TASK MANAGEMENTREADY QUEUESBY PRIOR
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
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CHAPTER 5DATA SHARING, ALIASING, AN
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DATA SHARING, ALIASING, AND SYNCHRO
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interDATA SHARING, ALIASING, AND SV
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CHAPTER 6SIGNALS AND INTERRUPTSInte
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interSIGNALS AND INTERRUPTSlOTGOTTS
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SIGNALS AND INTERRUPTSTable 6-1. In
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SIGNALS AND INTERRUPTSSend interrup
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SIGNALS AND INTERRUPTSprocedure suc
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Handling Exception Conditions 7
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HANDLING EXCEPTION CONDITIONSError
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HANDLING EXCEPTION CONDITIONSAn exc
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HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
Page 181 and 182: CHAPTER 11BINDING AND LOADINGBindin
Page 183 and 184: BINDING AND LOADINGNamingThe names
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Page 189 and 190: BIND.ING AND LOADINGConverting a Pr
Page 191 and 192: BINDING AND LOADINGThe OMF of each
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Page 195 and 196: BINDING AND LOADINGPL/M-2B6 COMPILE
Page 197 and 198: BINDING AND LOADI.NGPL/M-286 COMPIL
Page 199 and 200: BINDING AND LOADINGPL/M-286 COMPILE
Page 201 and 202: BINDING AND LOADINGPL/M-2B6 COMPILE
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Page 207 and 208: BINDING AND LOADINGPL/M-286 COMPILE
Page 209: Numerics Processor Extension 12
Page 212 and 213: NUMERICS PROCESSOR EXTENSIONMath Pr
Page 214 and 215: interNUMERICS PROCESSOR EXTENSION
Page 217: Extended Protection13
Page 220 and 221: EXTENDED PROTECTIONIndirect NamingT
Page 222 and 223: EXTENDED PROTECTIONanother procedur
Page 225: Glossary
Page 228 and 229: GLOSSARYbootloadable module: a modu
Page 230 and 231: GLOSSARYexception: a processor-dete
Page 234 and 235: GLOSSARYoutward call: the attempt t
Page 236 and 237: GLOSSARYscheduling state: one of se
Page 238 and 239: GLOSSARYvirtual address: an address
Page 240 and 241: INDEXES register, 2-17, 2-18, 2-21,
Page 242 and 243: INDEXpresent bit, 2-2, 2-3, 2-9, 5-
Page 245 and 246: interu.s. SALES OFFICESALAIWIA IlEQ
Page 247 and 248: interu.s. DISTRIBUTORSNEW YORK (C"n
Page 249 and 250: intJINTEL INTERNATIONAL SALES OFFIC
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iAPX 286 Operating System Writers Guide 1983

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