iAPX 286 Operating System Writers Guide 1983
iAPX 286 Operating System Writers Guide 1983
iAPX 286 Operating System Writers Guide 1983
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
GLOSSARYhandler table: a table of selectors to call gates that identify the procedures for servicing asynchronousevents such as interrupts or software signals. A handler table is used by an operating system's interruptdistributor and signalling primitives.I bit: a Boolean in the error code which, when set, indicates that index portion of the error code pointsto an entry in the IDT.<strong>iAPX</strong> <strong>286</strong> Binder: an <strong>iAPX</strong> <strong>286</strong> program development utility used to link modules, combine segments,and create a single-task, loadable output module.<strong>iAPX</strong> <strong>286</strong> <strong>System</strong> Builder: the configuration utility for <strong>iAPX</strong> <strong>286</strong> protected-mode systems.IDT register: an 80<strong>286</strong> register that stores the base address and limit of the IDT.index: the field of a selector that identifies a slot in a descriptor table.indirect I/O: a style of I/O interface in which I/O operations are executed by an independent processor,not by the CPU.interrupt: 1) the electrical or logical signal that an event has occurred; 2) the mechanism by which acomputer system responds quickly to events that occur at unpredictable times.interrupt controller: a device (such as Intel's 8259A Programmable Interrupt Controller) that assiststhe CPU in responding to multiple externalinterrupt signals by performing such functions as detection,priority resolution, and identification.interrupt descriptor table (IDT): a descriptor table that contains gates to the handler procedures orhandler tasks for interrupts and traps. The IDT may contain only interrupt gates, trap gates, and taskgates.interrupt distributor: an operating-system interrupt procedure that transfers control to a task-definedprocedure for servicing the interrupt.interrupt-enable flag (IF): a control flag of the 80<strong>286</strong> that determines whether the processor respondsto external interrupt signals presented at the processor's INTR pin.interrupt gate: a gate that identifies the entry point of a procedure for handling an interrupt. When aninterrupt transfers control through an interrupt gate, the processor resets the interrupt-enable flag.Interrupt gates are valid only in the IDT.interrupt handler: a procedure or task that is invoked by an interrupt.interrupt latency: the time from the occurrence of an interrupt signal to the execution of the firstinstruction of an interrupt handler.interrupt procedure: an interrupt handler that is identified by an interrupt gate or trap gate. An interruptprocedure runs in the interrupted task.interrupt task: an interrupt handler that is identified by a task gate and runs as a task separate fromthe interrupted task.interrupt vectoring: the mapping from an interrupt source to the interrupt handler. In the <strong>iAPX</strong> <strong>286</strong>architecture, the 8259A and the IDT are components of the interrupt vectoring process.Glossary-5 121960·001