iAPX 286 Operating System Writers Guide 1983

interNUMERICS PROCESSOR EXTENSION• The CPU encounters either the WAIT instruction or an ESC instruction when both MP and TS areset. In this case, the exception handler should update the state of the NPX if necessary.EMULATIONThe return link points to the first byte of the ESC instruction (or to the prefix byte, if any). As theemulator decodes the ESC instruction, it should step the return pointer so that, at the end of theemulation routine, the return from the exception handler causes execution to resume at the firstinstruction following the ESC instruction.UPDATING STATETo make sure that the state of the NPX corresponds to the current task, the operating system shouldimplement the concept of "ownership" of the NPX. Ownership can be indicated by a Boolean in thetask database (TDB). The operating system must ensure that only one task at a time is marked as theowner of the NPX. The exception handler should follow these steps:1. Use the CL TS instruction to reset TS.2. Return if the current task owns the NPX.3. Use the FSAVE ESC instruction (PL/M-286 SAVE$REAUSTATUS) to store NPX context inthe former owner's task database.4. Record the current task as the owner of the NPX.5. Use the FRSTOR ESC instruction (PL/M-286 RESTORE$REAUSTATUS) to load the NPXcontext from the new owner's TDB.Since task switches may occur during execution of the exception handler, steps 3, 4, and 5 are a criticalregion and must be protected by a mechanism such as a semaphore.The exception handler must run at PL 0, both because it alters the critical task database at PL 0 andbecause it uses the privileged instruction CL TS.The exception handler must be an interrupt procedure, not an interrupt task. If it were an interrupttask, the task switch that occurs upon returning from the exception handler would set TS, therebycausing the exception again.The return link points to the first byte of the interrupted instruction. Return from the exception handlercauses restart of that instruction, but this time TS is reset and the instruction can proceed.Interrupt 9-Processor Extension Segment Overrun (MP)This exception occurs when a memory operand of an 80287 instruction has a segment-limit violation.Since the 80287 executes in parallel with the 80286, two difficulties may arise:• The occurrence of this exception may not relate directly to the instruction stream being executedby the current task. A task switch may have occurred since the 80287 began executing the instruction.Even if the interrupted task is the correct task, its IP may have been advanced by severalinstructions beyond the ESC instruction.• Since the exception is not maskable, it may occur while interrupts are disabled. If minimum interruptlatency is important, the exception handler must do as little as possible. It could, for cxample,record the error for later handling.12-4 121960·001