iAPX 286 Operating System Writers Guide 1983

CHAPTER 12NUMERICS PROCESSOR EXTENSIONThe iAPX 286/20 is a configuration of chips consisting of an 80286 CPU and an 80287 NumericsProcessor Extension (NPX). With these two cooperating processors it is possible to construct powerfulnumerics processing systems, but the operating system must multiplex the 80287 among the tasks thatuse it. If the system does not include an 80287, you may choose to have the operating system emulateits functions.i.APX 286/20 NUMERICS PROCESSING FEATURESSeveral features of the iAPX 286/20 are of special interest to operating-system designers and programmers.You can find more details on how to use the iAPX 286/20 in the iAPX 286 Programmer'sReference Manual.ESCAPE InstructionsThe 80287 NPX extends the instruction set of the iAPX 286 by over fifty opcodes. The CPU identifiesthe extended instruction set by the bit pattern 110118 in the high-order five bits of the first byte ofthe instruction. Instructions thus marked are called ESCAPE or ESC instructions.The CPU performs some functions upon encountering an ESC instruction, before sending the instructionto the NPX. Those functions that are of interest to the operating system include• Testing the emulation mode (EM) flag to determine whether NPX functions are being emulated bysoftware.• Testing the TS flag to determine whether there has been a context change since the last ESCinstruction.• For some ESC instructions, testing the ERROR pin to determine whether an error condition existsat the NPX as a result of a previous ESC instruction.The ASM286 Assembly Language Reference Manual provides more information on each 80287instruction.Emulation Mode Flag (EM)The EM bit of the 80286 machine status word (MSW) indicates to the CPU whether NPX functionsare to be emulated. If the processor finds EM set when executing an ESC instruction, it causes trap 7,giving the exception handler an opportunity to emulate the functions of an 80287. The EM flag can bechanged with the aid of LMSW (load machine status word) instruction (legal only at privilege level 0(PL 0)) and tested with the aid of the SMSW (store machine status word). The built-iri variableMACHINE$STATUS gives PL/M-286 programs access to the MSW.The EM bit also controls the function of the WAIT instruction. If the processor finds EM set whileexecuting aWAlT, the processor does not check the ERROR pin for an error indication.Note that EM must never be set concurrently with MP.12-1 121960-001