iAPX 286 Operating System Writers Guide 1983
iAPX 286 Operating System Writers Guide 1983
iAPX 286 Operating System Writers Guide 1983
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CHAPTER 10SYSTEM INITIALIZATIONThe initialization performed at power-on or RESET by the 80<strong>286</strong> processor is not, by itself, adequatefor running in protected mode. Software must perform additional initialization before it is possible tofully use protected mode.INITIAL STATEWhen you power up an 80<strong>286</strong> system Or perform a RESET, the state of the processor is as follows:• The MSW(machine status word) is zero; i.e., the 80<strong>286</strong> starts running in the real-address mode.• CS:IP be set to FOOO:FFFO, and the CS limit is OFFFFH.• The four high-order address lines A 23 -20 are automatically asserted for all subsequent references toCS until your initialization code changes CS.• SS, DS, ES are set to zero, and the corresponding limit registers are set to OFFFFH.• The flag word is zero. This means that the 80<strong>286</strong> starts running with the maskable interrupts disabled.The initial state of the address lines and CS:IP causes the processor to begin executing instructions atphysical address OFFFFFOH. Presumably, this addresses a JMP instruction in an initialization procedurelocated in ROM or in RAM that has been loaded by another processor. The initialization proceduremay occupy any portion of the last 65,536 bytes of the 16-megabyte address space. The JMPinstruction at physical address OFFFFFOH transfers control to the actual beginning of the initializationprocedure. The first instruction that modifies the CS register causes the processor to cease assertingthe high-order four address lines; therefore, the initialization procedure must avoid using any instruc~tions that modify the CS register, except for the final JMP instruction. -The initial state of the DS, ES, and SS registers gives the initialization procedure access to the first65,536 bytes of the address space. The initialization procedure may change these registers, however,to gain access to any location in the first megabyte of the address space. (With regard to segmentationarid addressing, the 80<strong>286</strong> in real-address mode behaves just as an 8086.) Access to other portions ofmemory is possible only after switching into protected mode.SWITCHING TO PROTECTED MODEYou use the LMSW (load machine status word) instruction to set the PE bit in,the MSW,'therebyswitching the 80<strong>286</strong> into protected, virtual-address mode. The current privilege level (CPL) starts atzero. The segment registers continue to point to the same physical memory areas as in real-addressmode.Immediately after setting the PE flag, the initialization code must· flush the processor's instructionqueues by executing a' JMP instruction. The 80<strong>286</strong> fetches and decodes instructions and addressesbefore they are used; however, after a change into protected, virtual-address mode, the prefetchedinstruction information (which pertains to real-address mode) is no longer valid. A JMP forces theprocessor to discard the invalid information. An intrasegment JMP will cause the processor to drop thefour high-order address lines; however, in protected mode this is not a problem. All addressing inprotected mode uses the 24-bit base address from the segment descriptor; so, once in protectedmpde,all of physical memory is accessible.10-1 121960-001