iAPX 286 Operating System Writers Guide 1983

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INPUT /OUTPUTAPPLICATIONDEVICE DRIVERREQUEST110CONTINUEPROCESSINGDO OTHERPROCESSINGRECEIVERESPONSEHARDWARE I/O DEVICEGETCOMMAND• WAIT 001/0APPLICATIONREQUESTI/OCAUSEINTERRUPTCONTINUEPROCESSINGDO OTHERPROCESSINGRECEIVERESPONSE121960-37Figure 8-2. Synchronization with Simple Device DriverAPPLICATIONDEVICE DRIVER (PART A)REQUEST1/0CONTINUEPROCESSINGDO OTHERPROCESSINGRECEIVERESPONSEHARDWARE I/O DEVICEGETCOMMANDAPPLICATION00110REQUESTI/OCAUSEINTERRUPTCONTINUEPROCESSINGDO OTHERPROCESSINGRECEIVERESPONSE121960-38Figure 8-3. Synchronization with Two-Part Device Driver8-6 121960-001
INPUT /OUTPUTtask the I/0 procedures run in. The I/O interface procedures (READ, WRITE, etc.) must have DPLequal to that of the global I/0 data and therefore must have call gates at the privilege level of applicationprocedures (PL 3). If these call gates reside in the LDTs of application tasks, then I/0 interfaceprocedures can be shared by (but limited to) those tasks that need them. The call gates can also residein the GDT, where all tasks can access them. In either case the interface procedures run in the callingtask.The possibilities for running device drivers in parallel with the calling task suggests that they be separatetasks. Such a separation also serves to protect applications and device drivers from one another, adefinite advantage because inherent complexity and frequency of change tend to place device driversamong the least reliable of operating system functions. The I/0 interface procedures have the responsibilityfor managing the details of communication between the calling task and the device drivers.You can implement a sophisticated device driver such as that illustrated in figure 8-3 as two cooperatingtasks: one scheduled by interrupts via a task gate in the IDT, and the other scheduled by I/Orequests via an operating-system mailbox facility.It is possible to implement device drivers as interrupt procedures that run within applications tasks.Such a structure is advantageous in these cases:• Efficiency of I/0 is an overriding goal.• Interrupts may arrive when a driver is busy.The lack of protection inherent in such a structure becomes apparent, however, when you consider thatthe driver procedure that fields an I/O-complete interrupt may run as part of a task completely unrelatedto the task that originally requested the I/O operation, and must run at PL O.Viewing the possible implementations of buffers from the perspective of the iAPX 286 architecture,the most pertinent consideration is whether a segment contains just one buffer or several buffers. Anapproach that uses one segment per buffer has several advantages:• The protection mechanism of the iAPX 286 (working as it does on segment descriptors) focuses oneach buffer individually.• The selector of a buffer segment serves as a convenient buffer identifier, fitting easily into thealiasing and mailbox schemes outlined in Chapter 5.You can avoid the potential GDT congestion that may result from having one segment (and thereforeat least one segment descriptor) per buffer by storing buffer descriptors in LDTs.When tasks share buffers (as between an application task and one or more device-driver tasks), youhave a choice between• Leaving the buffer at all times within the address spaces of all the sharing tasks• Transferring the buffer from the address space of one task into that of anotherThe mailbox scheme outlined in Chapter 5 easily accomplishes the latter approach. This scheme hasthe advantage that the application task cannot use the buffer at the same time as I/O is in progress.The "usage privilege level" (UPL), if set to IOPL, provides additional protection by limiting mailboxaccess to I/O procedures. The application's requirements for I/O efficiency may, however, precludeuse of mailboxes for this purpose.8-7 121960-001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESo
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USING HARDWARE PROTECTION FEATURESL
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESE
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inl:el~USING HARDWARE PROTECTION FE
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IntelUSING HARDWARE PROTECTION FEAT
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IntelU~ING HARDWARE PROTECTION FEAT
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lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
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CHAPTER 3REAL MEMORY MANAGEMENTIn d
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REAL MEMORY MANAGEMENTIALLOCATEGATE
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interREAL MEMORY MANAGEMENTBEFOREAF
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REAL MEMORY MANAGEMENTGLOBAL DESCRI
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REAL MEMORY MANAGEMENTTable 3-1. Ac
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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IIIIIIIIIIIIIIIIIIIIII
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II I telTASK MANAGEMENTCPUTASK REGI
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TASK MANAGEMENTIf the proc~sser, wh
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TASK MANAGEMENTUsually, termination
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TASK MANAGEMENTTASK XTSS TSS TSS TS
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TASK MANAGEMENTSCHEDULING POLICIEST
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TASK MANAGEMENTThe example in figur
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TASK MANAGEMENTREADY QUEUESBY PRIOR
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Page 101 and 102: CHAPTER 5DATA SHARING, ALIASING, AN
Page 103 and 104: DATA SHARING, ALIASING, AND SYNCHRO
Page 105 and 106: interDATA SHARING, ALIASING, AND SV
Page 117: DATA SHARING, ALIASING, AND SYNCHRO
Page 121 and 122: CHAPTER 6SIGNALS AND INTERRUPTSInte
Page 123 and 124: interSIGNALS AND INTERRUPTSlOTGOTTS
Page 125 and 126: SIGNALS AND INTERRUPTSTable 6-1. In
Page 127 and 128: SIGNALS AND INTERRUPTSSend interrup
Page 129 and 130: SIGNALS AND INTERRUPTSprocedure suc
Page 131: Handling Exception Conditions 7
Page 134 and 135: HANDLING EXCEPTION CONDITIONSError
Page 136 and 137: HANDLING EXCEPTION CONDITIONSAn exc
Page 138 and 139: HANDLING EXCEPTION CONDITIONSA few
Page 140 and 141: HANDLING EXCEPTION CONDITIONSAn ins
Page 143 and 144: CHAPTER 8INPUT /OUTPUTMany of the c
Page 145 and 146: INPUT /OUTPUTYou can still take adv
Page 147: INPUT /OUTPUT• Only the operating
Page 153 and 154: CHAPTER 9VIRTUAL MEMORYThe memory l
Page 155 and 156: VIRTUAL MEMORYthose segments that a
Page 157 and 158: VIRTUAL MEMORY• Return the RAM sp
Page 159 and 160: VIRTUAL MEMORYReplacementThe operat
Page 161 and 162: System Initialization10
Page 163 and 164: CHAPTER 10SYSTEM INITIALIZATIONThe
Page 165 and 166: SYSTEM INITIALIZATIONStarting the f
Page 167 and 168: iAPX286 "ACRO ASSEMBLERLOCOBJEnter
Page 169 and 170: iAPX286 MACRO ASSEMBLEtEnter Protec
Page 171 and 172: iAPX286 MACRO ASSEMBLER·· Enter ~
Page 173 and 174: iAPX286 'UCRO USE148LER Ente,. P,.o
Page 175 and 176: iAPX286 MACRO ASSEMBLEREnt9~ P~otec
Page 177: iAPX286 MACRO ASSEMBLE~ INITIAL TAS
Page 181 and 182: CHAPTER 11BINDING AND LOADINGBindin
Page 183 and 184: BINDING AND LOADINGNamingThe names
Page 185 and 186: BINDING AND LOADING$ COMPACT (NUCLE
Page 187 and 188: interBINDING AND LOADINGsystem-IDiA
Page 189 and 190: BIND.ING AND LOADINGConverting a Pr
Page 191 and 192: BINDING AND LOADINGThe OMF of each
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Page 195 and 196: BINDING AND LOADINGPL/M-2B6 COMPILE
Page 197 and 198: BINDING AND LOADI.NGPL/M-286 COMPIL
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BINDING AND LOADINGPL/M-286 COMPILE
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOAD.INGPL/M-286 COMPIL
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interBINDING AND LOADINGPL/M-286 CO
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BINDING AND LOADINGPL/M-286 COMPILE
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Numerics Processor Extension 12
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NUMERICS PROCESSOR EXTENSIONMath Pr
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interNUMERICS PROCESSOR EXTENSION
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Extended Protection13
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EXTENDED PROTECTIONIndirect NamingT
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EXTENDED PROTECTIONanother procedur
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Glossary
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GLOSSARYbootloadable module: a modu
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GLOSSARYexception: a processor-dete
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GLOSSARYintersegment reference: a r
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GLOSSARYoutward call: the attempt t
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GLOSSARYscheduling state: one of se
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GLOSSARYvirtual address: an address
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INDEXES register, 2-17, 2-18, 2-21,
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INDEXpresent bit, 2-2, 2-3, 2-9, 5-
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interu.s. SALES OFFICESALAIWIA IlEQ
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interu.s. DISTRIBUTORSNEW YORK (C"n
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intJINTEL INTERNATIONAL SALES OFFIC
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