iAPX 286 Operating System Writers Guide 1983

HANDLING EXCEPTION CONDITIONSA few of the conditions that can cause this exception are recoverable. If the system incorporates virtualmemory, the solution for a not present LDT may be to bring it in from virtual store. In the case of aninvalid. back-link, you can make the assumption that the NT flag was set by mistake, give control tothe scheduler, and hope ....Interrupt 11-5egment Not Present (NP)This exception occurs when the processor detects that the present bit of a descriptor is reset. It mayoccur in any of these cases:• While loading the CS, DS, or ES registers, but not while loading the SS register (a stack faultoccurs in that case). .• White loading the LDT register with an LLDT instruction, but not while loading the LDT registerduring it task switch operation (the "invalid TSS" fault occurs in that case). .• While attempting to use a gate that is marked "not present."An operating system typically uses the "not present" exception to implement a virtual memory system.Refer to Chapter 9 for more information on virtual memory.The processor pushes an error code onto the stack of the exception handler. The error code containsthe selector of the descriptor that is marked "not present."·A "not present" indication in a gate descriptor usually has. special significance for the operating system.for gates in the IDT, the present bit may serve as a sign that the interrupt task is in software scheduledmode and temporarily unable to service an interrupt. If an interrupt arrives in this case, there may bean error either in the device that generates the interrupt or in the handling of the Interrupt MaskRegister of the 8259A PIC. (Refer to Chapter 6 for more information on interrupt handling). for gatesin the GDT or LDTs, the present bit may serve to signal an unresolved linkage. (Refer to Chapter 11for information on binding.)The instruction that causes a "not present" fault is restartable (except in the case of a task switch).Execution of an IRET by the exception handler causes the processor to execute the faulting instructionagain. When the processor detects the "not present" exception while loading CS, DS, or ES during atask switch, the exception occurs in the new task, and the return pointer points to the first instructionof the new task.Interrupt 12-5tack Exception (55)This exception occurs in either of two general conditions:• As a result ofa limit violation in any operation that refers to the SS register. This includes stackorientedinstructions such as POP, PUSH, ENTER, and LEAVE as well as other memory referencesthat implicitly use SS (for example, MOV AX,[BP+6] ). ENTER causes this exception whenthe stack is too small. for the indicated . local variable space. An interlevel CALL references twostacks; a stack~limit exception can.result from either of them.• When attempting to load the SS register with a descriptor that is marked "not present" but isotherwise valid. This can occurin a task switch, an interlevelCALL, an inter level return, or a MOVor POP instruction to SS.7-6 121960-001