iAPX 286 Operating System Writers Guide 1983
iAPX 286 Operating System Writers Guide 1983
iAPX 286 Operating System Writers Guide 1983
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CHAPTER 6SIGNALS AND INTERRUPTSInterrupts are a mechanism long used in single-task microprocessors for reacting quickly to externalevents. In the multitasking architecture of the <strong>iAPX</strong> <strong>286</strong>, each task may have the same needs forinformation about external events as the one task ina single-task system. In a multitasking system,several generalizations of interrupts are useful:• Some tasks may do nothing but service a specific external event. While the task waits for an eventto occur, the processor can service other tasks.• Information about an external event must be routed to the correct task.• Events external to a task may include events occurring in other tasks as well as events external tothe processor.• The ability to selectively ignore events must then extend to those events occurring in other tasks.• Each task can benefit from a vector table to automatically route information about events to thecorrect handler procedures within the task.• Scheduling of tasks that service events must be coordinated with the software scheduler, whileretaining the ability to respond rapidly to events.The 80<strong>286</strong> implements some of these generalizations of interrupts onto the multitasking environment,but the operating system has responsibility for others. Not all are relevant to every application of the80<strong>286</strong>.INTERRUPT FEATURES OF THE <strong>iAPX</strong> <strong>286</strong> ARCHITECTUREThe <strong>iAPX</strong> <strong>286</strong> architecture includes a number of features that work together to enable efficient responseto events.VectoringThe processor associates each event with an identifying number in the range 0-255. The processorrecognizes three classes of events:• External. Events occurring outside the 80<strong>286</strong> processor's environment are communicated to theprocessor via the INTR or NMI (non-maskable interrupt) pins. The NMI is interrupt 2. Otherexternal interrupts share the INTR pin via one or more 8259A Programmable Interrupt Controllers,which can map each interrupt to a unique interrupt ID in the range 32-255.• Processor. When the processor detects a condition that it cannot handle, it communicates this factby causing an interrupt with an ID in the range 0-16 (except for interrupt 2; which is the NMI).• Software. Programs can generate signal events by executing the instructions INT n and INTO.With INT n, the value of n can be any interrupt indentifier in the range 0-255. This gives softwarethe ability to simulate hardware interrupts as well as the ability to cause interrupts that are notdirectly associatcd with hardware events. (Note that many software systems use the software interruptto call on operating-system services. With the <strong>iAPX</strong> <strong>286</strong>, an interlevel CALL through a CALLgate serves this purpose.)6-1 121960·001