DATA BOOK - Al Kossow's Bitsavers

CMOSDATA BOOKCYPRESSSEMICONDUCTORr1u~/!r~~f»' INC.presentatives451 N. Shoreline BlvdMt. View, CA 94043 .(415) 960-1550

CMesDATAJ:iOOKCYPRESSSEMICONDUCTOR1~Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.Cypress Semiconductor, 3901 North First St., San Jose, CA 95134 (408) 943-2600Telex: 821032 CYPRESS SNJ UD, TWX: 910 997 0753, FAX: (408) 943-2741

PRODUCTINFORMATIONSTATIC RAMS,.PROMS•EPLDS ,~.•LOGICRISCBRIDGEMOSQUICKPRO,.QUALITY ANDRELIABILITYAPPLICATION BRIEFSPACKAGESIDI

~ Table of Contents~~~~u~================================================================General Product InformationPage NumberCypress Semiconductor Background ....................................................................... 1-1Cypress CMOS Technology ............................................................................... 1-2Military Overview ....................................................................................... 1-3Product Selection Guide ................................................................................. 1-5Military Product Selection Guide .......................................................................... 1-7Ordering Information .................................................................................... 1-9Product Line Cross Reference ............................................................................ 1-10Static RAMs (Random Access Memory)Device NumberCY2147CY2148CY21L48CY2149CY21L49CY6116CY7C122CY7C123CY7C128CY7C130CY7C140CY7C132CY7C142CY7C147CY7C148CY7C149CY7C150CY7C152CY7C158CY7C159CY7C161CY7C162CY7C164CY7C166CY7C167CY7C168CY7C169CY7C170CY7C171CY7CI72CY7C185CY7C186CY7C187CY7C189CY7C190CY7C191CY7CI92CY7C194CY7C196CY7C197CY7C198CY7C199CY74S189CY27LS03CY27S03CY27S07CY93422ACY93L422ACY93422CY93L422Description4096 x 1 Static RAM ...................................................... 2-11024 x 4 Static RAM ...................................................... 2-61024 x 4 Static RAM, Low Power ............................................ 2-61024 x 4 Static RAM ...................................................... 2-61024 x 4 Static RAM, Low Power ............................................ 2-62048 x 8 Static RAM ..................................................... 2-12256 x 4 Static RAM Separate 1/0 .......................................... 2-19256 x 4 Static RAM Separate 1/0 .......................................... 2-262048 x 8 Static RAM ..................................................... 2-331024 x 8 Dual Port Static RAM ............................................ 2-401024 x 8 Dual Port Static RAM ............................................ 2-402048 x 8 Dual Port Static RAM ............................................ 2-502048 x 8 Dual Port Static RAM ............................................ 2-504096 x 1 Static RAM ..................................................... 2-601024 x 4 Static RAM ..................................................... 2-671024 x 4 Static RAM ..................................................... 2-671024 x 4 Static RA~.1 Separate I/O ....... , ............................ , .... . 2-i4Self-Timed Cache Static RAM ................................................ 2-82Self-Timed Pipelined Static RAM ............................................. 2-83Self-Timed Pipelined Static RAM ............................................. 2-8316,384 x 4 Static RAM Separate 1/0 . ......................................... 2-8416,384 x 4 Static RAM Separate 1/0 .......................................... 2-8416,384 x 4 Static RAM ..................................................... 2-9216,384 x 4 Static RAM with Output Enable .................................... 2-9216,384 x 1 Static RAM .................................................... 2-1014096 x 4 Static RAM .................................................... 2-1084096 x 4 Static RAM .................................................... 2-1084096 x 4 Static RAM with Output Enable ................................... 2-1154096 x 4 Static RAM Separate 1/0 ......................................... 2-1214096 x 4 Static RAM Separate 1/0 . ........................................ 2-1218192 x 8 Static RAM .................................................... 2-1288192 x 8 Static RAM .................................................... 2-12865,536 x 1 Static RAM .................................................... 2-13716 x 4 Static RAM .................................................... 2-14616 x 4 Static RAM .................................................... 2-14665,536 x 4 Static RAM Separate I/O ......................................... 2-153·65,536 x 4 Static RAM Separate 1/0 . ........................................ 2-15365,536 x 4 Static RAM .................................................... 2-159·65,536 x 4 Static RAM with Output Enable ................................... 2-159262,144 x 1 Static RAM .................................................... 2-16532,768 x 8 Static RAM .................................................... 2-17132,768 x 8 Static RAM .................................................... 2-17116 x 4 Static RAM .................................................... 2-17716 x 4 Static RAM .................................................... 2-177 I16 x 4 Static RAM .................................................... 2-17716 x 4 Static RAM .................................................... 2-177 .256 x 4 Static RAM Separate 1/0 . ........................................ 2-183256 x 4 Static RAM Separate 1/0 ......................................... 2-183256 x 4 Static RAM Separate 1/0 ......................................... 2-183256 x 4 Static RAM Separate 1/0 ......................................... 2-183

~ Table of Contents (Continued)~~~ucr~==================================================================PROMs (Programmable Read Only Memory)Page NumberIntroduction to PROMs .................................................................................. 3-1Device NumberDescriptionCY7C225 512 x 8 Registered PROM .................................................. 3-4CY7C235 1024 x 8 Registered PROM ................................................. 3-15CY7C245 2048 x 8 Reprogrammab1e Registered PROM .................................. 3-26CY7C245A 2048 x 8 Reprogrammab1e Registered PROM .................................. 3-38CY7C251 16,384 x 8 Reprogrammable Power Switched PROM ............................. 3-50CY7C254 16,384 x 8 Reprogrammable PROM ........................................... 3-50CY7C261 8192 x 8 Reprogrammable Power Switched PROM ............................. 3-60CY7C263 8192 x 8 Reprogrammable PROM ........................................... 3-60CY7C264 8192 x 8 Reprogrammable PROM ........................................... 3-60CY7C268 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-71CY7C269 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-71CY7C271 32,768 x 8 Reprogrammable Power Switched PROM ............................. 3-84CY7C281 1024 x 8 PROM .......................................................... 3-90CY7C282 1024 x 8 PROM .......................................................... 3-90CY7C291 2048 x 8 Reprogrammable PROM ........................................... 3-99CY7C291A 2048 x 8 Reprogrammable PROM .......................................... 3-108CY7C292 2048 x 8 PROM .......................................................... 3-99CY7C292A 2048 x 8 Reprogrammable PROM .......................................... 3-108CY7C293A 2048 x 8 Reprogrammable PROM .......................................... 3-108PROM Programming Information ....................................................................... 3-117EPLDs (Eraseable Programmable Logic Devices)Introduction to EPLDs .................................................................................. 4-1Device NumberDescriptionPAL C 20 Series 16L8, 16R8, 16R6, 16R4 Reprogrammable CMOS PAL@ Device ................... .4-7PLD C 20G 10 CMOS Generic 24 Pin Reprogrammable PLD ................................... 4-25PLD C 20RAIO Reprogrammable Asynchronous CMOS Programmable Logic Device ............... .4-44PAL C 22VIOReprogrammable CMOS PAL Device .......................................... ±2l---CY7C330 Synchronous State Machine .................................................. 4-70CY7C331 Asynchronous Registered EPLD .............................................. 4-79CY7C332 Combinatorial Registered EPLD .............................................. 4-87PLD Programming Information .......................................................................... 4-92LOGICDevice NumberCY2901CCY2909ACY2911ACY2910ACY3341CY7C401CY7C402CY7C403CY7C404CY7C408CY7C409CY7C420CY7C421CY7C424CY7C425CY7C428CY7C429CY7C510CY7C516PAL® is a registered trademark of Monolithic Memories Inc.DescriptionCMOS 4-Bit Slice ............................................................ 5-1CMOS Microprogram Sequencer ............................................... 5-9CMOS Microprogram Sequencer ............................................... 5-9CMOS Microprogram Controller .............................................. 5-1464 x 4 FIFO Serial Memory .................................................. 5-19Cascadeable 64 x 4 FIFO .................................................... 5-24Cascadeable 64 x 5 FIFO .................................................... 5-24Cascadeable 64 x 4 FIFO with Output Enable ................................... 5-24Cascadeable 64 x 5 FIFO with Output Enable ................................... 5-24Cascadeable 64 x 8 FIFO with Output Enable ................................... 5-34Cascadeable 64 x 9 FIFO .................................................... 5-34Cascadeable 512 x 9 FIFO ................................................... 5-48Cascadeable 512 x 9 FIFO ................................................... 5-48Cascadeable 1024 x 9 FIFO .................................................. 5-48Cascadeable 1024 x 9 FIFO .................................................. 5-48Cascadeable 2048 x 9 FIFO .................................................. 5-48Cascadeable 2048 x 9 FIFO .................................................. 5-4816 x 16 Multiplier Accumulator ............................................... 5-5916 x 16 Multiplier ........................................................... 5-71

~CYPRFSSTable of Contents (Continued)~~~OO~UaoR================================================~==~==========~LOGIC (Continued)Device NumberCY7C517CY7C901CY7C909CY7C911CY7C91OCY7C9101CY7C9116CY7C9117DescriptionPage Number16 x 16 Multiplier ........................................................... 5-71CMOS 4-Bit Slice ........................................................... 5-83Microprogram Sequencer .................................................... 5-98Microprogram Sequencer .................................................... 5-98Microprogram Controller ................................................... 5-109CMOS 16-Bit Slice ......................................................... 5-120CMOS 16-Bit Microprogrammed ALU ........................................ 5-137CMOS 16-Bit Microprogrammed ALU ........................................ 5-137RISCIntroduction to RISC .................................................................................... 6-1Device Number DescriptionCY7C60132-Bit RISC Integer Unit ..................................................... 6-5CY7C608Floating Point Controller .................................................... 6-11BridgeMOSBridgeMOS Overview ................................................................................... 7-1Device Number~escriptionCY8C150CY8C245"""'CTO 1'""'1 ..... n1\....~ O\....~:11CY8C901CY8C909CY8C911QuickProDevice NumberCY3000BridgeMOS 1024 x 4 Static RAM Separate I/O ................................... 7-1BridgeMOS 2048 x 8 Reprogrammable Registered PROM .......................... 7-1BridgeM:OS Reprogrammable 2048 x 8 PROM ................................... 7-1BridgeMOS 4-Bit Slice ........................................................ 7-1BridgeMOS Microprogram Sequencer ........................................... 7-1BridgeMOS Microprogram Sequencer ........................................... 7-1DescriptionCombined PROM, PLD, and EPROM Programmer ............................... 8-1Quality and ReliabilityQuality, Reliability and Process Flows ...................................................................... 9-1Application BriefsRAM Input and Output Characteristics .................................................................... 10-174F189 Application Brief. ........................................................... , ................... 10-8Programmable Logic Device Application Brief ............................................................. 10-10PAL C 16R6 GCR Encoder/Decoder .................................................................... 10-22Understanding FIFOs ................................................................................. 10-39Interfacing to the FIFOs ............................................................................... 10-51Power Characteristics of Cypress Products ................................................................ 10-53System Design Considerations when Using Cypress CMOS Circuits ............................................ 1O-6qMicrocoded Systems Application Brief. ................................................................... 10-78Introduction to Diagnostic PROMs ...................................................................... 10-81CY7C330 Asynchronous SCSI Controller ................................................................. 10-87PackagesThermal Management and Component Reliability ............................................................ 11-1Package Diagrams ..................................................................................... 11-6

~ Numeric Device Index~~~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==Device Number DescriptionPage Number2147214821L48214921L4927LS0327S0327S072901C2909A2910A2911A30003341611674F18974S1897C1227C1237C1287C1307C1327C1407C1427C1477C1487C1497C1507C1527C1587C1597C1617C1627C1647C1667C1677C1687C1697C1707C1717CI727C1857C1867C1877C1897C1907C1917C1927C1947C1967C1977C1987C1994096 x 1 Static RAM ...................................................... 2-11024 x 4 Static RAM ...................................................... 2-61024 x 4 Static RAM, Low Power ............................................ 2-61024 x 4 Static RAM ...................................................... 2-61024 x 4 Static RAM, Low Power ............................................ 2-616 x 4 Static RAM .................................................... 2-17716 x 4 Static RAM .................................................... 2-17716 x 4 Static RAM .................................................... 2-177CMOS 4-Bit Slice ............................................................ 5-1CMOS Microprogram Sequencer ............................................... 5-9CMOS Microprogram Controller .............................................. 5-14CMOS Microprogram Sequencer ............................................... 5-9Combined PROM, PLD, and EPROM Programmer ............................... 8-164 x 4 FIFO Serial Memory .............................................. 5-192048 x 8 Static RAM ..................................................... 2-1216 x 4 Static RAM ..................................................... 10-816 x 4 Static RAM .................................................... 2-177256 x 4 Static RAM Separate I/O .......................................... 2-19256 x 4 Static RAM Separate I/O .......................................... 2-262048 x 8 Static RAM ..................................................... 2-331024 x 8 Dual Port Static RAM ............................................ 2-402048 x 8 Dual Port Static RAM ............................................ 2-501024 x 8 Dual Port Static RAM ............................................ 2-402048 x 8 Dual Port Static RAM ............................................ 2-504096 x 1 Static RAM ..................................................... 2-601024 x 4 Static RAM ..................................................... 2-671024 x 4 Static RAM ..................................................... 2-671024 x 4 Static RAM Separate I/O .......................................... 2-74Self-Timed Cache Static RAM ................................................ 2-82Self-Timed Pipelined Static RAM ............................................. 2-83Self-Timed Pipelined Static RAM ............................................. 2-8316,384 x 4 Static RAM Separate I/O .......................................... 2-8416,384 x 4 Static RAM Separate I/O .......................................... 2-8416,384 x 4 Static RAM ..................................................... 2-9216,384 x 4 Static RAM ..................................................... 2-9216,384 x 1 Static RAM .................................................... 2-1014096 x 4 Static RAM .................................................... 2-1084096 x 4 Static RAM .................................................... 2-1084096 x 4 Static RAM with Output Enable ................................... 2-1154096 x 4 Static RAM Separate I/O ......................................... 2-1214096 x 4 Static RAM Separate I/O ......................................... 2- t 218192 x 8 Static RAM .................................................... 2-1288192 x 8 Static RAM .................................................... 2-12865,536 x 1 Static RAM .................................................... 2-13716 x 4 Static RAM ..................................................... 2-14616 x 4 Static RAM .................................................... 2-14665,536 x 4 Static RAM Separate I/O ......................................... 2-15365,536 x 4 Static RAM Separate I/O ......................................... 2-15365,536 x 4 Static RAM .................................................... 2-15965,536 x 4 Static RAM with Output Enable ................................... 2-159262,144 x 1 Static RAM .................................................... 2-16532,768 x 8 Static RAM .................................................... 2-17132,768 x 8 Static RAM .................................................... 2-171

~CYPRESSNumeric Device Index (Continued)~~~OO~UaoR==================================================================Device Number Description Page Number7C225 512 x 8 Registered PROM .................................................. 3-47C235 1024 x 8 Registered PROM ................................................. 3-157C245 2048 x 8 Reprogrammable Registered PROM .................................. 3-267C245A 2048 x 8 Reprogrammable Registered PROM .................................. 3-387C251 16,384 x 8 Reprogrammable Power Switched PROM ............................. 3-507C254 16,384 x 8 Reprogrammable PROM ................. , ......................... 3-507C261 8192 x 8 Reprogrammable Power Switched PROM ............................. 3-607C263 8192 x 8 Reprogrammable PROM ........................................... 3-607C264 8192 x 8 Reprogrammable PROM ........................................... 3-607C268 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-717C269 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-717C271 32,768 x 8 Reprogrammable Power Switched PROM ... , ......................... 3-847C281 1024 x 8 PROM .......................................................... 3-907C282 1024 x 8 PROM .......................................................... 3-907C291 2048 x 8 Reprogrammable PROM ........................................... 3-997C291A 2048 x 8 Reprogrammable PROM .......................................... 3-1087C292 2048 x 8 PROM .......................................................... 3-997C292A 2048 x 8 Reprogrammable PROM .......................................... 3-1087C293A 2048 x 8 Reprogrammable PROM .......................................... 3-1087C330 Synchronous State Machine Reprogrammable PLD ............................... 4-707C331 Asynchronous Registered EPLD .............................................. 4-797C332 Combinatorial Registered EPLD .............................................. 4-877C401 Cascadeable 64 x 4 FIFO .................................................... 5-247C402 Cascadeable 64 x 5 FIFO .................................................... 5-247C403 Cascadeable 64 x 4 FIFO with Output Enable ................................... 5-247C404 Cascadeable 64 x 5 FIFO with Output Enable ................................... 5-247C408 Cascadeable 64 x 8 FIFO with Output Enable ................................... 5-347C409 Cascadeable 64 x 9 FIFO .................................................... 5-34iC420 Cascadeabie 512 x 9 FIFO ................................................... 5-487C421 Cascadeable 512 x 9 FIFO ................................................... 5-487C424 Cascadeable 1024 x 9 FIFO .................................................. 5-487C425 Cascadeable 1024 x 9 FIFO .................................................. 5-487C428 Cascadeable 2048 x 9 FIFO .................................................. 5-487C429 Cascadeable 2048 x 9 FIFO .................................................. 5-487C51O 16 x 16 Multiplier Accumulator ............................................... 5-597C516 16x 16 Multiplier ........................................................... 5-717C517 16 x 16 Multiplier ........................................................... 5-717C901 CMOS Four-Bit Slice ........................................................ 5-837C909 Microprogram Sequencer .................................................... 5-987C91O Microprogram Controller ................................................... 5-1097C911 Microprogram Sequencer .................................................... 5-987C9101 CMOS 16-Bit Slice ......................................................... 5-1207C9116 CMOS 16-Bit Microprogrammed ALU ....................... , ................ 5-1377C9117 CMOS 16-Bit Microprogrammed ALU ........................................ 5-1378C 150 BridgeMOS 1024 x 4 Static RAM Separate I/O ................................... 7-18C245 BridgeMOS 2048 x 8 Reprogrammable Registered PROM .......................... 7-18C291 BridgeMOS Reprogrammable 2048 x 8 PROM ................................... 7-18C901 BridgeMOS Four-Bit Slice .................................................... 7-18C909 BridgeMOS Microprogram Sequencer ........................................... 7-18C911 BridgeMOS Microprogram Sequencer ....... '" ................................. 7-193422 256 x 4 Static RAM Separate I/O ............................................ 2-18393422A 256 x 4 Static RAM Separate I/O ............................................ 2-18393L422 256 x 4 Static RAM Separate I/O ............................................ 2-18393L422A 256 x 4 Static RAM Separate I/O ............................................ 2-183PAL C 20 Series Reprogrammable CMOS PAL Device ........................................... 4-716L8 ............................................................................................... 4-716R4 ............................................................................................... 4-716R6 ...... " ....................................................................................... 4-716R8 .............. " ............................................................................... 4-7PLD C 20G 10 CMOS Generic 24 Pin Reprogrammable PLD ................................... 4-25PLD C 20RAlO Reprogrammable Asynchronous CMOS Programmable Logic Device ................ 4-44PAL C 22VlO Reprogrammable CMOS PAL Device ......................................... .4-53

PRODUCTINFORMATIONSTATIC RAMS,.PROMS•EPLDS ,~.•LOGICRISCBRIDGEMOSQUICKPROQUALITY ANDRELIABILITYAPPLICATION BRIEFSPACKAGESIIIiiiB

$i~Section Contents~. ~~UcrOR~======================================================~~~~~~~General Product InformationPage NumberCypress Semiconductor Background ....................................................................... 1-1Cypress CMOS Technology ............................................................................... 1-2Military Overview ....................................................................................... 1-3Product Selection Guide ................................................................................. 1-5Military Product Selection Guide .......................................................................... 1-7Ordering Information .................................................................................... 1-9Product Line Cross Reference ............................................................................ 1-10

Cypress Semiconductor BackgroundCypress Semiconductor was founded in April of 1983, becamea public company in May 1986, and has establisheditself as a leader in high performance CMOS products. TheCypress CMOS product line is targeted to replace slowerbipolar and NMOS products with higher reliability, highspeed and low power. The initial process employed 1.2 microngeometries. Cypress has now placed into production asubmicron (0.8 micron) process, further enhancing densityand performance at manageable power levels.Cypress products fall into three families: High Speed StaticRAMs, Programmable Products, and Logic. Members ofthe Static RAM family include devices in densities of 64bits to 64K bits and performance from 7 to 35 ns. Thevarious organizations from 16 x 4, 256 x 4 through 64K x1, 8K x 8, and 16K x 4 provide field applications in largemainframes, high speed controllers, communications, andgraphics display.Cypress Programmable Products consist of high speedCMOS PROMs and Eraseable Programmable Logic Devices(EPLDs), both employing an EPROM programmingelement. Like the High Speed Static RAM family, theseproducts are the natural choice to replace older devices,manufactured in bipolar technology, because they providesuperior performance at one half of the power consumption.Densities range from 4K bits to 256K in byte wideorganization. To support new programmable products Cypressintroduced the QuickPro programming system(CY3000). A single, IBM PC compatible board is availableto program all Cypress PLDs and PROMs. The programmingis updated via floppy disk, thereby allowing for quicksupport from Cypress Semiconductor on new products.Logic products include a 16-bit slice, the CY7C9101, andsupport devices, as well as a family of FIFOs that rangefrom 64 x 4 to 2048 x 9. FlFOs provide the interface betweendigital information paths of widely varying speeds.This allows the information source to operate at its ownintrinsic speed while the results may be processed or distributedat a speed commensurate with need.Cypress' semiconductors are "Made in USA". Situated inCalifornia's Silicon Valley and Round Rock (Austin) Texas,Cypress houses R&D, design, wafer fabrication, assembly,and administration. The facilities are designed to themost demanding technical and environmental specificationsin the industry. At the Texas Facility the entire waferfabrication area is specified to be a class 1 environment.This means that the ambient air has less than 1 particulateof greater than 0.2 microns in diameter per cubic foot ofair. Other environmental considerations are carefully insured:temperature is controlled to a ± 0.2 degree Fahrenheittolerance; filtered air is completely exchanged > 10times each minute throughout the fab; critical equipment issituated on isolated slabs to minimize vibration.Attention to assembly is just as critical. Assembly is donein a clean room until the silicon die is sealed in a package.Lead frames are handled in carriers or cassettes throughthe entire operation. Automated robots remove and replaceparts into cassettes. Using sophisticated automated equipment,parts are assembled and tested in less than five days.The Cypress assembly line is the most flexible, automatedline in the United States.The Cypress motto has always been "only the best". Thebest facilities, the best equipment, the best employees ...all striving to make the best CMOS product. Cypress hasgrown very quickly to become "the best".II1-1

~~~ =====================================================================Cypress CMOS TechnologyIn the last decade, there has been a tremendous need forhigh performance semiconductor products manufacturedwith a balance of SPEED, RELIABILITY, and POWER.Cypress Semiconductor has overcome the classically heldperceptions that CMOS is a moderate performance technology.That places its product lines ahead of its bipolarcompetitors in all three areas.Cypress initially introduced a 1.2 micron "N" well technologywith double layer poly, and a single layer metal.The process employs lightly doped extensions of the heavilydoped source and drain regions for both "N" and "P"channel transistors for significant improvement in gate delays.Further improvements in performance, through theuse of substrate bias techniques, have added the benefit ofeliminating the input and output latchup characteristics associatedwith the older CMOS technologies.Cypress pushed process development to new limits in thearea of PROMs (Programmable Read Only Memory) andEPLDs (Eraseable Programmable Logic Devices). BothPROMs and EPLDs have existed since the early 1970s in abipolar process which employed various fuse technologiesand was the only viable high speed non-volatile processavailable. Cypress PROMs and EPLDs use EPROM technology,which has also been in use in MOS (Metal OxideSilicon) also since the early 1970s. EPROM technology hastraditionally emphasized density advantages, while forsakingperformance. Through improved technology, Cypresshas produced the first high performance CMOS PROMsand EPLDs, replacing their bipolar counterparts.Cypress uses a differential memory cell and sense amplifiertechnique in lower density devices. High density devices(64K or larger), employ a single-ended cell and sense amplifiertechnique.To maintain our leadership position in CMOS Technology,Cypress has introduced a sub-micron technology into production.This process reduces the channel length from thecurrent 1.2 microns to 0.8 microns. This sub-micron breakthroughmakes Cypress' CMOS one of the most advancedproduction processes in the world.To further enhance the technology from the reliability direction,improvements have been incorporated in the processand design, minimizing electrostatic discharge and inputsignal clipping problems.Finally, although not a requirement in the high performancearena, CMOS technology substantially reduces thepower consumption for any device. This improves reliabilityby allowing the device to operate at a lower die temperature.Now higher levels of integration are possible withouttrading performance for power. For instance, devices maynow be delivered in plastic packages, without any impacton reliability.While addressing the performance issues of CMOS technology,Cypress has not ignored the quality and reliabilityaspects of technology development. Rather, the traditionalfailure mechanisms of electrostatic discharge (ESD) andlatchup have been addressed and solved through processand design technology innovation.ESD-induced failure has been a generic problem for manyhigh performance MOS and bipolar products. Although inits earliest years MOS technology experienced oxide reliabilityfailures, this problem has largely been eliminatedthrough improved oxide growth techniques and a betterunderstanding of the ESD problem. The effort to adequatelyprotect against ESD failures is perturbed by circuit delaysassociated with ESD protection circuits. Focusing onthese constraints, Cypress has developed ESD protectioncircuitry specific to 1.2 and 0.8 micron CMOS processtechnology. Cypress products are designed to withstandvoltage and energy levels in excess of 2000 volts and0.4 milli-joules, more than twice the energy level specifiedby MIL STD 883C.Latchup. a traditional problem with CMOS technologics,has been eliminated through the use of substrate bias generationtechniques, the elimination of the "P" MOS pullupsin the output drivers, the use of guardring structures,and care in the physical layout of the products.Cypress has also developed additional process innovationsand enhancements: the use of multi-layer metal interconnections,advanced metal deposition techniques, silicides,exclusive use of plasma for etching and ashing processsteps, and 100% stepper technology with the world's mostadvanced equipment. The drive to maintain process technologyleadership has not stopped with the 0.8 micron devices.Cypress is developing fine line geometries beyondthis to insure technology leadership in the next decade.The Cypress CMOS technology has been carefully designed,creating products that are "only the best" in highspeed, excellent reliability, and low power.1-2

~ Military Overview~~~NDUcrOR =====================================================================IntroductionSuccess at any endeavor requires a high level of dedicationto the task. Cypress Semiconductor has demonstrated itsdedication through its corporate commitment to supportthe military marketplace. The commitment starts withproduct design. All products are designed on our state-ofthe-artCMOS processes and they must meet the full - 55to + 125 degree C operational criteria for military use. Thecommitment continues with the 1986 DESC certificationof our automated U.S. facility in San Jose, California. Thecommitment shows in our dedication to meet and exceedthe stringent quality and reliability requirements of MIL­STD-883 and MIL-M-38510. It shows in Cypress' participationin each of the military processing programs: 883C­Compliant, SMD (Standard Military Drawing) and JAN.Finally, our commitment shows in our leadership positionin special packages for military use.Product DesignEvery Cypress product is designed to meet or exceed thefull temperature and functional requirements of militaryproduct. This means that Cypress builds military productas a matter of course, rather than as an accidental benefitof favorable test yield. Designs are being carried out on ourindustry-leading 0.8 micron CMOS process. Cypress is ableto offer a family of products that are industry leaders indensity, low operating and standby current and high speed.In addition, our technology results in products with verysmall manufacturable die sizes that will fit into the LCC'sand flatpacks so often used on military programs.DESC-Certified FacilityOn May 8, 1986, the Cypress facility at 3901 North FirstStreet in San Jose, California was certified by DESC for theproduction of JAN Level B CMOS Microcircuits (copyattached). This certification not only provided Cypresswith the ability to qualify product for JAN use, but it alsobenefitted all of our customers by acknowledging that ourSan Jose facility has the necessary documentation and proceduresin place to manufacture product to the most stringentof quality and reliability requirements. Our wafer fabricationfacilities are Class 10 (San Jose) and Class 1(Round Rock, TX) manufacturing environments and ourassembly facility is also a clean room. In addition, ourhighly automated assembly facility is entirely located in theU.S.A. and is capable of handling virtually any hermeticpackage configuration.Data Sheet DocumentationEvery Cypress final data sheet is a corporate documentwith a revision history. The document number and revisionappears on each final data sheet. Cypress maintains a listingof all data sheet documentation and a copy is availableto customers upon request. This gives a customer the abilityto verify the current status of any data sheet and it alsogives that customer the ability to obtain updated specificationsas required.Every final data sheet also contains detailed Group A subgrouptesting information. Each of the specified parametersthat are tested at Group A are listed in a table at the end ofeach final data sheet, with a notation as to which specificGroup A test subgroups apply.Assembly Traceability CodeCypress Semiconductor marks an assembly traceabilitycode on every military package that is large enough to containthe code. The A TC automatically provides traceabilityfor that product to the individual wafer lot. This uniquecode provides Cypress with the ability to determine whichoperators and equipment were used in the manufacture ofthat product from start to finish.Quality and ReliabilityMIL-STD-883 and MIL-M-38510 spell out the toughest ofquality and reliability standards for military products. Cypressproducts meet all of these requirements and more.Our in-house quality and reliability programs are being updatedregularly with tighter and tighter objectives. Pleaserefer to the chapter on Quality, Reliability and ProcessFlows for further details.Military Product OfferingsCypress offers three different levels of processing for militaryproduct.First, all Cypress products are available with processing infull compliance with MIL-STD-883, Revision C.Secondly, selected products are available to the SMD(Standard Military Drawing) program supervised byDESC. These products are not only fully 883C-compliantbut they are also screened to the electrical requirements ofthe applicable military drawing.Third, selected products are available as JAN devices.These products are processed in full accordance with MIL­M-38510 and they are screened to the electrical requirementsof the applicable JAN slash sheet.Product PackagingAll packages for military product are hermetic. A look atthe package appendix in the back of this data book willgive the reader an appreciation of the variety of packagesoffered. Included are cerdips, windowed cerdips, leadlesschip carriers (LCC's), leadless chip carriers with windowsfor reprogrammable products, cerpack, windowed cerpak,bottom-brazed flatpacks and pin grid arrays. As indicatedabove, all of these packages are assembled in the U.S. inour highly automated San Jose plant.SummaryCypress Semiconductor is committed to the support of themilitary marketplace. Our commitment is demonstrated byour product designs, our DESC-certified facility, our documentationand traceability, our quality and reliability programs,our support of all levels of military processing andby our leadership in special packaging.IIAssembly Traceability Code is a trademark of Cypress Semiconductor Corporation.1-3

~> 1(f(lS(.... ~ ClllEI ~ 1 ,\1M 86.~.J.~~rCOMMANDER, ~DEFENSE ELECTRONICS SUPPLY CENTER"g8~ . ~..,~.f""f'-= ....~o....~()oS.s·s=e0105-1

~ Product Selection Guide~~~NDUcrOR=====================================================================Size Organization Pins Part Number Speed (ns)SRAMs 64 16 x 4--Inverting 16 CY7CI89 tAA = 15, 2564 16 x 4--Non-Inverting 16 CY7CI90 tAA = 15,2564 16 x 4--Inverting 16 CY74S189 tAA =3564 16 x 4--Inverting 16 CY27S03A tAA =25,3564 16 x 4--Non-Inverting 16 CY27S07A tAA =25,3564 16 x 4--lnv. Low Power 16 CY27LS03M tAA =65IK 256 x4 22 CY7CI22 tAA = 15, 25, 35IK 256 x4 24S CY7CI23 tAA = 7, 12, 15IK 256 x4 22 CY9122/91L22 tAA = 25, 35,45IK 256x 4 22 CY93422A/93L422A tAA = 35, 45, 604K 4096 x I-CS Power Down 18 CY7CI47 tAA = 25, 35, 454K 4096 x I-CS Power Down 18 CY2 147/2 IL47 tAA = 35, 45, 554K 1024 x 4--CS Power Down 18 CY7CI48 tAA = 25, 35,454K 1024 x 4--CS Power Down 18 CY2148/21L48 tAA = 35, 45, 554K 1024 x 4 18 CY7CI49 tAA = 25, 35, 454K 1024 x 4 18 CY2 149/21 L49 tAA = 35, 45, 554K 1024 x +-Separate I/O, Reset 24S CY7CI50 tAA = 12, 15,25,358K 1024 x 8-Dual Port 48 CY7C130 tAA = 25, 35,45, 558K 1024 x 8-Dual Port (Slave) 48 CY7CI40 tAA = 25, 35,45, 5516K 2048 x 8-CS Power Down 24S CY7C128 tAA = 25, 35, 45, 5516K 2048 x 8-CS Power Down 24 CY6116 tAA = 35, 45, 5516K 16384 x I-CS Power Down 20 CY7CI67/L tAA = 25, 35,4516K 4096 x 4-CS Power Down 20 CY7CI68/L tAA = 25, 35, 4516K 4096 x 4 20 CY7CI69/L tAA = 25, 35,4016K 4096 x 4--0utput Enable 22S CY7CI70 tAA = 25, 35,4516K 4096 x 4--Separate I/O 24S CY7C171/L tAA = 25, 35,4516K 4096 x 4--Separate I/O 24S CY7C172/L tAA = 25, 35,4516K 2048 x 8-Dual Port 48 CY7C132 tAA = 25, 35,45, 5516K 2048 x 8-Dual Port (Slave) 48 CY7CI42 tAA = 25, 35,45, 5564K 8192 x 8-CS Power Down 28S CY7CI85/L tAA = 25, 35, 45, 5564K 8192 x 8-CS Power Down 28 CY7CI86/L tAA = 25, 35,45, 5564K 16384 x 4-CS Power Down 22S CY7CI64/L tAA = 25, 35, 4564K 16384 x 4--0utput Enable 24S CY7CI66/L tAA = 25, 35,4564K 16384 x 4--Separate I/O 28S CY7CI61/L tAA = 25, 35,4564K 16384 x +-Separate I/O 28S CY7CI62/L tAA = 25, 35,4564K 16384 x 4--Self-Timed Cache RAM 28S CY7CI52 TBD64K 16384 x 4--Self-Timed Pipeline RAM 28S CY7CI58 TBD64K 16384 x +-Self-Timed Pipeline RAM 28S CY7CI59 TBD64K 65536 x I-CS Power Down 22S CY7CI87/L tAA = 25, 35, 45256K 32768 x 8-CS Power Down 28 CY7CI98 tAA = 35, 45, 55256K 32768 x 8-CS Power Down 28S CY7CI99 tAA = 35, 45, 55256K 65536 x 4-CS Power Down 24S CY7CI94 tAA = 25, 35, 45256K 65536 x 4-CS Power Down With OE 28S CY7CI96 tAA = 25, 35, 45256K 65536 x 4--Separate I/O 28S CY7CI91 tAA = 25, 35,45256K 65536 x 4--Separate I/O 28S CY7CI92 tAA = 25, 35,45256K 262144 x I-CS Power Down 24S CY7CI97 tAA = 25, 35, 45PROMs 4K 512 x 8-Registered 24S CY7C225 tSA/CO = 25/12,30/158K 1024 x 8-Registered 24S CY7C235 tSA/Co=25/12,30/158K 1024 x 8 24S CY7C28I tAA =30,458K 1024 x 8 24 CY7C282 tAA =30,4516K 2048 x 8-Registered 24S CY7C245/L tSA/CO = 25/12,35/1516K 2048 x 8-Registered 24S CY7C245A/L tSA/co= 18/1216K 2048 x 8 24S CY7C291/L tAA =35,5016K 2048 x 8 24S CY7C291A/L tAA = 25, 30, 35, 5016K 2048 x 8 24 CY7C292/L tAA =35,5016K 2048 x 8-CS Power Down 24S CY7C293A/L tAA = 25, 30, 35, 5064K 8192 x 8-CS Power Down 24S CY7C261 tAA = 35, 40, 45, 5564K 8192 x 8 24S CY7C263 tAA = 35, 40, 45, 55Notes:The above specifications are for the commercial temperature range ofO°C to 70°e.Military temperature range (-55°C to + 125°C) product processed to MIL-STD-883 Revision C is also available.Speed and power selections may vary from those above.Commercial grade product is available in plastic, CERDIP, or LCC. Military grade product is available inCERDIP or LCe. PLCC, SOJ, and SOIC packages are available on some products.All power supplies are VCC = 5V ± 10%.m~b~D~m~b~m~m~b~m~F, K and T packages are special order only.IcdIsB/IcCDR(mA@ns)Packages55 @ 25 D,L,P55 @ 25 D,L,P90 @ 35 D,P90@25 D,L,P90@25 D,L,P38 @ 65 D,L60@25 D,L,P,S120@7 D,L,P120@25 D,P80@45 D,P,L80/10 @ 35 D,L,P,S125/25 @ 35 D,P80/10 @ 35 D,L,P,S120/20 @ 35 D,P,S80 @ 35 D,L,P,S120@ 35 D,P90@ 12 D,L,P,S120@25 D,J,L,P120@ 25 D,J,L,P90/20 @ 55 D,L,P,S120/20@45 D,L45/15 @ 25 D,L,P,S70/15 @ 25 D,L,P,S70@25 D,L,P90@45 D,L,P70/10@ 25 D,L,P,S70/10 @ 25 D,L,P,S120 @ 25 D,J,L,P120@ 25 D,J,L,P100/20/1 @ 25 D,L,P, V100/20/1 @ 25 D,P70/20/1 @ 25 D,L,P,V70/20/1 @ 25 D,L,P,V70/20/1 @ 25 D,L,P,V70/20/1 @ 25 D,L,P,VTBDD,L,P,VTBDD,L,P,VTBDD,L,P,V70/20/1 @ 25 D,L,P,V110/20@ 35 D,P110/20 @ 35 D,L,P,V80/20 @ 25 D,L,P,V80/20@ 25 D,L,P,V80/20 @ 25 D,L,P, V80/20 @ 25 D,L,P,V70/20@ 25 D,L,P,V90 D,L,P90 D,L,P90 D,L,P90 D,L,P100,60 D, L,P,Q, W,S60@35 D, L, P, Q, W, S90,60 D, L, P, Q, W, S60@35 D, L, P, Q, W, S90,60 D,P60/15 @ 35 D, L, P, Q, W, S100/30 D, L, P,Q, W,S100 D, L, P, Q, W, SPackage Code:D = CERAMIC DIPF = FLATPAKG = PIN GRID ARRAYJ = PLCCK = CERPAKL = LCCP = PLASTICQ = WINDOWED LCCS = SOICT = WINDOWED CERPAKV = SOJW = WINDOWED CERDIPII1-5

I~ Product Selection Guide (Continued)~~~~u~==================================================================Size Organization Pins Part Number Speed(ns)PROMs 64K 8192 x 8 24 CY7C264 tAA = 35, 40, 45, 5564K 8192 x 8-Registered, Diagnostic 28S CY7C269 tSA/CO = 40/20, 50/2564K 8192 x 8-Registered, Diagnostic 32 CY7C268 tSA/CO = 40/20, 50/25128K 16384 x 8-CS Power Down 28S CY7C25I tAA = 45, 55, 65128K 16384 x 8 28 CY7C254 tAA = 45, 55, 65256K 32768 x 8-CS Power Down 28S CY7C27I tAA = 45,55,65PLDs PALC20 16L8 20 CYPALCI6L8/L tpo=20PALC20 16R8 20 CYPALCI 6R8/L tS/CO= 15/12PALC20 16R6 20 CYPALCI 6R6/L tpO/S/CO = 20/20/15PALC20 16R4 20 CYPALCI 6R4/L tpO/S/CO = 20/20/15PLDC24 22VIO-Macro Cell 24S CYPALC22VIO/L tpo/S/CO= 25/15/15PLDC24 22VIO-Macro Cell 24S CYPALC22VIO-I5 tpO/S/CO= 15/12/10PLDC24 200 I O-Generic 24S CYPLDC200 10 tpO/S/CO = 25/15/15PLDC24 200 IO-Generic 24S CYPLDC20010-15 tpO/S/CO= 15/12/10PLDC24 20RA IO-Asynchronous 24S CYPLDC20RAIO tpO/S/CO = 20/10/20PLDC28 7C330-State Machine 28S CY7C330 50, 40, 33, 28 MHzPLDC28 7C33 I-Asynchronous 28S CY7C33I 25, 30, 35, 40PLDC28 7C332-Combinatorial 28S CY7C332 20, 25, 30, 35FIFOs 256 64 x 4-Cascadeable 16 CY3341 1.2,2MHz256 64 x 4-Cascadeable 16 CY7C401 5,1O,15MHz256 64 x 4-Cascadeable/OE 16 CY7C403 10,15,25 MHz320 64 x 5-Cascadeable 18 CY7C402 5,10,15 MHz320 64 x 5-Cascadeable/OE 18 CY7C404 10, 15,25 MHz512 64 x 8-Cascadeable/OE 28S CY7C408 15,25,35 MHz576 64 x 9-Cascadeable 28S CY7C409 15,25,35 MHz4608 512 x 9-Cascadeable 28 CY7C420 30,40,654608 512 x 9-Cascadeable 28S CY7C421 30,40,659216 1024 x 9-Cascadeable 28 CY7C424 30,40,659216 1024 x 9-Cascadeable 28S CY7C425 30,40,6518432 2048 x 9-Cascadeable 28 CY7C428 30,40,6518432 2048 x 9-Cascadeable 28S CY7C429 30,40,65LOGIC 2901-4 Bit Slice 40 CY7C901 tCLK=23,312901-4 Bit Slice 40 CY2901 C4 x 2901-16 Bit Slice 64 CY7C9101 tCLK=30,4O29116 -16 Bit Controller 52 CY7C9116 tCLK = 53,79,10029117 -16 Bit Controller 68 CY7C9117 tcLK=53, 79,1002909-Sequencer 28 CY7C909 tCLK = 30, 402911-Sequencer 20 CY7C911 tCLK= 30, 402909-Sequencer 28 CY2909 A2911-sequencer 20 CY2911 A291O-Controller (17 Word Stack) 40 CY7C91O tCLK = 40, 50, 93291O-Controller (9 Word Stack) 40 CY2910 A16 x 16-Multiplier 64 CY7C516 tMC= 38, 45, 55, 7516 x 16-Multiplier 64 CY7C517 tMC = 38, 45, 55, 7516 x 16-Multiplier/ Accumulator 64 CY7C51O tMC = 45, 55, 65, 75RISC SPARC 32 Bit Integer Unit 208 CY7C601 tCYC = 33, 25 MHzFloating Point Controller 281 CY7C608 tCYC = 33, 25 MHzNotes:The above specifications are for the commercial temperature range of O°C to 70°C.Military temperature range (-SSoC to + 12S°C) product processed to MIL-STD-883 Revision C is also available.Speed and power selections may vary from those above.Commercial grade product is available in plastic, CERDIP, or LCC. Military grade product is available inCERDIP or LCC. PLCC, SOJ, and SOIC packages are available on some products.All power supplies are V CC = SV ± 10%.22S stands for 22-pin 300 mil. 24S stands for 24-pin 300 mil. 28S stands for 28-pin 300 mil.F, K and T packages are special order only.IccIISB(mA@ns)Packages100 D,P100 D,L,P,Q, W,S100 D,L,Q,W100/30 D,L,P,Q, W,S100 D,P100/30 D,L,P,Q, W,S70,45 D, L, P, Q, V, W70,45 D,L,P,Q, V, W70,45 D,L,P,Q, V, W70,45 D, L, P, Q, V, W90,55 D,L,P,Q, W,J90,55 D,L,P,Q, W,J55 D,L,P,Q, W,J70 D,L,P,Q, W,J80 D,L,P,Q, W,J120@50MHz D,L,P,Q, W,J180 D,L,P,Q, W,J120 D,L,P,Q, W,J45 D,P75 D,L,P,V75 D,L,P,V75 D,L,P,V75 D,L,P,V100 D,L,P,V100 D,L,P,V100 D,P100 D,J,L,P, V100 D,P100 D,J,L,P, V100 D,P100 D,J,L,P, V70 D,L,P,J140 D,P60 D,L,P,G,J150 D,L,P,G,J150 L,G, J55 D,L,P,J55 D,L,P,J70 D,P70 D,P100 D,L,P,J170 D,L,P,JlOO@ 10 MHz D,L,P,G,Jl00@IOMHz D,L,P,G,JlOO@ 10 MHz D,L,P,G,J600 GTBDGPackage Code:D = CERAMIC DIPF = FLATPAKG = PIN GRID ARRAYJ = PLCCK = CERPAKL= LCCP = PLASTICQ = WINDOWED LCCS = SOICT = WINDOWEDCERPAKV = SOJW = WINDOWED CERDIPi!IIII1-6

~ Military Product Selection Guide.- ?~~®UcrOR~~~~~~~~~~~~~~~~~~~~~~~~======================~Size Organization Pins Part NumberJAN/SMDNumberSpeed (ns)SRAMs 64 16 x 4-lnverting 16 CY7C189 tAA = 2564 16 x 4-Non-Inverting 16 CY7C190 tAA = 2564 16 x 4-lnverting 16 CY27S03/A tAA = 25,3564 16 x 4-Non-Inverting 16 CY27S07/A tAA = 25,3564 16 x 4-lnverting/Low Power 16 CY27LS03lK 256 x 4 22 CY7C122tAA = 65tAA = 25,35lK 256 x 4 24 CY7C123 tAA = 151K 256 x 4 22 CY9122/91 L22 tAA = 35,45lK 256 x4 22 CY93422A/93U22A tAA = 45, 55, 60, 754K 4K x 1-CS Power Down 18 CY7C1474K 4Kx l-CSPowerDown 18 CY21474K 1K x 4-CS Power Down 18 CY7C1484K lK x 4-CS Power Down 18 CY7C1484K lK x 4-CS Power Down 18 CY21484K lK x 4-CS Power Down 18 CY21484K lKx4 18 CY7C1494K lKx4 18 CY21494K lK x 4-Separate I/O 24 CY7C1508K lK x 8-Dual Port 48 CY7C1308K lK x 8-Dual Port Slave 48 CY7C14O16K 2K x 8-CS Power Down 24 CY7C12816K 2K x 8-CS Power Down 24 CY611616K 16K x 1-CS Power Down 20 CY7C16716K 4K x 4-CS Power Down 20 CY7C16816K 4Kx4 20 CY7C16916K 4K x 4-Output Enable 22 CY7C17016K 4K x 4-Separate I/O 24 CY7C17116K 4K x 4-Separate I/O 24 CY7C17216K 2K x 8-Dua1 Port 48 CY7C13216K 2K x 8-Dual Port Slave 48 CY7C14264K 8K x 8-CS Power Down 28 CY7CI85/L64K 8K x 8-CS Power Down 28 CY7CI86/L64K 16K x 4-Registered/Latched 28 CY7C15264K 16K x 4-Registered/Sep I/O 28 CY7C15864K 16K x 4-Registered/Sep I/O 28 CY7C15964K 16K x 4-CS Power Down 22 CY7CI64/L64K 16K x 4-0utput Enable 24 CY7CI66/L64K 16K x 4-Separate I/O 28 CY7CI61/L64K 16K x 4-Separate I/O 28 CY7CI62/L64K 64K x l-CS Power Down 22 CY7CI87/L256K 32K x 8-CS Power Down 28 CY7C198256K 32K x 8-CS Power Down 28 CY7C199256K .64K x 4-CS Power Down 24 CY7C194256K 64K x 4-CS Power Down 28 CY7C196+ OE/CE2256K 64K x 4-Separate I/O 28 CY7C191256K 64K x 4-Separate I/O 28 CY7CI92256K 256K x l-CS Power Down 24 CY7C197Size Organization Pins Part NumberPROMs 4K 512K x 8-Registered 24 CY7C2258K 1K x 8-Registered 24 CY7C2358K lKx 8 24 CY7C2818K lKx8 24 CY7C28216K 2K x 8-Registered 24 CY7C24516K 2K x 8-Registered 24 CY7C245A16K 2Kx8 24 CY7C29116K 2Kx8 24 CY7C291A16K 2K x 8-CS Power Down 24 CY7C293ANotes:The Cypress facility at 3901 North First Street in San Jose, CA isDESC-certified for JAN class B production.All of the above products are available with processing toMIL-STD-883C at a minimum. Many of these products are also availableeither to SMDs (Standard Military Drawings) or to JAN slashsheets.The speed and power specifications listed above cover the full militarytemperature range. All power supplies are V CC = 5V ± 10%.M38510/289M385 10/289M385 10/2895962-87513M38510/2895962-875138403684036841325962-855255962-855255962-868595962-868595962-86015JAN/SMDNumber5962-885185962-876515962-876515962-875295962-875295962-876505962-87650Package Codes:D = Ceramic DIPF = F1atpackG = Pin Grid ArrayK = CerpackL = LCCQ = Windowed LCCT = Windowed CerpackW = Windowed CERDIPtAA = 35,45tAA = 45,55tAA = 35,45tAA = 35,45tAA = 45,55tAA = 45,55tAA = 35,45tAA = 45,55tAA = 15,25,35tAA = 35,45, 55tAA = 35, 45, 55tAA = 35, 45, 55tAA = 35,45, 55tAA = 35,45tAA = 35,45tAA = 35,40tAA = 35,45tAA = 35,45tAA = 35,45tAA = 35,45, 55tAA = 35, 45, 55tAA = 35, 45, 55tAA = 35,45, 55TBDTBDTBDtAA = 35,45tAA = 35,45tAA = 35,45tAA = 35,45tAA = 35,45tAA = 45,55tAA = 45,55tAA = 35,45tAA = 35,45tAA = 35,45tAA = 35,45tAA = 35,45Speed (ns)tSA/CO = 30/15,35/20,40/25tSA/CO = 30/15,40/20tAA = 45tAA = 45tSAICO = 35/15,45/25tSA/CO = 25/15, 35/20tAA = 35,50tAA = 30, 35, 50tAA = 35,50IcciIsBlIcCDR(mA@ns)70@2570@25l00@ 25l00@ 2538 @ 6590@25150@ 1590@4590@ 55110/10 @ 35140/25 @ 45110/10 @ 35110/10 @ 35140/25 @45140/25 @45110 @ 3514O@ 45l00@ 15120/4O@ 35120/4O@ 35100/20 @ 55130/20 @ 3550/20 @ 4570/20@ 4570@4O120@ 3570@4570@45120/40 @ 35120/40 @ 35100/20/1 @ 45100/20/1 @ 45TBD@TBDTBD@TBDTBD@TBD70/20/1 @ 3570/20/1 @ 3570/20/1 @ 3570/20/1 @ 3570/20/1 @ 35120/20 @45120/20 @4590/20 @ 3590/20 @ 3590/20 @ 3590/20 @ 3580/20 @ 35IcclIsB(mA@ns)120 @ 30/15120@ 30/15120@45120@45120 @ 35/15120 @ 25/15120@ 35120@ 30120/30 @ 35•1-7

~ Military Product Selection Guide (Continued)~~~NDU~ ================================================================~Size Organization PinsPROMs 16K 2Kx8 2416K 2Kx8 2464K 8K x 8-CS Power Down 2464K 8Kx8 2464K 8Kx8 2464K 8K x 8-RegisteredIDiagnostic 2864K 8K x 8-RegisteredIDiagnostic 32128K 16K x 8--CS Power Down 28128K 16Kx8 28256K 32K x 8--CS Power Down 28Size Organization PinsPLDs PALC20 16L8 20PALC20 16R8 20PALC20 16R6 20PALC20 16R4 20PLDC24 22VIO-MacroCeII 24PLDC24 20G IO-Generic 24PLDC24 20RAIO-Asynchronous 24PLDC28 7C330-State Machine 28PLDC28 7C33 I-Asynchronous 28PLDC28 7C332--CombinatoriaI 28Size Organization PinsFIFOs 256 64 x 4--Cascadeable 16256 64 x 4--Cascadeable 16256 64 x 4--Cascadeable/OE 16320 64 x 5--Cascadeable 18320 64 x 5--Cascadeable/OE 18512 64 x 8--Cascadeable/OE 28576 64 x 9-Cascaueabie 2114K 512 x 9--Cascadeable 284K 512 x 9--Cascadeable 289K IK x 9--Cascadeable 289K IK x 9--Cascadeable 2818K 2K x 9--Cascadeable 2818K 2K x 9--Cascadeable 28Size Organization PinsLOGIC 2901-4 Bit Slice 402901-4 Bit Slice 404 x 2901-16 Bit Slice 642909-Sequencer 282911-Sequencer 202909-Sequencer 282911-Sequencer 20,.2910--C0ntroller (17 Word) 402910--C0ntroller (9 Word) 4016-Bit Microprogrammed ALU 5216-Bit Microprogrammed ALU 6832-Bit RISC Processor 208Floating Point Controller 28016 x 16 Multiplier 6416 x 16 Multiplier 6416 x 16 Multiplier/Accumulator 64Notes:The Cypress facility at 3901 North First Street in San Jose, CA isDESC-certified for JAN class B production.All of the above products are available with processing toMIL-STD-883C at a minimum. Many of these products are also availableeither to SMDs (Standard Military Drawings) or to JAN slashsheets.The speed and power specifications listed above cover the full militarytemperature range. All power supplies are V CC = 5V ± 10%.Part NumberJAN/SMDNumberCY7C292 5962-87650CY7C292A 5962-87650CY7C26I 5962-87515CY7C263 5962-87515CY7C264 5962-87515CY7C269CY7C268CY7C25ICY7C254CY7C27IJAN/SMDPart NumberNumberCYPALCI6L8CYPALCI6R8CYPALCI6R6CYPALCI 6R4CYPALC22VIOCYPLDC20G 10CYPLDC20RAIOCY7C330CY7C33ICY7C332JAN/SMDPart NumberNumberCY3341CY7C401 5962-86846CY7C403 5962-86846CY7C402 5962-86846CY7C404 5962-86846CY7C408CY7C409CY7C420CY7C421CY7C424CY7C425CY7C428CY7C429JAN/SMDPart NumberNumberCY7C901CY290lCCY7C9101CY7C909CY7C911CY2909ACY2911ACY7C91O 5962-87708CY29 lOA 5962-87708CY7C9116CY7C9117CY7C601CY7C608CY7C516 5962-87686CY7C517 5962-87686CY7C51OPackage Codes:D = Ceramic DIPF = FlatpackG = Pin Grid ArrayK = CerpackL= LCCQ = Windowed LCCT = Windowed CerpackW = Windowed CERDIPSpeed(ns)tAA = 50tAA = 30, 35, 50tAA = 45,55tAA = 45,55tAA = 45,55tSA/CO = 50/25, 60/25tSA/CO = 50/25, 60/25tAA = 55,65tAA = 55,65tAA = 55,65Speed (ns/MHz)tpo = 20ts/CO = 20/15tpo/S/CO = 20/20/15tpo/S/CO = 20/20/15tpo/s/CO = 20/17/15tpo/s/CO = 20/17/15tpo/su/co = 25/15/254O,28MHztpo/s/co = 30/25/30tICO/ISIIH = 25/5/7Speed (ns/MHz)1.2,2.0MHz1O,I5MHz10, 15,25 MHz1O,I5MHz10, 15,25 MHz15. 25 MHz15,25MHztAA = 30,40,65tAA = 30, 40, 65tAA = 30,40,65tAA = 30,40, 65tAA = 30,40, 65tAA = 30,40, 65Speed(ns)!eLK = 27,32CSpeedtCLK = 35,45tCLK = 30,40tCLK = 30,40A SpeedA Speed!eLK = 46,51, 99A Speed53,79,10053,79,10025 MHz25 MHztMC = 42, 55, 75tMC = 42, 55, 75tMC = 55, 65, 75Icc/ISB(mA@ns)120@50120@30120/30@45120@45120@45lOO@60/25100@ 60/25120/35 @ 55120@55130/40 @ 55Icc(mA @ ns/MHz)70@2070@20/1570 @ 20/20/1570@ 20/20/15100 @ 25/20/2080 @ 30/20/20100 @ 25/15/25150@4OMHz200 @ 30/25/30150@25/5/7IccIIsB(mA @ ns/MHz)6O@2.0MHz9O@ 15 MHz9O@25MHz90@ 15 MHz90@25MHz120 @ 25 ~,fHz120@25MHz120/20@ 30120/20@ 30120/20@ 30120/20@30120/20@30120/20@30Icc(mA@ns)9O@27180@3285 @ 3555@3055@309O@4O90@4O9O@46170@5121O@ 10 MHz21O@ 10 MHzTBD@25MHzTBD@25MHzllO@ 10 MHzllO@ 10 MHzllO@ 10 MHz1-8

Ordering InformationSpecific ordering codes are indicated in the detailed data sheets. In general, the product codes followthe format below:PAL 8c PLDPREFIXi PAL C iPAL CPAL CPLD CCYDEVICE16R816R822V1020G107C330RAM, PROM, FIFO, JJ.PPREFIX DEVICECY i I 7C128CYCYCY7C2457C4047C901SUFFIXi -25 P CL-35 P C-25 W C-25 W C-33 P CSUFFIXi -45 D M B iL-35 P C-25 D M B-23 P CL PROCESSINGB = HI REL MIL STD 883 CFOR MILITARY PRODUCT= LEVEL 2 PROCESSING FOR COMMERCIAL PRODUCTIITEMPERATURE RANGEC = COMMERCIAL (OOC TO 70 0 C)M= MILITARY (-55 0 C TO +125 0 C)---- PACKAGED = CERDIPF = FLATPAKG = PIN GRID ARRAY (PGA)J = PLCCK = CERPAK (GLASS SEALED FLAT PACKAGE)L = LEADLESS CHIP CARRIERP = PLASTICQ = WINDOWED LEADLESS CHIP CARRIERS = SOIC (GULL WING)T = WINDOWED CERPAKV = SOIC (J LEAD)W= WINDOWED CERDIPX = DICE (WAFFLE PACK)i.e. CY7C128-35PC, PALC16R8L-25PC---- SPEED'------ LOW POWER OPTION0018-1Cypress FSCM # 657861-9

~ Product Line Cross Reference~~~~u~==================================================================CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS2147·35C 7C147·35C 29llAM 7C911-40M 7Cl64L-45M 7Cl64L.35M2147·45C 7C147·45C 3341C 334l·2C 7Cl64-25C 7Cl64L·25C2l47-45C 2147·35C 3341M 334l·2M 7Cl64-35C 7Cl64L-35C2147·45M 7C147·45M 334l·2C 7C402·5C 7Cl64-35M 7Cl64L·35M2147·55C 2l47-45C 334l·2C 7C40l·5C+ 7Cl64-45C 7Cl64L-45CCYPRESS7C186·35C7C186-45C7C186·45M7C186·55C7C186·55MCYPRESS7C186L·35C7C186L·45C7C186L·45M7C186L·55C7C186L·55M2147·55M 2l47-45M 54Sl89M 27S03M 7Cl64-45M 7Cl64L-45M2148·35C 7C148·35C 6116-45C 6116·35C 7C166L·35C 7C166L·25C2148·35C 21U8·35C 6116·55C 6116·45C 7C166L-45C 7C166L·35C2148·35M 7C148·35M 6116·55M 6ll6-45M 7C166L-45M 7C166L·35M2l48-45C 2148·35C 74Sl89C 27S03C 7C166·25C 7C166L-25C2148·45C 21U8·45C 7C122·25C 7C122·l5C+ 7C166·35C 7C166L·35C2148·45M 2148·35M 7C122·35C 7C122·25C 7C166·35M 7C166L·35M2l48-45M 7C148·45M 7C122·35M 7C122·25M 7C166-45C 7C166L-45C2148·55C 21U8·55C 7C123·l2C 7C123·7C 7C166·45M 7C166L-45M2148·55C 2148·45C 7C128·35C 7C128·25C 7C167L·35C 7C167L·25C2148·55M 2148·45M 7C128·45C 7Cl28·35C 7C167·25C 7C167L·25C2149·35C 7C149·35C 7C128-45M 7C128·35M+ 7C167·35C 7C167·25C7C187L·35C7C187L·45C7C187L·45M7C187·25C7C187·35C7C187·35M7C187-45C7C187·45M7C189·l8C7C189·25C7C190·l8C7C190·25C7C187L·25C7C187L·35C7C187L·35M7C187L·25C7C187L·35C7C187L·35M7C187L·45C7C187L-45M7C189·l5C7C189·l5C+7C190·l5C7C190-l5C+2149·35C 21U9·35C 7C128·55C 7C128-45C+ 7C167-45C 7C167L·35C2149·35M 7C149·35M 7C128·55M 7C128-45M + 7C167·45M 7C167·35M2149·45C 21U9-45C 7C130·45C 7C130·35C 7C168L·35C 7C168L·25C2l49-45M 7C149·45M 7C130·55C 7C130-45C 7C168·25C 7C168L·25C2149·45M 2149·35M 7C130·55M 7C130-45M 7C168·35C 7C168·25C2149·55C 21U9·55C 7C132·45C 7C132·35C 7C168-45C 7C168L·35C7C225·30C 7C225·25C7C225·30M 7C225·25M7C225·4OC 7C225·30C7C225·40M 7C225·35M7C235·4OC 7C235·30C7C245AL·35C 7C245A·25C +2149·55C 2149·45C 7C132·55C 7C132-45C 7C168-45M 7C168·35M +2l49·S5M 2149·45M 7C132·55M 7C132-45M 7C169L·35C 7C169L·25C21U8·35C 7C148·35C 7C147·35C 7C147·25C+ 7C169·25C 7C169L·25C21U8·45C 7C148·45C 7C147·45C 7C147·35C 7C169·35C 7C169·25C21U8-45C 21U8·35C 7C148-35C 7C148·25C 7C169-4OC 7C169L·35C21U8·55C 21U8·45C 7C148-45C 7C148·35C 7C169-40M 7C169·35M+21U9·35C 7C149·25C 7C149·35C 7C149·25C+ 7C170-35C 7C170·25C21U9·45C 21U9·35C 7C149·45C 7C149·35C 7C170·45C 7C170·35C+21U9·45C 7C149·45C 7C149·45M 7C149·35M 7C170-45M 7C170·35M+21U9·55C 21U9·45C 7C150·25C 7C150·l5C 7Cl7lL·35C 7Cl71L·25C27S03AC 7C189·25C 7C150·35C 7C150·25C 7C17l·25C 7C171L·25C27S03AM 7C189·25M 7C150·35M 7C150·25M 7C17l·35C 7Cl7l·25C27S03C 27S03AC 7C161L·35C 7C161L·25C 7C171-45C 7Cl7lL·35C27S03C 74Sl89C 7C161L·45C 7C161L·35C 7C17l·45M 7Cl7l·35M +27S03M 27S03AM 7C161L-45M 7C161L·35M 7C172L·35C 7C172L·25C27S03M 54Sl89M 7C16l·25C 7C161L·25C 7C172·25C 7Cl72L-25C27S07AC 7C190·25C 7C16l·35C 7C161L·35C 7C172·35C 7C172·25C27S07AM 7C190·25M 7C16l·35M 7C161L·35M 7C172·45C 7C172L·35C27S07C 27S07AC 7C16l-45C 7C161L-45C 7C172-45M 7C172·35M+27S07M 27S07AM 7C16l-45M 7C161L-45M 7C185L·45C 7C185L·35C27S07M 7C190·25M 7C162L·35C 7C162L·25C 7C185L·55C 7C185L-45C290 ICC 7C901·31C 7C162L-45C 7C162L·35C 7C185L·55M 7C185L-45M2901CM 7C90l·32M 7C162L·45M 7C162L·35M 7C185·35C 7C185L-35C2909AC 7C909·40C 7C162·25C 7C162L·25C 7C185·45C 7C185L·45C2909AM 7C909·40M 7C162·35C 7C162L·35C 7C185-45M 7C185L·45M29lOAC 7C91O·5OC 7C162·35M 7C162L·35M 7C185·55C 7C185L-55C29lOAM 7C91O·51M 7C162·45C 7C162L-45C 7C185·55M 7C185L·55M29lOC 29lOAC 7C162·45M 7C162L-45M 7C186L·45C 7C186L·35C2910M 29 lOAM 7Cl64L·35C 7Cl64L·25C 7C186L·55C 7C186L·45C29llAC 7C911-40C 7Cl64L-45C 7Cl64L·35C 7C186L·55M 7C186L·45MNote: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;+ = meets all performance specs but may not meet Icc or ISB ;* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-107C245A·25C7C245A·35C7C245A·35M7C245L·35C7C245L·45C7C245·35C7C245-45C7C245·45M7C25l·55C7C25l·65C7C25l·65M7C253·65M7C254·55C7C254·65C7C254·65M7C26l·45C7C26l·55C7C26l·55M7C263·45C7C263·55C7C263·55M7C264·45C7C264·55C7C264·55M7C268·50C7C268·60C7C268·60M7C269·50C7C269·60C7C269·60M7C245A·18C7C245AL-35C7C245A·25M7C245·35C·7C245L·35C7C245·25C7C245·35C7C245·35M7C25l·45C7C25l·55C7C25l·55M7C253·55M7C254·45C7C254·55C7C254·55M7C26l·35C7C26l-45C7C26l·45M7C263·35C7C263·45C7C263·45M7C264·35C7C264·45C7C264·45M7C268·40C+7C268·50C7C268·50M+7C269·40C+7C269·50C7C269·50M+

~ Product Line Cross Reference (Continued)~~~U~==================================================================CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS7C2S1-4SC 7C2S1-3OC 7C424-4OC 7C424-3OC 93U22M 93U22AM7C2S2-4SC 7C2S2-30C+ 7C424-40M 7C424-30M PALC16LSL-3SC PALC16LSL-2SC7C291AL-3SC 7C291A-2OC' 7C424-6SC 7C424-4OC PALC16LS-2SC PALC16LSL-2SC7C291AL-SOC 7C291AL-3SC 7C424-6SM 7C424-40M PALC16LS-30M PALC16LS-20M7C291A-3SC 7C291AL-3SC 7C42S-4OC 7C42S-3OC PALCI6LS-3SC PALC16LS-2SCAMD214S-7OC214S-70M2149-3SC2149-4SC2149-4SMCYPRESS214S-SSC214S-SSM2149-3SC2149-4SC2149-4SM7C291A-3SM 7C291A-30M 7C42S-40M 7C42S-30M PALC16LS-40M PALC16LS-30M7C291 A-SOC 7C291AL-SOC 7C42S-6SC 7C42S-4OC PALC16R4L-3SC PALC16R4L-2SC7C291A-SOM 7C291A-3SM 7C42S-6SM 7C42S-40M PALC16R4-2SC PALC16R4L-2SC7C291L-3SC 7C291-3SC' 7C42S-4OC 7C42S-3OC PALC16R4-30M PALCI 6R4-20M7C291L-SOC 7C291L-3SC 7C42S-40M 7C42S-30M PALC16R4-3SC PALC16R4-2SC7C291-3SC 7C291-2SC+ 7C42S-6SC 7C42S-4OC PALCI 6R4-40M PALC16R4-30M7C291-SOC 7C291-3SC 7C42S-6SM 7C42S-40M PALC16R6L-3SC PALC16R6L-2SC7C291-S0M 7C291-3SM 7C429-4OC 7C429-3OC PALC16R6-2SC P ALC16R6L-2SC7C292L-3SC 7C292-3SC' 7C429-40M 7C429-30M PALCI6R6-30M PALC16R6-20M7C292L-SOC 7C292L-3SC 7C429-6SC 7C429-4OC PALCI6R6-3SC PALC16R6-2SC7C292-3SC 7C292-2SC+ 7C429-6SM 7C429-40M PALCI 6R6-40M PALC16R6-30M7C292-SOC 7C292-3SC 7CS10-SSC 7CS10-4SC PALC16RSL-3SC PALC16RSL-2SC2149-SSC 2149-SSC2149-SSM 2149-SSM2149-7OC 2149-SSC2149-70M 2149-SSM2167-3SC 7C167-3SC2167-3SM 7C167-3SM2167-4SC 7C167-4SC2167-4SM 7C167-4SM2167-SSC 7C167-4SC2167-SSM 7C167-4SM2167-7OC 7C167-4SC2167-70M 7C167-4SMII7C293AL-3SC 7C293A-2OC' 7CS10-6SC 7CS10-SSC PALC16RS-2SC PALC16RSL-2SC7C293AL-SOC 7C293AL-3SC 7CS10-6SM 7CSIO-SSM PALC16RS-30M PALC16RS-20M7C293A-3SC 7C293AL-3SC 7CS10-7SC 7CS10-6SC PALC16RS-3SC PALC16RS-2SC7C293A-3SM 7C293A-30M 7CS10-7SM 7CS10-6SM PALC16RS-40M PALC16RS-30M7C293A-SOC 7C293AL-SOC 7CS16-4SC 7CSI6-3SC PALC22VIOL-2SC PALC22V10-2SC'7C293A-SOM 7C293A-3SM 7CS16-SSC 7CS16-4SC PALC22VIOL-3SC PALC22VIOL-2SC216S-3SC216S-4SC216S-4SM216S-SSC216S-SSM216S-7OC7C16S-3SC7C16S-4SC7C16S-4SM7C16S-4SC7CI6S-4SM7C16S-4SC7C401-IOC 7C401-1SC 7CS16-SSM 7CS16-42M PALC22V10-3SC PALC22V1 0-2SC7C401-IOM 7C401-1SM 7CSl6-6SC 7CS16-SSC PALC22V10-40M PALC22V10-30M7C401-SC 7C401-1OC 7CS16-6SM 7CS16-SSM PLDC2OG10-2SC PLDC2OG10-1SC7C402-1OC 7C402-1SC 7CS16-7SC 7CS16-6SC PLDC20G 10-3SC PLDC20G 10-2SC7C402-IOM 7C402-ISM 7CS16-7SM 7CS16-6SM PLDC2OG10-40M PLDC2OGIO-30M7C402-SC 7C402-IOC 7CS17-SSC 7CS17-4SC216S-70M 7C16S-45M2169-4OC 7C169-40C2169-SOC 7C169-40C2169-S0M 7C169-40M2169-70C 7C169-4OC2169-70M 7C169-40M7C403-1OC 7C403-1SC 7C517-6SC 7C517-SSC AMD CYPRESS7C403-IOM 7C403-1SM 7C517-6SM 7C517-SSM PREFIX:Am PREFIX:CY7C403-1SC 7C403-2SC 7CS17-7SC 7CS17-6SC PREFIX:SN PREFIX:CY7C403-1SM 7C403-2SM 7CSI7-7SM 7CS17-6SM SUFFIX:B SUFFIX:B7C404-1OC 7C404-1SC 7C901-31C 7C901-23C+ SUFFIX:D SUFFIX:D7C404-10M 7C404-1SM 7C901-32M 7C901-27M SUFFIX:F SUFFIX:F7C404-1SC 7C404-2SC 7C909-40C 7C909-3OC SUFFIX:L SUFFIX:L7C404-1SM 7C404-2SM 7C909-40M 7C909-30M SUFFIX:P SUFFIX:P7C40S-1SC 7C40S-2SC 7C9101-4OC 7C9101-3OC 2130-100c 7C13O-SSC7C40S-1SM 7C40S-2SM 7C9101-4SM 7C9101-3SM 2130-120C 7C13O-SSC7C40S-2SC 7C40S-3SC 7C910-SOC 7C91O-4OC 2130-7OC 7C13O-SSC7C40S-2SM 7C40S-3SM 7C9IO-SIM 7C91O-46M 2147-3SC 2147-3SC21U7-4SC21U7-SSC21U7-7OC21US-4SC21US-SSC21US-7OC21L49-4SC2IU9-SSC21U9-7OC27LS03C27LS03M27LS07C7C147-4SC7C147-4SC7C147-4SC2IUS-4SC21US-SSC21US-SSC21U9-4SC21U9-SSC21U9-SSC27LS03C27LS03M+27S07C+7C409-ISC 7C409-2SC 7C910-93C 7C910-SOC 2147-4SC 2147-4SC7C409-1SM 7C409-2SM 7C91O-99M 7C910-S1M 2147-4SM 2147-4SM7C409-2SC 7C409-3SC 7C911-4OC 7C911-3OC 2147-SSC 2147-SSC7C409-2SM 7C409-3SM 7C911-40M 7C911-30M 2147-SSM 2147-SSM7C420-4OC 7C420-3OC 93422AC 7C122-3SC 2147-7OC 2147-SSC7C420-40M 7C420-30M 93422AM 7C122-3SM 2147-70M 2147-SSM7C420-6SC 7C420-4OC 93422C 93U22AC 2148-3SC 214S-3SC7C420-6SM 7C420-40M 93422M 93422AM 214S-3SM 214S-3SM7C421-4OC 7C421-3OC 93422M 93U22AM 2148-4SC 2148-4SC7C421-40M 7C421-30M 93U22AC 7C122-3SC 214S-4SM 214S-4SM7C421-6SC 7C421-4OC 93U22AM 7C122-3SM 214S-SSC 2148-SSC7C421-6SM 7C421-40M 93U22C 93U22AC 214S-SSM 2148-SSM27LS19lC 7C292-3SC27LS291C 7C291-3SC27LS291M 7C291-3SM27PSISIAC 7C2S2-4SC27PSI81AM 7C282-4SM +27JlSI81C 7C282-4SC27PSIS1M 7C2S2-4SM +27PSI91AC 7C292-SOC27PSI9lAM 7C292-S0M .•27PSl91C 7C292-5OC27PS191M 7C292-S0M +27PS281AC 7C281-4SCNote: Unless otherwise noted, product meets all performance specs and IS within 10 rnA on Icc and 5 rnA on ISB ;+ = meets all performance specs but may not meet Icc or ISB ;* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-11

iI~ Product Line Cross Reference (Continued)~~~~UaoR==================================================================AMD CYPRESS AMD CYPRESS AMD CYPRESS27PS281AM 7C281·45M+ 27S49C 7C2M-55C 29L516C 7C516·75C27PS281C 7C281·45C 27S49M 7C264·55M 29L516M 7C516·75M27PS281M 7C281-45M+ 27S51C 7C254·55C 29L517C 7C517·75C27PS291AC 7C29l·5OC 27S51M 7C254·65M 29L517M 7C5l7·75M27PS291AM 7C291·50M+ 2841AC 3341C 3341C 3341CAMDCYPRESS99C165·55M 7C166-45M +99C165·70 7CI66·45C+99C165·70M 7CI66·45M+99C641·25C 7C187·25C99C641·35C 7C187·35C27PS291C 7C291·50C 2841AM 3341M 3341M 3341M27PS291M 7C291·50M+ 2841C 3341C 54S189M 54S189M27S03AC 27S03AC 2841M 3341M 74S189C 74S189C27S03AM 27S03AM 290lBC 2901CC 9122·25C 9122·25C27S03C 27S03C 290lBM 2901CM 9122·35C 9122·35C27S03M 27S03M 2901CC 2901CC 9122·35M 7C122·35M99C641-45C99C641·45M99C641·55C99C641·55M99C641·7OC99C641·70M7C187-45C7C187·45M7C187-45C7C187-45M7C187-45C7C187·45M27S07AC 27S07AC 2901CM 2901CM 9128·100C 6116·55C27S07AM 27S07AM 2909AC 2909AC 9128· 120M 6116-55M27S07C 27S07C 2909AM 2909AM 9128·150C 6116·55C27S07M 27S07M 2909C 2909AC 9128·150M 6116·55M27S181AC 7C282·3OC 2909M 2909M 9128·200C 6116·55C27S181AM 7C282·45M 2910AC 2910AC 9128·200M 6116·55M27S181C 7C282·45C 29 lOAM 29 lOAM 9128·70C 6116·55C27S181M 7C282·45M 29l0C 29l0C 9128·90M 6116·55M27S191AC 7C292·35C 29 10M 29 10M 9150·20C 7C150·15C27S191AM 7C292·50M 291O·1C 29l0C 9150·25C 7C150·25C27S191C 7C292·5OC 291O·1M 29 10M 9150-25M 7C150·25M27S191M 7C292·50M 2911AC 2911AC 9150·35C 7C150-35C27S191SAC 7C292A·20C 2911AM 2911AM 9150·35M 7C150·35M27S2S.A.C 7C225-30C 2911C 2911AC 9150-45C 7C150-35C27S25AM 7C225·35M 2911M 2911M 9150·45M 7C150·35M27S25C 7C225·40C 29116C 7C9116·79C 91L22·35C 91L22·35C27S25M 7C225·40M 29 116M 7C9116·99M 91L22·35M 7C122·35M27S25SAC 7C225·25C 29116AC 7C9116·53C 91L22·45C 91L22·45C27S25SAM 7C225·35M 29C116C 7C9116·79C 91L22·45M 7C122·35M27S281AC 7C281·30C 29C116M 7C9116·99M 91L22·60C 7C122·35C+27S281AM 7C281·45M 29C116AC 7C9116·53C 91L50·25C 7C150·25C27S281C 7C281·45C 29117C 7C9117·79C 91L50·35C 7C150·35C27S281M 7C281·45M 29117M 7C9117·99M 91L50·45C 7C150·35C27S291AC 7C291·35C 29C117C 7C9117·99C 93422AC 93422AC99C68·35 7C168·35C99C68·45 7CI68·45C*99C68·45M 7C168·45M*99C68·55 7CI68·45C*99C68·55M 7C168·45M*99C68·70 7C168-45C*99C68·70M 7C168·45M*99C88H·35C 7C186·35C99C88H·45C 7C186·45C99C88H·45M 7C186·45M99C88H·55C 7C186-55C99C88H·55M 7C186-55M99C88H·70C 7C186·55C99C88H-70M 7C186-55M99C88·IOC 7C186L·55C +99C88·IOM 7C186L·55M +99C88·12C 7CI86L·55C+99C88·12M 7C186L·55M +99C88·15C 7CI86L·55C+99C88·15M 7C186L·55M +99C88·20C 7C186L·55C+99C88·20M 7C186L·55M +99C88·7OC 7CI86L·55C+99C88·70M 7C186L·55M +II!27S291AM 7C291·50M 295lOC 7C51O·75C 93422AM 93422AM27S291C 7C291·50C 295 10M 7C51O·75M 93422C 93422C27S291M 7C291·50M 29516AM 7C516·55M 93422M 93422M27S291SAC 7C291A·20C 29516C 7C516·55C 93U22AC 93L422AC27S291SAM 7C291A·30M 29516M 7C516·55M 93L422AM 93U22AM27S35AC 7C235·30C 29517C 7C517·55C 93L422C 93U22C99CL68·3599CL68·4599CL68·45M99CL68·5599CL68·55M99CL68·707C168·35C7CI68·45C*7CI68-45M*7C168·45C*7CI68·45M*7CI68·45C*27S35AM 7C235-40M 29517M 7C517·55M 93L422M 93L422M27S35C 7C235·40C 29701C 27S07C 99CI64·35 7CI64·35C+27S35M 7C235·40M 29701M 27S07M 99CI64·45 7CI64·45C+27S45AC 7C245·35C 29703C 27S03C 99CI64·45M 7CI64·45M+27S45AM 7C245·45M 29703M 27S03M 99CI64·55 7CI64·45C+27S45C 7C245·45C 29C01BC 7C901·31C 99CI64·55M 7CI64·45M+27S4SM 7C245-45M 29C01CC 7C901·31C 99C164·70 7CI64·45C+27S4SSAC 7C245·2SC 29ClOIC 7C9101·4OC 99Cl64·70M 7C164-45M27S4SSAM 7C245A·2SM - 29ClO1M 7C9101·35M 99C165·35 7C166·35C+27S49AC 7C264-45C 29C10AC 7C91O·93C 99C165·45 7CI66·45C+27S49AM 7C264·55M 29L510C 7C51O·75C 99C165·45M 7CI66-45M+27S49A·4SC 7C264·45C 29L5lOM 7C51O·75M 99C165·55 7CI66·45C+Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;+ = meets all performance specs but may not meet Icc or ISB ;'" = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-1299CL68·70M 7CI68·45M*99CL88·10C 7C186L·55C +99CL88·12C 7CI86L·55C+99CL88·15C 7C186L·55C +99CL88·70C 7CI86L·55C+99CS88·IOM 7C186L·55M +99CS88·12M 7C186L·55M +99CS88·15M 7C186L·55M +99CS88·20M 7C186L·55M +99CS88·70M 7C186L·55M +PALl6L8AC PALCI6L8·25CPALl6L8ALC PALCI6L8·25CIII'I

~ Product Line Cross Reference (Continued)~~~NDUcroR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===AMD CYPRESS ANALOGDEV. CYPRESS FAIRCHILD CYPRESSPAL16L8ALM PALCI6L8-30M PREFIX:ADSP PREFIX:CY 16R6A PALCI6R6-20MPAL16L8AM PALCI6L8-30M SUFFIX:8S3B SUFFIX:B 16R6A PALCI6R6-25CPAL16LSA-4C PALCI6LSL-35C SUFFIX:D SUFFIX:D 16RSA PALCI6RS-25CPAL16LSA-4M PALCI6LS-40M + SUFFIX:E SUFFIX:L 16R8A PALCI6R8-20MPAL16LSBM PALCI6LS-20M SUFFIX:F SUFFIX:F 16RP4A PALCI6R4-20M -PAL16L8C PALCI6L8-35C SUFFIX:G SUFFIX:G 16RP4A PALCI6R4-25C-PAL16L8LC PALCI6LS-35C 10 lOA 7C51O-65C+ 16RP6A PALCI6R6-20M -PAL16LSLM PALCI6LS-40M 1010J 7C51O-75C+ 16RP6A PALCI6R6-25C-PAL16LSM PALCI6LS-40M 1010K 7C51O-75C+ 16RPSA PALCI6RS-20M -PAL16LSQC PALCI6LSL-35C 10 lOS 7C51O-75M + 16RPSA PALCI6RS-25C-PAL16LSQM PALCI6LS-40M + 10 lOT 7C51O-75M + 3341AC 3341CPAL16R4ALC PALCI6R4-25C 7C901-27M 7C901-32M 3341C 3341CPAL16R4ALM PALCI6R4-30M 7C901-32M 290lCM 54F1S9 7C1S9-25M -PAL16R4AM PALCI6R4-30M 54F219 7CI90-25M-PAL16R4A-4C PALCI6R4L-35C FAIRCHILD CYPRESS 54F413 7C401-15MPAL16R4A-4M PALCI6R4-40M + PREFIX:F PREFIX:CY 54S189M 54S1S9MPAL16R4BM PALCI6R4-20M SUFFIX:D SUFFIX:D 74AC1010-40 7C51O-45CFUJITSU CYPRESSSUFFIX:Z SUFFIX:D2147H-35 2147-35C2147H-45 2147-45C2147H-55 2147-55C2147H-70 2147-55C214S-55L 21L4S-55C214S-70L 21L4S-55C2149-45 2149-45C2149-55L 21L49-55C2149-70L 21L49-55C7132E7C2S2-45C7132E-SK7132E-W7132H7132H-SK7132Y7132Y-SK7C2S1-45C7C2S2-45M7C2S2-45C7C2S1-45C7C282-30C7C281-30CIIPAL16R4C PALCI6R4-35C SUFFIX:F SUFFIX:F 74FI89 7CI89-25C-PAL16R4LC PALCI6R4-35C SUFFIX:L SUFFIX:L 74F219 7CI90-25C-PAL16R4LM PALCI6R4-40M SUFFIX:P SUFFIX:P 74F413 7C401-15CPAL16R4M PALCI6R4-40M SUFFIX:QB SUFFIX:B 74LS189 27LS03CPAL16R4QC PALCI6R4L-35C 1600C45 7C187-45C 74S189 74S189CPAL16R4QM PALCI6R4-40M + 1600C55 7C187-45C 93422AC 93422ACPAL16R6AC PALCI6R6-25C 1600C70 7C1S7-45C 93422AM 93422AMPAL16R6ALC PALCI6R6-25C 1600M55 7C187-45M 93422C 93422CPAL16R6ALM PALCI6R6-30M 1600M70 7C187-45M 93422M 93422MPAL16R6AM PALCI6R6-30M 1601C45 7C187L-45C 93475C 2149-45CPAL16R6A-4C PALCI6R6L-35C 1601C55 7C187-45C 93L422AC 93L422ACPAL16R6A-4M PALCI6R6-40M 1601C70 7C187L-45C 93L422AM 93L422AM7138E7138E-SK7138E-W713SH713SH-SK7138Y7138Y-SK7144E7144E-W7144H7144Y7226RA-207C292-50C7C291-50C7C292-50M7C292-35C7C291-35C7C292-35C7C291-35C7C264-55C7C264-55M7C264-55C7C264-45C7C225-30CPAL16R6BM PALCI6R6-20M 1601M55 7C187L-45M 93L422C 93L422CPAL16R6C PALCI6R6-35C 1601M70 7C187L-45M 93L422M 93L422MPAL16R6LC PALCI6R6-35C 1620C25 7CI64L-25C+ 93Z451AC 7C282-30CPAL16R6LM PALCI6R6-40M 1620C35 7CI64-35C+ 93Z451AM 7C282-45MPAL 16R6M PALCI6R6-40M 1620M35 7CI64-35M 93Z451C 7C282-30CPAL16R6QC PALCI6R6L-35C 1620M45 7CI64-45M 93Z451M 7C282-45MPAL 16R6QM PALCI6R6-40M + 1621C25 7CI64-25C+ 93Z511C 7C292-35CPAL16R8AC PALCI6R8-25C 1621C35 7CI64L-35C+ 93Z511M 7C292-50MPAL16R8ALC PALCI6R8-25C 1621M35 7CI64L-35M 93Z565AC 7C264-45CPAL16R8ALM PALCI6RS-30M 1621M45 7CI64L-45M 93Z565AM 7C264-55MPAL16R8AM PALCI6R8-30M 1622C25 7CI66-25C+ 93Z565C 7C264-55CPAL16R8A-4C PALCI6R8L-35C 1622C35 7CI66-35C+ 93Z565M 7C264-55MPAL16R8A-4M PALCI6R8·40M 1622M35 7C166·35M 93Z611C 7C292·25CPAL16R8BM PALCI6RS-20M 1622M45 7C166-45M 93Z611M 7C291A-30MPAL16R8C PALCI6R8-35C 1623C25 7C166L-25C + 93Z665C 7C264·35CPAL16R8LC PALCI6R8·35C 1623C35 7C166L-35C + 93Z665M 7C264·45MPAL16R8LM PALCI6R8·40M 1623M35 7C166L-35M 93Z667C 7C263·35CPAL16R8M PALCI6R8·40M 1623M45 7C166L-45M 93Z667M 7C261-45MPAL16R8QC PALCI6R8L·35C 16L8A PALCI6L8·20MPAL16R8QM PALCI6R8·40M + 16L8A PALCI6L8-25C FUJITSU CYPRESSPAL22VIOAC PALC22VIO-25C 16P8A PALCI6L8-25C- PREFIX:MB PREFIX:CYPAL22V10AM PALC22VIO-30M 16P8A PALCI6L8·20M - PREFIX:MBM PREFIX:CYPAL22V10C PALC22V 1O-35C 16R4A PALCI6R4-25C SUFFIX:F SUFFIX:FPAL22VIOM PALC22VIO-40M 16R4A PALCI6R4-20M SUFFIX:M SUFFIX:P7226RA-25 7C225-30C7232RA-20 7C235-30C7232RA-25 7C235-3OC7238RA-20 7C245-25C7238RA-25 7C245-35C8128-10 7C128-55C812S-15 7C128-55C8167A-55 7C167-45C8167A-70 7C167-45C8167-70W 7C167-45M816S-55 7C168-45C816S-70 7C168-45C8168·70W 7C168-45M8171·55 7C1S7-458171·70 7C187·45C81C67·35 7C167·35C81C67·45 7C167-45C81C67-55W 7C167·45M81C6SA-25 7C168L·25C81C68A-30 7C168L·25C81C68A-3S 7C168L·35C81C68·35 7C168L·35CSIC68·45 7C168·45C81C68-55W 7CI68·45M+lote: Unless otherwise noted, product meets all performance specs and is withm 10 rnA on Icc and 5 rnA on ISB;+ = meets all performance specs but may not meet Icc or ISB ;• = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-13

"~ Product Line Cross Reference (Continued)~~~~==============================~~~==~~~~~~~====~==~~~FUJITSU CYPRESS HARRIS CYPRESS HITACHI CYPRESS81C69A-25 7C169L-25C 65262C-9 7CI67-45M' 6148H1-55 7CI48-45C'81C69A-30 7C169L-25C 65262S-9 7CI67-45M' 6148H-35 21U8-35C81C69A-35 7C169L-35C 65262-8 7CI67-45M' 6148H-45 7CI48-45C+81C71-45 7C187-45C 65262-9 7CI67-45M' 6148H-55 7CI48-45C+81C71-55 7C187-45C 6-76161A-2 7C291-50M 6148L 7CI48-45C'IDT39C01C39C01CB39COID39COIDB39C09ACYPRESS7C901-31C+7C901-32M+7C901-23C+7C901-27M+7C909-4OC+81C74-25 7CI64-25C 6-76161A-5 7C291-5OC 6167HL-55 7CI67-45C'81C74-35 7CI64-35C+ 6-7616IB-5 7C291-35C 6167HL-70 7CI67-45C'81C74-45 7CI64-45C 6-76161-2 7C291-50M 6167H-55 7C167-45C81C75-25 7C166-25C 6-76161-5 7C291-5OC 6167H-70 7C167-45C81C75-35 7C166-35C 6-7681A-5 7C281-45C 6167L-6 7CI67-45C'81C78-45 7C186-45C 6-7681-5 7C281-45C 6167L-8 7CI67-45C'39C09AB39C10B39CIOBB39ClIA39ClIAB49C4017C909-40M+7C910-5OC-7C910-51M-7C911-40C+7C911-40M+7C9101-4OC-81C78-55 7C186-55C 76161A-2 7C292-50M 6167-6 7CI67-45C+81C81-45 7C197-45C 76161A-5 7C292-5OC 6167-8 7CI67-45C+81C81-55 7C197-45C 76161B-5 7C292-35C 6168HL-45 7CI68-45C'81C84-45 7C194-45C 76161-2 7C292-50M 6168HL-55 7CI68-45C'81C84-55 7C194-45C 76641A-5 7C264-45C 6168HL-70 7CI68-45C'81C86-55 7CI92-45C+ 76641-2 7C264-55M 6168H-45 7CI68-45C+81C86-70 7CI92-45C+ 76641-5 7C264-55C 6168H-55 7CI68-45C+8464L-100 7CI85-55C+ 7681A-5 7C282-45C 6168H-70 7CI68-45C+8464L-70 7CI85-45C+ 7681-2 7C282-45M 62641-10 7C186L-55C +7681-5 7C282-45C 6264L-12 7C186L-55C +HARRIS CYPRESS 6264L-15 7C186L-55C +PREFIX: 1 SUFFIX:D HITACHI CYPRESS 6264-10 7CI86-55C+49C401 7C9101-45M -6116L120B 6116-55M'6116L150B 6116-55M'6116L55 6116-55C'6116L55B 6116-S5M'6116L70 6116-55C'6116L70B 6116-55M'6116L90 6116-55C'6116L90B 6116-55M'61I6LA120B 6116-55M'6116LA120TB 7CI28-55M'6116LA35 6116-35C'PREFIX:3 SUFFIX:P PREFIX:HM PREFIX:CY 6264-12 7CI86-55C+PREFiX:4 SUFFIX:L FREFIX:HN FREFiX:CY 6264-i5 7Ci86-55C+PREFIX:9 SUFFIX:F SUFFIX:CG SUFFIX:L 6267L-35 7C167L-35CPREFIX:HM PREFIX:CY SUFFIX:G SUFFIX:D 6267-35 7C167-35C+PREFIX:HPL PREFIX:CY SUFFIX:P SUFFIX:P 6267-45 7C167L-35CSUFFIX:8 SUFFIX:B 25089 7C282-45C 6267-45 7C167-45C16LC8-5 PALCI6L8L-35C- 25089S 7C282-45C 6268L-25 7C168L-25C16LC8-8 PALCI6L8-40M + 25169S 7C292-5OC 6268L-35 7C168L-35C16LC8-9 PALC16L8-40M + 4847 2147-55C 6268-25 7C168-25C16RC4-5 PALC16R4L-35C - 4847-2 2147-45C 6268-35 7C168-35C16RC4-8 PALCI6R4-40M + 4847-3 2147-55C 6287L-55 7C187L-45C16RC4-9 PALCI6R4-40M + 6116ALS-12 6116-55C' 6287L-70 7C187L-45C6116LA35B6ii6LA35T6116LA35TB6116LA456116LA45B6116LA45T6116LA45TB6116LA556116LA55B6116LA55T6116LA55TB6116LA706116-45M'7CI2M-35C'7C128-35M'6116-45C'6116-45M'7CI28-45C'7CI28-45M'6116-55C'6116-55M'7CI28-55C'7CI28-55M'6116-55C'16RC6-5 PALCI6R6L-35C- 6116ALS-15 6116-55C' 6287-45 7C187-45C16RC6-8 PALCI6R6-40M + 6116ALS-20 6116-55C" 6287-55 7C187-45C16RC6-9 PALC16R6-40M + 6116AS-12 6116-55C+ 6287-70 7C187-45C16RC8-5 PALCI6R8L-35C- 6116AS-15 6116-55C+ 6288-35 7CI64-35C16RC8-8 PALC16R8-40M + 6116AS-20 6116-55C+ 6288-45 7Cl64-45C16RC8-9 PALC16R8-40M + 6147 7CI47-45C' 6288-55 7Cl64-45C6116LA70B 6116-55M'6116LA70T 7CI28-55C'6116LA70TB 7C128-55M'6116LA90 6116-55C'6116LA90B 6116-55M"6116LA9OT 7CI28-55C' i65162B-5 6116-55C' 6147 7CI47-45C' 6716 7C128-25C65162B-8 6116-55M" 6147HL-35 7CI47-35C' 6787-30 7C187-25C65162B-9 6116-55M' 6147HL-45 7C147-45C" 6788-25 7Cl64-25C65162C-8 6116-55M" 6147H1-55 7C147-55C" 6788-30 7CI64-3OC65162C-9 6116-55M' 6147H-35 7CI47-35C+65162S-5 6116-55C' 6147H-45 7CI47-45C+ IDT CYPRESS6116LA9OTB 7CI28-55M'6116S120B 6116-55M +6116S150B 6116-55M +6116S55 6116-55C+6116S55B 6116-55M +6116S70 6116-55C+65162S-9 6116-55M" 6147H-55 7CI47-45C+ PREFIX:IDT PREFIX:CY65162-5 6116-55C· 6147-3 7CI47-45C' SUFFIX:B SUFFIX:B65162-8 6116-55M" 6147-3 7CI47-45C' SUFFIX:D SUFFIX:D65162-9 6116-55M* 6148 7C148-45C SUFFIX:F SUFFIX:F65262B-8 7CI67-45M' 6148HL-35 21U8-35C' SUFFIX:L SUFFIX:L65262B-9 7CI67-45M' 6148HL-45 7CI48-45C' SUFFIX:P SUFFIX:PNote: Unless otherwIse noted, product meets all performance specs and IS wlthm 10 rnA on ICC and 5 rnA on ISB;+ = meets all performance specs but may not meet Icc or ISB ;,.. = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-146116S70B6116S906116S90B6116SA120B6116SA120TB6116SA356116-55M+6116-55C+6116-55M+6116-55M+7C128-55M+6116-35C+

~ Product Line Cross Reference (Continued)~~~NDUcrOR ==================~==~====~~==================================~lOT CYPRESS lOT CYPRESS lOT CYPRESS61168A35B 6116-45M+ 6168L85B 7C168-45M' 7130855 7C130-55C61168A35T 7CI28-35C+ 6168LA25 7C168-25C' 7130870 7C130-55C61168A35TB 7C128-35M + 6168LA35 7C168-35C' 7130890 7C130-55C61168A45 6116-45C+ 6168LA35B 7C168-35M' 7132LlOO 7C132-55C'61168A45B 6116-45M+ 6168LA45 7CI68-45C' 7132LlOOB 7C132-55M'lOTCYPRESS71681855B 7C171-45M +71681870 7C171-45C+71681870B 7C171-45M+71681885B 7CI71-45M+716818A25 7CI71-25C+61168A45T 7CI28-45C+ 6168LA45B 7C168-45M' 7132Ll20B 7C132-55M'61168A45TB 7CI28-45M+ 6168LA55 7C168-45C' 7132L55 7C132-55C'61168A55 6116-55C+ 6168LA55B 7CI68-45M' 7132L70 7C132-55C'61168A55B 6116-55M + 6168LA70B 7CI68-45M' 7132L70B 7C132-55M'61168A55T 7CI28-55C+ 61688100B 7C168-45M + 7132L90 7C132-55C'61168A55TB 7CI28-55M+ 6168845 7CI68-45C+ 7132L90B 7C132-55M'61168A70 6116-55C+ 6168855 7CI68-45C+ 71328100 7C132-55C+61168A70B 6116-55M+ 6168855B 7CI68-45M+ 71328100B 7C132-55M +61168A70T 7CI28-55C+ 6168870 7C168-45C 71328120B 7C132-55M +61168A70TB 7CI28-55M+ 6168870B 7C168-45M 7132855 7C132-55C+61168A90 6116-55C+ 6168885 7C168-45C 7132870 7CI32-55C+61168A90B 6116-55M+ 6168885B 7C168-45M 7132870B 7C132-55M +716818A35 7CI71-35C+716818A35B 7C171-35M +716818A45 7CI71-45C+716818A45B 7CI71-45M+716818A55 7CI71-45C+716818A55B 7CI71-45M+716818A70B 7CI71-45M+71682LlOOB 7C172-45M'71682L45 7C172-45C'71682L55 7C172-45C'71682L55B 7C172-45M'71682L70 7C172-45C'II61168A90T 7CI28-55C+ 61688A25 7CI68-25C+ 7132890 7C132-55C+61168A90TB 7CI28-55M+ 61688A35 7CI68-35C+ 7132890B 7C132-55M +6167LlOOB 7C167-45M' 61688A35B 7CI68-35M+ 7164L35 7C186L-35C +6167L45 7C167L-35C 61688A45 7CI68-45C+ 7164L45 7CI86L-45C+6167L55B 7C167-45M' 61688A45B 7CI68-45M+ 7164L45B 7C186L-45M +6167L70B 7C167-45M' 61688A55 7CI68-45C+ 7164L55 7CI86L-55C+71682L70B71682L85B71682LA2571682LA3571682LA35B71682LA457C172-45M'7C172-45M'7C172-25C'7C172-35C'7C172-35M'7C172-45C'6167L85B 7C167-45M' 61688A55B 7CI68-45M+ 7164L55B 7C186L-55M +6167LA25 7C167-25C' 61688A70B 7CI68-45M+ 7164L70 7CI86L-55C+6167LA35 7C167-35C' 71256845 7C198-45C 7164L70B 7C186L-55M +6167LA35B 7C167-35M' 71256855 7C198-55C 7164L85B 7C186L-55M +6167LA45 7C167-45C' 71256855B 7C198-55M 7164835 7C186-35C6167LA45B 7C167-45M' 71256870 7C198-55C 7164845 7C186-45C6167LA55 7C167-45C' 71256870B 7C198-55M 7164845B 7C186-45M6167LA55B 7CI67-45M' 71257835 7C197-35C 7164855 7C186-55C6167LA70B 7CI67-45M' 71257845 7C197-45C 7164855B 7C186-55M61678100B 7C167-45M 71257845B 7C197-45M 7164870 7C186-55C6167845 7C167-45C 71257855 7C197-45C 7164870B 7C186-55M6167855 7C167-45C 71257855B 7C197-45M 7164885B 7C186-55M71682LA45B 7C172-45M'71682LA55 7C172-45C'71682LA55B 7CI72-45M'716828100B 7C172-45M+71682845 7CI72-45C+71682855 7CI72-45C+71682855B 7C172-45M+71682870 7C172-45C+71682870B 7C172-45M+71682885B 7CI72-45M+716828A25 7C172-25C+716828A35 7C172-35C+6167855B 7C167-45M 71257870 7C197-45C 71681LlOOB 7C171-45M'6167870B 7C167-45M 71257870B 7C197-45M 71681L45 7C171-45C'6167885B 7C167-45M 71258835 7C194-35C 71681L55 7C171-45C'61678A25 7CI67-25C+ 71258845 7C194-45C 71681L55B 7C171-45M'61678A35 7CI67-35C+ 71258845B 7C194-45M 71681L70 7C171-45C'61678A35B 7CI67-35M+ 71258855 7C194-45C 71681L70B 7C171-45M'716828A35B716828A45716828A45B716828A55716828A55B7187L307CI72-35M+7C172-45C+7CI72-45M+7Cl72-45C+7CI72-45M+7C187L-25C61678A45 7CI67-45C+ 71258855B 7C194-45M 71681L85B 7C171-45M'61678A45B 7CI67-45M+ 71258870 7C194-45C 71681LA25 7C171-25C'61678A55 7CI67-45C+ 71258870B 7C194-45M 71681LA35 7C171-35C'61678A55B 7CI67-45M+ 7130LlOO 7C130-55C' 71681LA35B 7CI71-35M'61678A70B 7CI67-45M+ 7130LlOOB 7C130-55M 71681LA45 7C171-45C'6168LlOOB 7CI68-45M' 7130Ll20B 7C130-55M 71681LA45B 7CI71-45M'6168L45 7CI68-45C* 7130L55 7C130-55C' 71681LA55 7CI71-45C'6168L55 7C168-45C' 7130L70 7C130-55C' 71681LA55B 7C171-45M'6168L55B 7CI68-45M' 7130L90 7C130-55C' 7l68lLA70B 7CI71-45M*6168L70 7CI68-45C' 71308100 7C130-55C 716818100B 7CI71-45M+6168L70B 7C168-45M' 71308100B 7C130-55M 71681845 7CI71-45C+6168L85 7C168-45C' 71308l20B 7C130-55M 71681855 7CI7l-45C-1ote: Unless otherwise noted, product meets all performance specs and IS wlthm 10 mA on Icc and 5 mA on Iso;+ = meets all performance specs but may not meet Icc or ISB ;>/0 = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-157187L35 7C187L-35C7187L35B 7C187L-35M7187L45 7C187L-45C71871.45B 7C187L-45M71871.55 7C187L-45C71H7L55B 7C187L-45M71H7L70 7C187L-45C71H7L85 7C187L-45C7187L85B 7C187L-45M7187830 7C187-25C7187835 7C187-35C7187835B 7C187-35M

SEMICONDUCfORProduct Line Cross Reference (Continued)IDT CYPRESS lOT CYPRESS lOT CYPRESS7187845 7C187-45C 71982L70B 7C162L-45M 7201LA-35 7C420-3OC+7187845B 7C187-45M 71982L85B 7C162L-45M 7201LA-4OB 7C420-25M+7187855 7C187-45C 71982835 7C162-35C 7201LA-50 7C42O-4OC+7187855B 7C187-45M 71982835B 7C162-35M 7201 LA-50B 7C420-4OM+7187870 7C187-45C 71982845 7C162-45C 7201LA-65 7C420-65C+lOTCYPRESS72161140 7C516-75C+72161185B 7C516-75M+7216L55 7C516-55C+7216L55B 7C516-55M7216L65 7C516-65C+7187870B 7C187-45M 71982845B 7C162-45M 7201LA-65B 7C420-65M+7187885 7C187-45C 71982855 7C162-45C 7201LA-80 7C420-65C+7187885B 7C187-45M 71982855B 7C162-45M 7201 LA-80B 7C420-65M +7188130 7CI64L-25C 71982870 7C162-45C 7201LA-120 7C420-65C+7188L35 7CI64L-35C 71982870B 7C162-45M 7201LA-120B 7C420-65M +7188135B 7CI64L-35M 71982885B 7C162-45M 72018A-35 7C420-30C7216L65B7216L757216L75B7216L907216L90B72171120B7C516-65M7C516-75C+7C516-75M7C516-75C+7C516-75M+7C517-75M+7188145 7CI64L-45C 7198135 7C166L-35C 72018A-4OB 7C420-4OM7188145B 7CI64L-45M 7198135B 7C166L-35M 72018A-50 7C420-4OC7188L55 7CI64L-45C 7198L45 7C166L-45C 72018A-50B 7C420-4OM7188L55B 7CI64L-45M 7198L45B 7C166L-45M 72018A-65 7C420-65C7188L70 7CI64L-45C 7198L55 7C166L-45C 72018A-65B 7C420-65M7188L70B 7CI64L-45M 7198L55B 7C166L-45M 72018A-80 7C420-65C72171140 7C517-75C+72171185B 7C517-75M+7217145 7C517-45C+7217L55 7C517-55C+7217L55B 7C517-55M7217L65 7C517-65C+7188L85B 7CI64L-45M 7198L70 7C166L-45C 72018A-80B 7C420-65M7188830 7CI64-25C 7198L70B 7C166L-45M 72018A-120 7C420-65C7188835 7CI64-35C 7198L85B 7C166L-45M 72018A-120B 7C420-65M7188835B 7CI64L-35M 7198835 7C166-35C 7202LA-35 7C424-3OC+7188845 7CI64-45C 7198835B 7C166-35M n02LA-4OB 7C424-4OM+7188845B 7CI64-45M 7198845 7C166-45C 7202LA-50 7C424-4OC+7188855 7CI64-45C 7198845B 7C166-45M 7202LA-50B 7C424-4OM+7188855B 7CI64-45M 7198855 7Ci66-45C...... ,,"'y , /1:I.WL.Lft-UJ 7C424·65C+7188S70 7CI64-45C 7198S55B 7C166-45M 7202LA-65B 7C424-65M+7188S70B 7CI64-45M 7198S70 7C166-45C 7202LA-80 7C424-65C+7188S85B 7CI64-45M 7198S70B 7C166-45M 7202LA-80B 7C424-65M+71981L35 7C161L-35C 7198885B 7C166-45M 7202LA-120 7C424-65C+7217L65B7217L757217L75B7217L907217L90BINMOSPREF!X:!MS8UFFIX:B8UFFIX:P8UFFIX:88UFFIX:W7C517-65M7C517-75C+7C517-75M7C517-75C+7C517-75M+CYPRESSPREFIX:CY8UFFIX:B8UFFIX:P8UFFIX:D8UFFIX:L71981L35B 7C161L-35M 72401-10C 7C401-1OC+ n02LA-120B 7C424-65M+71981145 7C161L-45C 72401-10M 7C401-IOM 72028A-35 7C424-30C71981145B 7C161L-45M 72401-15C 7C401-15C+ n028A-4OB 7C424-4OM71981L55 7C161L-45C 72401-15M 7C401-15M n028A-50 7C424-4OC71981L55B 7C161L-45M 72401-25C 7C401-25C+ 72028A-50B 7C424-4OM71981L70 7C161L-45C 72401-25M 7C401-25M 72028A-65 7C424-65C71981L70B 7C161L-45M 72402-IOC 7C402-IOC+ 72028A-65B 7C424-65M71981L85B 7C161L-45M 72402-IOM 7C402-IOM 72028A-80 7C424-65C71981S35 7C161-35C 72402-15C 7C402-15C+ 7202SA-80B 7C424-65M11981S35B 7C161-35M 72402-15M 7C402-15M n02SA-120 7C424-65C71981S45 7C161-45C 72402-25C 7C402-25C+ 72028A-120B 7C424-65M71981845B 7C161-45M 12402-25M 7C402-25M 72101100 7C51O-75C+71981855 7C161-45C 72403-10C 7C403-IOC+ 72101165 7C51O-75C+71981S55B 7C161-45M 12403-IOM 7C403-IOM 7210L45 7C510-45C+71981S70 7C161-45C 12403-15C 7C403-15C+ 72IOL55 7C51O-55C+71981870B 7C161-45M 12403-15M 7C403-15M 7210L65 7C51O-65C+71981885B 7C161-45M 12403-25C 7C403-25C+ 7210L75 7C51O-75C+71982L35 7C162L-35C 12403-25M 7C403-25M 121O-120B 7C51O-75M +71982135B 7C162L-35M 12404-1OC 7C404-10C+ 721O-2ooB 7C51O-75M +71982L45 7C162L-45C 12404-10M 7C404-10M 721O-55B 7C51O-55M719821458 7C162L-45M 72404-15C 7C404-15C+ 7210-658 7C510-65M71982L55 7C162L-45C 12404-15M 7C404-15M 7210-75B 7C51O-75M71982L558 7C162L-45M 12404-25C 7C404-25C+ 121O-85B 7C510-75M71982L70 7C162L-45C 12404-25M 7C404-25M 72161120B 7C516-75M+Note: Unless otherWIse noted, product meets all performance specs and IS WIthin 10 rnA on Icc and 5 rnA on ISB;+ = meets all performance specs but may not meet Icc or ISB ;* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-161203M-35 7CI47-35M+1203M-45 7CI47-45M+1203-25 7CI47-25C+1203-35 7CI47-35C+1203-45 7CI47-45C+1223M-25 7C148-25M1223M-35 7CI48-25M+1223M-45 7CI48-45M+1223-25 7C148-25C1223-35 7C148-35C1223-45 7C148-45C1400M-45 7C167-45M1400M-55 7C167-45M1400M-70 7C167-45M1400-35 7C167-35C1400-45 7C167-45C1400-55 7C167-45C1403LM-35 7CI67-35M*1403M-35 7CI67-35M+1403M-45 7CI67-45M+1403M-55 7CI67-45M+1403M-70 7CI67-45M+1403-25 7C167-25C1403-35 7CI67-35C+I

~ Product Line Cross Reference (Continued)~~~~~================================================================INMOS CYPRESS INMOS CYPRESS LAmCE CYPRESS1403-45 7CI67-45C+ 1630LM-70 7ClS6-55M PREFIX:SR PREFIX:CY1403-55 7CI67-45C+ 1630L-45 7ClS6L-45C+ SUFFIX:B SUFFIX:B1420L-1O 7C16S-45C 1630L-55 7ClS6L-55C+ SUFFIX:D SUFFIX:D1420L-70 7C16S-45C 1630L-70 7ClS6L-55C+ SUFFIX:L SUFFIX:L1420M-55 7C16S-45M + 1630M-45 7ClS6-45M SUFFIX:P SUFFIX:PLATflCE CYPRESS20VS-35L PLDC20G 1O-35C20VS-35L PLDC20G 10-30M20VS-35Q PLDC2OGI0-30M +20VS-35Q PLDC2OG1O-35C +64E4-35 7C166-35C1420M-70 7C16S-45M 1630M-55 7ClS6-55M+ 16K4-25 7C16S-25C1420-45 7C16S-35C 1630M-70 7ClS6-55M 16K4-35 7C16S-35C1420-55 7C16S-45C 1630-45 7ClS6-45C+ 16K4-35M 7C16S-35M1421C-40 7C169-4OC 1630-55 7ClS6-55C+ 16K4-45 7C16S-45C1423M-35 7CI6S-35M* 1630-70 7ClS6-55C+ 16K4-45M 7C16S-45M1423M-45 7CI6S-45M* 16KS-35 7CI2S-35C+1423M-55 7CI6S-45M* INTEL CYPRESS 16KS-55 7CI2S-45C+1423M-70 7C16S-45M + PREFIX:D SUFFIX:D 16VS-25 PALCI6RS-25C1423-25 7CI6S-25C+ PREFIX:L SUFFIX:L 16VS-25 PALCI6LS-25C1423-35 7CI6S-35C+ PREFIX:P SUFFIX:P 16VS-25 PALCI6R4-25C1423-45 7CI6S-45C+ SUFFIX:!B SUFFIX:B 16VS-25 PALCI6R6-25C1433M-35 7CI2S-35M+ 2147H 2147-55C 16VS-25L PALCI6LS-25C64E4-45 7C166-45C64E4-55 7C166-45C64KI-35 7ClS7-35C64KI-45 7ClS7-45C64KI-45M 7ClS7-45M64KI-55 7C1S7-45C64KI-55M 7ClS7-45M64K4-35 7CI64-35C64K4-45 7CI64-45C64K4-45M 7CI64-45M64K4-55 7CI64-45C64K4-55M 7CI64-45M•1433M-45 7C12S-45M + 2147HL 7C147-45C 16VS-25L PALCI6R6-25C1433M-55 7CI2S-55M+ 2147H-l 2147-35C 16VS-25L PALCI6RS-25C1433-35 7CI2S-35C+ 2147H-l 2147-35C 16VS-25L PALCI6R4-25C1433-45 7CI2S-45C+ 2147H-2 2147-45C 16VS-25Q PALCI6R6L-25C1433-55 7CI2S-55C+ 2147H-2 2147-45C 16VS-25Q PALCI6LSL-25C1600M-45 7ClS7-45M + 2147H-3 2147-55C 16VS-25Q PALCI6RSL-25C64KS-3564KS-4564KS-4564KS-45M64KS-5564KS-557ClS6-35C7C1S6-45C7C264-45C7ClS6-45M7C264-55C7ClS6-55C1600M-55 7ClS7-45M + 2147H-3 2147-55C 16VS-25Q PALCI6R4L-25C1600M-70 7ClS7-45M + 214SH 214S-55C 16VS-30 PALCI6LS-30M1600-35 7ClS7-35C 214SHL 21US-55C 16VS-30 PALCI6RS-30M1600-45 7ClS7-45C 214SHL-3 21US-55C 16VS-30 PALCI6R6-30M1600-55 7ClS7-45C 214SH-2 214S-45C 16VS-30 PALCI6R4-30M1600-70 7ClS7-45C 214SH-3 214S-55C 16VS-30L PALCI6R6-30M64KS-55M 7ClS6-45M64KS-70 7C264-55CL1010-45 7C51O-45C+LlOI0-65 7C51O-65C+L1010-65B 7C51O-65M+L1010-90 7C51O-75C+1601L-45 7ClS7L-45C+ 2149H 2149-55C 16VS-30L PALCI6LS-30M1601L-55 7ClS7L-45C+ 2149HL 21U9-55C 16VS-30L PALCI6R4-30M1601L-70 7ClS7L-45C+ 2149H-l 2149-35C 16VS-30L PALCI6RS-30M1601LM-55 7ClS7L-45M + 2149H-2 2149-45C 16VS-3OQ PALCI6LS-30M +1601 LM-70 7ClS7L-45M + 2149H-3 2149-55C 16VS-3OQ PALCI6RS-30M +1620LM-45 7CI64L-45M 51C66-25 7CI67-25C- 16VS-3OQ PALCI6R6-30M +1620LM-55 7CI64L-45M 51C66-30 7CI67-25C- 16VS-3OQ PALCI6R4-30M +1620LM-70 7CI64L-45M 51C66-35 7CI67-25C- 16VS-35 PALCI6R6-35C1620M-45 7CI64-45M 51C66-35L 7CI67-25C- 16VS-35 PALCI6LS-35C1620M-55 7CI64-45M 51C67-30 7CI67-25C+ 16VS-35 PALCI6R4-35C1620M-70 7CI64-45M 51C67-35 7CI67-35C+ 16VS-35 PALCI6RS-35C1620-35 7CI64-35C 51C67-35L 7CI67-35C+ 16VS-35L PALCI6LS-35CL1010-90BMITSUBISHIPREFIX:M5MSUFFIX:APSUFFIX:FPSUFFIX:KSUFFIX:P21C67P-3521C67P-4521C67P-5521C6SP-357C51O-75M+CYPRESSPREFIX:CYSUFFIX:LSUFFIX:FSUFFIX:DSUFFIX:P7C167-35C7C167-45C7C167-45C7C16S-35C1620-45 7CI64-45C 51C6SL-35 7CI6SL-35C+ 16VS-35L PALCI6R4-35C,1620-55 7CI64-45C 51C6S-30 7CI6S-25C+ 16VS-35L PALCI6RS-35C1620-70 7CI64-45C 51C6S-35 7CI6S-35C+ 16VS-35L PALCI6R6-35C1620L-35 7CI64L-35C M2147H-3 7C169-40M 16VS-35Q PALCI6R4L-35C1620L-45 7CI64L-45C M214SH 214S-55M 16VS-35Q PALCI6RSL-35C1620L-55 7CI64L-45C M2149H 2149-55M 16VS-35Q PALCI6LSL-35C1620L-70 7CI64L-45C M2149H-2 2149-45M 16VS-35Q PALCI6R6L-35C1624-35 7CI66-35C+ M2149H-3 2149-55M 20VS-25 PLDC20G 10-25C1624-45 7CI66-45C+ 20VS-25L PLDC20G 10-25C1624-55 7CI66-4~C+ LAmCE CYPRESS 20VS-25Q PLDC20G 10-25C +1630LM-45 7ClS6L-45M PREFIX:EE PREFIX:CY 20VS-35 PLDC20G 10-35C1630LM-55 7ClS6L-55M + PREFIX:GAL PREFIX:CY 20VS-35 PLDC20G 10-30M21C6SP-45 7C168-45C21C6SP-55 7C168-45C5165L-100 7ClS6-55C+5165L-120 7ClS6-55C+5165L-70 7ClS6-55C+5165P-l00 7ClS6-55C+5165P-120 7ClS6-55C+5165P-70 7ClS6-55C+517SP-45 7ClS6-45C+517SP-55 7ClS6-55C+51S7P-25 7ClS7-25C51S7P-35 7ClS7-35C)te: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;+ = meets all performance specs but may not meet Icc or ISB ;* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-17

~ Product Line Cross Reference (Continued)~~~UaoR==================================================================MITSUBIsm CYPRESS MMI CYPRESS MMI CYPRESS5187P·45 7C187-45C 63S881 7C282-45C PALI6R4A-4C PALCI6R4L·35C5187P·55 7C187-45C 63S881 7C281·45C PALl6R4A·4M PALCI 6R4·4OM +5188p·25 7CI64-25C 63S881A 7C282·30C PALl6R4BM PALCI6R4-20M5188P·35 7CI64-35C 63S881A 7C281·30C PALl6R4B·2C PALCI6R4·25C5188p·45 7CI64·45C 67401 7C401·IOC PALl6R4B·2M PALCI6R4-30MMMICYPRESSPAL20R4A·2C PLDC20GIO·35CPAL20R4A·2M PLDC20G 10-40MPAL20R4B PLDC20GIO·15CPAL20R6AC PLDC20G 1O·25CPAL20R6AM PLDC20G 1O·30M5188p·55 7CI64-45C 67401 7C401·IOC PALl6R4B·4C PALCI6R4L·35C6740IA 7C401·15C PALl6R4B·4M PALCI6R4·4OM +MMI CYPRESS 6740IB 7C403·25C PALl6R4C PALCI6R4·35CSUFFIX:883B SUFFIX:B 674010 7C403·25C PALl6R4D·4C PALCI6R4L·25CSUFFIX:F SUFFIX:F 67402 7C402·IOC PALl6R4M PALCI6R4-40M +SUFFIX:J SUFFIX:D 67402A 7C402·15C PALl6R6AC PALCI 6R6·25CPAL20R6A·2C PLDC20G 1O·35CPAL20R6A·2M PLDC20G 1O·4OMPAL20R6B PLDC20G 1O·15CPAL20R8AC PLDC20G 10-25CPAL20R8AM PLDC20G 10-30MPAL20R8A·2C PLDC20G 10-35CSUFFIX:L SUFFIX:L 67402B 7C402·25C PALl6R6AM PALCI 6R6·30MSUFFIX:N SUFFIX:P 67402D 7C404·25C PALl6R6A·2C PALCI6R6·35CSUFFIX:SHRP SUFFIX:B 67411 7C403·25C PALl6R6A·2M PALCI 6R6·4OM538IS·1 7C281·45M 67412 7C402·25C PALl6R6A·4C PALCI6R6L·35C5381S·2 7C281·45M 671402 7C402·IOC PALl6R6A·4M PALCI6R6·4OM5381·1 7C282·45M C57401 7C401·IOM PALl6R6BM PALCI6R6·20M5381·2 7C282-45M C5740IA 7C401·IOM PALl6R6B·2C PALCI6R6·25C53RA1681AS 7C245·35M- C57402 7C402·IOM PALl6R6B·2M PALCI6R6·30M53RAI681S 7C245-45M - C57402A 7C402·IOM PALl6R6B-4C PALCI6R6L·35C53RA48 lAS 7C225·35M C67401 A 7C401·15C PALl6R6B-4M PALC16R6·4OM +53RA481S 7C225-40M C6740lB 7C403·25C PALl6R6C PALC16R6·35C53RS1681AS 7C245·35M - C67402 7C402·1OC PALl6R6D·4C PALC16R6L·25CPAL20R8A·2MPAL20R8BPAL20RAIOCPAL20RAIOMPALC22VIO/APLElOP8CPLEIOP8CPLElOP8MPLEIOP8MPLE10R8CPLElOR8MPLE11P8C53RS1681S 7C245-45M - C67402A 7C402·15C PALl6R6M PALC16R6·4OM +53RS881AS 7C235·4OM- C67402B 7C404·25C PALl6R8AC PALC16R8·25C53RS881S 7C235-40M- C671401 7C401·5C PAL16R8AM PALC16R8·30M53S1681 7C292·50M C6714010 7C401·15C PALl6R8A·2C PALC16R8·35C53S1681AS 7C291·35M C671402D 7C402·15C PALl6R8A·2M PALCI6R8·4OM53S1681S 7C291·50M PALl 2Ll OC PLDC20G 1O·35C PALl6R8A·4C PALCI6R8L·35CPLDC20G 10-4OMPLDC20G 1O·15CP ALC20RAIO·30CPALC20RAIO·35MPALC22VIO·35C7C282·30C7C281·30C7C281·45M7C282·45M7C235·30C-7C235·4OM-7C291·35CPLEl1P8M 7C291·35MIPLE11RA8C 7C245·35C-PLE11RA8M 7C245·35M-PLE11RS8C 7C245·35C-PLE11RS8M 7C245·35M-PLE9R8C 7C225·30C53S881 7C282-45M PALl2LlOM PLDC20G 10·4OM PALl6R8A·4M PALCI6R8·4OM53S881A 7C282-45M PALl4L8C PLDC20G 1O·35C PALl6R8BM PALCI6R8·20M53S881AS 7C281-45M PALl4L8M PLDC20G 1O·4OM PALl6R8B·2C PALCI6R8·25C53S881S 7C281-45M PALl6L6C PLDC20G 1O·35C PALl6R8B·2M PALCI6R8·30M57401 7C401·IOM PALl6L6M PLDC20G 1O·4OM PALl6R8B-4C PALCI6R8L·35C57401A 7C401·IOM PALl6L8AC PALCI6L8·25C PALl6R8B·4M PALCI6R8·4OM +PLE9R8MMOTOROLAPREFIX:MCMSUFFIX:PSUFFIX:S7C225·35MCYPRESSPREFIX:CYSUFFIX:PSUFFIX:D57402 7C402·IOM PAL16L8AM PALCI6L8·30M PALl6R8C PALCI6R8·35C57402A 7C402·IOM PALl6L8A·2C PALCI6L8·35C PAL 16R8D-4C PALCI6R8L·25C6381S·1 7C281·45C PALl6L8A·2M PALCI6L8·4OM PALl6R8M PALCI6R8·4OM +63~IS·2 7C281·45C PALl6L8A·4C PALC16L8L·35C PALl8L4C PLDC20G 1O·35C6381·1 7C282·45C PALl6L8A·4M PALCI6L8·4OM + PALl8L4M PLDC20GlO·4OM6381·2 7C282·45C PALl6L8BM PALCI6L8·20M PAL20LlOAC PLDC20G 1O·35C63RA1681AS 7C245·35C- PALl6L8B·2C PALCI6L8·25C PAL20LlOAM PLDC2OGIO·30M63RA1681S 7C245·35C- PALl6L8B·2M PALCI6L8·30M PAL20LlOC PLDC20GIO·35C63RA481AS 7C225·25C PALl6L8B·4C PALCI6L8L·35C PAL20LlOM PLDC20G 1O·4OM63RA481S 7C225·3OC PALl6L8B·4M PALCI6L8·4OM + PAL20L2C PLDC20G 1O·35C63RS1681AS 7C245·35C- PALl6L8C PALC16L8·35C PAL20L2M PLDC20G 1O·4OM63RS1681S 7C245·35C- PALI6L8D-4C PALCI6L8L·25C PAL20L8AC PLDC20G 1O·25C63RS881AS 7C235·3OC- PALl6L8D-4M PALCI6L8·30M + PAL20L8AM PLDC20G 1O·30M63RS881S 7C235·3OC- PAL16L8M PALCI6L8·4OM PAL20L8A·2C PLDC20G 1O·35C63S1681 7C292·5OC PALl6R4AC PALCI6R4·25C PAL20L8A·2M PLDC20G 10·4OM63S1681A 7C292·35C PALl6R4AM PALCI6R4·30M PAL20L8B PLDC2OG10·15C63S1681AS 7C291·35C PALl6R4A·2C PALCI6R4·35C PAL20R4AC PLDC20G 1O·25C63S1681S 7C291·5OC PALl6R4A·2M PALCI 6R4·4OM PAL20R4AM PLDC20G 10·30MNote: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB ;+ = meets all performance specs but may not meet Icc or ISB ;* = meets all performance specs except 2V data retention-may not meet ICC or ISB ;- = functionally equivalent1-18SUFFIX:Z SUFFIX:L1423·45 7CI68·45C+2016H·45 6116·452016H·55 6116·55C2016H·70 6116·55C2018·35 7C128·35C2018·35 7C128·35C2018·45 7C128·45C2167H·35 7C167·35C2 I 67H·45 7C167·45C2167H·55 7C167-45C6147·55 7CI47-45C'6147·70 7C147·45C·6164·45 7C186·45C6164·55 7C186·55C6164·70 7C186·55C6168·35 7CI68·35C+6168·45 7CI68·45C+

~ Product Line Cross Reference (Continued)~~~~================================================================MOTOROLA CYPRESS NATIONAL CYPRESS NATIONAL CYPRESS6168·55 7C168-45C+ 2147H 2147·55M 87S191 7C292·5OC6168·70 7C168-45C+ 2147H 2147·55C 87S191A 7C292·35C61L47·55 7C147-45C· 2147H·l 2147·35C 87S19lB 7C292·35C61L47·70 7C147-45C· 2147H·2 2147-45C 87S281 7C281-45C61L64-45 7C186-45C 2147H·3 2147·55C 87S281A 7C281-45CNATIONAL CYPRESSPALl6R8AM PALC16R8·30MPALl6R8B2C PALC16R8·25CPALl6R8B2M PALC16R8·30MPALl6R8B4C PALCI6R8L·35CPALl6R8B4M PALC1 6R8-40M +61L64-55 7C186-55C 2147H·3 2147·55M 87S291 7C291·5OC61L64-70 7C186-55C 2147H·3L 7C147-45C 87S291A 7C291·35C6268·25 7C168·25C 2148H 2148·55C 87S291B 7C291·35C6268·35 7C168·35C 2148HL 21L48·55C 878401 7C401·1OC6269·25 7C169·25C 2148H·2 2148-45C 878401A 7C401·15C6269·35 7C169·35C 2148H·3 2148·55C 878402 7C402·1OC6270-25 7C170-25C 2148H·3L 21L48·55C 878402A 7C402·15C6270-35 7C170-35C 2901AC 7C901·31C 87SR181 7C235·3OC6270-45 7C170-45C 2901AM 7C901·32M 87SR25 7C225-4OC6287·25 7C187·25C 2901A·IC 7C901·31C 87SR25B 7C225·3OC6287·35 7C187·35C 2901A·IM 7C901·32M 87SR476 7C225-4OC-6287-45 7C187-45C 2901A·2C 7C901·31C 87SR476B 7C225·3OC-6288·25C 7Cl64-25C 2901A·2M 7C901·32M PALl6L8A2C PALC16L8·35C6288·35C 7Cl64-35C 2909AC 2909AC PALl6L8A2M PALC16L8-40M6288·35M 7Cl64-35M 2909AM 2909M PALl6L8AC PALC16L8·25C6288-45M 7Cl64-45M 2911AC 2911AC PALl6L8AM PALC16L8·30M6290-25C 7C166·25C 2911AM 2911M PALl6L8B2C PALC16L8·25C6290-35C 7C166·35C 54S189 54S189M PALl6L8B2M PALC16L8·30M6290-35M 7C166-35M 54S189A 7C189·25M PALl6L8B4C PALC16L8L·35C6290-45C 7C166-45C 74S189 74S189C PALl6L8B4M PALC1 6L8-40M +6290-45M 7C166-45M 74S189A 27S03AC PALl6L8BM PALC1 6L8·20M62L87·25 7C187·25C 75S07 7C190-25M PALl6L8C PALC16L8·35C62L87·35 7C187·35C+ 75S07A 27S07AM PALl6L8M PALC1 6L8-40M7681 7C282-45C 77LS181 7C282-45M PALl6R4A2C PALC16R4-35C7681A 7C282-45C 77S181 7C282-45M PALl6R4A2M PALC1 6R4-40M93422 93422C 77S181A 7C282-45M PALl6R4AC PALC16R4-25C93422 93422M 77S191 7C292·50M PALl6R4AM PALC16R4-30M93422A 93422AM 77S191A 7C292·50M PALl6R4B2C PALC16R4-25C93422A 93422AC 77S19lB 7C292·50M PALl6R4B2M PALC16R4-30M93L422 93L422C 77S281 7C281-45M PALl6R4B4C PALC16R4L·35CPALl6R8BM PALC16R8·20MPALl6R8C PALC16R8·35CPALl6R8M PALC16R8-40M +PAL20LlOB2C PLDC20G 10-25CPAL20LlOB2M PLDC2OGI0-30MPAL20LlOC PLDC2OGI0-35CPAL20LlOM PLDC20G 10-40MPAL20L2C PLDC2OGI0-35CPAL20L8AC PLDC20G 1O·25CPAL20L8AM PLDC20G 10-30MPAL20L8BC PLDC20G 10-25CPAL20L8BM PLDC2OGI0-30MPAL20L8C PLDC2OGI0-35CPAL20L8M PLDC2OGIO-4OMPAL20R4AC PLDC20G 10·25CPAL20R4AM PLDC2OGlO·30MPAL20R4BC PLDC20G 10-25CPAL20R4BM PLDC2OGI0-30MPAL20R4C PLDC2OGI0-35CPAL20R4M PLDC20G 10-4OMPAL20R6AC PLDC20G 1O·25CPAL20R6AM PLDC2OGI0-30MPAL20R6BC PLDC20G 10-25CPAL20R6BM PLDC20G 1O·30MPAL20R6C PLDC2OGlO·35CPAL20R6M PLDC20G 1O·4OMPAL20R8AC PLDC2OGI0-25CPAL20R8AM PLDC20G 1O·30MPAL20R8BC PLDC20G 10-25CPAL20R8BM PLDC2OGlO·30M..93L422 93L422M 77S281A 7C281-45M PALl6R4B4M PALC16R4-40M +93L422A 93L422AC 77S291 7C291·50M PALl6R4BM PALC16R4-20M93L422A 93L422AM 77S291A 7C291·50M PALl6R4C PALC16R4-35C77S29lB 7C291·50M PALl6R4M PALC16R4-40M +NATIONAL CYPRESS 77S401 7C401· 10M PALl6R6A2C PALC16R6-35CPREFIX:DM PREFIX:CY 778401A 7C4O 1· 10M PALl6R6A2M PALC16R6-40MPAL20R8CPAL20R8MNEePREFIX:uPDSUFFIX:CPLDC2OGIO-J5CPLDC20G 10040MCYPRESSPREFIX:CYSUFFIX:PPREFIX:IDM PREFIX:CY 778402 7C402·lOM PALl6R6AC PALC16R6·25CPREFIX:NMC PREFIX:CY 778402A 7C402·lOM PAL 16R6AM PALC16R6-30MSUFFIX:J SUFFIX:D 77SR181 7C235-40M PALl6R6B2C PALC16R6·25CSUFFIX:N SUFFIX:P 77SR25 7C225-40M PALl6R6B2M PALC16R6·30M12LlOC PLDC2OGI0-35C 77SR25B 7C225-40M PALl6R6B4C PALC16R6L·35C14L8C PLDC20G 10-35C 77SR476 7C225-40M- PAL 16R6B4M PALC16R6-40M +14L8M PLDC20G 10-40M 77SR476B 7C225-40M- PALi6R6BM PALC16R6·20M16L6C PLDC20G 10-35C 85S07 27S07C PALl6R6C PALC16R6-35C16L6M PLDC20G 10-40M 85S07A 27S07AC PALl6R6M PALC16R6-40M +18L4C PLDC20G 10-35C 85S07A 7C128-45C+ PALl6R8A2C PALC16R8·35C18L4M PLDC20G 10-40M 87LS181 7C282-45C PALl6R8A2M PALC1 6R8-40M20L2M PLDC20G 10-40M 87S181 7C282-4SC PAL 16R8AC PALC16R8·2SCote: Unless otherwise noted, product meets all performance specs and 1S within 10 mA on Icc and 5 mA on 19B ;+ = meets all performance specs but may not meet Icc or Isn ;* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-19SUFFIX:D SUFFIX:DSUFFIX:K SUFFIX:LSUFFIX:L SUFFIX:F2147A·25 7C147·25C2147A·35 2147·35C2147A-45 2147·45C2147·2 2147·55C2147·3 2147·55C2149 2149·55C2149·1 2149-45C2149·2 2149·35C2167·2 7C167-45C

~ Product Line Cross Reference (Continued)~~~~u~==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==NEe CYPRESS RAYTHEON CYPRESS TI CYPRESS2167·3 7C167-45C 29683AC 7C292·5OC+ PREFIX:TBP PREFIX:CY429 7C292·5OC 29683AM 7C292·50M+ PREFIX:TIB PREFIX:CY429·1 7C292·5OC 29683ASC 7C291·5OC+ SUFFIX:F SUFFIX:F429·2 7C292·5OC 29683ASM 7C291·50M+ SUFFIX:J SUFFIX:L429·3 7C292·35C 29683C 7C292·5OC+ SUFFIX:N SUFFIX:DTIPALl6L8A·2MPALl6L8·20MPALl6L8·25CPALl6L8·30MPAL16R4ACCYPRESSPALCI6L8-40MPALCI6L8·20MPALCI6L8B·2CPALCI6L8·30MPALCI6R4-25C4311·35 7C167L·35C 29683M 7C292·50M+ 22VlOAC PALC22V10-25C4311·45 7C167·45C 29683SC 7C291·5OC+ 22V10AM PALC22V10·30M4311·55 7C167·45C 29683SM 7C291·50M+ 27C291·3 7C291L·35C+4314-35 7CI68L·35C+ 29VP864DB 7C264·55M 27C291·30 7C291L·35C+4314-45 7C168L·45C + 29VP864SB 7C263·55M 27C291·5 7C291L·50C+4314-55 7C168L·45C + 29VS864SB 7C261·55M 27C291·50 7C291L·5OC +4361-40 7C187·35C 39VP864D 7C264·55C 27C292·3 7C292L·35C +4361·45 7C187-45C 39VP864S 7C263·55C 27C292·35 7C292L·35C +4361·55 7C187·45C 39VS864S 7C261·55C 27C292·5 7C292L·5OC +4361·70 7C187-45C 27C292·50 7C292L·5OC +4362·45 7CI64·45C SIGNETICS CYPRESS 28Ll66W 7C292·5OC4362·55 7CI64-45C PREFIX:N PREFIX:CY 28L86AMW 7C282·45M4362·70 7CI64·45C PREFIX:S PREFIX:CY 28L86AW 7C282-45C4363-45 7C166·45C SUFFIX:883B SUFFIX:B 28S166W 7C292·5OC4363·55 7C166-45C SUFFIX:F SUFFIX:D 28S86AMW 7C282-45M4363·70 7C166·45C SUFFIX:G SUFFIX:L 28S86AW 7C282·45CSUFFIX:N SUFFIX:P 38Ll65·35C 7C291·35CRAYTHEON CYPRESS SUFFIX:R SUFFIX:F 38Ll65·45C 7C291·35CPALl6R4AMPALl6R4A·2CPALl6R4A·2MPALl6R4-20MPALl6R4·25CPALl6R4-30MPALl6R6ACPALl6R6AMPALI6R6A·2CPALl6R6A·2MPALl6R6·20MPALl6R6·25CPALl6R6·30MPALl6R8ACPALl6R8AMPALl6R8A·2CPALl6R8A·2MPALl6R8·20MPALCI6R4-30MPALCI6R4-25CPALCI6R4-40MPALCI6R4·20MPALCI6R4·25CPALCI6R4-30MPALCI6R6·25CPALCI6R6·30MPALCI6R6·25CPALCI6R6·40MPALCI6R6·20MPALCI6R6·25CPALCI6R6-30MPALCI6R8·25CPALCI6R8·30MPALCI6R8·25CPALCI6R8·40MPALCI6R8·20MPREFIX:R PREFIX:CY N74S189 74S189C 38Ll66·35 7C292·35CSUFFIX:B SUFFIX:B N82HS641 7C264·55C 38Ll66·45 7C292·35CSUFFIX:D SUFFIX:D N82HS641A 7C264·45C 38L85-45C 7C281·45CSUFFIX:F SUFFIX:F N82HS641B 7C264·35C 38R165·18C 7C245·25CSUFFIX:L SUFFIX:L N82LS181 7C282·45C 38R165·25C 7C245·35CSUFFIX:S SUFFIX:S N82S181 7C282-45C 38R85·15C 7C235·3OCPALl6R8·25C PALCI6R8·25CPALl6R8·30M PALCI6R8·30MPAL20LlOAC PLDC20G 1O·35CPAL20LlOAM PLDC20G 10·30MPAL20LlOA·2C PLDC2OG10·25CPAL20LlOA·2M PLDC20G 10·30M29631AC 7C282-45C N82S181A 7C282·45C 38S165·25C 7C291·25C29631AM 7C282·45M N82S181B 7C282·45C 38S165·35C 7C291·35C29631ASC 7C281·45C N82S191A-3 7C291·5OC 38S85·30C 7C281·3OC29631ASM 7C281·45M N82S191A-6 7C292·5OC 54HC189 7C189·25M29631C 7C282·45C N82S1918-3 7C291·35C 54HCT189 7C189·25M29631M 7C282·45M N82S1918-6 7C292·35C 54LS189A 27LS03MPAL20L8ACPAL20L8AMPAL20L8A·2CPAL20L8A·2MPAL20R4ACPAL20R4AMPLDC20G 1O·25CPLDC20GIO·30MPLDC20G 1O·25CPLDC20G 1O·30MPLDC20G 1O·25CPLDC20G 1O·30M29631SC 7C281·45C N82S191-3 7C291·5OC 54LS219A 7CI90·25M+29631SM 7C281·45M N82S191-6 7C292·5OC 54S189A 54S189M29633AC 7C282·45C+ S54S189 54S189M 74ACT29116 7C9116AC29633AM 7C282·45M+ S82HS641 7C264·55M 74ACT29116·1 7C9116AC29633ASC 7C281-45C+ S82LS181 7C282·45M 7489 7C189·25C29633ASM 7C281·45M+ S82S181 7C282·45M 74HC189 7C189·25CPAL20R4A·2C PLDC20G 1O·25CPAL20R4A·2M PLDC20G 1O·30M iPAL20R6AC PLDC20G 1O·25CPAL20R6AM PLDC2OG10-30M iPAL20R6A·2C PLDC2OG10·25CPAL20R6A·2M PLDC20G 10·30M!29633C 7C282·45C+ S82S181A 7C282-45M 74HC219 7C190·25C29633M 7C282·45M+ S82S191A-3 7C291·50M 74HCT189 7C189·25C29633SC 7C281-45C+ S82S191A-6 7C292·50M 74LS189A 27LS03C29633SM 7C281-45M+ S82S1918-3 7C291·50M 74LS219A 27S07C+29681AC 7C292·5OC S82S1918-6 7C292·50M 74S189A 74S189C29681AM 7C292·50M S82S191-3 7C291·50M 74S189B 7C189·25CPAL20R8ACPAL20R8AMPAL20R8A·2CPAL20R8A·2MTOSHIBAPLDC20G 1O·25CPLDC20G 1O·30MPLDC20G 1O·25CPLDC20G 1O·30MCYPRESSII29681ASC 7C291·5OC S82S191-6 7C292·50M HCT9510E 7C510·75C+29681ASM 7C291·50M HCT9510E·1O 7C510·75C+29681C 7C292·5OC TI CYPRESS HCT9510M 7C51O·75M +29681M 7C292·50M PREFIX:JBP PREFIX:CY PALl6L8AC PALCI6L8·25C29681SC 7C291·50C PREFIX:PAL SUFFIX:P PALl6L8AM PALCI6L8·30M29681SM 7C291·50M PREFIX:SN PREFIX:CY PALl6L8A·2C PALCI6L8·35CNote: Unless otherwise noted, product meets all performance specs and is within 10 rnA on IcC and 5 rnA on ISB ;+ = meets all performance specs but may not meet Icc or ISB ;* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-20PREFIX:P SUFFIX:PPREFIX:TMM PREFIX:CYSUFFIX:D SUFFIX:D2015A·10 7CI28·55C+2015A·12 7CI28·55C+2015A·15 7CI28·55C+

II~ Product Line Cross Reference (Continued)~~~U~================================================================TOSHIBA CYPRESS VTI CYPRESS WSI CYPRESS2015A·90 7CI28·55C+ 20C98·45 7CI85-45C+ SUFFIX:D PREFIX:CY2018·25 7C128·25C 2OC99·35 7CI85·35C+ SUFFIX:M SUFFIX:P2018·35 7C128·35C 2OC99-45 7CI85-45C+ SUFFIX:P PREFIX:CY2018·45 7C128-45C 2130-10 7C130-55C 29COIC 7C901·31C2018·55 7CI28·55C+ 2130-12 7C130-55C 57C128F·70 7C251·55C2068·25 7C168·25C 7C122·15 7C122·15 57C128F·70M 7C251·55M +2068·35 7C168·35C 7C122·25 7C122·25 57C128F·90 7C251·55C2068-45 7C168-45C 7C122·35 7C122·35 57C128F·90M 7C251·55M+2068·55 7C168·45C VL2010-65 7C510-65C 57C191-40 7C292·35C2069·35 7C169·35C VL2010·70 7C510-65C 57C191·55 7C292·50C2078·25 7C170-25C VL2010-90 7C510-75C 57C191·55M 7C292·50M2078·45 7C170-45C VT64KS4·35 7CI64·35C 57C191·70 7C292·5OC2078·55 7C170-45C VT64KS4-45 7CI64-45C 57C191·70M 7C292·50M2088·35 7C186·35C VT64KS4-55 7CI64-45C 57C291·40 7C291·35C2088-45 7C186-45C VT65KS4-35 7C166·35C 57C291·55 7C291·5OC2088·55 7C186·55C VT65KS4-45 7C166-45C 57C291·55M 7C291·50M55416·25 7CI64-25C VT65KS4-55 7C166-45C 57C291·70 7C291·5OCII55416·35 7CI64-35C 57C291·70M 7C291·50M55416-45 7CI64-45C WEITEK CYPRESS 57C49·55 7C264·55C+55417·25 7C166·25C 1010AC 7C510-75C 57C49·55M 7C264-55M55417·35 7C166·35C 1010AM 7C510·75M 57C49·70 7C264-55C+55417·45 7C166-45C 1010BC 7C51O·75C 57C49·70M 7C264-55M5561-45 7CI87-45C+ 1010BM 7C51O·75M 57C49·90 7C264-55C+5561·55 7CI87-45C+ 1010C 7C51O·75C 57C49·90M 7C264·55M5561·70 7CI87-45C+ 1010M 7C510-75M 59016C 7C9101-40C5562·35 7C187·35C 1516AC 7C516·75C 59016C 7C9101-45M5562·45 7C187-45C 1516AM 7C516·75M 5901C 2901CC+5562·55 7C187-45C 1516BC 7C516·55C 5901M 2901CM+1516BM 7C516·75M 5910AC 7C91O-4OCTRW CYPRESS 1516C 7C516·75C 5910AM 7C910-46MMPY016HA 7C516·75M 1516M 7C516-75M 59510 7C51OMPY016HC 7C516·75C 2010AC 7C510-55C 59516 7C516MPY016KA 7C516·75M 2010AM 7C510-75M 59517 7C517MPY016KC 7C516·75C 2010BC 7C510-45CTDCI0I0A 7C510-75M 2010BM 7C510-55MTDC1010C 7C510-75C 2010C 7C510·75CTMC2010A 7C51O·75M + 2010DC 7C510·55CTMC2010C 7C510-75C+ 2010DM 7C51O·75MTMC2110A 7C510-75M 2010M 7C51O·75M +TMC2110C 7C510-75C 2516AC 7C516·55CTMC216HA 7C516·75M 2516AM 7C516·75MTMC216HC 7C516·75C+ 2516C 7C516·75C2516DC 7C516-45CVTI CYPRESS 2516DM 7C516·55M2OC18·35 7CI28·35C+ 2516M 7C516·75M+2OC68·25 7C168·25C 2517AC 7C517·55C2OC68·35 7C168·35C 2517AM 7C517·75M2OC69·25 7C169·25C 2517C 7C517·75C2OC69·35 7C169·35C 2517M 7C517·75M+2OC79·25 7C170·25C2OC79·35 7C170·35C WSI CYPRESS2OC79-45 7C170-45C PREFIX:WS PREFIX:CY20C98·35 7CI85·35C+ SUFFIX:C PREFIX:CY\Tote: Unless otherwise noted, product meets all performance specs and is wlthm 10 mA on Icc and 5 mA on ISB ;+ = meets all performance specs but may not meet Icc or ISB ;* = meets all performance specs except 2V data retention-may not meet Icc or ISB ;- = functionally equivalent1-21

~ Section Contents~~~~UcrOR================================================================Static RAMs (Random Access Memory)Device NumberCY2147CY2148CY21L48CY2149CY21L49CY6116CY7C122CY7C123CY7C128CY7C130CY7C140CY7C132CY7C142CY7C147CY7C148CY7C149CY7C150CY7C152CY7C158CY7C159CY7C161CY7C162CY7C164CY7C166CY7C167CY7C168CY7C169CY7C170CY7C171CY7CI72CY7C185CY7C186CY7C187CY7C189CY7C190CY7C191CY7C192CY7C194CY7C196CY7C197CY7C198CY7C199CY74S189CY27LS03CY27S03CY27S07CY93422ACY93L422ACY93422CY93L422DescriptionPage Number4096 x 1 Static RAM ...................................................... 2-11024 x 4 Static RAM ...................................................... 2-61024 x 4 Static RAM, Low Power ............................................ 2-61024 x 4 Static RAM ...................................................... 2-61024 x 4 Static RAM, Low Power ............................................ 2-62048 x 8 Static RAM ..................................................... 2-12256 x 4 Static RAM Separate I/O .......................................... 2-19256 x 4 Static RAM Separate I/O .......................................... 2-262048 x 8 Static RAM ..................................................... 2-331024 x 8 Dual Port Static RAM ............................................ 2-401024 x 8 Dual Port Static RAM ............................................ 2-402048 x 8 Dual Port Static RAM ............................................ 2-502048 x 8 Dual Port Static RAM ............................................ 2-504096 x 1 Static RAM ..................................................... 2-601024 x 4 Static RAM ..................................................... 2-671024 x 4 Static RAM ..................................................... 2-671024 x 4 Static RAM Separate I/O .......................................... 2-74Self-Timed Cache Static RAM ................................................ 2-82Self-Timed Pipelined Static RAM ............................................. 2-83Self-Timed Pipelined Static RAM ............................................. 2-8316,384 x 4 Static RAM Separate I/O .......................................... 2-8416,384 x 4 Static RAM Separate I/O .......................................... 2-8416,384 x 4 Static RAM ..................................................... 2-9216,384 x 4 Static RAM with Output Enable .................................... 2-9216,384 x 1 Static RAM .................................................... 2-1014096 x 4 Static RAM .................................................... 2-1084096 x 4 Static RAM .................................................... 2-1084096 x 4 Static RAM with Output Enable ................................... 2-1154096 x 4 Static RAM Separate I/O ......................................... 2-1214096 x 4 Static RAM Separate I/O ......................................... 2-1218192 x 8 Static RAM .................................................... 2-1288192 x 8 Static RAM .................................................... 2-12865,536 x 1 Static RAM .................................................... 2-13716 x 4 Static RAM .................................................... 2-14616 x 4 Static RAM .................................................... 2-14665,536 x 4 Static RAM Separate I/O ......................................... 2-15365,536 x 4 Static RAM Separate I/O ......................................... 2-15365,536 x 4 Static RAM .................................................... 2-15965,536 x 4 Static RAM with Output Enable ................................... 2-159262,144 x 1 Static RAM .................................................... 2-16532,768 x 8 Static RAM .................................................... 2-17132,768 x 8 Static RAM .................................................... 2-17116 x 4 Static RAM .................................................... 2-17716 x 4 Static RAM .................................................... 2-17716 x 4 Static RAM .................................................... 2-17716 x 4 Static RAM .................................................... 2-177256 x 4 Static RAM Separate I/O ......................................... 2-183256 x 4 Static RAM Separate I/O ......................................... 2-183256 x 4 Static RAM Separate I/O ......................................... 2-183256 x 4 Static RAM Separate I/O ......................................... 2-183

CY21474096 x 1 Static R/W RAMFeatures• Automatic power-down whendeselected• CMOS for optimumspeed/power• High speed-35 ns• Low active power- 690 m W (commercial)- 770 mW (military)• Low standby power-140 mW• TTL compatible inputs andoutputs• Capable of withstanding greaterthan 2000V electrostaticdischargeFunctional DescriptionThe CY2147 is a high performanceCMOS static RAM organized as4096 x 1 bit. Easy memory expansion isprovided by an active LOW chip enable(CE) and three-state drivers. TheCY2147 has an automatic power-downfeature, reducing the power consumptionby 80% when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.Data on the input pin (DI) is writteninto the memory location specified onthe address pins (Ao through All).Reading the device is accomplished bytaking the chip enable (CE) LOW,while write enable (WE) remainsHIGH. Under these conditions thecontents of the memory location specifiedon the address pins will appear onthe data output (DO) pin.The output pin stays in high impedancestate when chip enable (CE) is HIGHor write enable (WE) is LOW.fILogic Block DiagramPin Configuration...--------c .----- 011---+---41 .>----DOAoAlA2A3A4AsVeeA6A7AsAgA10DOAllWE 01GNOCE0013-2WE0013-1Selection Guide (For higher performance and lower power refer to CY7C147 data sheet.)I 2147-35 2147-45 2147-55IMaximum Access Time (ns) 35 45 55Maximum Operating Commercial 125 125 125Current (rnA)Military 140 140IMaximum Standby Commercial 25 25 25Current (rnA)Military 25 252-1

~ CY2147~~~NDUcroR =======================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latchup Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 18 to Pin 9) ..................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto + 70°C 5V ±1O%Output Current into Outputs (Low) ............. 20 rnAMilitary [5] - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over Operating Range[4]Parameters Description Test Conditions Min. Max. UnitsVOH Output HIGH Voltage Vee = Min.,IOH = -4.0 rnA 2.4 VVOL Output LOW Voltage Vee = Min.,IOL = 12.0mA 0.4 VVIH Input HIGH Voltage 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 VIIX Input Load Current GND ~ VI ~ Vee -10 +10 p.AlozlosIccISBCapacitance [3]Output Leakage CurrentOutput Short CircuitCurrent [I]GND ~ Vo ~ VeeOutput DisabledVee-50 +50 p.AVee = Max., VOUT = GND -350 rnAVee Operating Supply Vee = Max. Commercial 125Current lOUT = OmA Military 140Automatic CE[2) Max. Vee, Commercial 25Power Down Current CE ~ VIH Military 25Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = I MHz 5COUTOutput CapacitanceVee = 5.0V 6Notes:1. Duration of the short circuit should not exceed 30 seconds.2. A pull-up resistor to Vee on the CE input is required to keep thedevice deselected during Vee power-up, otherwise ISB will exceedvalues given.AC Test Loads and Waveforms5Vo-------~~~OUTPUT 0---...... ---...R13291! R1329H5Vo-------~~-,OUTPUT 00-----_._-------.pFrnArnA3. Tested initially and after any design or process changes that mayaffect these parameters.4. See the last page of this specification for Group A subgroup testinginformation.5. TA is the "instant on" case temperature.INPUT PULSES'NCLUD'NGI30 pFJIG ANDSCOPER220H!'NCLUD'NlJIG ANDSCOPE ':'5 pFR2202 Sl3.0 v----:-:±-~~-~~GND-----=:Ir-Figure laFigure Ib0013-3Figure 20013-4Equivalent to:THEVENIN EQUIVALENT12SSlOUTPUT~1.90V0013-52-2

~ CY2147~~~~UcrOR=====================================================================Switching Characteristics Over Operating Range[4, 6]Parameters Description I 2147-35 2147-45 2147-55Min. Max. Min. Max. Min. Max. IREAD CYCLEtRC Read Cycle Time 35tAAAddress to Data ValidtOHA Data Hold from Address Change 5tACECE LOW to Data ValidtLZCE CE LOW to Low Z[S] 5tHZCE CE HIGH to High Z[7, S]tpu CE LOW to Power Up 0tpDWRITE CYCLE[9]CE HIGH to Power Downtwc Write Cycle Time 35tSCE CE LOW to Write End 35tAW Address Set-up to Write End 35tHA Address Hold from Write End 0tSA Address Set-up to Write Start 0tpwE WE Pulse Width 20tSD Data Set-up to Write End 20tHD Data Hold from Write End 10tLzwE WE HIGH to Low Z[S] 0tHzwE WE LOW to High Z[7, S] 0Notes:6. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IorJIOH and 30 pF load capacitance.7. tHZCE and tHzwE are tested with CL = 5 pF as in Figure lb. Transitionis measured ± 500 m V from steady state voltage.8. At any given temperature and voltage condition, tHZ is less than tLZfor all devices.Switching WaveformsRead Cycle No.1 (Notes 10, 11)Units45 55 ns35 45 55 ns5 5 ns35 45 55 ns5 5 ns30 30 30 ns0 0 ns20 20 20 ns45 55 ns45 45 ns45 45 ns0 10 ns0 0 ns25 25 ns25 25 ns10 10 ns0 0 ns20 0 25 0 25 ns9. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.10. WE is HIGH for read cycle.11. Device is continuously selected, CE = VIL.12. Address valid prior to or coincident with CE transition LOW.'''''M =F~--==---==-tR_C--------.j*-~tOHADATA OUTDATA VALIDfI0013-6Read Cycle No.2 (Notes 10, 12)J~1\tRCtACEt LZCE :-! -tHZCE1HIGHHIGH IMPEDANCE I, , I I I IMPEDANCEDATA OUT1DATA VALIDI\.~\.\. \./_tpu-tPDSUPPLY Vee _____ 60%t~50%CURRENT _ 158,l0013-72-3

~ CY2147~~~U~ ==================================================================~Switching Waveforms (Continued)Write Cycle No.1 (WE Controlled) (Note 9)f4------------twc--------------lADDRESS--tsA-----.\DATA INDATA OUTDATA UNDEFINED0013-8Write Cycle No.2 (CE Controlled) (Note 9)f4-------------~c-------------~ADDRESSf4-+-------tw---~~DATA INDATA-IN VALIDtHZWE~----------------'\jHIGH IMPEDANCEDATA OUT DATA UNDEFINED J)--------.-",;,~.;,;;;;.;;;;;.;.;;.;.;;.;;.-----Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state_0013-9Ordering InformationSpeedPackageOperatingOrdering Code(ns) Type Range35 CY2147-35 PC P3 CommercialCY2147-35 DCD445 CY2147-45 PC P3 CommercialCY2147-45 DCD4CY2147-45 DMB D4 Military55 CY2147-55 PC P3 CommercialCY2147-55 DCD4CY2147-55 DMB D4 Military2-4

~ CY2147~~~~UcrOR==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3Icc 1,2,3ISB 1,2,3•Switching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAw 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00023-B2-5

CYPRESSSEMICONDUCTORCY2148/CY21L48CY2149/CY21L491024 X 4 Static R/W RAMFeatures• Automated power-down whendeselected (2148)• CMOS for optimum speed/power• Low power- 660 mW (commercial)- 770 mW (military)• 5 volt power supply ± 10%tolerance both commercial andmilitary• TTL compatible inputs andoutputsFunctional DescriptionThe CY2148 and CY2149 are high performanceCMOS static RAMs organizedas 1024 x 4 bits. Easy memoryexpansion is provided by an activeLOW chip select (CS) input, and threestateoutputs. The CY2148 andCY2149 are identical except that theCY2148 includes an automatic (CS)power-down feature. The CY2148 remainsin a low power mode as long asthe device remains unselected, i.e. (CS)is HIGH, thus reducing the averagepower requirements of the device. Thechip select (CS) of the CY2149 doesnot affect the power dissipation of thedevice.An active LOW write enable signal(WE) controls the writing/reading operationof the memory. When the chipselect (CS) and write enable (WE) inputsare both LOW, data on the fourdata input/output pins (1/00 through1/03) is written into the memory locationaddressed by the address presenton the address pins (Ao through A9).Reading the device is accomplished byselecting the device, (CS) active LOW,while (WE) remains inactive or HIGH.Under these conditions, the contents ofthe location addressed by the informationon address pins (Ao through A9) ispresent on the four data input/outputpins (1/00 through 1/03).The input/output pins (1100 through1/03) remain in a high impedance stateunless the chip is selected, and writeenable (WE) is high.Logic Block DiagramPin ConfigurationSTORAGE MATRIXA6VeeA5A7A4AsA3AgAoAl1/0 0I/O,A21/02cs----'---...WE------...DATA BUFFERSCSGNDVss1/0 3WE0015-2Vcc_Vss_1/00 1/030015-1Selection Guide (For Higher Performance and Lower Power Refer to CY7C148/9 Data Sheet)2148/9-35 21L48/9-35 2148/9-45 21L48/9-45Maximum Access Time (ns) 35 35 45 45Maximum Operating I Commercial 140 120 140 120Current (rnA)I Military 1402148/9-55 21L48/9-5555 55140 1201402-6

5'ACY2148/CY21L48... CY2149/CY21L49~ ~UcrOR ~===================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 18 to Pin 9) ..................... -0.5V to + 7.OVDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.OVElectrical Characteristics Over Operating Range[12]DC Input Voltage ................... - 3.0V to + 7.OVOutput Current into Outputs (Low) ............. 20 rnAOperating RangeRangeAmbientVeeTemperatureCommercial O°C to + 70°C 5V ± 10%Military[ll] - 55°C to + 125°C 5V ±1O%Parameters Description Test Conditions21L48/9 2148/9Min. Max. Min. Max.UnitsIOH Output HIGH Current VOH = 2.4V Vee = 4.5V -4 -4 rnATAIOL Output LOW Current VOL == 70°C 8 8O.4VTA = 125°C 8rnAVIH Input HIGH Voltage 2.0 6.0 2.0 6.0 VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 VIIX Input Load Current VSS:::;: VI:::;: Vee -10 10 -10 10 ,."AIOZOutput Leakage GND:::;: Va:::;: VeeCurrentOutput DisabledTA = -55°C to + 125°C -50 50 -50 50 p,ACI Input Capacitance[13]5 5Test Frequency = 1.0 MHzCliOInput/OutputCapacitance[13]TA = 25°C,AllPinsatOV, Vee = 5V 7 7pFleeSupply Current Output OpenTA = - 55°C to + 125°C 140Vee Operating Max. Vee, CS :::;: VIL TA = O°Cto + 70°C 120 140rnAISB Power Down Current CS ~ VIH only TA = - 55°C to + 125°C 30Automatic CS Max. Vee, 2148 TA = O°Cto + 70°C 20 30rnAIpOCurrent CS ~ VIH l3] only TA = -55°C to + 125°C 50Peak Power-On Max. Vee, 2148 TA = O°C to + 70°C 30 50rnAlOSOutput Short GND :::;: Va :::;: VecllO] TA = O°Cto + 70°C ±275 ±275Circuit CurrentTA = - 55°C to + 125°C ±350rnANotes:1. Test conditions assume signal transition times of 10 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IOlJIOH and 30 pF load capacitance. Outputtiming reference is 1.5V.6. At any given temperature and voltage condition, tHZ is less than tLZfor all devices. Transition is measured ± 500 m V from steady statevoltage with specified loading in Figure lb.7. WE is HIGH for read cycle.2. !he internal write time of the memory is defined by the overlap of8. Device is continuously selected, CS = VIL.es LOW and WE LOW. Both signals must be LOW to initiate a9. Address valid prior to or coincident with es transition LOW.write and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the rising10. For test purposes, not more than one output at a time should beedge of the signal that terminates the write.shorted. Short circuit test duration should not exceed 30 seconds.3. A pull up resistor to Vee on the es input is required to keep the11. T A is the "instant on" case temperature.device deselected during Vee power up. Otherwise current will exceedvalues given (eY2148 only).information.12. See the last page of this specification for Group A subgroup testing4. ehip deselected greater than 55 ns prior to selection.13. Tested initially and after any design or process changes that may5. ehip deselected less than 55 ns prior to selection.affect these parameters.AC Test Loads and WaveformsRl481U5VO-------JV~~OUTPUT o-----_------tI30 pF R2255nINCLUDING_JIG AND _- SCOPE -Rl481U5Vo-------~~~OUTPUT 0----..------4I5 pF R2255UINCLUDINGJIG AND-::"SCOPE "::"0015-3Figure laFigure IbEquivalent to:THEVINEN EQUIVALENT167nOUTPUT O~--~"'''''''''~ .. ~--O 1.73V 0015-42-7ALL INPUT PULSES3.0V-----j ....----"""IiGND10 ns 10nsFigure 20015-5II

finCY2148/CY21L48. CY2149/CY21IA9~UaoR================================================================~Switching Characteristics [12]ParametersREAD CYCLEtRCtAAtACSl[4]tACS2[5]tACStLZ[6]tHZ[6]tOHtpDtpuWRITE CYCLEtwctwp[2]tWRtwz[6]tDWtDHtAStcw[2]tow [6]tAWDescriptionAddress Valid to Address Do NotCare Time (Read Cycle Time)Address Valid to Data OutValid Delay (Address Access Time)Chip Select LOW to Data Out Valid(CY2148 only)Chip Select LOW to Data Out Valid(CY2149 only)Chip Select LOW toData Out OnChip Select HIGH to DataOut OffAddress Unknown to Data OutUnknown TimeChip Select HIGH toPower-Down DelayChip Select LOW toPower-Up DelayAddress Valid to Address Do NotCare (Write Cycle Time)Write Enable LOW toWrite Enable HIGHAddress Hold from Write EndWrite Enable LOW to Outputin High ZData in Valid to Write Enable HIGHData Hold TimeAddress Valid to WriteEnable LOWSwitching WaveformsChip Select LOW to WriteEnable HIGHRead Cycle No.1 (Notes 7, 8)ADDRESS _--1Write Enable High to Outputin LowZAddress Valid to End of Write2148/9-35Min.352148 102149 5Max.353545150 2002148 302148 0353050 102000300302148/9-45 2148/9-55Min. Max. Min. Max.Units45 55 ns45 55 ns45 5555 65ns20 25 ns10 105 5ns0 20 0 20 ns5 5 ns30 30 ns0 0 ns45 55 ns35 40 ns5 5 ns0 15 0 20 ns20 20 ns0 0 ns0 0 ns40 50 ns0 0 ns35 50 ns-----J;~~----------------------tRc------------------------~1~___ *________"I_::-_~~-_~~-_~~tO~H~-_=~ __ =t~_A_A:-_;-! _____._,_____________ DATA OUT PREVIOUS DATA VALID DATA VALID----------------------------------0015-62-8

(;ACY2148/CY21L48CY2149/CY21L49~~NDUcrOR =====================================================================Switching Waveforms (Continued)Read Cycle No.2 (Notes 7,9)~--------------------------tRC--------------------------~1-------------tAcs------------~t LZ --!HIGH IMPEDANCEDATAOUT--~~---------lPVcc _____ t _U15 0%SUPPLYCURRENTWrite Cycle No.1 (WE Controlled)I ~Irlllr""'ll'l""t~~-------------+--DATA VALID~----------------------------twc--------------------------~50%HIGHIMPEDANCEt..--ICCIS80015-9fIADDRESS~---------------------t~--------------------~~----------------------tAW-----------------------+~--1+----------tAs----------.,j~-------~P--------~I+--'------tow------..... -DATA 1/0DATA-IN VALID~Z~DATA 1/0 ----------D-AT-A-U-N-D-E-FI-N-ED------->).--....;.;.;.;;,;...;.;.;;.;.;,;;~.;..;;.--~"' _______0015-8Write Cycle No.2 (CS Controlled)I----------------------------~c--------------------------~\C towDATAI/O ---------------iT' L~,;;VAUDDATA I/O DATA UNDEFINED »o_______H_IG_H_IM_P_E.;;.DA_N..;C;.;;;E _______Note: IfCS goes HIGH simultaneously with WE HIGH, the output remains in a HIGH impedance state.0015-72-9

WnCY2148/CY21L48. CY2149/CY21L49~D~OR================================================================Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type Range35 CY2148-35 PC P3 CommercialCY2149-35 PCCY2148-35 DCCY2149-35 DCD4CY21L48-35 PC P3 CommercialCY21L49-35 PCCY21 L48-35 DCCY21L49-35 DC45 CY2148-45 PC P3 CommercialCY2149-45 PCCY2148-45 DCCY2149-45 DCD4D4CY2148-45 DMB D4 MilitaryCY2149-45 DMBCY21 L48-45 PC P3 CommercialCY21L49-45 PCCY21 L48-45 DCCY21 L49-45 DC55 CY2148-55 PC P3 CommercialCY2149-55 PCCY2148-55 DCCY2149-55 DCD4D4CY2148-55 DMB D4 MilitaryCY2149-55 DMBCY21L48-55 PC P3 CommercialCY21L49-55 PCCY21L48-55 DCCY21L49-55 DCD42-10

finCY2148/CY21L48. CYPRFSS CY2149/CY21L49S~IOO~UcrOR==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersIOH 1,2,3IOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3ISB[ll 1,2,3SubgroupsfISwitching CharacteristicsParametersREAD CYCLESubgroupstRC 7,8,9,10,11tAA 7,8,9,10,11tACSl [1] 7,8,9,10,11tACS2[1] 7,8,9,10,11tACS[2] 7,8,9,10,11tOH 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11twp 7,8,9,10,11tWR 7,8,9,10,11tDw 7,8,9,10,11tDH 7,8,9,10,11tAS 7,8,9,10,11tAW 7,8,9,10,11Notes:1. CY2148 only.2. CY2149 only.Document #: 38-00024-B2-11

Features• Automatic power-down whendeselected• CMOS for optimumspeed/power• High speed-35 ns• Low active power- 660 mW• Low standby power-110 mW• TTL compatible inputs andoutputs• Capable of withstanding greaterthan 2001V electrostaticdischargeCYPRESSSEMICONDUCTORFunctional DescriptionThe CY 6116 is a high performanceCMOS static RAM organized as 2048words by 8 bits. Easy memory expansionis provided by an active LOW chipenable (CE), and active LOW outputenable (OE) and three-state drivers.The CY6116 has an automatic powerdownfeature, reducing the power consumptionby 83% when deselected.An active LOW write enable signal(WE) controls the writing/reading operationof the memory. When the chipenable (CE) and write enable (WE) inputsare both LOW, data on the eightdata input! output pins (1/00 through1/07) is written into the memory loca-CY61162048 x 8 Static R/W RAMtion addressed by the address presenton the address pins (Ao through AlO).Reading the device is aqcomplished byselecting the device and enabling theoutputs, CE and OE active LOW,while (WE) remains inactive or HIGH.Under these conditions, the contents ofthe location addressed by the informationon address pins is present on theeight data input/output pins.The input/output pins remain in a highimpedance state unless the chip is selected,outputs are enabled, and writeenable (WE) is HIGH.The CY6116 utilizes a die coat to ensurealpha immunity.Logic Block DiagramPin Configurations1/0 01/011/0 21/0 31/0 40087-21/0 50.. II) CD ..... 0IX>««> «'"CEWEDEA3A2A, Ao1/0 61/070087-1WEA3A2OENCA10NCNCA, NCAoCEI/O, 1/°8N'" C..,. II) CD ,...~~t5~~~~0087-3Selection GuideMaximum Access Time (ns)Maximum OperatingCurrent (rnA)Maximum StandbyCurrent (rnA)CY6116-3535Commercial 120Military 130Commercial 20Military 20CY6116-45 CY6116-5545 55120 120130 13020 2020 202-12

Maximum- Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CStatic Discharge Voltage ..................... > 2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°C to + 70°C 5V ± 10%Output Current into Outputs (Low) ............. 20 rnA Military [4] - 55°C to + 125°C 5V ± 10%VeeElectrical Characteristics Over Operating Range[3]Parameters Description Test ConditionsCY6116-35, 45, 55Min. Max.UnitsVOH Output HIGH Voltage Vee = Min.,IOH = -4.0 rnA 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 VVIH Input HIGH Voltage 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 VIIX Input Load Current GND ~ VI ~ Vee -10 10 p,AlozOutput LeakageGND ~ VI ~ VeeCurrentOutput Disabled10 p,AlOSOutput ShortCircuit Current[1]Vee = Max., VOUT = GND -300 rnAleeVee Operating Vee = Max. Commercial 120Supply CurrentlOUT = OmA Military 130rnAISBAutomatic CE Max. Vee, Commercial 20Power Down Current CE:2: VIHMilitary 20rnAfJICapacitance [2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C,f= 1 MHz 5pFCOUT Output Capacitance Vee = 5.0V 7Notes:1. Not more than 1 output should be shorted at one time. Duration of3. See the last page of this specification for Group A subgroup testingthe short circuit should not exceed 30 seconds.information.2. Tested initially and after any design or process changes that may4. TA is the "instant on" case temperature.affect these parameters.AC Test Loads and WaveformsR1481!l5 V O----~N~ ....OUTPUT 0---.----'"I30 pF R225S!lINCLUDING_ JIG AND _- SCOPE - 0087-4Figure la5VOUTPUTR1481n5pF R2GND255!lIINCLUDING_JIG AND _ALL INPUT PULSES3.0 V-=dt- SCOPE - 0087-5 Figure 2Figure Ibb0087-6Equivalent to:THEVENIN EQUIVALENT16mOUTPUT O----J.-\l.I'\I""". ---0 1.73 V 0087-72-13

~ CY6116~~~~UcrOR ~~~~==~~==~~~~==~~==~====~====~~~~~~==~~~~~Switching Characteristics Over Operating Rangel4, 6]ParametersREAD CYCLEtRCtAAtOHAtACEtDOEtLZOEtHZOEtLZCEDescriptionRead Cycle TimeAddress to Data ValidData Hold from Address ChangeCE LOW to Data ValidOE LOW to Data ValidOE LOW to Low ZOE HIGH to High Z[7]CE LOW to Low Z[8]tHZCE CE HIGH to High Z[7, 8]tputpDWRITE CYCLE[9]twctSCEtAWtHAtSAtpwEtSDtHDtHzwECE LOW to Power UpCE HIGH to Power DowoWrite Cycle TimeCE LOW to Write EodAddress Set-up to Write EodAddress Hold from Write EodAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EodWE LOW to High ZMin.tLZWE WE HIGH to Low Z0Notes:5. Data I/O Pins enter high-impedance state, as shown, when OE isheld LOW during write.6. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IorJIOH and 30 pF load capacitance.7. tHZOE, tHZCE and tHzwE are specified with CL = 5 pF as in Figure1 b. Transition is measured ± 500 m V from steady state voltage.8. At any given temperature and voltage condition, tHZCE is less thantLzCE for any given device.Switching WaveformsRead Cycle No.1 (Notes 10, 11)35505035303000201506116-35 6116-45 6116-55Max. Min. Max. Min. Max.Units45 55 ns35 45 55 ns5 5 ns35 45 55 ns15 20 25 os0 0 os15 15 20 os5 5 os15 20 20 os0 0 os20 25 25 os45 55 os40 40 os40 40 os0 0 os0 0 os20 25 os20 25 os0 0 os15 15 20 os0 0 os9. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.10. WE is HIGH for read cycle.11. Device is continuously selected. OE, CE = VIL'12. Address valid prior to or coincident with CE transition LOW.~~~---------------------------tRC----------------------------~:1.ADDRE~ _~_. _____ I~_::--~~-_=~-_=~~~_H-A~~~~~t~A __A--_.-,------------.-'---_________________________ ~------------------DATA OUT PREVIOUS DATA VALID DATA VALID------------------------------------------------0087-82-14

~ CY6116~~~NDUcrOR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Switching Waveforms (Continued)Read Cycle No.2 (Notes 10, 12)DATA OUT~~ -~J~~tACEtOOEI--tLZOEitRC1""':3I--tHZCE~IMPEDANCEHIGH IMPEDANCE 1/ / / / f VJDATA VALID.. I' , , , , 1\ftLZCEI-----tpo---jf---tpuSUPPLY VCC ______ 50"10CURRENT_HIGHICC=t-IS60087-9IIWrite Cycle No.1 (WE Controlled) (Notes 5, 9)~-------------------------------~C----------------------------~ADDRESS~------------------------tAW------------------------~~---1+-----------tSA--------+i~----tME-----~~~-'----- tso----------o.l...-DATA INDATA-IN VAliDtHZWE~DATA 110 ----------D-A-T-A-U-N-D-E-FI-N-E-D-------- ) ___ ..;.;.;;.;.;.;..;.;;..;;;.;.~;;... __ ~------ 0087-10Write Cycle No.2 (CE Controlled) (Notes 5, 9)~----------------------------~C---------------------------~"--t------------- tSCE -------------.1~----------tMe------------~~__+--------------tso'---------'+-O>--DATA-IN VALIDtHzwe----l-------------------~ HIGH IMPEDANCEDATA 1/0 DATA UNDEFINED /)0-----------------------0087_11Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.2-15

~ CY6116~~~~u~~~~~~~==~==~~~~~~====================================Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.41.211 1.0c.i::c 0.8wN::i /'0.6«2;a:0 0.4z0.20.04.0./IVIS8L4.5 5.0 5.5 6.0SUPPLY VOLTAGE (VINORMALIZED ACCESS TIMEvs. SUPPLY VOLTAGE1.41.3«j 1.2CwN::i 1.1 1-0...«2;a:0 1.0z0.90.84.0........... "-.......TA = 25°C~-4.5 5.0 5.5 6.0SUPPLY VOLTAGE (VI1U!i0wN::::ic:IEa:0z1.21.00.80.60.40.2NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE~IS8~Vee -6.0VVIN - 6.0 V0.0·56 26.0 125.01.6AMBIENT TEMPERATURE (OCINORMALIZED ACCESS TIMEvs. AMBIENT TEMPERATURE1.4 I-----i-------I«$S 1.2 I-----i----~~-IN::::i«~ 1.0 I-----,...~-----Ioz0.8 ~"----i-------t0.6 '------"------.......-55 26 126AMBIENT TEMPERATURE (OCI!"....zwa:a:~(Jw(Ja:~g....~~....~0!"....a:a:~(J:.:ziii....~~....~012010080604020140OUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE~~o0.0'"120Z100w80604020Vee = 5.0 VTA = 25>C'"1.0 2.0 3.0OUTPUT VOLTAGE (VIOUTPUT SINK CURRENTvs. OUTPUT VOLTAGE.-/V/I// I" 4.0Vee = 5.0 VTA = 25°C00.0 1.0 2.0 3.0OUTPUT VOLTAGE (V)4.0j0wN::::i«~a:iTYPICAL POWER·ON CURRENTvs SUPPLY VOLTAGE3.02.52.01.51.00.50.00.0/--- V1.0 2.0 3.0 4.0 5.0SUPPL Y VOL TAG E (VI30.025.0! 20.0«< 15.0......Jl!: 10.05.00.0TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADING~---/L'TAV= 26°CVee = 4.50 V~Vo 200 400 600 800 1000CAPACITANCE (pFI

~ CY6116~~~NDUcrOR ==================================================================~Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type Range35 CY6116-35PC Pll CommercialCY6116-35DC Dl2CY6116-35LC L64CY6116-35DMB D12 MilitaryCY6116-35LMB L6445 CY6116-45PC Pll CommercialCY6116-45DC D12CY6116-45LC L64CY6116-45DMB D12 MilitaryCY6116-45LMB L6455 CY6116-55PC Pll CommercialCY6116-55DC D12CY6116-55LC L64CY6116-55DMB D12 MilitaryCY6116-55LMB L64Address DesignatorsAddressNameAoAlA2A3A4AsA6A7AsA9AlOAddressFunctionY3Y2YIYoX2X4X3XoXsX6XlPinNumber87654321232219IIBitMap.... 0123 3210 ... 32104567 ... 4567 7654 ... 7654-======:"'-ROW1o23125124126----ROW 127*~ REDUNDANT COLUMN# ~REDUNDANTROW0087-132-17

MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3ISB 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tDOE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAw 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00055-B2-18

CYPRESSSEMICONDUCTORCY7C122256 X 4 Static R/W RAMl?eatures• 256 x 4 static RAM for controlstore in high speed computers• CMOS for optimumspeed/power• High speed- 15 ns (commercial)- 25 ns (military)• Low power- 330 mW (commercial)- 495 mW (military)• Separate inputs and outputs• 5 volt power supply ± 10%tolerance both commercial andmilitary• Capable of withstanding greaterthan 2000V static discharge• TTL compatible inputs andoutputsLogic Block DiagramFunctional DescriptionThe CY7C122 is a high performanceCMOS static RAM organized as 256words x 4 bits. Easy memory expansionis provided by an active LOW chip selectone (CSl) input, an active HIGHchip select two (CS2) input, and threestateoutputs.An active LOW write enable input(WE) controls the writing/reading operationof the memory. When the chipselect one (CSl) and write enable (WE)inputs are LOW and the chip selecttwo (CS2) input is HIGH, the informationon the four data inputs Do to D3 iswritten into the addressed memoryword and the output circuitry is preconditionedso that the correct data ispresent at the outputs when the writecycle is complete. This preconditioningoperation insures minimum write recoverytimes by eliminating the "writerecovery glitch."Reading is performed with the chip selectone (CSl) input LOW, the chip selecttwo input (CS2) and write enable(WE) inputs HIGH, and the output enableinput (OE) LOW. The informationstored in the addressed word is readout on the four non-inverting outputs00 to 03.The outputs of the memory go to anactive high impedance state wheneverchip select one (CSl) is HIGH, chip selecttwo (CS2) is LOW, output enable(OE) is HIGH, or during the writingoperation when write enable (WE) isLOW.Pin ConfigurationsA7 03GNO 03AoA1A2A3A4A5A6A7",,,,00 (.)(.)«« z z >A1 4 A4Ao 5 WEAs CS 1AsOEA7 CS 2GNO 9 °3DO 0 30003-2o - _ N NOCOCO 0003-10,election GuideMaximum Access Time (ns)Maximum Operating Current (mA)7C122·15Commercial 15MilitaryNACommercial 90MilitaryNA7C122·25 7C122·3525 3525 3560 6090 902-19

~ CY7C122~~~U~==================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2oo1VAmbient Temperature with (per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latchup Current .......................... > 200 rnASupply Voltage to Ground PotentialPin 22 to Pin 8) ..................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current, into Outputs (Low) ............. 20 rnALogic TableInputsOE CSt CS2 WE Do-D3Operating RangeRangeAmbientTemperatureVeeCommercial O°Cto + 70°C 5V ±1O%Military [5] - 55°C to + 125°C 5V ±1O%OutputsX H X X X HighZ Not SelectedX X L X X HighZ Not SelectedL L H H X 00-0 3 Read Stored DataX L H L L HighZ Write "0"X L H L H HighZ Write "I"H L H H X HighZ Output DisabledNotes:H = HIGH Voltage L = LOW Voltage x = Don't eareHigh Z = High ImpedanceElectrical Characteristics Over the Operating Range[4]7C122-2S7C122-1SParameters Description Test Conditions 7C122·3S UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = - 5.2 rnA 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 VVIR Input HIGH Voltage 2.1 Vee 2.1 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND S VI S Vcc 10 10 /LAVCDIozlosIccInput Diode ClampVoltageOutput Current (High-Z)Output Short CircuitCurrent (Note 1)Power SupplyCurrentVOL S VOUT S VOHOutput DisabledVcc = Max.,VOUT = GNDVcc = Max.,lOUT = OmAModeNote 2 Note 2 V-10 +10 -10 +10 /LACommercial -70 -70 rnAMilitary -80 -80 rnACommercial 90 60 rnAMilitary NA 90 rnACapacitance [3]ParametersCINDescriptionInput CapacitanceCoUTOutput CapacitanceNotes:L For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.2. The CMOS process does not provide a clamp diode. However, theCY7C122 is insensitive to - 3V dc input levels and - 5V undershootpulses ofless than 10 ns (measured at 50% point).Test Conditions Max. UnitsTA = 25°C,f= 1 MHz 4Vee = 5.0V 73. Tested initially and after any design or process changes that mayaffect these parameters.4. See the last page of this specification for Group A subgroup testinginformation.5. T A is the "instant on" case temperature.pF2-20

t!;.nCY7C122~ ~~NDUaOR =======================================================================Switching Characteristics Over the Operating Range[6, 7]ParametersREAD CYCLEtRCtACSDescriptionRead Cycle TimeChip Select TimeTestConditionstZRCS Chip Select to High-Z Note 8tAOSOutput Enable TimetZROS Output Enable to High-Z Note 8tAAAddress Access TimeWRITE CYCLEtwcWrite Cycle Timetzws Write Disable to High-Z Note 8tWRWrite Recovery Timetw Write Pulse Width Note 6tWSDtWHDData Setup Time Prior to WriteData Hold Time After WritetWSA Address Setup Time Note 6tWHA Address Hold Timetwscs Chip Select Setup TimetWHCS Chip Select Hold TimeNotes:6. tw measured at tWSA = min.; tWSA measured at tw = min.7. Test conditions assume signal transition times of 5 ns or less for the- 15 product and 10 ns or less for the - 25 and - 35 product. Timingreference levels of 1.5V and output loading of the specified IorJIOHand 30 pF load capacitance as in Figure 10.BitMapROWO·ROW 31·CY7C122-15 CY7C122-25 CY7C122-35Min. Max. Min. Max. Min. Max.Units15 25 35 ns8 15 25 ns12 20 30 ns8 15 25 ns12 20 30 ns15 25 35 ns15 25 35 ns12 20 30 ns12 20 25 ns11 15 25 ns0 5 5 ns2 5 5 ns0 5 10 ns4 5 5 ns0 5 5 ns2 5 5 ns8. Transition is measured at steady state HIGH level - 500 m V orsteady state LOW level + 500 m V on the output from 1.5V level onthe input with load shown in Figure 1 h.Address DesignatorsAddress Address PinName Function NumberAo AXO 4Al AX1 3A2 AX2 2A3 AX3 1A4 AX4 21As AYO 5A6 AY1 6A7 AY2 7EI0003-32-21

~ CY7C122~~~~UcrOR=======================================================================AC Test Loads and WaveformsAC Test LoadsR1470nOUTPUT5V~1 ':" 224n30 pF R2Input Pulses3.0V-----.... ~ .... ---""'_GNDFigure 20003-5Equivalent to:Figure laTHEVENIN EQUIVALENT152nOUTPUT O~-~·\I~\I .."'".---01.62 VFigure Ib0003-6Read ModeAo-A7ADDRESS~~tAA...,1J1,~~Jif-DATAOUTPUTS00-03tAOSfffffffffl'-""""tACSDATA VALID-----....-tZROS,NOTE 6~:.r-LNOTE6!+-tZACS_0003-7Write ModeAo-A7ADDRESSCS,-CS2CHIP SELECT00-0 3DATA IN-twc-twHA-twHCSJf-I--~(-I---H---tWSA _--it-tWSCS-1'f------ twsotwWE-0-WRITE ENABLE'.tzwsDATA OUTPUTS_-'~----~--(LOADlb -------------------------r'LNOTE6 .~~twHO I---...,"-_twANOTE 600-0 3 ~.r 1_0003-8(All above measurements referenced to 1.5V unless otherwise stated.)Note:Timing diagram represents one solution which results in an optimum cycle time. Timing may be changed in various applications as long as the worst caselimits are not violated.2-22

~ CY7C122~~~~ucr~==================================================================fypical DC and AC Characteristics]SN::::;

~ CY7C122~~~UaoR================================================================Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type Range15 CY7C122-15PC P7 CommercialCY7C122-150C 08 Commercial25 CY7C122-25PC P7 CommercialCY7C122-250C 08 CommercialCY7C122-25LC L53 CommercialCY7C122-250MB 08 Military35 CY7C122-35PC P7 CommercialCY7C122-350C 08 CommercialCY7C122-35LC L53 CommercialCY7C122-350MB 08 MilitaryCY7C122-35LMB L53 Military2-24\ .

~ CY7C122~~~~UcrOR================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3IcC 1,2,3SubgroupsfJI~witching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tACS 7,8,9,10,11tAOS 7,8,9,10,11tAA 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tWR 7,8,9,10,11tw 7,8,9,10,11tWSD 7,8,9,10,11tWHD 7,8,9,10,11tWSA 7,8,9,10,11tWHA 7,8,9,10,11twscs 7,8,9,10,11tWHCS 7,8,9,10,11)ocument #: 38-00025-B2-25

Features• 256 x 4 static RAM for controlstore in high speed computers• CMOS for optimumspeed/power• High speed- 7 ns (commercial)- 15 ns (military)• Low power- 660 mW (commercial)- 825 mW (military)• Separate inputs and outputs• 5 volt power supply ± 10%tolerance both commercial andmilitary• TTL compatible inputs andoutputs• 24 pin• 300 MIL packageCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C123 is a high performanceCMOS static RAM organized as 256words x 4 bits. Easy memory expansionis provided by an active LOW chip selectone (CS1) input, an active HIGHchip select two (CS2) input, and threestateoutputs.An active LOW write enable input(WE) controls the writing/reading operationof the memory. When the ~select one (CS1) and write enable (WE)inputs are LOW and the chip selecttwo (CS2) input is HIGH, the informationon the four data inputs Do to D3 iswritten into the addressed memoryword and the output circuitry is preconditionedso that the write data ispresent at the outputs when the writecycle is complete. This preconditioningoperation insures minimum write re-PRELIMINARYCY7C123256 X 4 Static R/W RAMcovery times by eliminating the "writerecovery glitch."Reading is performed with the chip selectone (CS1) input LOW, the chip selecttwo input (CS2) and write enable(WE) inputs HIGH, and the output enableinput (OE) LOW. The informationstored in the addressed word is readout on the four non-inverting outputs00 to 03.The outputs of the memory go to anactive high impedance state wheneverchip select one (CS1) is HIGH, chip selecttwo (CS2) is LOW, output enable(OE) is HIGH, or during the writingoperation when write enable (WE) isLOW.A die coat is used to insure alpha immunity.Logic Block DiagramPin ConfigurationsA2A3A4ASVeeAIAoWIAsBIA7OfVssveeDo ~20 1 0 3°0 O 2° 1 °3Vss °20088-2~ ~ -

! loz5A PRELIMINARY CY7Cl23. §Y~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 6SoC to + 1S0°CAmbient Temperature withPower Applied .................... - SSoC to + 12SoCOutput Current, into Outputs (Low) ............. 20 rnALatchup Current .......................... > 200 rnAOperating RangeSupply Voltage to Ground PotentialPins 24 & 18 to Pins 7 & 12 ........... -O.SV to + 7.0VAmbientRangeVeeTemperatureDC Voltage Applied to Outputsin High Z State ...................... -O.SV to + 7.0V Commercial O°C to +70°C SV ± 10%DC Input Voltage ................... -3.SV to +7.0V Military [3] - SsoC to + }2S0C SV ± 10%Logic TableInputsOE CSt CS2 WE 00-03OutputsModeX H X X X HighZ Not SelectedX X L X X HighZ Not SelectedL L H H X 00-0 3 Read Stored DataX L H L L HighZ Write "0"X L H L H HighZ Write"}"H L H H X HighZ Output DisabledNotes: H = HIGH Voltage L = LOW Voltage x = Don't CareHigh Z = High ImpedanceElectrical Characteristics Over the Operating Range[4]7C123-7Parameters Description Test Conditions 7C123-127C123-15Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = - S.2 rnA 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 VVIH Input HIGH Voltage 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 VIIX Input Load Current Vss ~ VI ~ Vee 10 10 JLAOutput Current (High-Z)IccCapacitance [2]UnitsVOL ~ VOUT ~ VOH -10 +10 -10 +10 JLAOutput DisabledPower Supply Vee = Max., I Commercial }20 120 rnACurrentlOUT = OmA I Military NA ISO rnAParameters Description Test Conditions Max. UnitsCIN Input Capacitance T A = 2SoC, f = 1 MHz 4pFCOUT Output Capacitance Vcc = S.OV 7"Iotes:I. For test purposes, not more than one output at a time should be3. TA is the "instant on" case temperature.shorted. Short circuit test duration should not exceed 30 seconds.4. See the last page of this specification for Group A subgroup testing!. Tested initially and after any design or process changes that mayinformation.affect these parameters.2-27

Switching Characteristics Over the Operating Range[4]ParametersREAD CYCLEtRCtAAtACStOOEDescriptionRead Cycle TimeAddress Access TimeChip Select TimeOutput Enable TimetHZCS Chip Select to Output Hi-Z Notes 5, 6tHZOE Output Enable to Out Hi-Z Note 5tLZCS Chip Select to Out Low-Z Notes 5, 6tLZOE Output Enable to Out Low-Z Note 5WRITE CYCLEtwctHzwEtLzwEtPWEtsotHOtSAtHAtscsWrite Cycle TimeWrite Enable to Hi-ZWrite Enable to Low-ZWrite Pulse WidthData Setup to End of WriteData Hold Time After WriteAdd Setup to Start of WriteAddress Hold TimeCS Active Low to End of WritetAW Add Setup to End of WriteNotes:5. Transition is measured at steady state HIGH level - 500 m V orsteady state LOW level + 500 mV on the output from 1.5V level onthe input with load shown in Figure J b.Test 7C123-7 7C123-12 7C123-15ConditionsMin. Max. Min. Max. Min. Max.Units7 12 15 ns7 12 15 ns7 8 10 ns7 8 10 ns5 6.5 8 ns5 6.5 8 ns2 2 2 ns2 2 2 ns7 12 15 ns5.5 7 8 ns2 2 2 ns5 8 11 ns5 8 11 ns1 1 1 ns1 2 2 ns1 2 2 ns5 8 11 ns6 10 13 ns6. At any given temperature and voltage condition, tHZCS is less thantLZCS for any given device.2-28

~ PRELIMINARY CY7C123~~~UaoR==================================================================SVi4OUTPUTr -:OUTPUT20pF R2224nAC Test Loads and WaveformsAC Test LoadsFigure 1aInput PulsesRI 470 n RI 470 n 3.0 V-----. ____""'"5V~I5PF- -Figure 1bR2224n0088-4GNDFigure 20088-5Equivalent to: THEVENIN EQUIVALENT152nOUTPUT O~-~·'V~'V"'''', ---0 1.62 VRead Mode0088-6PIADDRESSCS 1 /CS 2OrDATAOUTI' t RCII~ ~tAAIX ::-tACS-~ l_t _ :HZCSt LzcS -- I II I I\: l~tDOE-'I ItLzoE~ l+- I -tHZOE~I I~~~~~~ jI0088-11Write ModeADDRESS__________.J~,________________________________________ ~I'------CS 1 /CS 2WEDATAINDATAOUT'Itwc.'II·IIItAWI,' tHA~0088-12(All above measurements referenced to 1.5V unless otherwise stated.)Note:Timing diagram represents one solution which results in an optimum cycle time. Timing may be changed in various applications as long as the worst caselimits are not violated.tscs.1IXIi >c~------------------------- ~ ,-------------------,..:.----tSA---·..I ...-- t pWE-:~' ______________ .J,(~-------------------~,.~-----I-tSD-----~.:.-tHD~II----------------~~~----------..-----------------;----~~~-----------­- t LZWE -________________-.J)~-------~~~___II2-29

~ PRELIMINARY CY7C123~~~NDU~ ~~~~~~~~~~~~~~~~~~=================================Typical DC and AC CharacteristicsjU2QIIIN::;cr:Iia:0Z1.41.21.00.80.60.4NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE./I~/V~0.2Isa0.04.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (V)NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.21.0~ID..U 0.8~.!:!cIIIN 0.6::;c(:Iia: 0.40Vee: 5.0VzVIN = 5.0 V0.2 ~Isa0.0-55 25.0 125.0AMBIEI\IT TEMPERATURE (OC)~!I-~a:t:r:::lCo)IIICo)t:r:::::lSlI-:la.I-:l09075 ~60453015o oOUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE~Vee = 5.0 VTA : 25·C" ~" ,,~~1.0 2.0 3.0 4.0OUTPUT VOLTAGE (V)

~ PRELIMINARY CY7C123~~~~UcrOR~~~~~~~~~~~~~~~~~==============================Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type Range7 CY7CI23-7PC P13A CommercialCY7C123-70C 014CY7CI23-7LC L5312 CY7C123-12PC P13ACY7C123-120C 014CY7C123-12LC L5315 CY7C123-150MB 014 MilitaryCY7CI23-15LMB L53fI2-31

~ PRELIMINARY CY7C123~,-~======~;=======--~~====================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tACS 7,8,9,10,11tOOE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tPWE 7,8,9,10,11tso 7,8,9,10,11tHO 7,8,9,10,11tSA 7,8,9,10,11tHA 7,8,9,10,11tscs 7,8,9,10,11tAw 7,8,9,10,11Document :#: 38-OOO60-B2-32

Features• Automatic power-down whendeselected• CMOS for optimumspeed/power• High speed-25 ns• Low active power- 660 mW (commercial)- 825 mW (military)• Low standby power-110 mW• SOIC package• TTL compatible inputs andoutputs• Capable of withstanding greaterthan 2000V electrostaticdischargeCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7Cl28 is a high performanceCMOS static RAM organized as 2048words by 8 bits. Easy memory expansionis provided by an active LOW chipenable (CE), and active LOW outputenable (OE) and three-state drivers.The CY7Cl28 has an automatic powerdownfeature, reducing the power consumptionby 83% when deselected.An active LOW write enable signal(WE) controls the writing/reading operationof the memory. When the chipenable (CE) and write enable (WE) inputsare both LOW, data on the eightdata input/output pins (1/00 through1/07) is written into the memory loca-CY7C1282048 x 8 Static R/W RAMtion addressed by the address presenton the address pins (Ao through AlO).Reading the device is accomplished byselecting the device and enabling theoutputs, CE and OE active LOW,while (WE) remains inactive or HIGH.Under these conditions, the contents ofthe location addressed by the informationon address pins is present on theeight data input/ output pins.The input/ output pins remain in a highimpedance state unless the chip is selected,outputs are enabled, and writeenable (WE) is HIGH.The 7Cl28 utilizes a die coat to ensurealpha immunity.IILogic Block DiagramPin Configurations1/0 01/011/0 21/0 31/041/0 5&0 fD,.... () co«

~ CY7C128. ~~NDUCTOR ==========================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°e to + 150 0 e Static Discharge Voltage ..................... > 2001 VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°e to + 125°e Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current into Outputs (Low) ............. 20 rnAElectrical Characteristics Over Operating Range[3]Operating RangeRangeAmbientTemperatureVeeCommercial O°C to + 70°C 5V ± 10%Military [4) - 55°C to + 125°C 5V ± 10%7C128Parameters Description Test ConditionsMin. Max.UnitsVOH Output HIGH Voltage Vee = Min., IOH = - 4.0 mA 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 VCommercial-25, Military -35 2.2 Vee VVIHInput HIGH VoltageAll Others 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 VIIX Input Load Current GND::;; VI::;; Vee -10 10 /-t AOutput LeakageGND::;; VI::;; VeeIOZ-40 40CurrentOutput Disabled/-t AlosOutput ShortCircuit Current(1)Vee = Max., VOUT = GND -300 rnAIcc Vee Operating Vee = Max. Commercial -25, -35, -45 120 rnASupply Current lOUT = OmA Commercial -55 90 rnAISB*35 liS and 55 ns onlyCapacitance [2]Military -35 150 rnAMilitary -45 130 rnAMilitary -55 100 rnAAutomatic CE Max. Vee, Commercial 20Power Down Current CE 2 VIH Military * 20Parameters Description Test Conditions Max. UnitsCIN Input Capacitance T A = 25°C, f = 1 MHz 5COUT Output Capacitance Vee = 5.0V 7pFNotes:1. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.3. See the last page of this specification for Group A subgroup testinginformation.2. Tested initially and after any design or process changes that mayaffect these parameters.4. T A is the "instant on" case temperature.AC Test Loads and WaveformsRl481n5V~------~~~~OUTPUT 0-----... ------4Equivalent to:I30 pF R2255nINCLUDING_ JIGAND _- SCOPE - 0036-4Figure laTHEVENIN EQUIVALENT16mOUTPUT 0-----""' .. 11 .. 11"'_--0 1.73 V 0036-13Rl481n5 V o-------....... 'V'l,..,..--.OUTPUT 0-----... ------......5pF,NCLUD,NGI _JIG AND_- SCOPE -Figure lb2-34R2255n0036-5ALL INPUT PULSES3.0V-~----j~~ __ ~~%GNO -;;::f'i:rnA~ ~Figure 20036-6

tzCY7C128~~~~UcrOR =====================================================================Switching Characteristics Over Operating Range[3, 6]ParametersREAD CYCLEDescription7C128-25Min.tRC Read Cycle Time 25tAAAddress to Data ValidtOHA Data Hold from Address Change 3tACEtDOECE LOW to Data ValidOE LOW to Data ValidtLzOE OE LOW to Low Z 0tHZOEOE HIGH to High Z[7]tLZCE CE LOW to Low Z[S] 5tHZCE CE HIGH to High Z[7, S]tpu CE LOW to Power Up 0tPDWRITE CYCLE[9]CE HIGH to Power Downtwc Write Cycle Time 25tSCE CE LOW to Write End 20tAW Address Set-up to Write End 20tHA Address Hold from Write End 0tSA Address Set-up to Write Start 0tPWE WE Pulse Width 20tSD Data Set-up to Write End 10tHD Data Hold from Write End 0tHZWEWE LOW to High Z[7]tLzwE WE HIGH to Low Z 0Notes:5. Data I/O Pins enter high-impedance state, as shown, when OE isheld LOW during write.6. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified lor/IOH and 30 pF load capacitance.7. tHZOE, tHzCE and tHzwE are specified with CL = 5 pF as in Figure1 b. Transition is measured ± 500 m V from steady state voltage.S. At any given temperature and voltage condition, tHzCE is less thantLZCE for any given device.Switching WaveformsRead Cycle No.1 (Notes 10, 11)Max.252512121220107C128-35 7C128-45 7C128-55Min. Max. Min. Max. Min. Max.Units35 45 55 ns35 45 55 ns5 5 5 ns35 45 55 ns15 20 25 ns0 0 0 ns15 15 20 ns5 5 5 ns15 20 20 ns0 0 0 ns20 25 25 ns35 45 55 ns30 40 50 ns30 40 50 ns0 0 0 ns0 0 0 ns20 20 25 ns15 20 25 ns0 0 0 ns15 15 20 ns0 0 0 ns9. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.10. WE is HIGH for read cycle.II. Device is continuously selected. OE, CE = VIL.12. Address valid prior to or coincident with CE transition LOW.~~~--------------------------tRC----------------------------~:1~ADDRE~_~ ______ ~I_::-_~~-_:~-_=~~~_H-_A-_~-_-_~t-A__A--_.-,------------I-!----------------------------~-----------------------------------------------------------0036-7DATA OUT PREVIOUS DATA VALID DATA VALID2-35

~ CY7C128~~~NDU~ =====================================================================Switching Waveforms (Continued)Read Cycle No.2 (Notes 10, 12)DATA OUT~k- 1\~~j..-tputACEtOOEf--tLZOEitRCHIGH IMPEDANCE 1/ / / / / IftLZCEVce ]SUPPL Y ______ 50010CURRENT_.~ \. \. \. \. 1\DATA VALIDl'~'M:3]'1-f---tHZCE-I---tpoHIGHIMPEDANCE/--1 ICCSO;~!'-IS80036-8Write Cycle No.1 (WE Controlled) (Notes 5, 9)~-----------------------------twc---------------------------~ADDRESS~------------ tSCE -------------------'~----------------------tAW----------------------~~---14-------tSA-----------..i~-------t~E--------~--------------------~~~I14----'------tso-----.-I-_DATA INDATA-IN VALIDDATA 110 ----------D-A-T-A-U-N-D-EF-I-N-ED--------tHZWE~)). __ "';';';';;;~';;"::;;';;'= __ .....ij,-_____ _0036-9Write Cycle No.2 (CE Controlled) (Notes 5, 9)~----------------------------twc---------------------------.---t--------- tSCE ---------+114--------t~E----------~~__+--------------tso'-------I--DATA-IN VALIDtHZWE---l------------------~ HIGH IMPEDANCEDATA I/O DATA UNDEFINED J)o-----------~-.;.;...;.;.;;.;;...------0036-10Note: IfeE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.2-36

Typical DC and AC Characteristics~~cwN::;

~ CY7C.~28~~~~~~~~=;=;=;=;=;=;=;~~=;~~=;=;=;=;=;=;=;=;~=;===;========Ordering InformationSpeed(ns)Ordering CodePackageType25 CY7C128-25PC P13CY7C128-25SC S13CY7C128-250C 014CY7C128-25LC L5335 CY7C 128-35PC P13CY7C128-35SC S13CY7C128-350C 014CY7C128-35LC L53CY7C128-350MB 014CY7CI28~35LMB L5345 CY7C128-45PC P13CY7C128-45SC S13CY7C128-450C 014CY7C 128-45LC L53CY7C128-450MB 014CY7CI28-45LMB L5355 CY7C128-55PC P13CY7C128-55SC S13CY7C128-550C 014CY7C128-55LC L53BitMapCY7CI28-55DMB 014CY7CI28-55LMB L53OperatingRangeCommercialCommercialMilitaryCommercialMilitaryCommercialMilitaryAddress Designators4581 .. 4567 7654 ... 7654AddressNameAoAlA2A3A4AsA6A7AsA9AlOAddressFunctionY3Y2YIYoX2X4X3XoXsX6XlPinNumber87654321232219125124126---!IJWI27# *',REDUNDANTCDlUMN~REDUNDANTRDW0036-122-38

MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3Icc 1,2,3ISB 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tOOE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpWE 7,8,9,10,11tso 7,8,9,10,11tHO 7,8,9,10,11Document #: 38-00026-B2-39

Features• 0.8 micron CMOS for optimumspeed/power• Automatic power-down• TIL compatible• Capable of withstanding greaterthan 2001V electrostaticdischarge• Fully asynchronous operation• Master CY7C130 easily expandsdata bus width to 16 or morebits using SLAVE CY7CI40• BUSY output flag on CY7C130;BUSY input on CY7C140• INT flag for port to portcommunicationCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C130/CY7C140 are highspeed CMOS lK x 8 Dual Port StaticRAMS. Two ports are provided permittingindependent access to any locationin memory. The CY7C130 can beutilized as either a stand-alone 8-bitDual Port Static RAM or as a MAS­TER Dual Port RAM in conjunctionwith the CY7C140 SLAVE Dual Portdevice in systems requiring 16-bit orgreater word widths. It is the solutionto applications requiring shared orbuffered data such as cache memoryfor DSP, Bit-Slice, or multiprocessordesigns.Each port has inde~dent controlpins; Chip Enable (CE), Write EnablePRELIMINARYCY7C130CY7C1401024 X 8 Dual PortStatic RAM(WE), and Output Enable (OE). Twoflags are provided on each port, BUSYand INT. BUSY signals that the port istrying to access the same location currentlybeing accessed by the other port.!NT is an interrupt flag indicating thatdata has been placed in a unique locationby the other port. An automaticpower down feature is controlled independentlyon each port by the Chip Enable(CE) pin.The CY7C130/CY7C140 are availablein both 48-pin DIP, 48-pin LCC and52-pin PLCC.A die coat is used to insure alpha immunity.Logic Block DiagramPin ConfigurationR/WRfERIj0 7L ----L.:::....t-L::....::......JBUSYL(1) +--~------'ASL ---Hr::::::::---.AOL---t-+L...."":':"..JOE RA9RASRIjOSRI/07RBUSY R (1)ASRAORA7RINTL(2) +-----------'Notes:1. CY7C130 (Master): BUSY is open drain output and requires pullup resistor.CY7Cl40 (Slave): BUSY is input.2. Open drain outputs: pullup resistor required.0114-1DIPTop View0114-2Selection Guide7C130-25 7C130-357Cl40-25 7Cl40-35Maximum Access Time (ns) 25 35Maximum Operating Commercial 120 90Current (rnA)Military 120Maximum Standby Commercial 30 30Current (rnA)Military 407C130-457Cl40·45459012030407C130-557Cl40·55559012030402-40

5ACY7C130PRELIMINARY CY7C140' ~~NDUcrOR~~~~~~~~~~~==~=============================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 48 to Pin 24) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VStatic Discharge Voltage ..................... > 2001V(Per MIL-STD-883 Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.5V to + 7.0V Commercial O°Cto + 70°C 5V ±1O%Output Current into Outputs (Low) ............. 20 rnA Military [7] - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over Operating Range[8]7C130-25 7C130-35, 45, 55Parameters Description Test Conditions 7Cl40-25 7C140-35, 45, 55 UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = -4.0 rnA 2.4 2.4 VVOLOutput LOW VoltageIOL = 4.0 rnA 0.4 0.4IOL = 16.0 mA[6] 0.5 0.5VIH Input HIGH Voltage 2.2 2.2 VVIL Input LOW Voltage 0.8 0.8 VIIX Input Load Current GND s: VI s: Vee -5 +5 -5 +5 p,AIozlosleeISBOutput LeakageCurrentOutput Short[3]Circuit CurrentGND s: Vo s: VeeOutput DisabledVee = Max.,VOUT = GNDVee-5 +5 -5 +5 p,A-350 -350 rnAVee Operating Vee = Max. Commercial 120 90Supply CurrentlOUT = OmAMilitary 120Automatic CE[4]Power Down CurrentISBl Both Ports, TTL Inputs Commercial 30 30 rnAISB2 One Port, TTL Input 75 75 rnAISB3 Both Ports, CMOS Inputs 15 15 rnAISB4 One Port, CMOS Inputs 65 65 rnAISBI Both Ports, TTL Inputs Military 40 rnAISB2 One Port, TTL Input 100 rnAISB3 Both Ports, CMOS Inputs 30 rnAISB4 One Port, CMOS Inputs 80 rnACapacitance [5]Parameters Description Test Condtions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 10COUTOutput CapacitanceVee = 5.0V10Notes:3. Duration of the short circuit should not exceed 30 seconds. 6. BUSY and INT pins only.4. A pull-up resistor to Vee on the CE input is required to keep the7. TA is the "instant on" case temperature.device deselected during Vee power-up, otherwise ISB will exceedvalues given.5. Tested initially and after any design or process changes that mayaffect these parameters.pFVrnA8. See the last page of this specification for Group A subgroup testinginformation.2-41

(;nCY7C130PRELIMINARY CY7C140~~NDUcrOR ==~~~~========~========~~~~==~==~~~~~~~~~~~~~AC Test Loads and WaveformsEquivalent to:R1893n5Vo---------~~~OUTPUT 0-----..-----...'NCLUD'NGI30 pFJIG ANDSCOPEFigure 1R23470THEVENIN EQUIVALENTOUTPUT O-----A"R189305Vo-------~~~OUTPUT 0----..... -----..'NCLUD'NlJIG ANDSCOPE -:Figure 25 pF0114-7R234700114-5sv_~280.nBUSYORiNTI 30P F'0114-4Figure 3. BUSY Output Load(CY7C130 Only)ALL INPUT PULSES3.0V----j!.'""""' ___ ~GNDSwitching Characteristics Over Operating RangerS, 1017C130-25 7C130-35Parameters Description 7C140-25 7C140-35READ CYCLEMin. Max. Min. Max.tRC Read Cycle Time 25 35tAA Address to Data Valid 25 35tOHA Data Hold from Address Chaoge 2 3tACE CE LOW to Data Valid 30 35tDOE OE LOW to Data Valid 15 15tLZOE OE LOW to Low Z 2 3tHzOE OE HIGH to High Z[II] 15 15tLzCE CE LOW to Low Z[12] 2 5tHZCE CE HIGH to High Z[II, 12] 15 15tpu CE LOW to Power Up 0 0tPD CE HIGH to Power Dowo 20 20WRITE CYCLE[13]twc Write Cycle Time 25 35tSCE CE LOW to Write Eod 20 30tAW Address Set-up to Write Eod 20 30tHA Address Hold from Write End 2 2tSA Address Set-up to Write Start 0 0tpwE WE Pulse Width 15 20tSD Data Set-up to Write Eod 15 15tHD Data Hold from Write Eod 0 0tHZWE WE LOW to High Z 15 15tLzwE WE HIGH to Low Z 0 0Figure 40114-67C130-45 7C130-557C140-45 7C140-55 UnitsMin. Max. Min. Max.45 55 os45 55 os3 3 os45 55 os20 25 os3 3 os20 25 os5 5 os20 25 os0 0 os25 30 os45 55 os35 40 os35 40 os2 2 os0 0 os20 25 os20 20 os0 0 os20 25 os0 0 os2-42

• ~CY7C130. PRELIMINAR Y CY7C140~~NDUcrOR =======================================================================Switching Characteristics Over Operating Range[8, 10] (Continued)7C130-25 7C130-35 7C130-45 7C130-55ParametersDescription7C140-25 7Cl40-35 7C140-45 7C140-55 UnitsMin. Max. Min. Max. Min. Max. Min. Max.BUSY/INTERRUPT TIMINGtRC Read Cycle Time25 35 45 55nstwc Write Cycle Time25 35 45 55nstBLA BUSY LOW from Address Match15 20 25 30 nstBHA BUSY HIGH from Address Mismatch20 20 25 30 nstBLC BUSY LOW from CE LOW20 20 25 30 nstBHC BUSY HIGH from CE HIGH20 20 25 30 nstps Port Set Up for Priority5 5 5 5nstWINS WE to INTERRUPT Set Time12 15 20 25 nstEINS CE to INTERRUPT Set Time20 25 35 45 nstiNS Add to INTERRUPT Set Time20 25 35 45 nstOINR OE to INTERRUPT Reset Time15 15 20 25 nstEINR CE to INTERRUPT Reset Time20 25 35 45 nstlNR Add to INTERRUPT Reset Time20 25 35 45 nsBUSY TIMINGtWB* WE LOW after BUSY0 0 0 0nstWH WE HIGH after BUSY10 15 15 15nstBDD BUSY HIGH to Valid Data20 20 25 30 nstDDD Write Data Valid to Read Data Valid Note 17 Note 17 Note 17 Note 17 nstWDD Write Pulse to Data DelayNote 17 Note 17 Note 17 Note 17 ns• CY7C140 OnlyNotes:9. Data 1/0 pins enter high impedance state, as shown when OE is held 14. WE is HIGH for read cyele.LOW during write.15. Device is continuously selected OE, CE = VIL.10. Test conditions assume signal transition times of 5 ns or less, timing 16. Address valid prior to or coincident with CE transition LOW.reference levels of 1.5V, input pulse levels ofOV to 3.0V and output 17. A write operation on Port A, where Port A has priority, leaves theloading of the specified lorJIOH and 30 pF load capacitance.data on Port B's outputs undisturbed until one access time after one11. tHZOE, tHzCE, and tHZWE are specified with CL = 5 pF in Figure 2.of the following:Transition is measured ± 500 mV from steady state voltage.A. BUSY on Port B goes HIGH.12. At any given temperature and voltage condition, tHZCE is less thanB. Port B's address toggled.tLZCE for any given device.C. CE for Port B is toggled.13. The internal write time ofthe memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate aD. WE for Port B is toggled.write and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.Switching WaveformsRead Cycle No.1 (Notes 14, 15)Either Port Address AccessADDRE§=b_t:=====~-------------------------tRC------------------------~~~.."___tIDATA OUT PREVIOUS DATA VALID DATA VALID0114-82-43

5IlCY7C130.. PRELIMINARY CY7C140~~~UcrOR~================================================================Switching Waveforms (Continued)Read Cycle No.2 (Notes 14, 16)DATA OUTICCEither Port CE/OE Access'1\ ),..I t ACE I--tHZCE -~I\.ItooEt HZOEI-tLZOE -I---t LZCE---HIIIIII/IIIIII~\.\.\.\.\."'.\.\.\.\.\."tpu- - I--tpD'IDATA VALIDIS8 ______ ~I1-----Timing Waveform of Read with BUSY (Note 14)0114-9ADDRESS RADDRESS MATCH)~ADDRESS LADDRESSMATCHBUSY LDOUT LtWDD~-It800-- -~IlVALID-tO~~0114-10Write Cycle No.1 (Notes 9, 13)Either PorttwcADDRESS f-~.1\. \. \. \.~I----- tSA ---"1tSCEtAW tHA --t pWE----;'f.777 17///~-\.-\: -;'f.tSDtHO I1""I.1DATA VALID ~///~ ~\.\.\.'\. '\. '\. '\. '\. '\. ~ HIGH IMPEDANCEDOUT IIIIII..L0114-122-44

finCY7C130. CYPRESS PRELIMINAR Y CY7C140~oo~u~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==~~Switching Waveforms (Continued)Write Cycle No.2 (Notes 9, 13)Either Porttwc-ADDRESS f- 1[DATAOUTLtHA-tSCE\.\.\ \.\.~{1"-/ / / fT /7tAW- tSA----J tpWE~\. ~ 1'-tHO~tso.1 DATA VALID II-- t HZWE --j !--tLZWE -HIGH IMPEDANCE" " " " " " " " " " " " " "k' I II I I I I I I I I I I I I -z-... " " II-0114-13Busy Timing Diagram No.1 (CE Arbitration)CEL Valid First:ADDRESS ::::)(LAND RCE Lt'bADDRESS MATCHCE Rt BLC =1BUSY R0114-14ttB"CjXCER Valid First:ADDRESS ::::)(LAND RCE Rt'bADD~ESS MATCHCE Lt BLC =1BUSY L0114-15ttB"CjX2-45

5ACY7C130.' PRELIMINAR Y CY7C140~~UaoR========~==~~~~~~~~~~~~~~~~~~~~~============Switching Waveforms (Continued)Busy Timing Diagram No.2 (Address Arbitration)Left Address Valid First:ADDRESS L --'''''''1"'---------""'1'tBLA=tADDRESS MISMATCH.....-------"ADDRESS R -----....I'I'-----~-+----~-------'tBHAJRight Address Valid First:0114-16t RC OR twcADDRESS R __"""'1"'-________""'1'....._______ ADDRESS MISMATCH "ADDRESSL _____ ....I'I~ ______ _+-----------""'"tBLA=ttBHAJBusy Timing Diagram No.3Write with BUSY (Slave: CY7Cl40):-,t~-------------tpwE----------~--~~-----BU:: -t_tw_B_~ ___________ r=tw~ ~0114-110114-172-46

5nCY7C130. CYPRESS PRELIMINAR Y CY7C140s~CO~UcrOR==================================================================Switching Waveforms (Continued)Interrupt Timing DiagramsLeft Side Sets INTR:ADDRl----'I-------------------~~~----------JWE l0114-18Right Side Clears INTR:fIRight Side Sets INTVINTR ______________________________________ '1 0114-19~----------twc--------~ADDRR ____ JI'~ ____ ~--------------~~~-------------J'-------0114-20Left Side Clears INTV------~*--________________________________-JIINTl0114-212-47

WnCY7C130. . PRELIMINAR Y CY7C140. ~DUCl'OR =====;;;;;;;::======================================Pin Configurations~ ...JItit! .;:jl~~lt ~~I~...J~ltTl~ ~I{~6 5 4 3 2 1 1 525150494847AILA2L46 O'ERAORA1RA3LA4LASLASL 41A7L 14ASL 15A9L 16I/OOL 171/0lL 181/ 0 2L 19A2RA3RA4RASRASRA7RASRA9RNCI/ 0 3L I/0 7R21222324252627282930313233A1LA2LA3LA4LASLASLA7LASLA9LI/OOLI/ O ILl/a 2 L3231192021222324252627282930AORA1RA2RA3RA4RASRA6RA7RASRA9RI/0 7RI/ 0 6RPLCCTop View0114-3LCCTop View0114-22Ordering InformationSpeed Ordering Package(ns) Code Type25 CY7C 130-25PC P25CY7C130-25DCCY7C 130-25LCCY7C130-25JCD26L68J6935 CY7C130-35PC P25CY7C130-35DCCY7C 130-35LCCY7C130-35JCCY7C130-35DMBCY7C130-35LMBD26L68J69D26L6845 CY7C130-45PC P25CY7C 130-45DCCY7C130-45LCCY7C130-45JCCY7C130-45DMBCY7C130-45LMBD26L68J69D26L6855 CY7C130-55PC P25CY7C130-55DCCY7C130-55LCCY7C130-55JCCY7C130-55DMBCY7C130-55LMBD26L68J69D26L68OperatingRangeCommercialCommercialMilitaryCommercialMilitaryCommercialMilitarySpeed(ns)25354555OrderingCodeCY7Cl40-25PCCY7Cl40-25DCCY7Cl40-25LCCY7Cl40-25JCCY7Cl40-35PCCY7Cl40-35DCCY7Cl40-35LCCY7Cl40-35JCCY7Cl40-35DMBCY7Cl40-35LMBCY7Cl40-45PCCY7Cl40-45DCCY7Cl40-45LCCY7Cl40-45JCCY7Cl40-45DMBCY7C1 4O-45LMBCY7Cl40-55PCCY7Cl40-55DCCY7Cl40-55LCCY7Cl40-55JCCY7Cl40-55DMBCY7Cl40-55LMBPackageTypeP25D26L68J69P25D26L68J69D26L68P25D26L68J69D26L68P25D26L68J69D26L68OperatingRangeCommercialCommercialMilitaryCommercialMilitaryCommercialMilitary2-48

5nCY7C130__. PRELIMINARY CY7C140~ ~aIDUcrOR================================================================~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIR 1,2,3VIL 1,2,3IIX 1,2,3loz 1,2,3los 1,2,3Icc 1,2,3ISBI 1,2,3ISB2 1,2,3ISB3 1,2,3SubgroupsParametersISB4 1,2,3SubgroupsIISwitching CharacteristicsParametersREAD CYCLESubgroupstAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tDOE 7,8,9,10,11WRITE CYCLEtSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11BUSY/INTERRUPTTIMINGtBLA 7,8,9,10,11tBHA 7,8,9,10,11tBLC 7,8,9,10,11tBHC 7,8,9,10,11tps 7,8,9,10,11tWINS 7,8,9,10,11tEINS 7,8,9,10,11tINS 7,8,9,10,11I'Note:11. CY7Cl40 only.Document #: 38-00027-BParametersBUSY/INTERRUPTTIMING (Continued)SubgroupstOINR 7,8,9,10,11tEINR 7,8,9,10,11tINR 7,8,9,10,11BUSY TIMINGtWB[l] 7,8,9,10,11tWH 7,8,9,10,11tBDD 7,8,9,10,11tDDD 7,8,9,10,11tWDD 7,8,9,10,112-49

Features• 0.8 micron CMOS for optimumspeed/power• Automatic power· down• TTL compatible• Capable of withstanding greaterthan 2001 V electrostaticdischarge• Fully asynchronous operation• MASTER CY7C132 easilyexpands databus width to 16 ormore bits using SLA VECY7C142• BUSY output flag on CY7C132;BUSY input on CY7C142• INT flag for port to portcommunication (LCC version)CYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C132/CY7CI42 are highspeed CMOS 2K x 8 Dual Port StaticRAMs. Two ports are provided permit·ting independent access to any locationin memory. The CY7C132 can be utilizedas either a stand-alone 8-Bit DualPort RAM or as a MASTER DualPort RAM in conjunction with theCY7Cl42 SLAVE Dual Port device insystems requiring 16-Bit or greaterword widths. It is the solution to applicationsrequiring shared or buffereddata such as cache memory for DSP,bit-slice or multiprocessor designs.Each port has independent controlpins; Chip Enable (CE), Write Enable(WE), and Output Enable (OE). BUSYflags are provided on each port. In ad-PRELIMINARYCY7C132CY7C1422048 X 8 Dual PortStatic RAMdition, an interrupt flag (INT) is providedon each port of the LCC version.BUSY signals that the port is trying toaccess the same location currently beingaccessed by the other port. On theLCC version, INT is an interrupt flagindicating that data has been placed ina unique location by the other port.An automatic power-down feature iscontrolled independently on each portby the Chip Enable (CE) pin.The CY7C132/CY7CI42 are availablein both 48-pin DIP, 48-pin LCC and52-pin PLCC.A die coat is used to insure alpha immunity.Logic Block DiagramPin ConfigurationOE lA10lA7l :==~~12I/OOl ---...... ..--:-..... .--........OERr-;::::::tl--- A10Rr-f't--- A7R"--+'r==~r=~':t---- I/0 9RCE lR!WlBUSY lA 10lOE l 5I/07l ---~L.=:...J-L~~BUSYl(1) +--_------'M l (2.6)AOl ---+-+L...........-JL.:~--..HL.=:...J--+---- I/07R'-----.---+ BUSYR(1)r:::::-l+,f--- ASRL...:..:.=-...J+'+--- AORiNi'R(2,6)Notes: 0106-11. CY7C132 (MASTER): BrSY is open drain output and requires pullup resistor.CY7C142 (SLAVE): BU Y is input.2. Open drain outputs: pullup resistor required.Selection Guide7C132·257C142·257C132·357C142·35Maximum Access Time (ns) 25 35Maximum Operating Commercial 120 90Current (rnA) Military 120Maximum Standby Commercial 30 30Current (rnA) Military 40A2RA3RA4RA5RASRA7RASRA9RI/07R31 I/OSRI/05RI/0 4RI/03RI/02RI/01RI/OORDIP 0106-2Top View7C132·457C142·457C132·557C142·5545 5590 90120 12030 3040 402·50

iACY7C132..; PRELIMINARY CY7C142~ ~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=\.1aximum RatingsAbove which the useful life may be impaired. For user guidelines, not tested.)Itorage Temperature ............... - 65°C to + 150°C\.mbient Temperature with)ower Applied .................... - 55°C to + 125°C;upply Voltage to Ground PotentialPin 48 to Pin 24) .................... -0.5V to + 7.0V)C Voltage Applied to Outputsn High Z State ...................... -0.5V to + 7.0VStatic Discharge Voltage ..................... > 2001 V(per MIL-STD-883 Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeAmbientTemperature)CInputVoltage ................... -3.5Vto +7.0V Commercial O°C to + 70°C 5V ± 10%)utput Current into Outputs (Low) ............. 20 rnA Military[S] - 55°C to + 125°C 5V ± 10%Vee8;lectrical Characteristics Over Operating Rangd9]7C132-2S 7C132-35, 45, 55Parameters Description Test Conditions 7C142-25 7C142.35, 45, SS UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = -4.0mA 2.4 2.4VIOL = 6.0 rnA 0.40.4VOL Output LOW VoltageIOL = 8.0 rnA 0.50.5VIOL = 16.0 mA[7] 0.50.5VIH Input HIGH Voltage 2.2 2.2VVIL Input LOW Voltage 0.80.8 VIIX Input Load Current GND::;: VI::;: Vee -5 +5 -5 +5 J-lAlozlOSleeOutput LeakageCurrentOutput Short [3]Circuit CurrentGND::;: Vo::;: VeeOutput DisabledVee = Max.,VOUT = GND-5 +5 -5-350Vee Operating Vee = Max. Commercial 120Supply CurrentlOUT = OmAMilitaryISB Automatic CE [4]Power Down CurrentISBI Both Ports, TTL Inputs Commercial 30ISB2 One Port, TTL Input 75ISB3 Both Ports, CMOS Inputs 15ISB4 One Port, CMOS Inputs 65ISBI Both Ports, TTL Inputs MilitaryISB2 One Port, TTL InputISB3 Both Ports, CMOS InputsISB4 One Port, CMOS Inputs+5 J-lA-350 rnA90120rnA30 rnA75 rnA15 rnA65 rnA40 rnA100 rnA30 rnA80 rnAtil;apacitance [5]Parameters Description Test Conditions Max.CIN Input Capacitance T A = 25°C, f = 1 MHz 10COUTOutput CapacitanceVCC = 5.0V10:otes:Duration of the short circuit should not exceed 30 seconds.A pull-up resistor to Vee on the CE input is required to keep thedevice deselected during Vee power-up, otherwise ISB will exceed, values given.Tested initially and after any design or process changes that mayaffect these parameters.Units6. LCC version only.7. BUSY and INT pins only.S. TA is the "instant on" case temperature.9. See the last page of this specification for Group A subgroup testinginformation.pF2-51

5nCY7C132.. PRELIMINARY CY7C142~~NDUcrOR=======================================================================AC Test Loads and WaveformsR144805Vo---------~~~OUTPUT 0------...------....Equivalent to:INCLUDINGI30 pFJIG ANDSCOPEFigure 1R224500106-4THEVENIN EQUIVALENT1580OUTPUT O-----..J

tWACY7C132. PRELIMINARY CY7C142~U~================================================================Switching Characteristics Over Operating Range [9, 11] (Continued)7C132-25 7C132-35 7C132-45 7C132-55Parameters Description 7C142-25 7C142-35 7C142-45 7C142-55BUSY/INTERRUPT TIMINGMin. Max. Min. Max. Min. Max. Min. Max.tRc Read Cycle Time 25 35 45 55twc Write Cycle Time 25 35 45 55tBLA BUSY LOW from Address Match 15 20 25 30tBHA BUSY HIGH from Address Mismatch 20 20 25 30tBLC BUSY LOW from CE LOW 20 20 25 30tBHC BUSY HIGH from CE HIGH 20 20 25 30tps Port Set-Up for Priority 5 5 5 5tWINS WE to INTERRUPT Set Time 12 15 20 25tEINS CE to INTERRUPT Set Time 20 25 35 45tINS Add to INTERRUPT Set Time 20 25 35 45tolNR OE to INTERRUPT Reset Time 15 15 20 25tEINR CE to INTERRUPT Reset Time 20 25 35 45tINR Add to INTERRUpT Reset Time 20 25 35 45BUSYTIMINGtWB* WE LOW after BUSY 0 0 0 0tWH WE HIGH After BUSY 10 15 15 15tBDD BUSY HIGH to Valid Data 20 20 25 30tDDD Write Data Valid to Read Data Valid Note 18 Note 18 Note 18 Note 18tWDD Write Pulse to Data Delay Note 18 Note 18 Note 18 Note 18'CY7C142 OnlylJotes:.0. Data I/O pins enter high-impedance state, as shown, when 00 is15. WE is HIGH for read cycle.held LOW during write. 16. Device is continuously selected. 00, cr = VIL .. 1. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IOrJIOH and 30 pF load capacitance.2. tHZOE, tHZCE and tHZWE are specified with CL = 5 pF as in Figure2. Transition is measured ± 500 m V from steady state voltage.3. At any given temperature and voltage condition, tHZCE is less thantLzcE for any given device.4. The internal write time of the memory is defined by the overlap ofcr LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns17. Address valid prior to or coincident with CE transition LOW.18. A write operation on Port A, where Port A has priority, leaves thedata on Port B's outputs undisturbed until one access time after oneof the following:A. BUSY on Port B goes HIGH.B. Port B's address toggled.C. cr for Port B is toggled.D. WE for Port B is toggled.)witching Waveformslead Cycle No.1 (Notes 15, 16)*_Either Port-Address Access~~------------------------tRc--------------------------1~~ADORESS· ________ ~I_::~~~_-__ ~_HA _____ ~_A_~,--------------------------------------__ __DATA OUT PREVIOUS DATA VALID ~ DATA VALID0106-92-53

fiACY7C132. PRELIMINARY CY7C142~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==Switching Waveforms (Continued)Read Cycle No.2 (Notes 15, 17),Either Port-CE/OE AccessI\. tACE I--tHZCE -~I\.tOOEtHZOEI-tLZOE -I---t LZCE -----...,W////////////IDATA OUTDATA VALID-'~""" " y\. \. \. \. \. \. \."tpu- I--tpoICC ______-J)158 •1----I-l0106-10Read Cycle No.3 (Note 15)ADDRESS RREAD with BUSYADDRESS MATCH~ ....(-ADDRESS L ADDRESS MATCH~DOUT LtWDDtODO¥t 800 ---JlVALID1-0106-11Write Cycle No.1 (Notes 10, 14)Either PorttwcADDRESS j~\. \. \ \.~tSCE~'f./ / / V///tAW tHA ---I--- tSA ---Jt pWE---~\.~ 'f."'ItsoDATA VALIDtHO Il///~ It~ \. \., , , , , , .,.HIGH IMPEDANCEDOUT 0106-13X2-54

5nCY7C132. PRELIMINARY CY7C142~ucr~==============================================~================Switching Waveforms (Continued)Write Cycle No.2 (Notes 10, 14)Either PorttwcADDRESS ( (-I.tHA-DATAOUT" "tSCE\.\.\.~ /// "/7tAW;+-- tSA--J tpWE~ \. ' j"tHOI-tSDrDATA VALID X"I-- t HZWE --j !-tLZWE -y -yy~ HIGH IMPEDANCE I II I " I " I " I " I " I " I " I " I " I " I .,~ ~0106-14EllBUSY Timing Diagram No.1 (CE Arbitration)eEL Valid First:ADDRESS =::::xLAND R:ER Valid First:CE LCE Rl~SbADDRESS MATCH'BLC~t'BHCjBUSY R0106-15ADDRESS =::::xLAND RCE RCE Ll'PSbADDRESS MATCH'BLC~t'BHCjBUSY L0106-16XX2-55

finCY7C132. , PRELIMINARY CY7C142~~UaoR==================================================================Switching Waveforms (Continued)BUSY Timing Diagram No.2 (Address Arbitration)LEFf Address Valid First:ADDRESS L ___ I _________ ""I' ...... _A_D_DR_E_S_S _M_IS_M_AT_C_H_" "' _____ _BUSY Timing Diagram No.2RIGHT Address Valid First:ADDRESSR _____ ~'I~ _____-+____________-----------tB-~-=iBUSY RtBHAJ ___________----0106-17ADDRESS R ___ r _________ ""I' ...... _A_D_DR_E_SS_M_IS_M_AT_C_H_" "' _____ __________ADDRESS L -----~'I'-----~-+----~------..,tB_~_===1 tBHA~L---~-------BUSYL ~..10106-18BUSY Timing Diagram No.3WRITE with BUSY (SLAVE: CY7C142)j-------------tPwE----------~--~WE I--twa!=:: tWH ~----BUSY~~ ____________________ _J~0106-122-56

~RFSSPRELIMINAR YCY7C132CY7C142WnICONDUCIOR ==================================================================:;;Switching Waveforms (Continued)Interrupt Timing Diagram (Note 6)LEFT Side Sets INTR:~----------twc--------~ADDRESSL ____ JI~~ ____________________ ~~~ ____________ _J'_ ____ __INTR0106-19RIGHT Side Clears INTR:INTR ______________________________________ -JI0106-20RIGHT Side Sets INTL:~---------twc--------~ADDRESSR ____ JI'~ ____________________ ~~~-------------J'-------0106-21... EFT Side Clears INTL:______________________________________ JIINTL0106-222-57

finCY7C132. PRELIMINAR Y CY7C142~NDUcroR ==================================================================~Pin Configurations6 5 4 3 2111525150494847All'-' 46A2l 9A3lA4lASlA6l 13A7L 14ASl 15A9l 16I/OOl 17I/Oll 18I/0 2l 19OE RAORA1RA2RA3RA4RASRA6RA7RASRA9RNCI/ 0 3l I/ 0 7R21222324252627282930313233AllA2lA3lA4lASl 11A6lA7lASlA9lI/OOlI/ O llI/ 0 2l5 4 3 2 111484746454443'-' 42 AOR41 A1R40 A2R39 A3RA4RASRA6R35 A7R34 ASR33 A9R32 I/07R31 I/06R192021222324252627282930PLCCTop View0106-23...J ...J ...J ...J ...Je a: a: Q: Q: a: Q:.., ~ 10 CD r-.z 0 - N .., ~ 10~~~~~C>~~~~~~LCCTop View0106-24Ordering InformationSpeed Ordering Package(ms) Code Type25 CY7C132-25PC P25CY7C 132-25DC D26CY7C132-25LC L68CY7C132-25JC J6935 CY7C132-35PC P25CY7C132-35DC D26OperatingRangeCommercialCommercialSpeed(ms)2535OrderingCodeCY7C142-25PCCY7C142-25DCCY7C142-25LCCY7C142-25JCCY7C142-35PCCY7C142-35DCPackageTypeP25D26L68J69P25D26OperatingRangeCommercialCommercialCY7C132-35LCCY7C132-35JCCY7C132-35DMBCY7C132-35LMBL68J69D26L68MilitaryCY7C142-35LCCY7C142-35JCCY7C142-35DMBCY7C142-35LMBL68J69D26L68Military45 CY7C132-45PC P25Commercial45CY7C142-45PCP25CommercialCY7C132-45DCCY7C132-45LCCY7C132-45JCCY7C132-45DMBD26L68J69D26MilitaryCY7C142-45DCCY7C142-45LCCY7C142-45JCCY7C142-45DMBD26L68J69D26MilitaryCY7C132-45LMB L6855 CY7C132-55PC P25Commercial55CY7C142-45LMBCY7C142-55PCL68P25CommercialCY7C132-55DCCY7C132-55LCCY7C132-55JCCY7C132-55DMBCY7C132-55LMBD26L68J69D26L68MilitaryCY7C142-55DCCY7C142-55LCCY7C142-55JCCY7C142-55DMBCY7C142-55LMBD26L68J69D26L68Military2-58

fillCY7C132.. PRELIMINARY CY7C142~~NDUcrOR==================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3loz 1,2,3lOS 1,2,3ICC 1,2,3ISBI 1,2,3ISB2 1,2,3ISB3 1,2,3SubgroupsParametersISB4 1,2,3SubgroupsSwitching CharacteristicsParametersREAD CYCLESubgroupstAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tDOE 7,8,9,10,11WRITE CYCLEtSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tPWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11BUSY/INTERRUPTTIMINGtBLA 7,8,9,10,11tBHA 7,8,9,10,11tBLC 7,8,9,10,11tBHC 7,8,9,10,11tps 7,8,9,10,11tWINS 7,8,9,10,11; tEINS 7,8,9,10,11tINS 7,8,9,10,11Note:t. CY7C142 only.Document #: 38-00061-AParametersBUSY/INTERRUPTTIMING (Continued)SubgroupstOINR 7,8,9,10,11tEINR 7,8,9,10,11tINR 7,8,9,10,11BUSY TIMINGtWB[l) 7,8,9,10,11tWH 7,8,9,10,11tBDD 7,8,9,10,11tDDD 7,8,9,10,11tWDD 7,8,9,10,112-59

CYPRESSSEMICONDUCTORCY7C1474096 X 1 Static R/W RAMFeatures• Automatic power-down whendeselected• CMOS for optimumspeed/power• High speed-25 ns• Low active power- 440 mW (commercial)- 605 mW (military)• Low standby power-55mW• TTL compatible inputs andoutputs• Capable of withstandinggreater than 2000Velectrostatic dischargeLogic Block DiagramFunctional DescriptionThe CY7C147 is a high performanceCMOS static RAM organized as 4096words by 1 bit. Easy memory expansionis provided by an active LOW chipenable (CE) and three-state drivers.The CY7C147 has an automatic power-downfeature, reducing the powerconsumption by 80% when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.Data on the input pin (DI) is writteninto the memory location specified onthe address pins (Ao through All).Reading the device is accomplished bytaking the chip enable (CE) LOW,while write enable (WE) remainsHIGH. Under these conditions thecontents of the memory location specifiedon the address pins will appear onthe data output (DO) pin.The output pin stays in high impedancestate when chip enable (CE) is HIGHor write enable (WE) is LOW.Pin Configurations~-----------00AuAlA2A3A4VeeA6A7AsAgAsAl000 AllWE 01GNOEE0.,...00 co«>

~ CY7C147~~~~UcrOR =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 18 to Pin 9) ..................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to +7.0VStatic Discharge Voltage ............ " ....... > 2001V(Per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.OV to + 7.0V Commercial O°C to +70°C SV ± 10%Output Current into Outputs (Low) ............. 20 rnA Military [3] - SSoC to + 12SoC SV ± 10%Electrical Characteristics Over Operating Range[4]Parameters Description Test Conditions7C147·25 7C147·35, 45Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min. IOH = -4.0mA 2.4 2.4 VVOL Output LOW Voltage Vee = Min. IOL = 12.0mA 0.4 0.4 VVIH Input High Voltage 2.0 6.0 2.0 6.0 VVIL Input Low Voltage -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND::;; VI::;; Vee -10 +10 -10 +10 f-LAIozlOSIccOutput LeakageCurrentOutput Short[1]Circuit CurrentGND::;; Va::;; VeeOutput DisabledVeeUnits-so +SO -so +SO f-LAVee = Max. VOUT = GND -3S0 -350 mAVee Operating Vee = Max. Commercial 90 80Supply Current lOUT = OmA Military 110mAEIISB1Automatic CE[2] Max. Vee, Commercial 15 10Power Down Current CE 2 VIHMilitary 10mACapacitance [5]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA=2soC,f=IMHz SpFCOUTOutput CapacitanceVee = S.OV6Notes:1. Duration of the short circuit should not exceed 30 seconds. 3. T A is the "instant on" case temperature.2. A pull-up resistor to Vee on the eE input is required to keep the4. See the last page of this specification for Group A subgroup testingdevice deselected during Vee power-up, otherwise ISB will exceedinformation.values given.5. Tested initially and after any design or process changes that mayaffect these parameters.AC Test Loads and WaveformsR1329 nR1329n5Vo---------~~~ 5Vo-------~vv~~ALL INPUT PULSESOUTPUT 0----1------1OUTPUT 0----..... ---...3.0 v------t~~--"""-Equivalent to:'NCLUDINGI30 pFJIG ANDSCOPER220H25 pF,NCLUD,NlJIG ANDSCOPE -=Figure laFigure IbTHE-VENIN EQUIVALENTR2202.n0019-4GNDFigure 2:;;;5 ns0019-6125.nOUTPUT O---..JIVV\.,.---_O 1.90 V 0019-52-61

~ CY7C147~~~UcrOR =======================================================================Switching Characteristics Over Operating Range[6]ParametersREAD CYCLEDescriptionMin.tRC Read Cycle Time 25tAAAddress to Data ValidtOHA Data Hold from Address Change 3tACECS Low to Data ValidtLZCE CE LOW to Low Z[S] 5tHZCE CEHIGH to High Z[7, S]tpu CE LOW to Power Up 0tpDWRITE CYCLE[9]CE HIGH to Power Downtwc Write Cycle Time 25tSCE CE LOW to Write End 25tAW Address Set-up to Write End 25tHA Address Hold from Write End 0tSA Address Set-up to Write Start 0tPWE WE Pulse Width 15tSD Data Set-up to Write End 15tHD Data Hold from Write End 0tLzwE WE HIGH to Low Z[S] 0tHZWE WE LOW to High Z[7, s]Notes:6. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified 101l10H and 30 pF load capacitance.7. tHZCE and tHZWE are tested with CL = 5 pF as in Figure lb.Transition is measured ± 500 m V from steady state voltage.S. At any given temperature and voltage condition, tHZ is less than tLZfor all devices.Switching WaveformsRead Cycle No.1 (Notes 10, 11)7C147-25 7C147-35 7C147-45Max. Min. Max. Min. Max.Units35 45 ns25 35 45 ns5 5 ns25 35 45 ns5 5 ns20 30 30 ns0 0 ns20 20 20 ns35 45 ns35 45 ns35 45 ns0 0 ns0 0 ns20 25 ns20 25 ns10 10 ns0 0 ns15 20 25 ns9. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.10. WE is HIGH for read cycle.II. Device is continuously selected, CE = VIL.12. Address valid prior to or coincident with CE transition LOW.DATA OUTPREVIOUS DATA VALIDDATA VALID0019-72-62

~ CY7C147~~~NDUcroR~~~~~~~~~~~~~~~~~~~~~~~~~~~=================Switching Waveforms (Continued)Read Cycle No.2 (Notes 10, 12)DATA OUT~r-'"tRCtACE .~tHZCE1tLZCE:-!HIGHHIGH IMPEDANCE If I I I I , IMPEDANCEDATA VALIDf_tpu1SUPPLY VCC ______ 50%CURRENT_Write Cycle No.1 (WE Controlled) (Note 9)I" " " " " \.~----------------------------~c---------------------------~,'f-Ji+---tpot,~50%1580019-8IIADDRESS~------------------ tSCE --------------+1~------------------tAW---------------------+\4_---\4---------tSA-----+iDATA INDATA-IN VALIDtHZWE~DATA OUT -------------------DA-T-A-U-N-D-EF-I-NE-D--------------- )~----~~~~~~----_(~_____________0019-9Write Cycle No.2 (CE Controlled) (Note 9)~------------------------~C--------------------------~_-t------------tSCE---------___+!~------t~E------~tHZWE~-------------------__\!\4_-'----,----tso --------~-\4_-+----------tso-------+-DATA-IN VALIDHIGH IMPEDANCEDATA OUT DATA UNDEFINED J~------------------------Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.0019-102-63

~ CY7C147~~~U~==================================================================Typical DC and AC Characteristics.!1U.!:!0wN::;«~a:0zNORMALIZED SUPPLY CURRENT1.4 vs. SUPPLY VOLTAGE1.21.00.80.60.40.20.04.0,,/"VyISBVIN = 5 VTA ~ 25·C4.5 5.0 5.5SUPPLY VOLTAGE (V)~6.01lU.::0wN::;«~a:0z1.21.00.80.6NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE~ Icc~0.4Vee = 5.0 VVIN = 5.0 V0.2ISB0.0-55 25.0 125.0AMBIENT TEMPERATURE (·C);t!I- Zwa:a:::l(Jw(Ja:::l~I- ::l~I-::l010080604020OUTPUT SOURCE CURRENTVS. OUTPUT VOLTAGE"""" "\~Vee = 5.0 VTA = 25·C'"OUTPUT VOLTAGE (V)'"o0.0 1.0 2.03.0 4.0«$0wN::;«~a:0z1.41.31.21.11.00.9NORMALIZED ACCESS TIMEVS. SUPPLY VOLTAGE""'" "TA= 25·C...............----0.84.0 4.5 5.0 5.5SUPPLY VOLTAGE (V)6.0NORMALIZED ACCESS TIMEVS. AMBIENT TEMPERATURE1.6 r------,.-------....,1.4 t------r-------i$~ 1.2 t------r------::ofI#C--iN::;«~ 1.0 I----~~------Ioz0.8 I-----+------~0.6 ~----........ -----.....-55 25 125AMBIENT TEMPERATURE ('C)160;t 140!I- 120Zwa: 100a:::l(J80:.i:Zin!5~I-::l0604020OUTPUT SINK CURRENTVS. OUTPUT VOLTAGEo,,~~/VL ~~e= =2~;~ V -//Vo 1.0 2.0 3.0OUTPUT VOLTAGE (V)4.0TYPICAL POWER-ON CURRENTVS. SUPPLY VOLTAGE (7Cl48)3.0 "'--"T""--r---,r---..,......-....,2.5 t---t---+---1r--+---I2 TAJ25.C _o 2.0 t---t---+- lK n CS PULL-UP~ RESISTOR TO Vee::; 1.5t---t---+---1"-----+---I~~ 1.0 t-_-+-_-+_--j"""IS;,;;:B;....+-_",,,0.5/t---t---+--r--~~~___ V0.0 ~_"""_-=::::::::;,..,J.._.....JL---J0.0 1.0 2.0 3.0 4.0 5.0SUPPLY VOLTAGE (V)30.025.0! 20.0«: 15.0~wo 10.05.00.0TYPICAL ACCESS TIME CHANGEVS. OUTPUT LOADING~V//V/---TA = 25·CVee = 4.5 VYo 200 400 600 800 1000CAPACITANCE (pF)u.::cwN::;«~a:0zNORMALIZED IccVS. CYCLE TIME1.4ItVee =5.0 V1.3 "--TA = 25·CVIN = 0.5 V1.21.11.00.9--- .,/~~ "".-0.8o 10 20 30 40 50CYCLE FREQUENCY (MHz)0019-112-64

~crPRESSCY7C147~~~~u~==================================================================Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type RangeAddress DesignatorsAddress Address PinName Function Number25 CY7C147-25PC P3 Commercial Ao Xo 1CY7C147-25DC D4 CommercialAl Xl 2CY7C147-25LC LSD CommercialA2 X2 335 CY7C147-35PC P3 CommercialCY7C147-35DC D4 Commercial A3 X3 4CY7C147-35LC LSD Commercial A4 Yo 5CY7CI47-35DMB D4 MilitaryCY7CI47-35LMB LSD MilitaryAs Yl 645 CY7C147-45PC P3 CommercialA6 X4 17CY7C147-45DC D4 Commercial A7 Xs 16CY7C147-45LC LSD CommercialAs Y2 15CY7CI47-45DMB D4 MilitaryCY7CI47-45LMB LSD MilitaryA9 Y3 14AlO Y4 13All Ys 12BitMap0019-122-65

~ CY7C147~~~~UaoR================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3ISBI 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tPWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00030-B2-66

Features• Automatic power·down whendeselected (7C148)• CMOS for optimumspeed/power• 25 ns access time• Low active power- 440 mW (commercial)- 605 mW (military)• Low standby power (7C148)- 82.5 m W (25 ns version)- 55 m W (all others)• 5 volt power supply ± 10%tolerance both commercial andmilitary• TTL compatible inputs andoutputsLogic Block DiagramCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C148 and CY7C149 are highperformance CMOS static RAMs organizedas 1024 x 4 bits. Easy memoryexpansion is provided by an activeLOW chip select (CS) input, and threestateoutputs. The CY7C148 andCY7C149 are identical except that theCY7C148 includes an automatic (CS)power-down feature. The CY7C148 remainsin a low power mode as long asthe device remains unselected, i.e. (CS)is HIGH, thus reducing the averagepower requirements of the device. Thechip select (CS) ofthe CY7C149 doesnot affect the power dissipation of thedevice.An active LOW write enable signal(WE) controls the writing/reading operationof the memory. When the chipCY7C148CY7C1491024 X 4 Static R/W RAMselect (CS) and write enable (WE) inputsare both LOW, data on the fourdata input/output pins (1/00 through1/03) is written into the memory locationaddressed by the address presenton the address pins (Ao through A9).Reading the device is accomplished byselecting the device, (CS) active LOW,while (WE) remains inactive or HIGH.Under these conditions, the contents ofthe location addressed by the informa- 2tion on address pins (Ao through A,) ispresent on the four data input/outputpins (1/00 through 1/03).The input/output pins (1/00 through1/03) remain in a high impedance

5nCY7C148. CY7C149~UaoR==================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 18 to Pin 9) ..................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VStatic Discharge Voltage(Per MIL-STD-883 Method 3015) ............. >2001VLatchup Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto +70°C 5V ±1O%Output Current into Outputs (Low) ............. 20 rnA Military [I 11 - 55°C to + 125°C 5V ±1O%Electrical Characteristics Over Operating Range[l2]Parameters Description Test ConditionsVee7Cl48/9-25 7Cl48/9-35,45Min. Max. Min. Max.IOH Output High Current VOH = 2.4V Vee = 4.5V -4 -4 mAIOL Output Low Current VOL = O.4V 8 8 mAVIR Input High Voltage 2.0 6.0 2.0 6.0 VVIL Input Low Voltage -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND S VI S Vee -10 10 -10 10 p,Aloz Output Leakage Current GND s Vo s Vee Output Disabled -50 50 -50 50 p,ACICliOIccISBIpolosInput Capacitance[13]Input/OutputCapacitance[13]Vee OperatingSupply CurrentTest Frequency = 1.0 MHz5 5T A = 25°C, All Pins at OV, Vee = 5V 7 7Max. Vec, CS s VILOutput OpenAutomatic CS Max. Vcc, 7C148Power Down Current CS ~ VIR onlyPeak Power-On Max. Vcc, 7C148Current CS ~ VIR[3] onlyOutput ShortCircuit Current Yccl lO ]GND s Yo sNotes:1. Test conditions assume signal transition times of 10 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified Iou'IOH and 30 pF load capacitance. Outputtiming reference is 1.5V.2. The internal write time of the memory is defined by the overlap ofCS low and WE low. Both signals must be low to initiate a write andeither signal can terminate a write by going high. The data inputsetup and hold timing should be referenced to the rising edge of thesignal that terminates the write.3. A pull up resistor to Vee on the CS input is required to keep thedevice deselected during Vee power up. Otherwise current will exceedvalues given (CY7C148 only).4. Chip deselected greater than 25 ns prior to selection.5. Chip deselected less than 25 ns prior to selection.AC Test Loads and WaveformsRl481Sl5Vo----y.,I',,-...,OUTPUTo---.----tRl481Sl5 V o----~\o-...OUTPUT 0--_---...30pF R25pF R2255nINCLUDINGI _JIGAND _ I ,NCLUDING 255n_JIG AND _- SCOPE - - SCOPE -Figure laFigure IbEquivalent To:THEVENIN EQUIVALENT167nOUTPUT O---~"~"'~",....--O 1.73V0001-40001-122-68Commercial 90 80Military 110Commercial 15 10Military 10Commercial 15 10Military 10Commercial ±275 ±275Military ±350UnitspFmArnArnArnA6. At any given temperature and voltage condition, tHZ is less than tLZfor all devices. Transition is measured ± 500 m V from steady statevoltage with specified loading in Figure 1 h.7. WE is high for read cycle.8. Device is continuously selected, CS = V IL.9. Address valid prior to or coincident with CS transition low.10. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.II. TA is the "instant on" case temperature.12. See the last page ofthis specification for Group A subgroup testinginformation.13. Tested initially and after any design or process changes that mayaffect these parameters.ALL INPUT PULSES3.0V-----J~~---~GND~10n.Figure 2~10n.0001-5

5JiCY7C148. CY7C149. ~UcrOR ==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===Switching Characteristics Over Operating Range(12)ParametersREAD CYCLEtRCtAAtACSltACS2tACStLZ[6]tHZ[6]tOHtpDtpuWRITE CYCLEtwctwp[2]tWRtwz[6]tDwtDHtAStCW[2]tow [6]tAWDescriptionAddress Valid to Address Do NotCare Time (Read Cycle Time)Address Valid to Data OutValid Delay (Address Access Time)Chip Select Low to Data Out Valid(CY7C148 only)Chip Select Low to Data Out Valid(CY7C149 only)Chip Select Low toData Out OnChip Select High to DataOut OffAddress Unknown to Data OutUnknown TimeChip Select High toPower-Down DelayChip Select Low toPower-Up Delay7C1487C1497C1487C148Address Valid to Address Do NotCare (Write Cycle Time)Write Enable Low toWrite Enable HighAddress Hold from Write EndWrite Enable to Outputin High ZData in Valid to Write Enable HighData Hold TimeAddress Valid to WriteEnable LowChip Select Low to WriteEnable HighWrite Enable High to Outputin Low ZAddress Valid to End of Write7Cl48/9-25Min.2585Max.2525[4]30[5]150 150025205200 81200200207C148/9-35 7Cl48/9-45Min. Max. Min. Max.Units35 45 ns35 45 ns35 4535 45ns15 20 ns10 105 50 20 0 20 ns0 5 nsns30 30 ns0 0 ns35 45 ns30 35 ns5 5 ns0 10 0 15 ns20 20 ns0 0 ns0 0 ns30 40 ns0 0 ns30 35 nsIISwitching WaveformsRead Cycle No.1 (Notes 7,8)-----Jr,~-------------------------tRc------------------------~1.ADDRE~_~ ______~~:-_=~~=~-_=~t_O-H~~-_~~-_~t_A=A=-_-.!-----------.-!-----------------------~~--------------------------------------------------0001-6DATA OUT PREVIOUS DATA VALID DATA VALID2-69

5ACY7C148. CY7C149~U~==================================================================Switching Waveforms (Continued)Read Cycle No.2 (Notes 7, 9)DATA OUT~r- \.tACStRCtLZ=I~'"'j HIGHHIGH IMPEDANCE I, , , , , , IMPEDANCEDATA VALID'\l\.\..\.\.\.\. ,~tpu1SUPPLY Vce _______ 50%CURRENT_Write Cycle No.1 (WE Controlled)~-----------------------------twc----------------------------~... J.1I*--tPDso::t-158---jICC0001 ... 7ADDRESS~---------------------t~--------------------~~-----------------------tAW----------------------~~---~-----tAS-----"""'~ ..... -------twP --------~~__:_------tDW --------.!14-DATA 110DATA-IN VALIDtwz~~w~----------------------~ HIGH IMPEDANCE 1,1'-------DATA 1/0 DATA UNDEFINED J~---;""--";;""";';"'--~\",. ______ _0001 ... 8Write Cycle No.2 (CS Controlled)..... ---------------------------twc----------------------------~\+--------twp --------~*DATA 1/0 ________________ L~,~NVALID.'. ~"l-----------~ HIGH IMPEDANCEDATA I/O __________ D_A_TA_U_ND_E_f_IN_E_D _________Note: If CS goes high simultaneously with WE high, the output remains in a high impedance state.0001 ... 92-70

~crPRFBSCY7C148CY7C149~~~OONDUcrOR ======================================~====~~~~~~~~==~~===Typical DC and AC Characteristics~~@N:;«::Ea:0z1.41.21.00.80.60.4NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE./V~VVIN = 5 VTA = 25'C0.2ISB0.04.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (V)~]@N:;«::Ea:0z1.21.00.80.60.40.20.0NORMALIZED SUPPLY CURRENTvs AMBIENT TEMPERATURE~ Icc~ .....ISBVee = 5.0VVIN = 5.0V-55 25.0 125.0AMBIENT TEMPERATURE (OC)«!~~~::>0100~~ 80a:a:::>u 60wua:::>040(I)20OUTPUT SOURCE CURRENTvs OUTPUT VOLTAGE~"-""'"Vee = 5.0 VTA = 25'C" I'"0.0 1.0 2.0 3.0OUTPUT VOLTAGE (V)4.0II~~cwN:;«::Ea:0z1.41.31.21.11.00.9NORMALIZED ACCESS TIMEvs. SUPPLY VOLTAGE"~TA = 25'C...............r--0.84.0 4.5 5.0 5.5 6.01.6NORMALIZED ACCESS TIMEvs. AMBIENT TEMPERATURE1.4 I------+-----~'_I~~@ 1.2 1-----+------:~--4N:;«~ 1.0 1-------,JtC------4~0.8 '-"'IC.....---+------40.6 '-____........._____....J-55 25 125«!~100~a:a:::> 80u~z 60iii~::> 404-~::>014012020OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE7// ~1/"", ~Vee =5.0 VTA = 25'CV o0.0 1.0 2.0 3.04.0SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE ('C)OUTPUT VOLTAGE (V)TYPICAL POWER·ON CURRENTvs. SUPPLY VOLTAGE (7Cl48)3.0 r---,---,---,...---r--.....,30.0TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADING1.4NORMALIZED Iccvs. ACCESS TIME2.5 t----I---+--I--I--l--~.E 2.0 I---+---+- TA = 25'C '---c1K n CS PULL-UP~ RESISTOR TO Vee:; 1.5 t---t---+----,r---t---i«::E~ 1.0 ...._+_-+_~~I;;;SB__ +-_ ....0.5 1---+---+---.,f----il;IC-/~.___V0.0 __..._IIIIIIII:=:-L-_...L..._....J0.0 1.0 2.0 3.0 4.0 5.025.0! 20.0~~;( 15.08c 10.05.00.0//1/.JV/...".-TA = 25'CVee = 4.5 VVo 200 400 600 800 1000ucwN:;«::Ea:0z1.31.21.11.00.9"......... ""-0.810 20 30 405060SUPPLY VOLTAGE (V)CAPACITANCE (pF)tAA (ns)0001-102-71

WnCY7C148. CY7C149~U~================================================================Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type RangeAddress DesignatorsAddress Address PinName Function Number25 CY7C148-25PC P3 Commercial Ao Yo 5CY7C149-25PCAl YI 6CY7C148-25DCD4CY7C149-25DCA2 Y2 7A3 Y3 4CY7C148-25LCL5DCY7C149-25LC A4 Xo 335 CY7C148-35PC P3 Commercial As X3 2CY7C149-35PC A6 X2 1CY7C148-35DC D4 A7 Xs 17CY7C149-35DCAs X4 16CY7C148-35LCL5DCY7C149-35LCA9 Xl 15CY7CI48-35DMB D4 MilitaryCY7CI49-35DMBCY7CI48-35LMB L5DCY7CI49-35LMB45 CY7CI48-45PC P3 CommercialCY7C149-45PCCY7C148-45DCD4CY7C149-45DCCY7C148-45LCL5DCY7C 149-45LCCY7CI48-45DMB D4 MilitaryCY7CI49-45DMBCY7CI48-45LMB L5DCY7CI49-45LMBBitMap0001-112-72

finCY7C148. CY7C149~~UcrOR================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersIOH 1,2,3IOL 1,2,3VIR 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3ISB[l] 1,2,3SubgroupsfISwitching CharacteristicsParametersREAD CYCLESubgroupstRC 7,8,9,10,11tAA 7,8,9,10,11tACSl[l] 7,8,9,10,11tACS2U] 7,8,9,10,11tACS[2] 7,8,9,10,11tOH 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11twp 7,8,9,10,11tWR 7,8,9,10,11tDw 7,8,9,10,11tDH 7,8,9,10,11tAS 7,8,9,10,11tAW 7,8,9,10,11Notes:1. 7C148 only.2. 7C149 only.Document #; 38-00031-B2-73

Features• Memory reset function• 1024 x 4 static RAM for controlstore in high speed computers• CMOS for optimumspeed/power• High speed- 12 ns (commercial)- 15 ns (military)• Low power- 495 m W (commercial)- 550 mW (military)• Separate inputs and outputs• 5 volt power supply ± 10%tolerance both commercial andmilitary• Capable of withstanding greaterthan 2001 V static discharge• TTL compatible inputs andoutputsCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C150 is a high performanceCMOS static RAM designed for use incache memory, high speed graphics,and data aquisition applications. Organizedas 1024 words x 4 bits, the entirememory can be reset to zero in twomemory cycles.Separate I/O paths eliminate the needto multiplex data in and data out, providingfor simpler board layout andfaster system performance. Outputs aretri-stated during write, reset, deselect,or when output enable (OE) is heldHIGH, allowing for easy memory expansion.Reset is initiated by selecting the device(CS = LOW) and pulsing the reset(RS) input LOW. Within two memorycycles all bits are internally cleared tozero. Since chip select must be LOWfor the device to be reset, a global resetsignal can be employed, with only selecteddevices being cleared at any giventime.CY7C1501024 X 4 Static R/W RAMAn active LOW write enable input(WE) controls the writing/reading operationof the memory. When the chipselect (CS) and write enable (WE) inputsare LOW, the information on thefour data inputs Do to D3 is writteninto the addressed memory locationand the output circuitry is preconditionedso that the write data is presentat the outputs when the write cycle iscompleted.Reading is performed with the chip select(CS) input LOW, and the write enable(WE) input HIGH, and the outputenable input (OB) LOW. The informationstored in the addressed word isread out on the four non-inverting outputs00 to 03.The outputs of the memory go to anactive high impedance state wheneverchip select (CS) is HIGH, Reset (RS) isLOW, output enable (OE) is HIGH, orduring the writing operation whenWrite Enable (WE) is LOW.A die coat is used to ensure alpha immunity.Logic Block DiagramPin ConfigurationsRS~ ",0 0 o N«z>

~ CY7C150~ ~~NDUcrOR =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 mASupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto + 70°C SV ±1O%Output Current into Outputs (Low) ............. 20 mA Military [3] - SsoC to + 12SoC SV ± 10%VeeElectrical Characteristics Over Operating Range[4]Parameters Description Test Conditions7CI50·12, 15,25,35VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 12.0 rnA 0.4 VVIH Input High Voltage 2.0 Vee VVIL Input Low Voltage -3.0 0.8 VIIX Input Load Current GND ~ VI ~ Vee -10 +10 /-LAIozOutput LeakageCurrentGND ~ Vo ~ VeeOutput DisabledMin.Max.Units-SO +SO /-LAlos Output Short[l] Vee = Max., VOUT = GND -300 rnAVee Operating Vee = Max. I Commercial 90IcCrnASupply Current lOUT = OmAI Military * 100*-15, -25 and -35 onlyCapacitance [2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 2SoC, f = 1 MHz, Vee = S.OV S pFCOUT Output Capacitance TA = 2SoC, f = 1 MHz, Vee = S.OV 7 pFNotes:1. Not more than 1 output should be shorted at one time. Duration of3. TA is the "instant on" case temperature.the short circuit should not exceed 30 seconds.2. Tested initially and after any design or process changes that may4. See the last page of this specification for Group A subgroup testinginformation.affect these parameters.IIAC Test Loads and WaveformsR1 329 n5VO---------~~~R1 329 n5Vo---------~~~OUTPUT 0------1-------4 OUTPUT 0----...... ---....R25 pFINCLUDING I 30 pF 202nJIG ANDSCOPE'NCLUD,NlJIG ANDSCOPE ":"R2202n3.0 V ----1r~---"""'-GND---""Is:3n8Figure 2. All Input Pulsess:3n80028-5Figure laEquivalent To:THEVENIN EQUIVALENT125nOUTPUT O-----.J\VV\~--~01.90 VFigure lb0028-40028-32-75

~ CY7C150~~~NDUcroR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=========Switching Characteristics Over Operating Rangd4, 5]ParametersREAD CYCLEtRCtAAtOHAtACStLZCSRead Cycle TimeDescriptionAddress to Data ValidOutput Hold from Address ChangeCS LOW to Data ValidCS LOW to Low Z[7]tHZCS CS HIGH to High Z[6, 7]tDOEtLZOEOE LOW to Data ValidOE LOW to Low Z[7]tHZOE OE HIGH to High Z[6, 7]WRITE CYCLErS]twctscstAWtHAtSAtpwEtSDtHDtLZWEWrite Cycle TimeCS LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to Low Z[7]tHZWE WE LOW to High Z[6, 7]RESET CYCLEtRRCtSARtswERtSCSRtpRStHCSRtHwERtHARtLZRSReset Cycle TimeAddress Valid to Beginning of ResetWrite Enable HIGH to Beginning of ResetChip Select LOW to Beginning of ResetReset Pulse WidthChip Select Hold after End of ResetWrite Enable Hold after End of ResetAddress Hold after End of ResetReset HIGH to Output in Low Z[7]tHZRS Reset LOW to Output in High Z[6, 7]Notes:5. Test conditions assume signal transition times of 5 ns or less, timingreference levels of I.5V, input pulse levels of 0 to 3.0V and output·loading of the specified Ior/IOH and 30 pF load capacitance.6. tHZCS, tHzoE, tHzR and tHZWE are tested with CL = 5 pF as inFigure lb. Transition is measured ± 500 m V from steady state voltage.7. At any given temperature and voltage condition, tHZ is less than tLZfor any given device.7C150·12 7C150·15 7C150·25 7C150·35Min. Max. Min. Max. Min. Max. Min. Max.12200012810228820024000120121200Units15 25 35 ns12 15 25 35 ns2 2 2 ns10 12 15 20 ns0 0 0 ns8 0 11 0 20 0 25 ns8 10 15 20 ns0 0 0 ns8 0 9 0 20 0 25 ns15 25 35 ns11 15 20 ns13 20 30 ns2 5 5 ns2 5 5 ns11 15 20 ns11 15 20 ns2 5 5 ns0 0 0 ns8 0 12 0 20 0 25 ns30 50 70 ns0 0 0 ns0 0 0 ns0 0 0 ns15 20 30 ns0 0 0 ns15 30 40 ns15 30 40 ns0 0 0 ns8 0 12 0 20 0 25 ns8. The internal write time of the memory is defined by the overlap ofCS LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.9. WE is HIGH for read cycle.10. Device is continuously selected, CS and OE = VIL.11. Address valid prior to or coincident with CS transition LOW.2-76

~ CY7C150~~~~UcrOR======================~~~~~=====================================Switching WaveformsRead Cycle No.1 (Notes 9, 10)DATA OUT PREVIOUS DATA VALID DATA VALID0028-6Read Cycle No.2 (Notes 9, 11)JtRCtACS~~{tOOEI4---tLZOEiHIGH IMPEDANCE 1/ / / / /DATA OUTI DATA VALIDWrite Cycle No.1 (WE Controlled) (Note 8)'"'0':3lues -I' , \. \. \. \. ,HIGHIMPEDANCE0028-8II~-----------------------------~C----------------------------~~------------------- tses --------------------fIo.\~----------------------tAW---------------------~~---f------tsA------------i~-----t~E------~~\ ]"-i--tHzes-~---;------tso----____f-DATA INDATA-IN VALIDtHZWE---1tLZWE-----l----------------------~ HIGH IMPEDANCE V'r-------DATA OUT DATA UNDEFINED J~----------"""\,". ______ _0028-92-77

~ CY7C150~~~ND~R==================================================================Switching Waveforms (Continued)Write Cycle No.2 (CS Controlled) (Note 8)~----------------------------twc--------------------------~~ADDRESS..... ------- tSA --------t-------------tscs--------l~------------~----------tAW--------------------~~-~----------t~E----------~WEf4--+-----------tso-------.... -DATA INDATA-IN VALIDtHZWE---!------------------~ HIGH IMPEDANCEDATA 1/0 DATA UNDEFINED ,)-----------------------Note: IfCS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.0026-10Reset Cycle..... ------------- t RRC ------------------1",ADDRESS -------- ){~-------01-04~~~~~~~~~~~~~0*------~~----~(DATA OUTPUT) i. HIGH 1'-_____________ _IMPEDANCENote: Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.OUTPUT VALID ZERO0026-112-78

~ CY7C150~~~~ua~================================================================~fypical DC and AC Characteristicsj1..;.::0....N::i4::!a:021.41.21.00.80.60.4NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE./leVV//0.2ISB0.04.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (VI~c.i.::~N::i4::!a:021.21.00.80.6NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE~~0.4Vee =5.0VVIN = 5.0V0.2 r--ISB0.0-55 25.0 125.0AMBIENT TEMPERATURE (OC)

~ CY7C150~~~~u~~~~~~~~~~~~~==============~~~~~~==~~~~======Truth TableInputsCS WE OE RSOutputsModeH X X X HighZ Not SelectedL H X L HighZ ResetL L X H HighZ WriteL H L H 00-0 3 ReadL X H H HighZ Output DisableOrdering InformationSpeedPackage OperatingOrdering Code(ns) Type Range12 CY7C150-12PC P13A CommercialCY7C150-12DC D14CY7C150-12LC L54CY7C150-12SC S1315 CY7C150·15PC P13A CommercialCY7C150-15DC D14CY7C150-15LC L54CY7C150-15SC S13CY7CI50-15DMB D14 MilitaryCY7CI50-15LMB L5425 CY7C150-25PC P13A CommercialCY7C150-25DC D14CY7C150-25LC L54CY7C 150-25SC S13CY7CI50-25DMB D14 MilitaryCY7CI50-25LMB L5435 CY7C150-35PC P13A CommercialCY7C150-35DC D14CY7C150-35LC L54CY7C150-35SC 813CY7CI50-35DMB D14 MilitaryCY7CI50-35LMB L54BitMapROW 012~.606162ROW 63Address DesignatorsAddressNameAoAlA2A3A4AsA6A7AsA9AddressFunctionPinNumberXo 21Xl 22X2 23X3 1X4 2Xs 3Yo 4YI 5Y2 6Y3 70028-152-80

~ CY7C150~~~UDOR==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACS 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tscs 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11RESET CYCLEtRRC 7,8,9,10,11tSAR 7,8,9,10,11tSWER 7,8,9,10,11tSCSR 7,8,9,10,11tpRS 7,8,9,10,11tHcSR 7,8,9,10,11tHwER 7,8,9,10,11tHAR 7,8,9,10,11Document #: 38-00028-B2-81

Features• 16K by 4• Common I/O• Asynchronous output enable• Registered address• Latched data inputs• Registered chip enable• Latched and pipelined chipenable• Self-timed write• Latched data outputs• 5 ns address setup time• 15 ns address access time• 28 pin package- 300 mil DIP-LCC, PLCC• Single 5V power supply• Low power- 100 mA (commercial)- 120 mA (military)• TTL Compatible inputs andoutputsLogic Block DiagramCYPRESSSEMICONDUCTORProduct CharacteristicsAD VANCED INFORMATIONThe CY7C152 is a registered address,latched Data In, latched Data Out highperformance CMOS static RAM forcache memory applications.The CY7C152 is organized 16,384words of 4 bits each. The device has asingle clock that controls loading theaddress register, data input and outputlatches, pipeline control latch and chipenable register. The chip enable (CE) isclocked into a register and pipelinedthrough a control register to conditionthe output enable. The write enable(WE) is self-timed with data setup andheld to the faIling edge of WE. A separateasynchronous output enable OE isprovided to disable the outputs duringa write operation or whenever other devicesrequire access to the bus.The data input has an asynchronousdata latch enable DLE which may beused to capture data during a write operation.The CY7C152 is designed tobe used with the CY7C181 CACHETAG to implement high speed instructionor data caches.CY7C152Self-Timed CacheStatic RAMFunctional DescriptionThe CE and address inputs (Ao-A13)are sampled on each LOW to HIGHtransition of the clock and stored inregisters. The data input latch on(1/00-1/03) is enabled with the logicalAND of the DLE and registeredCE signals. When enabled, the latch istransparent. When disabled, the latchretains the data present when it wasdisabled.Read/Write OperationThe CE signal must be LOW duringthe LOW to HIGH transition of theclock to initiate a memory cycle. TheWE signal should remain HIGH for acomplete read cycle to occur. TheLOW to HIGH transition of the clockloads the address and CE registers.Data propagates through the data outputlatch to the output if the OE is enabledLOW. The LOW to HIGH transitionof the clock closes the pipelinelatch and the data output latch holdingprevious data and state until new dataand state become available. As this newOLE ------IWE -~~_+--_acrelK --.... -~I-I0E------...04:J10128-12-82

'eatures16K by 4, Separate I/OIFully registered- Address- Data in- Data out-CE, WE, Self-timed write, Transparent write- CY7C159 only, 143 MHz operation- 5 ns setup time- 7 ns cycle time- 7 ns clock to output, 28 pin package- 300 mil DIP-LCC, PLCC, Single 5V power supply- 100 mA (commercial)- 120 mA (military), TTL compatible inputs andoutputsCYPRESSSEMICONDUCTORADVANCED INFORMATIONProduct CharacteristicsThe CY7C158 and CY7C159 are fullyregistered (pipelined) high performanceStatic RAMs. They are organized16,384 words by 4 bits each. Memoryexpansion is easily accomplished usingthe active LOW chip enable (CE) input.An asynchronous output enablesignal (OE) is provided to control thethree-state data outputs. The CY7C158is a normal non-transparent write deviceand the CY7C159 provides atransparent write capability for writethrough operation. Pipelined RAMsare used in writeable control store,DSP and logic analyzer/tester applicationswhere throughput is the criticalparameter.Read/Write OperationThe operation of these devices is completelysynchronous with the exceptionof the OE signal. All data, address andcontrol signals are sampled on eachlow to high transition of the clock.When the CE is LOW during this transition,the device is selected for operation.The type of operation is deter-CY7C158CY7C159Self-Timed PipelinedStatic RAMsmined by the state of the WE signalduring this same transition. WE LOWcauses a write operation while WEHIGH causes a read operation. Thedata input and data output as well asthe address register are also loaded oneach low to high transition of the clock.The outputs however are not enabledfor the address loaded on the currentcycle. The state of the outputs are controlledby the pipelined CE and WEdata from t~revious cycle and thestate of the OE signal. The data loadedinto the output register is also from theprevious cycle and in phase with theoutput control information. This featurecauses a single cycle latency forthe first read or write cycle, but allowsa word of data to be read or writteneach 7 ns cycle. When the data from awrite cycle reaches the output register,the non-transparent CY7C158 disablesthe outputs under all conditions. Thetransparent write CY7C159 will producethe data on the outputs if the OEsignal is LOW.tilLogic Block DiagramAO.RAM ARRAY16KX4A 13OE000- 00 32-830127-1

Features• Automatic power-down whendeselected• Transparent Write (7C161)• CMOS for optimum speed/power• High Speed- 25 ns tAA• Low active power- 385 mW• Low standby power-110 mW• TTL compatible inputs andoutputs• 2V data retention (L version)Logic Block DiagramCYPRESSSEMICONDUCTOR• Capable of withstanding greaterthan 2001 V electrostatic~ischargeFunctional DescriptionThe CY7C161 and CY7C162 are highperformance CMOS static RAMs organizedas 16,384 x 4 bits with separateI/O. Easy memory expansion is providedby active LOW chip enables(CEI, CE2) and three-state drivers.They have an automatic power-downfeature, reducing the power consumptionby 85% when deselected.Writing to the device is accomplishedwhen the chip enable (CEl. CE2) andwrite enablt:; (WE) inputs are bothCY7C161CY7C16216,384 X 4 Static R/W RAMSeparate I/OPin ConfigurationsLOW. Data on the four input pins (10through 13) is written into the memorylocation specified on the address pins(Ao through Al3).Reading the device is accomplished bytaking the chip enables (CEl. CE2)LOW, while write enable (WE) remainsHIGH. Under these conditionsthe contents of the memory locationspecified on the address pins will appearon the four data output pins.The output pins stay in high impedancestate when write enable (WE) is LOW(7C162 only), or one ofthe chip enables(CEI, CE2) are HIGH.A die coat is used to insure alpha immunity.AoA,A2A3A4ASA6A712As13 Vee(.) ..,A6 N~O(J-A4 «

iACY7C161. CY7C162~~UcrOR==========================================~==~~~~~~~~==~v.laximum RatingsAbove which the useful life may be impaired. For user guidelines, not tested.),torage Temperature ............... - 65°C to + 150°CStatic Discharge Voltage ..................... > 2001 V\.mbient Temperature with (Per MIL-STD-883 Method 3015)'ower Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnA:upply Voltage to Ground PotentialPin 24 to Pin 12) .................... -0.5V to + 7.0VOperating Range)C Voltage Applied to OutputsAmbientRangeVeetl High Z State ...................... -0.5V to + 7.0VTemperature)C Input Voltage ................... - 3.0V to + 7.0V Commercial O°C to + 70°C SV ±1O%)utput Current into Outputs (Low) ............. 20 rnA Military [3] - 5SoC to + 12SoC SV ± 10%~lectrical Characteristics Over Operating Range[4]7C161-25 7C161-35 7C161-45Parameters Description Test Conditions 7C162-25 7C162-35 7C162-45 UnitsMin. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 VVIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND::;; VI::;; Vee -10 +10 -10 +10 -10 + 10 }.LAIOZ Output Leakage Current GND ::;; Vo ::;; Vee, Output Disabled -10 +10 -10 +10 -10 +10 }.LAOutput Short CircuitloSCurrent[llVee = Max., VOUT = GND -3S0 -350 -3S0 rnAVee Operating Vee = Max. Commercial 70 70 50lee Supply Current lOUT = OmA Military 70 70rnAAutomatic CE Max. Vee, CE ~ VIH Commercial 20 20 20ISBI Power Down Current Min. Duty Cycle = 100% Military 20 20 20rnAISB2Automatic CEPower Down CurrentMax. Vee,CE ~ Vee -0.3VCommercial 20 20 20VIN ~ Vee -0.3V orVIN::;; 0.3V Military 20 20rnACapacitance [2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 2SoC, f = 1 MHz, Vee = 5.0V 5 pFCOUT Output Capacitance TA = 25°C, f = 1 MHz, Vee = S.OV 7 pF~otes:. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.~. Tested initially and after any design or process changes that mayaffect these parameters.\C Test Loads and WaveformsRl 481!!5 V O----~NIr-....,OUTPUT 0---...... ---..quivalent to:I30 pF R225SHINCLUDING_JIGAND _- SCOPE -Figure laTHEVENIN EQUIVALENTR1481H5 V o-----J'VV"w-....,OUTPUT 0---...... ---..SpF,NCLUD,NGI _JIG AND- SCOPE -Figure lb167HOUTPUT O--.-...·~~~·TW----O 1.73V 0062-52-853. T A is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation._R225SH0062-43.0 V ------' __ ----"'-GND.; 5 nsFigure 2-.; 5 ns0062-6

finCY7C161. CY7C162~~UcrOR==============================~~~~~~~~~~~~~~~~~~~Switching Characteristics Over Operating Range[4, 5, 12]7C161-25 7C161-35 7C161-45Parameters Description 7C162-25 7C162-35 7C162-45 UnitsREAD CYCLEtRCtAAtOHAtACEtLZCERead Cycle TimeAddress to Data ValidOutput Hold from Address ChangeCE LOW to Data ValidCE LOW to Low Z[7]tHZCE CE HIGH to High Z[6, 7]tDOEtLZOEtHzOEtputPDWRITE CYCLErS]twctSCEtAWtHAtSAtPWEtSDtHDtLzwEtHzWEtAWEOE LOW to Data ValidOE LOW to LOW ZOE HIGH to HIGH ZCE LOW to Power UpCE HIGH to Power DownWrite Cycle TimeCE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to Low Z[7] (7CI62)WE LOW to High Z[6, 7] (7CI62)WE LOW to Data Valid (7CI61)tADV Data Valid to Output Valid (7CI61)Notes:5. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified Ior/IOH and 30 pF load capacitance.6. tHzCE and tHzwE are specified with CL = 5 pF as in Figure lb.Transition is measured ± 500 m V from steady state voltage.7. At any given temperature and voltage condition, tHz is less than tLZfor any given device.Min.25353020202000201303Max. Min. Max. Min. Max.35 45 ns25 35 45 ns3 3 ns25 35 45 ns5 5 ns10 15 15 ns15 25 30 ns3 3 ns15 15 15 ns0 0 ns25 35 45 ns30 40 ns30 35 ns25 35 ns0 0 ns0 0 ns25 35 ns15 20 ns0 0 ns3 3 ns7 10 15 ns25 30 35 ns20 30 35 ns8. The internal write time of the memory is defined by the overlap ofCEI, CE2 LOW and WE LOW. Both signals must be LOW to initiatea write and either signal can terminate a write by going HIGH.The data input setup and hold timing should be referenced to therising edge of the signal that terminates the write.9. WE is HIGH for read cycle.to. Device is continuously selected, CEI. CE2 = VIL.11. Address valid prior to or coincident with CEI. eE2 transition LOW.12. Both CEI and CE2 are represented by CE in the Switching Characteristicsand Waveforms.2-86

5'ACY7C161CY7C162~~NDUcrOR =====================================================================lata Retention Characteristics (L Version only)[4]ParametersDescriptionVDRVee for Retention of DataIeeDR Data Retention CurrentteDRChip Deselect to Data Retention TimetROperation Recovery TimeILlInput Leakage Current~ote:3. tRC = Read Cycle Time.lata Retention WaveformVeeTest ConditionsVee = 2.0V,CE ~ Vee - 0.2VVIN ~ Vee - 0.2VorVIN:::;;: 0.2VDATA RETENTIONMODE....._V_O_R~_2_V_..... 1u~R-1'1.=CY7C161/CY7C162Min. Max.2.010000tRd13]2•. JI-- tCOR =-1'I V OR ,-____ ~~~~~~~~~~_CE IIIIIIIII 1 VIH ' I VIH }SSSSSSSSSSSSUnitsVIJ-AnsnsIJ-Atil0062-11,witching Waveforms [12]~ead Cycle No.1 (Notes 9, to)-----J:~~-----------------------tRc------------------------~1.ADDRE$~ ~I_;~~:~~:~~:~::HA::::t-A~A~~-I----------·-'1-_:::::::::::::::::::::~_~DATA OUT _____ PREVIOUS DATA VALID ~ DATA VALID__ :::::::::::::::0062-72-87

finCY7C161. CY7C162~~UcrOR ~~~~~~~~~~~~==~~~~======~==~====~~~==~~=======Switching Waveforms [12] (Continued)Read Cycle (Notes 9, 11)DATA OUT)k-1\_tpu~ ...\.tACEtDOE-tLZOEi·tRCHIGH IMPEDANCE If , , , , "tLZCE1-=t='"SUPPLY VCC _____ 50%CURRENT _• \" " " " " 1\DATA VALID-X-JI~f.--tPDHIGHIMPEDANCEJ50%IS80062-8Write Cycle No.1 (WE Controlled) (Note 8)twc-tSCE: .\\ \\~ f.1 I I I II I I I LL//~ADDRESS } ~tSAtAW t HA -_tpwE -I~\\ ..DATA INtso.1 tHODATA-IN VALID ~l-tHZWE..:-! ~tLZWE"'~:J~tHZCE-DATA OUT'\I HIGH IMPEDANCE JIDATA UNDEFINED(7C162).III\.-tAOV-DATA OUT ~L(7C161) _______ D_A_TA_UN_D_E_FI_NE_D _______ llo-____ D_A_TA_VA_L_ID _____0062-9Write Cycle No.2 (CE Controlled) (Note 8)twc .ADDRESS-tSA .t scE -~DATA INDATA OUT(7C162)~ ...tAW . -tHA -~tpWE-\\ .\\ \ \ \ \ \ \ \ \ \ \ \ \ \ \-'~ ... jllllllllili/DATA UNDEFINEDt---tsoI::~·1 tHODATA-IN VALID ~DATAOUT--------D-A-TA-U-N-D-EF-IN-E-D----------~(7C161) _____________________-tHZWE -\'\I HIGH IMPEDANCE.II-tAWE - ~. '-. --DA-T-A-V-AL-ID----- ________Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C162 only).0062-102-88

finCY7C161. CY7C162~~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=Typical DC and AC CharacteristicsIII~~N::;

fiACY7C161. CY7C162~~UcrOR==============================================~================~Ordering InformationSpeedPackage OperatingSpeedPackage Operating(ns)Ordering CodeOrdering CodeType Range(ns) Type Range25 CY7C161-25PC P21 Commercial 25 CY7C162-25PC P21 CommercialCY7CI6IL-25PC P21 CY7CI62L-25PC P21CY7C161-25DC D22 CY7C162-25DC D22CY7C16IL-25DC D22 CY7CI62L-25DC D2235 CY7C161-35PC P21 Commercial 35 CY7C162-35PC P21 CommercialCY7C16IL-35PC P21 CY7CI62L-35PC P21CY7C161-35DC D22 CY7C162-35DC D22CY7C161L-35DC D22 CY7C162L-35DC D22CY7C161-35LC L54 CY7C162-35LC L54CY7C16IL-35LC L54 CY7C162L-35LC L54CY7C161-35DMB D22 Military CY7C162-35DMB D22 MilitaryCY7C16IL-35DMB D22 CY7C162L-35DMB D22CY7CI61-35LMB L54 CY7C162-35LMB L54CY7CI61L-35LMB L54 CY7CI 62L-35LMB L5445 CY7C161-45PC P21 Commercial 45 CY7C162-45PC P21 CommercialBitMapCY7CI61L-45PC P21 CY7C I 62L-45PC P21CY7C161-45DC D22 CY7C162-45DC D22CY7C161L-45DC D22 CY7C162L-45DC D22CY7C161-45LC L54 CY7C162-45LC L54CY7C161L-45LC L54 CY7C162L-45LC L54CY7C161-45DMB D22 Military CY7C162-45DMB D22 MilitaryCY7C161L-45DMB D22 CY7CI62L-45DMB D22CY7C161-45LMB L54 CY7CI62-45LMB L54CY7C161L-45LMB L54 CY7C162L-45LMB L54Address DesignatorsAddress Address PinName Function NumberA5 X3 IA6 X4 2A7 X5 3A8 X6 4A9 X7 5AlO YO 6All YI 7Al2 Y5 8A13 Y4 9AO Y3 23Al Y2 24A2 XO 25A3 Xl 26A4 X2 270062-132-90

fiJiCY7C161. CY7C162~UaoR==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIR 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3los 1,2,3Icc 1,2,3ISB! 1,2,3ISB2 1,2,3Switching CharacteristicsParametersREAD CYCLESubgroupstRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tDOE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA· 7,8,9,10,11tpwE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11t AWE (1) 7,8,9,10,11tADVU) 7,8,9,10,11Note:1. 7C161 only.Document #: 38-00029-BData Retention Characteristics(L Version only)ParametersVDR 1,2,3IccDR 1,2,3Subgroups2-91

Features• Automatic power-down whendeselected• Output Enable (OE) Feature(7CI66)• CMOS for optimum speed/power• High speed- 25 ns tAA• Low active power- 275 mW• Low standby power-110 mW• TTL compatible inputs andoutputs• 2V data retention (L version)CYPRESSSEMICONDUCTOR• Capable of withstanding greaterthan 2001 V electrostaticdischargeFunctional DescriptionThe CY7C164 and CY7C166 are highperformance CMOS static RAMs organizedas 16,384 x 4 bits. Easy memoryexpansion is provided by an activeLOW chip enable (CE) and three-statedrivers. The CY7C166 has an activelow output enable (OE) feature. Bothdevices have an automatic power-downfeature, reducing the power consumptionby 60% when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW(and the output enable (OE) is LOWCY7C164CY7C16616,384 X 4 Static R/W RAMfor the 7CI66). Data on the fourinput/output pins (1/00 through 1/03)is written into the memory locationspecified on the address pins (Aothrough A13)'Reading the device is accomplished bytaking chip enable (CE) LOW (and OELOW for 7CI66), while write enable(WE) remains HIGH. Under theseconditions the contents of the memorylocation specified on the address pinswill appear on the four data I/O pins.The I/O pins stay in high impedancestate when chip enable (CE) is HIGH,or write enable (WE) is LOW (or outputenable (OE) is HIGH for 7CI66).A die coat is used to insure alpha immunity.Logic Block DiagramPin ConfigurationsAS Vcc VccA6 A4 A4A7 A3 A3AsA2A9AlA9AlA Ao10AoAllNCAll 1/°31/0 3A12 1/°2 1/0 2A 13 1/°11/°1A,A2A3A.AsAsA7AsSelection GuideMaximum Access Time (ns)Maximum OperatingCurrent (rnA)Maximum StandbyCurrent (rnA)1/03 CE 1/°0 OE 1/00GND WE GNO WE1/02I/O, (.)CD an 0 ...0056-2"""">""«zz>z11)00 go1/002 ~2221 3 2A6 4 NCA7 3 20 A3A7 5 A4A8 4 19 A2 As 6 A3CE Ag 5 18 Al A9 7 A2A 106 17 Ao AID 8 AlAll 7 16 1/°3 Al1 9 AoWE A12 15 1/°2 A12 10 1/°3(OE)A 13 14A131/°11/°2(7C166 ONLY)CE 1/°10056-1Ilj ~I~ ~I~ 3 ~I~ ~0056-40056-57CI64·25 7CIM-35 7CI64-457C166-25 7C166-35 7C166-4525 35 45Commercial 70 70 50Military 70 70Commercial 20/20 20/20 20/20Military 20/20 20/202-92

I~~~. CY7C166~UaoR==================================================================vlaximum RatingsA.bove which the useful life may be impaired. For user guidelines, not tested.),torage Temperature ............... - 65°C to + 150°CStatic Discharge Voltage ..................... > 2001 V~mbient Temperature with (Per MIL-STD-883 Method 3015)'ower Applied .................... -55°C to + 125°C Latch-up Current .......................... > 200 rnAiupply Voltage to Ground Potential .... -0.5V to + 7.0V)C Voltage Applied to Outputsn High Z State ...................... -0.5V to + 7.0V)C Input Voltage ................... - 3.0V to + 7.0V)utput Current into Outputs (Low) ............. 20 rnA~lectrical Characteristics Over Operating Range[4]Parameters Description Test ConditionsVOH Output HIGH Voltage Vee = Min., IOH = -4.0 rnAVOL Output LOW Voltage Vee = Min.,loL = 8.0 rnAVIH Input HIGH VoltageInput LOW VoltageOperating RangeRangeCommercialMilitary [3]7Cl64-257C166·25Min. Max.2.40.42.2 Vee-3.0 0.8Input Load Current GND ~ VI ~ Vee-10 + 10IOZ Output Leakage Current GND ~ Vo ~ Vee, Output Disabled -10 +10lOSIceCapacitance [5]Output Short CircuitCurrendllVee OperatingSupply CurrentAutomatic CE[2]Power Down CurrentVee = Max., VOUT = GND -350Vee = Max.lOUT = OmAMax. Vee,Automatic CE[2] CE ~ Vee - 0.3VPower Down Current VIN ~ Vee -0.3V orVIN ~ 0.3VParametersDescriptionCINInput CapacitanceI COUTOutput CapacitanceNotes:1. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. A pull-up resistor to Vee on the eE input is required to keep thedevice deselected during Vee power-up, otherwise ISB will exceedvalues given.AC Test Loads and WaveformsR1481H5V~------~~~~OUTPUT n----_----..30PFINCLUDINGr_ JIG AND _- SCOPE -Figure la~~5nEquivalent to: THEVENIN EQUIVALENT16712OUTPUT Ol---...J,.~"~;\r'. ---0 1.73 VAmbientTemperatureaoc to + 70°C- 55°C to + 125°C7Cl64·357C166·35Min.Vee5V ± 10%5V ± 10%7C164-457C166-45 UnitsMax. Min. Max.2.4 2.4 V0.4 0.4 V2.2 Vee 2.2 Vee v-3.0 0.8 -3.0 0.8 V-10 + 10 -10 + 10 J-LA-10 + 10 - 10 + 10 J-LA-350 -350 rnA~C_o_m_m __ e_rc_ia_I~~ __ +-_70 __ ~ ____ ~ ___Military 70 707_0 __ r-__ +-_50~ rnAMax. Vee, CE ~ VIH f-C:.o:..:m::m::::.:..e:.rc;,::ia::I----1I-__ +__::.2o~+_----_I---2..:..0--1_--+__-20__l rnAMin. Duty Cycle = 100% Military 20 20R1481H5 V ~-----.JW"w---.OUTPUT 0----..... -----...5 pFR225512INCLUDINGI JIG AND":'" SCOPE ":'" 0056-6Figure Ib0056-8Commercial 20 20 20~--------4---~--~r-----_4----~----r---~ rnAMilitary 20 20Test Conditions Max. UnitsTA = 25°C, f = 1 MHz, 5Vee = 5.0V pF72·933. T A is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.5. Tested initially and after any design or process changes that mayaffect these parameters.3.0 V -----.. ----.......GND" 5ns -" 5 ns0056-7Figure 2

finCY7CIM. CY7C166~U~~~~~~~====~================~====~~======~~====~~==~Switching Characteristics Over Operating Range[4, 6]7Cl64-25 7Cl64·35 7Cl64-45Parameters Description 7C166·25 7C166·35 7Cl66·45 UnitsREAD CYCLEtRCtAAtOHAtACERead Cycle TimeAddress to Data ValidOutput Hold from Address ChangeCE LOW to Data ValidtOOE OE LOW to Data Valid 7C166tLZOE OE LOW to LOW Z 7C166tHZOE OE HIGH to HIGH Z 7C166tLZCECE LOW to Low Z[S]tHZCE CE HIGH to High Z[7, s]tputPDWRITE CYCLE[9]twctSCEtAWtHAtSAtpwEtSDtHDtLzWECE LOW to Power UpCE HIGH to Power DownWrite Cycle TimeCE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to Low Z[s]tHZWE WE LOW to High Z[7, 8]Notes:6. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IorJIOH and 30 pF load capacitance.7. tHZCE and tHzwE are specified with CL = 5 pF as in Figure 1 h.Transition is measured ± 500 m V from steady state voltage.S. At any given temperature and voltage condition, tHZCE is less thantLZCE for any given device. These parameters are guaranteed and not100% tested.Min. Max. Min. Max. Min. Max.25335020202000201303035 45 ns25 35 45 ns3 3 ns25 35 45 ns15 25 30 ns3 3 ns15 15 15 ns5 5 ns10 15 15 ns0 0 ns25 35 45 ns30 40 ns25 35 ns25 35 ns0 0 ns0 0 ns25 35 ns15 20 ns0 5 ns3 3 ns7 0 10 0 15 ns9. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.10. WE is HIGH for read cycle.11. Device is continuously selected, CE = VIL. (7C166: OE = VILalso.)12. Address valid prior to or coincident with CE transition low.13. 7C166 only: Data I/O will be high impedance ifOE = VIH.2-94

&iCY7Cl64. CY7C166~U~================================================================~Data Retention Characteristics (L Version Only)ParameterDescriptionTestCY7Cl64/CY7Cl66Conditions Min. Max.VDR Vee For Retention of Data 2.0IeeDRData Retention CurrentVee = 2.0V,Chip Deselect to Data CE 2 Vee - 0.2VteDRRetention Time VIN 2 Vee - 0.2VtR Operation Recovery Time orVIN ~ 0.2VILlInput Leakage CurrentNote:14. tRC = read cycle time.Data Retention WaveformDATA RETENTIONt.AODE--lr-'cOR :.1'------1= tR IVee •. J V DR "'2V li.5V0tRcl l4 ]CE I//IIIIZI 1V1H' I V1Hl'\\\\\\\\\\\\10002UnitsVp.Ansnsp.AEI0056-13Switching WaveformsRead Cycle No.1 (Notes 10, 11)ADDRESS _--1-----J:~~-----------------------tRc------------------------~1~___ I_;~~~~~~to~~HA~~~~t-A_-A~_'-'-----'-! ------------*--------DATA OUT PREVIOUS DATA VALID DATA VALID----------------------------0056-92-95

fijiCY7C164. CY7C166~UcroR ==========~~~==~~~~~~==~============~======~====~~~==~=Switching Waveforms (Continued)Read Cycle No.2 (Notes 10, 12)OE(7e16 6)jr-~~~lACEIRC,~JlODEf4--- I LZOEiHIGH IMPEDANCE 1/ / / / / I/'DATA OUTJILZCE ----j'\. '\. '\. '\. '\. ~!---tpuSUPPL Vce Y ______ 50%CURRENT_L;--IHZCE-~ro':3DATA VALID/I------tpoHIGHIMPEDANCE0056-10Write Cycle No.1 (WE Controlled) (Notes 9,13)~-----------------------------twe----------------------------~14-------------------- IseE ------------------114---------------------tAW---------------~~--14----------ISA------~~------t~E------~I+---'--------tso ----------+-DATA INDATA-IN VALIDDATA I/O ----------D-A-TA-U-ND-E-F-IN-E-D-------IHZWE:::j»)0-----------< ______ _0056-11Write Cycle No.2 (CE Controlled) (Notes 9, 13)14---------------------twe----------------------~ADDRESS1-------- tSA --------1-- -----ISCE -------.j------t~E -----------.j14---+-----------tso--------+--DATA INDATA-IN VALIDtHZWE--!------------------~ HIGH IMPEDANCEDATA 1/0 DATA UNDEFINED j).----------------------Note: lfeE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.0056-122-96

;nCY7C164. CY7C166. ~====================================~fypical DC and AC Characteristics~~0'" N~c(:EII:0zNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.41.21.00.8VV./IV0.60.40.2 Iss0.04.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (V)~U20'" N~c(:EII:0z1.21.00.80.60.4NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE~~0.2 t---ISBVee -5.0VVIN -5.0V0.0-55 25.0 125.0AMBIENT TEMPERATURE I'C);(!~ffiII:II::>u'" uII::>51~~~:>012010080604020o0.0"OUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE~'"Vee= 5.0 VTA = 2S'C'"1.0 2.0 3.0OUTPUT VOLTAGE (VI4.0II«~~N~c(:EII:0 1.0z0.9NORMALIZED ACCESS TIMEvs SUPPLY VOLTAGE1.41.31.21.1"'" ~ TA" 25'C~............... r-0.84.0 4.5 5.0 5.5 6.01.6NORMALIZED ACCESS TIMEvs. AMBIENT TEMPERATURE1.4 ~----+-------I«~~ 1.2 ~----+-----:21'e::....-IN~c(~ 1.0 ~----~~-----Ioz0.8 h"c...---+------~0.6 .....____...1-_____--'-55 25 125;(!~ffiII:II::>u>lZiii~~~:>014012010080604020OUTPUT SINK CURRENTvs OUTPUT VOLTAGE1~..IV//7/Vee = 5.0VTA = 25'CoV0.0 1.0 2.0 3.04.0SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE I'C)OUTPUT VOLTAGE IVITYPICAL POWER-ON CURRENTvs SUPPLY VOLTAGE3.02.5j 2.0~N~ 1.5c(:EII:1.0i-/0.5V0.00.0 1.0 2.0 3.0 4.0 5.0SUPPLY VOLTAGE (VI30.025.01 20 . 0«;;, 15.0~o 10.05.00.0TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADING/I/'/---/,.IVTA .. 25°Cvee = 4.SOVl7o 200 400 600 800 1000CAPACITANCE (pFINORMALIZED Icc1.25 rV;';;s~. CY~CL..;;..;;;;E~TIM;.;;;.;,;;.;E;...... ____...,Vee = 5.0 VTA - 25·CVIN = 0.5 V~ 1.01----i-----lr------,4faN~~i 0.75,~---t"""::--...f_--__IO.SOlI0~---..I2~0---.... 30---.....I4OCYCLE FREQUENCY (MHz)0056-142-97

~CY7Cl64. CY7C166~U~~~~~~~~~~====~========================================7CI64 Truth Table7Cl66 Truth TableCE WE Input/Outputs Mode CE WE OE Inputs/Outputs ModeH X HighZ Oeselect Power Oown H X X HighZ Oeselect Power OownL H OataOut Read L H L Oata Out ReadL L OataIn Write L L X Oata In WriteL H H HighZ OeselectOrdering InformationSpeedPackage OperatingSpeedPackage OperatingOrdering Code(ns)Ordering CodeType Range(ns) Type Range25 CY7C164-25PC P9 Commercial 25 CY7C166-25PC P13 CommercialCY7C164L-25PC P9 CY7C 166L-25PC P13CY7Cl64-25VC V13 CY7C166-25VC V13CY7CI64L-25VC V13 CY7C166L-25VC V13CY7Cl64-250C 010 CY7C 166-250C 014CY7C164L-250C 010 CY7C166L-250C 014CY7C164-25LC L52 CY7C166-25LC L54CY7C164L-25LC L52 CY7C166L-25LC L5435 CY7Cl64-35PC P9 Commercial 35 CY7C166-35PC P13 CommercialCY7Cl64L-35PC P9 CY7C166L-35PC P13CY7C164-35VC V13 CY7C166-35VC V13CY7CI64L-35VC V13 CY7C166L-35VC V13CY7C164-350C 010 CY7C166-350C 014CY7C164L-350C 010 CY7C166L-350C 014CY7C 164-35LC L52 CY7C166-35LC L54CY7C164L-35LC L52 CY7C166L-35LC L54CY7C164-350MB 010 Military CY7C166-350MB 014 MilitaryCY7C164L-350MB 010 CY7C166L-350MB 014CY7Cl64-35LMB L52 CY7C 166-35LMB L54CY7C164L-35LMB L52 CY7C166L-35LMB L5445 CY7C164-45PC P9 Commercial 45 CY7C166-45PC P13 CommercialCY7Cl64L-45PC P9 CY7C166L-45PC P13CY7C164-45VC V13 CY7C166-45VC V13CY7CI64L-45VC V13 CY7C166L-45VC V13CY7C164-450C 010 CY7C 166-450C 014CY7C164L-450C 010 CY7C 166L-450C 014CY7C164-45LC L52 CY7C166-45LC L54CY7C164L-45LC L52 CY7C166L-45LC L54CY7C164-450MB 010 Military CY7C166-450MB 014 MilitaryCY7C164L-450MB 010 CY7C166L-450MB 014CY7C164-45LMB L52 CY7C166-45LMB L54CY7C164L-45LMB L52 CY7C166L-45LMB L542-98

WABitMapCY7C164. CY7C166~~~R================================================================Address DesignatorsAddress Address PinName Function NumberA5 X3 1A6 X4 2A7 X5 3A8 X6 4A9 X7 5A10 Y5 6All Y4 7A12 YO 8A13 Y1 9AO Y2 17A1 Y3 18A2 XO 19A3 Xl 20A4 X2 210056-152-99

WACY7C164. CY7C166~~============~~~==~~~==~==================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3Vm 1,2,3VIL 1,2,3IIX 1,2,3loz 1,2,3lOS 1,2,3IcC 1,2,3ISB! 1,2,3ISB2 1,2,3SubgroupsSwitching CharacteristicsParametersREAD CYCLESubgroupstRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tOOE[l] 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tso 7,8,9,10,11tHO 7,8,9,10,11Data Retention Characteristics(L Version Only)ParametersVOR 1,2,3IccoR 1,2,3Note:1. 7C166 only.Document #: 38-00032-BSubgroups2-100

Features• Automatic power-down whendeselected• CMOS for optimumspeed/power• High speed-25 ns• Low active power- 248 m W (commercial)- 275 mW (military)• Low standby power-83mW• TTL compatible inputs andoutputs• Capable of withstanding greaterthan 2001 V electrostaticdischargeCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C167 is a high performanceCMOS static RAM organized as16,384 words x 1 bit Easy memory expansionis provided by an active LOWchip enable (CE) and three-state drivers.The CY7C167 has an automaticpower-down feature, reducing the powerconsumption by 70% when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.Data on the input pin (DI) is writteninto the memory location specified onthe address pins (Ao through A 13).CY7C16716,384 X 1 Static R/W RAMReading the device is accomplished bytaking the chip enable (CE) LOW,while write enable (WE) remainsHIGH. Under these conditions thecontents of the memory location specifiedon the address pins will appear onthe data output (DO) pin.The output pin stays in high impedancestate when chip enable (CE) is HIGHor write enable (WE) is LOW.A die coat is used to insure alpha im- I!Wmunity. ~Logic Block DiagramPin ConfigurationsAoAlA2A3A4AsA6Uti')~OU...-«>< Ao VeeAlA13A12A2A12A3 A"A2DOA3A11A4 A 10A4 Al0ASAgAsAgA6 ASAsDO A7A7CE 01I~ ~I~ c(!)WE 0017-2GNDCE0017-30017-1Selection GuideMaximum Access Time (ns)Maximum OperatingCurrent (rnA)LSTD7C167-25 7C167-35 7C167-4525 35 45Commercial 45 45Commercial 60 60 50Military 60 502-101

~ CY7C167~~~~================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, nottested.)Storage Temperature ............... -65°C to + 150"C Static Discharge Voltage ..................... >2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 20 to Pin 10) .................... -0.5V to + 7.0V Operating RangeDC Voltage Applied to OutputsAmbientRangein High Z State ...................... -0.5V to + 7.0VTemperatureVeeDC Input Voltage ................... -3.0V to +7.0VOutput Current into Outputs (Low) ............. 20 rnACommercialMilitary [3]crCto +7crC- 55°C to + 125°C5V ±1O%5V ±10%Electrical Characteristics Over Operating Range[4]Parameters Description Test ConditionsVOHVOLVIHVILOutput HIGH Voltage Vee = Min.,IOH = -4.0mAOutput LOW VoltageInput HIGH VoltageInput LOW VoltageVee = Min., IOL = 12.0 rnA,8.0mAMiIIIX Input Load Current GND ~ VI ~ VeeOutput Leakage GND ~ Va ~ VeelozCurrentOutput DisabledlosleeISB• -35 and -45 onlyCapacitance [5]ParametersCINOutput Short[I]Circuit CurrentVee OperatingSupply CurrentAutomatic CE[2]Power Down CurrentVee = Max.,VOUT = GNDVee = Max.lOUT = OmAMax. Vee,~2VIHDescriptionInput CapacitanceCoUTOutput CapacitanceCeEChip Enable CapacitanceNotes:I. Duration of the short circuit should not exceed 30 seconds.2. A pull-up resistor to Vee on the CE input is required to keep thedevice deselected during Vee power-up, otherwise ISB will exceedvalues given.AC Test Loads and Waveforms7C167L-25, 35 7C167-25, 35 7C167-45Min. Max. Min. Max. Min. Max.Units2.4 2.4 2.4 V0.4 0.4 0.4 V2.0 Vee 2.0 Vee 2.0 Vee V-3.0 0.8 -3.0 0.8 -3.0 0.8 V-10 +10 -10 +10 -10 +10 p.A-50 +50 -50 +50 -50 +50 p.A-350 -350 -350 rnACommercial 45 60 50Military· 60 50Commercial 15 20 15Military· 20 20Test Conditions Max. UnitsTA = 25°C, f = 1 MHz4Vee = 5.0V 6 pF3. T A is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.5. Tested initially and after any design or process changes that mayaffect these parameters.5rnArnAEquivalent to:R13290(481 o MIL)6Vo-------~~~R13290(481 o MIL)5 V 0-------.-.,"""'-,OUTPUT 0-----.._--...... OUT~To----_----_1m=;ttINCLUDING I 30 pFJIG ANDSCOPEFigure laR2202n(266nMll)THEVENIN EQUIVALENT5pFINClUDINGfJIG AND .1.SCOPE ':'Figure Ib125AOUTPUT o--wY--O 1.9V COMMERCIAL167AOUTPUTo--wY--01.73V MILITARY 0017-5R2202n(26612 MILlALL INPUT PULSESkGND 10%5ns0017-4Figure 25ns0017-62-102

~RESSCY7C167~~~~UcrOR================================================================Switching Characteristics Over Operating Range[4, 6]ParametersREAD CYCLEtRCtRCtAAtAAtOHAtACEtLZCEDescriptionRead Cycle Time (Commercial)Read Cycle Time (Military)Address to Data Valid (Commercial)Address to Data Valid (Military)Data Hold from Address ChangeCE LOW to Data ValidCE LOW to Low Z[S]tHZCE CE HIGH to High Z[7, S]tputpDWRITE CYCLE[9]twctSCEtAWtHAtSAtPWEtSDtHDCE LOW to Power UpCE HIGH to Power DownWrite Cycle TimeCE LOW to Write EndAddress Set·up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndtHzwE WE LOW to High Z[7, s]tLzwEWE HIGH to Low Z[s]Notes:6. Test conditions assume signal transition times of 5 ns or less, timingrefe~ence levels of ~.5V, input pulse levels of 0 to 3.0V and outputloadmg of the specIfied Iov'IOH and 30 pF load capacitance.7. tHzCE and tHzwE are specified with CL = 5 pF as in Figure lb.Transition is measured ± 500 m V from steady state voltage.S. At any given temperature and voltage condition, tHZ is less than tLZfor any given device.Switching WaveformsRead Cycle No.1 (Notes 10, 11)ADDRE§ ~I+-_7C167·25 7C167·35 7C167·45Min. Max. Min. Max. Min. Max.25350252525001515000Units30 40 ns35 40 ns25 30 40 ns35 40 ns3 3 ns25 35 45 ns5 5 ns15 20 25 ns0 0 ns20 25 30 ns30 40 ns30 40 ns30 40 ns0 0 ns0 0 ns20 20 ns15 15 ns0 0 ns15 0 20 0 20 ns15 0 20 0 25 ns9. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going high. The datainput setup and hold timing should be referenced to the rising edgeof the signal that terminates the write.10. WE is HIGH for read cycle.II. Device is continuously selected, CE = V IL.12. Address valid prior to or coincident with CE transition LOW.-_ -_-_-_-_"~!-=--=--=--=--_~--..I*__----1...-I----tOHA ----101DATA OUT PREVIOUS DATA VALID DATA VALIDfI0017-72-103

~ CY7C167~~~UcrOR================================================================~Switching Waveforms (Continued)Read Cycle No.2 (Notes 10, 12))t- 1\tRCtAce .....,ljDATA OUTt Lzce:-! _tHzce~1HIGHIMPEDANCEHIGH IMPEDANCE 1/ / / / / "DATA VALID1'\ '\ '\ '\ , 1\Jr---tpo~tpu1SUPPLY Vcc ______ 50%CURRENT_so;t=158--jICC0017-8Write Cycle No.1 (WE Controlled) (Note 9)~-----------------------------~c------------------------__ ~~ADDRESS14-----------tsce -----------~14--------------tAw----------------1~---14------ISA----------+I ~------IME------~DATAI/O ----------D-A-TA-UN-D-E-F-,N-E-D-------IHzwe~»)0----------"'\. ______ _0017-9Write Cycle No.2 (CE Controlled) (Note 9)~--------------------------IWC----------------~----~t--------tsce ------__+1~------IME-------~14--'-------ISO------+-DATA INDATA-IN VALID14---+--------ISO------+-DATA-IN VALIDIHzwe------!------------------__""\!HIGH IMPEDANCEDATA I/O DATA UNDEFINED ,)0----------------------Note: If CE goes high simultaneously with WE high, the output remains in a high impedance state.0017-102-104

~ CY7C167~~~UCTOR ==~~~~~~~~~=================================================Typical DC and AC Characteristics'"]SN:;«::EIX:0Z1.41.21.00.80.60.4NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGELleyV~0.2ISB0.04.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (VI'"enUJ:cwN::;«::EIX:cz1.21.00.80.60.4NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE~0.2 ~ISB~Vee =5.0VVIN = 5.0 V0.0-55 25.0 125.0AMBIENT TEMPERATURE rCIC(!...ZwIX:IX::::>uwuIX::::>g......~:::>0OUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE605040302010~""~Vee = 5.0VTA = 25"C",3.0 4.0OUTPUT VOLTAGE (V)o o 1.0 2.0'"EI1.41.3~:J 1.2SN:; 1.1«::EIX:0 1.0z0.9NORMALIZED ACCESS TIMEvs. SUPPLY VOLTAGE.............""TAc 25°Cr"--. -0.84.0 4.5 5.0 5.5 6.0NORMALIZED ACCESS TIMEvs. AMBIENT TEMPERATURE1.6 r-----,------...,1.4 t-----+-------iot:JS 1.2 t-----+----7II"""--iN::;«~ 1.0 ~---____,~:...-------1oz0.8 .-..~---+--------I0.6 L.-____ "--_____ ~-55 25 125C(!...ZwIX:IX::::>u:.:ziii......~:::>0OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE150125100155025VL ,I....-'/'----/~~e= =2~;~ V -I1.0 2.0 3.0 4.0 5.0SUPPLY VOLTAGE (VIAMBIENT TEMPERATURE rCIOUTPUT VOLTAGE (V)3.0TYPICAL POWER-ON CURRENTvs. SUPPLY VOLTAGETYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADING3Or----,--~---,---r--...,NORMALIZED Iccvs. CYCLE TIME1.1 ~--......,----r---..,2.5~ 2.0SN:; 1.5«::EIX:0 1.0z0.5.---V0.00.0 1.0 2.0 3.0 4.0 5.0/c~:J«8cTA = 25°CVee =4.5 V20t--+--~-~L--+---i10t--~~~--1--+---1200 400 600 800 1000Vee G 5.0 VTA = 25°CVIN = OS V1l 1.0 t----f----+---~SN:;«::E~ 0.9 t----+-'7"'--+------I20 30 40SUPPLY VOLTAGE (VICAPACITANCE (pFICYCLE FREQUENCY (MHz)0017-112-105

~ CY7C167~~~U~================================================================Ordering InformationSpeed Icc Ordering(ns) mA Code25 45 CY7C 167L-25PCCY7C167L-250CCY7CI67L-25LC60 CY7C167-25PCCY7C167-250CCY7C167-25LC35 45 CY7CI67L-35PCCY7C167L-350CCY7CI67L-35LC60 CY7C167-35PCCY7C167-350CCY7C167-35LCCY7C167-350MBCY7CI67-35LMB45 50 CY7C167-45PCCY7C167-450CCY7C167-45LCCY7C167-450MBCY7CI67-45LMBBitMapPackageTypeP506L51P506L51P506L51P506L5106L51P506L5106L51OperatingRangeCommercialCommercialMilitaryCommercialMilitaryAddress DesignatorsAddress Address PinName Function NumberAo X2 1AI Xs 2A2 X6 3A3 Y3 4A4 Y4 5As Yo 6A6 YI 7A7 Y2 13As Ys 14A9 Y6 15AIO Xo 16All X3 17AI2 X4 18AI3 XI 19Y-ADD!ESS 00 ...... 31 32 ...... 83 84 ....•. 95 98 ..... 1271241211-----RDwlg•• BEDUNDAIIT COLUMN# • REDUNDANT ROW0017-122-106

~ CY7C167~~~UaDR==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3ICC 1,2,3ISB 1,2,3IISwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAw 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tPWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00033-B2·107

Features• Automatic power·down whendeselected (7CI68)• CMOS for optimum speed/power• High Speed- 25 ns tAA- 15 ns tACE (7CI69)• Low active power- 330 m W (commercial)- 385 mW (military)• Low standby power (7CI68)-83mW• TTL compatible inputs andoutputsCYPRESSSEMICONDUCTOR• Capable of withstanding greaterthan 2000V electrostaticdischargeFunctional DescriptionThe CY7C168 and CY7C169 are highperformance CMOS static RAMs organizedas 4096 x 4 bits. Easy memoryexpansion is provided by an activeLOW chip enable (CE) and three-statedrivers. The CY7C168 has an automaticpower-down feature, reducing thepower consumption by 77% when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.CY7C168CY7C1694096 X 4 Static R/W RAMData on the four input/output pins(1100 through 1/03) is written into thememory location specified on the addresspins (Ao through All).Reading the device is accomplished bytaking chip enable (CE) LOW, whilewrite enable (WE) remains HIGH. Underthese conditions the contents of thememory location specified on the addresspins will appear on the four dataI/O pins.The I/O pins stay in high impedancestate when chip enable (CE) is HIGH,or write enable (WE) is LOW.A die coat is used to insure alpha immunity.Logic Block DiagramPin Configurations1/001/011/02A4VeeA5A3A6A2A7AIAsAoAg 1/00Al0 1/01All 1/02CE 1/03GND0II)~O'"«>

• finCY7C168. CY7C169~~ucrOR~~~~~~~~~~=================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CStatic Discharge Voltage ..................... > 2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 20 to Pin 10) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - O. 5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current into Outputs (Low) ............. 20 rnAOperating RangeRangeAmbientTemperatureVeeCommercial O°C to + 70°C 5V ± 10%Military [2] - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over Operating Rangel3]7C168L-25, ·35 7C168·25, ·35 7C168·45Parameters Description Test Conditions 7C169L·25, ·35 7C169.25, ·35 7C169·40 UnitsMin. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,loH = -4.0mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 0.4 0.4 VVIH Input HIGH Voltage 2.0 Vee 2.0 Vee 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND S VI S Vee -10 +10 -10 +10 -10 +10 IJ-AOutput Leakage GND S Vo s Vee,loz-50 +50 -50 +50 -50CurrentOutput Disabled+50 IJ-AloSOutput Short CircuitCurrent[l] Vee = Max., VOUT = GND -350 -350 -350 mAVee Operating Vee = Max. Commercial 70 90 70lee Supply Current lOUT = OmA Military * 90 70mAfIISBlAutomatic CE Max. Vee, Commercial 15 20 15Power Down Current CE ~ VIR Military * 20 20ISB2Automatic CE Max. Vee, Commercial 11 11 11Power Down Current CE ~ Vee - 0.3V Military * 20 20mAmA*-35 and -45 onlyCapacitance [4]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz, Vee = 5.0V 4 pFCOUT Output Capacitance TA = 25°C, f = 1 MHz, Vee = S.OV 7 pFNotes:1. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. T A is the "instant on" case temperature.AC Test Loads and WaveformsR1481l!R14S1H5 v O-----..J\M_ .... 5 V D-----VV"w-....OUTPUT 0---..... ---... OUTPUT 0---..... ---..I30 pF R2255nINCLUDING_JIGAND _- SCOPE -Figure 1aIINCLUDING5 pFJIG AND-=- SCOPE -=-Figure Ib3. See the last page of this specification for Group A subgroup testinginformation.4. Tested initially and after any design or process changes that mayaffect these parameters.R2255l!0021-43.0 V -----.. ----.....GND

fmCY7C168. CY7C169~NDUcrOR =====================================================================Switching Characteristics Over Operating Range[3, 5]7C168·25Parameters Description 7C169·25READ CYCLEMin.tRC Read Cycle Time 25tAAAddress to Data ValidtOHA Output Hold from Address Change 3tACE CE LOW to Data ValidI 7C168I 7C169tLZCE CE LOW to Low Z[7] 5tHzCE CE HIGH to High Z[6, 7]tpu CE LOW to Power Up (7CI68) 0tpDCE HIGH to Power Down (7CI68)tRCS Read Command Set-up 0tRCH Read Command Hold 0WRITE CYCLE[S]twc Write Cycle Time 25tSCE CE LOW to Write End 25tAW Address Set-up to Write End 20tHA Address Hold from Write End 0tSA Address Set-up to Write Start 0tpwE WE Pulse Width 20tSD Data Set-up to Write End 10tHD Data Hold from Write End 0tLZWE WE HIGH to Low Z[7] 6tHzwE WE LOW to High Z[6, 7]Notes:5. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IoI/IoH and 30 pF load capacitance.6. tHZCE and tHzwE are tested with CL = 5 pF as in Figure lb. Transitionis measured ± 500 m V from steady state voltage.7. At any given temperature and voltage condition, tHZ is less than tLZfor all devices.Switching WaveformsRead Cycle No.1 (Notes 9, 10)Max.2525151525107Cl68·357C169-40 7C168·457C169·35 UnitsMin. Max. Min. Max. Min. Max.35 40 45 ns35 40 45 ns3 3 3 ns35 45 ns25 25 ns5 5 5 ns20 20 25 ns0 0 ns25 30 ns0 0 0 ns0 0 0 ns35 40 40 ns30 30 35 ns30 40 35 ns0 0 0 ns0 0 0 ns30 35 35 ns15 15 15 ns0 3 3 ns6 6 6 ns15 20 20 ns8. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.9. WE is HIGH for read cycle.10. Device is continuously selected, CE = VIL.11. Address valid prior to or coincident with CE transition LOW.-----,J;~~--------------------------tRc--------------------------~1~ADDRE~_~ ______ ~I_:~~~~~~~-_~~-~~H~A~~~~~t_A-A::'-_.-!----------..-.-'---------------------------~------------------DATA OUT PREVIOUS DATA VALID DATA VALID---------------------------------------------- 0021-72-110

5JlCY7C168. CY7C169~~~================================================================~witching Waveforms (Continued).lead Cycle (Notes 9, 11)~~tRC]'f-DATA OUT(7CI68) VCCSUPPLYCURRENTtACEtLZ=IHIGH IMPEDANCE 1/71 7 7'\ '- '- '- '-j..-tpu_f-511'1o'IT~tHZ~HIGHIMPEDANCEDATA VALID,f--tPD----+j511'10ICCIS8..J~-i--tRcSI--tRCH-.)~0021-8Write Cycle No.1 (WE Controlled) (Note 8)~----------------------------~C--------------------------~ADDRESS~-------------------t~E--------------------~I_~~~~~-r~~~~~~----------------------~w-----------------------.~---104---------tSA----------t *------tPWE------o.I--------------------~~~I 1_--------------------14-~------tsD-------~~DATA INDATA-IN VALIDDATA 110 ---------O-A-T-A-U-N-D-EF-IN-E-D-------tHZWE~)lo-----------c\. ______ _0021-9Write Cycle No.2 (CE Controlled) (Note 8)~----------------------~C---------------------~ADDRESS--------J.--------- tSCE -------~I,-----~------------!.--l----------tSD'------l-DATA INDATA-IN VALID____________ ~'~------------------JI'----------__tHZWE---!-----------------__'\(HIGH IMPEDANCEDATA 110 DATA UNDEFINED J~----------;.;.;.;;;;.;.;.;,;;.;.;;.;.;...;..;;.;;-------0021-10Note: IfCE goes HIGH simultaneously with WE high, the output remains in a high impedance state.2-111

(;nCY7C168CY7C169~~NDUcroR ======================================================~==~~=======Typical DC and AC Characteristics11U~0wN::;«~It0zNORMALIZED SUPPLY CURRENTvs SUPPLY VOLTAGE1.41.21.00.80.60.4VVIV/:0.2 ISB0.04.0 4.5 5.0 5.5 6.0SUPPL V VOLTAGE (VI~U~cwN:;c(:IEII:cZNORMALIZED SUPPLY CURRENT1.21.00.80.60.4vs AMBIENT TEMPERATURE~~Vee· 5.0 VVIN· 5.0 V0.2 r---ISB0.0-55 25.0125.0AMBIENT TEMPERATURE ('CI

5ACY7C168.. CY7C169~~~==============================~========================~==~====Ordering InformationSpeed Icc Package OperatingOrdering Code(ns) mA Type Range2S 70 CY7C 168L-2SPC PS CommercialCY7C 168L-2S0C 06CY7C 168L-2SLCCY7CI68L-2SSCLSISS90 CY7CI68-2SPC PSCY7C168-2S0C 06CY7CI68-2SLCCY7CI68-2SSCLSI3S 70 CY7CI68L-3SPC PS CommercialSSCY7CI68L-3SOC 06CY7CI68L-3SLCCY7CI68L-3SSCLSISS90 CY7CI68-3SPC PSCY7C168-3S0C 06CY7CI68-3SLCCY7CI68-3SSCLSISSCY7CI68-3S0MB 06 MilitaryCY7CI68-3SLMBLSI4S 70 CY7CI68-4SPC PS CommercialCY7C 168-4S0C 06CY7C 168-4SLCCY7CI68-4SSCLSISSCY7CI68-4S0MB 06 MilitaryCY7CI68-4SLMBLSISpeed(ns)IccrnA2S 60903S 609040 70BitMapOUTPUTS 3210 .. 3210Y-ADOREas 00 ••••• 07Ordering CodePackageTypeOperatingRangeCY7CI69L-2SPC PS CommercialCY7CI69L-2S0C 06CY7CI69L-2SLCCY7CI69-2SPCLSIP5CY7C169-2S0C 06CY7CI69-2SLCLSICY7CI69L-3SPC P5 CommercialCY7CI69L-3SOC 06CY7CI69L-3SLCCY7CI69-3SPCLSIP5CY7C169-3S0C 06CY7CI69-3SLCLSICY7CI69-3S0MB 06 MilitaryCY7CI69-3SLMBLSICY7CI69-4OPC P5 CommercialCY7C169-400C 06CY7C169-40LCLSICY7C169-400MB 06 MilitaryCY7CI69-40LMBLSI0123 .• 0123 3210 •• 3210 0123 •• 012308. '" •. 15 18 ••••• 23 24 •••.. 31IIAddress DesignatorsAddress Address PinName Function NumberAo Xo 16Al X3 17A2 Xt 18A3 Xl 19A4 X2 1As Xs 2A6 X6 3A7 Y3 4As Y4 SA9 Yo 6AlO YI 7All Y2 8~====

finCY7C168. . CY7C169~~U~R============================================================~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3Icc 1,2,3ISB1[12] 1,2,3ISB2[12] 1,2,3Note:12. 7C168 only.SubgroupsSwitching CharacteristicsParametersREAD CYCLESubgroupstRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tRCS 7,8,9,10,11tRCH 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00034-B2-114

[features• CMOS for optimumspeed/power• High speed- 25 ns tAA-15 ns tACE• Low active power- 495 mW (commercial)- 660 mW (military)• TTL compatible inputs andoutputs• Capable of withstandinggreater than 2001V~lectrostatic discharge• Output enableCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C170 is a high performanceCMOS static RAM organized as 4096words x 4 bits. Easy memory expansionis provided by an active LOW chip select(CS), an active LOW output enable(OE), and three-state drivers.Writing to the device is accomplishedwhen the chip select (CS) and write enable(WE) inputs are both LOW. Dataon the four input/output pins(1/00 through 1103) is written into thememory location specified on the addresspins (Ao through All).CY7C1704096 X 4 Static R/W RAMReading the device is accomplished bytaking chip select (CS) and output enable(OE) LOW, while write enable(WE) remains HIGH. Under theseconditions the contents of the memorylocation specified on the address pinswill appear on the four data I/O pins.The I/O pins stay in high impedancestate when chip select (CS) or outputenable (OE) is HIGH, or write enable(WE) is LOW.A die coat is used to insure alpha immunity.fillLogic Block DiagramPin Configuration1/°01/°10037-21/°21/°3CSWEOE0037-1Selection GuideMaximum Access Time (ns)Maximum OperatingCurrent (mA)II7C170·2525Commercial 90Military7C170·35 7C170·4535 4590 90120 1202-115

Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 22 to Pin 11) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current into Outputs (Low) ............. 20 rnAElectrical Characteristics Over Operating Rangel3]Static Discharge Voltage ............ , ........ >2oo1V(Per MIL-STD-883 Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureVeeCommercial O°C to + 70°C SV ±1O%Military (4) - SSoC to + 12SoC SV ±1O%Parameters Description Test Conditions7Cl70Min. Max.UnitsVOH Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 VVIH Input HIGH Voltage 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 VIIX Input Load Current GND~ VI ~ Vee -10 +10 J-LAlozOutput LeakageGND~ Vo ~ VeeCurrentOutput Disabled-SO +SO J-LAlosOutput Short[l)Circuit CurrentVee = Max., VOUT = GND -3S0 rnAleeCapacitance [2]Vee Operating Vee = Max. I Commercial 90 rnASupply Current lOUT = OmAI Military 120Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 2SoC, f = 1 MHz 4pFCOUT Output Capacitance Vee = S.OV 7Notes:1. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. Tested initially and after any design or process changes that mayaffect these parameters.AC Test Loads and WaveformsRl481H5 v D----~N_...,R1481H5 v D-------Jw\,-.....OUTPUT 0---..----.... OUTPUT 0---..... ---...Equivalent to:30PF5 pFR2~~5n25512INCLUDINGINCLUDINGr_JIGAND_ I JIG AND- SCOPE - ':"'SCOPE ':'"Figure laFigure Ib3. See the last page of this specification for Group A subgroup testinginformation.4. T A is the "instant on" case temperature.0037-43.0 V -----___ -----oLGND,,5 nsALL INPUT PULSESFigure 20037-6THEVENIN EQUIVALENT16712OUTPUT O--~· ~\.~"'w---"""O 1.73 V...0037-52-116

~ ~m~~~NDUcrOR=======================================================================:witching Characteristics Over Operating Range[3, 5]ParametersREAD CYCLEDescriptionMin.tRC Read Cycle Time 25tAAAddress to Data ValidtOHA Data Hold from Address Change 3tACStDOECS Low to Data ValidOE LOW to Data ValidtLZOE OE LOW to Low Z 0tHZOEOE HIGH to High Z[6]tLZCS CS LOW to Low Z[7] 3tHZCS CE HIGH to High Z[6, 7]WRITE CYCLErS]twc Write Cycle Time 25tscs CS LOW to Write End 25tAW Address Set-up to Write End 20tHA Address Hold from Write End 0tSA Address Set-up to Write Start 0tpwE WE Pulse Width 20tSD Data Set-up to Write End 10tHD Data Hold from Write End 0tHzWEWE LOW to High ZtLZWE WE HIGH to Low Z 6Jotes:5. Test conditions assume signal transition times of 5 ns or less, timingreference levels of I.5V, input pulse levels of 0 to 3.0V and outputloading of the specified lor/loH and 30 pF load capacitance.6. tHZOE tHZCS and tHzwE are tested with CL = 5 pF as in Figure lb.Transition is measured ± 500 m V from steady state voltage.7. At any given temperature and voltage condition, tHzcS is less thantLzcS for all devices. These parameters are sampled and not 100%tested.~witching Waveformslead Cycle No.1 (Notes 9, 10)7C170-25 7C170-35 7C170-45Max. Min. Max. Min. Max.Units35 45 ns25 35 45 ns3 3 ns15 25 30 ns15 15 20 ns0 0 ns15 15 15 ns5 5 ns15 20 25 ns35 40 ns35 35 ns30 35 ns0 0 ns0 0 ns30 35 ns15 15 ns0 3 ns10 15 20 ns6 6 ns8. The internal write time of the memory is defined by the overlap ofCS LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.9. WE is HIGH for read cycle.10. Device is continuously selected, CS = VIL and OE = VIL.11. Address valid prior to or coincident with cs transition LOW.12. Data I/O will be high impedance ifOE = Vm.ADDR'SS ---J:f4-~~~~_-_-_-_____ ___tR_:,-~~~~_-_-_-_-:*~~--~----tOHA--------~DATA OUT PREVIOUS DATA VALID DATA VALID0037-112-117

~ CY7C170~~~U~==========~~~~================================================Switching Waveforms (Continued)Read Cycle No.2 (Notes 9, 11)IRCJ, J'lDATA OUTlACS~r-\.-1-'LZOEilODE k-_IHlCS- "".~HIGH IMPEDANCE I, , , , ,lucs -\" \. " \. " \.DATA VALID,HIGHIMPEDANCE0037-7Write Cycle No.1 (WE Controlled) (Notes 8, 12)~-----------------------------IWC--------------------------~~/4-------------------- ISCS ----------------------1~-----------------------IAW-----------------------.~---/4------ISA-----------I~-----IME-----~DATA INDATA-IN VALIDDATA I/O ----------D-AT-A-U-N-D-E-F-,N-E-D-------IHZWE~)>---.......... --..... ---.\. ______ _0037-8Write Cycle No.2 (CS Controlled) (Notes 8, 12)~---------------------------~C--------------------------~-----+f------------ISCS-------~~-------IME---------~14--7-----ISO ---------1-/4-~-----------tso-------~-IHZWE----!DATA-IN VALID------------------~ HIGH IMPEDANCEDATA 110 DATA UNDEFINED , .. ----------------------Note: If CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.0037-92-118

~ CY7C170~~~~UcrOR=====================================================================Ordering InformationSpeed(ns)Ordering Code25 CY7C170-25PCCY7C170-25DC35 CY7C170-35PCCY7C170-35DCCY7CI70-35DMB45 CY7C170-45PCCY7C170-45DCCY7CI70-45DMBBitMapOUTPUTS 3210 .. 3210 0123 •• 0123 3210 •• 3210Y-AOORESS 00.. •. 07 011. .... 15 16 ..... 230123 012324 .... 31PackageTypeP9DI0P9DlODlOP9DlODlOOperatingRangeCommercialCommercialMilitaryCommercialMilitaryAddress DesignatorsAddress Address PinName Function NumberAo Xo 18Al X3 19A2 X4 20A3 Xl 21A4 X2 1As Xs 2A6 X6 3A7 Y3 4As Y4 5A9 Yo 6AlO YI 7All Y2 8fI124125127ROW 126• = REDUNDANT COlUMN# = REDUNDANT ROW0037-102-119

~ CY7C170~jr;~UcrOR~==========~======~==========~========================~==MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tAcS 7,8,9,10,11tDOE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tscs 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tPWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00035-C2-120

Features• Automatic power-down whendeselected• CMOS for optimum speed/power• High Speed- 25 ns tAA• Transparent Write (7Cl71)• Low active power- 385 mW (commercial)- 385 mW (military)• Low standby power-83mW• TTL compatible inputs andoutputsLogic Block DiagramCYPRESSSEMICONDUCTOR• Capable of withstanding greaterthan 2001 V electrostaticdischargeFunctional DescriptionThe CY7CI71 and CY7CI72 are highperformance CMOS static RAMs organizedas 4096 x 4 bits with separateI/O. Easy memory expansion is providedby an active LOW chip enable(CE) and three-state drivers. They havean automatic power-down feature, reducingthe power consumption by 77%when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.CY7C171CY7C1724096 X 4 Static R/W RAMSeparate I/OData on the four input pins (10 through13) is written into the memory locationspecified on the address pins (Aothrough All).Reading the device is accomplished bytaking chip enable (CE) LOW, whilewrite enable (WE) remains HIGH. Underthese conditions the contents of thememory location specified on the addresspins will appear on the four dataoutput pins.The output pins stay in high impedancestate when write enable (WE) is LOW(7CI72 only), or chip enable (CE) isHIGH. A die coat is used to insure alphaimmunity.Pin Configurationsfl·101213°0°1A4VccAsA3AsA2A7AlA8AoAg 10A 10All 0013 0 112 °2CE 0 3GNDWE°20051-2°3CEu"'COLn~(.)t')N««««>««AsAlAo10NCNCA 10NCAll 1113 000051-1_Nltl ~I~ 6'6'00051-3Selection GuideMaximum Access Time (ns)Maximum OperatingCurrent (rnA)LSTD7C171-257Cl72-2525Commercial 70Commercial 90Military7C171-35 7C171-457Cl72-35 7Cl72-4535 457090 7090 702-121

QCY7C171. CY7C172~~UcrOR=====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CStatic Discharge Voltage ..................... > 2001 VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VOperating RangeDC Voltage Applied to OutputsAmbientRangeVeein High Z State ...................... - 0.5V to + 7.0VTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto + 70°C 5V ±1O%Output Current into Outputs (Low) ............. 20 rnA Military [2] - 55°C to + 125°C 5V ±1O%Electrical Characteristics Over Operating Rangel3]7C171L-25, -35 7C171-25, -35 7C171-45Parameters Description Test Conditions 7Cl72L-25, -35 7Cl72-25, -35 7Cl72-45 UnitsMin. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 0.4 0.4 VVIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND ~ VI ~ Vee -10 +10 -10 +10 -10 +10 p,AlozOutput Leakage CurrentGND ~ Vo ~ Vee,Output Disabled-50 +50 -50 +50 -50 +50 p,Alos Output Short Circuit Current[1] Vee = Max., VOUT = GND -350 -350 -350 mAleeVee Operating Vee = Max. Commercial 70 90 70Supply Current lOUT = OmA Military'" 90 70Automatic CE Max. Vee, Commercial 15 20 15ISB} Power Down Current CE ~ VIH Military'" 20 20rnArnAAutomatic CE Max. Vee, Commercial 10 15 15ISB2 Power Down Current CE ~ Vee -0.3V Military'" 20 20mA• -35 and -45 onlyCapacitance [4]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz, Vee = 5.0V 4 pFCOUT Output Capacitance TA = 25°C, f = 1 MHz, Vee = 5.0V 7 pFNotes:1. Not more than} output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. TA is the "instant on" case temperature.AC Test Loads and WaveformsR1481H5VO-------~~~OUTPUT o---~~---,-,Equivalent to:r·30 pF· . ~~5nINCLUDING_JIGAND _- SCOPE -Figure laTHEVENIN EQUIVALENT16mOUTPUT O--~·\I~\I·\r". --~o 1.73 VR1 481S25Vo----~~~OUTPUT o---~---"I5pfINCLUDING3. See the last page of this specification for Group A subgroup testinginformation.4. Tested initially and after any design or process changes that mayaffect these parameters.R2255H":" ~6~~~D -r 0051-4Figure Ib0051-52-1223.0 V -----,...---""""'-.GND.; 5 ns -.; 5 nsFigure 20051-6

(;J]CY7C171. CY7C172. ~~========================================================~~~~Switching Characteristics Over Operating Rangd3, 5]ParametersREAD CYCLEtRCtAAtOHAtAcEtLZCERead Cycle TimeAddress to Data ValidDescriptionOutput Hold from Address ChangeCE LOW to Data ValidCE LOW to Low Z[7]tHzCE CE HIGH to High Z[6, 7]tputPDtRcstRCHWRITE CYCLE[8]twctSCEtAWtHAtSAtPWEtSDtHDtLzwEtHzwEtAWECE LOW to Power UpCE HIGH to Power DownRead Command Set-upRead Command HoldWrite Cycle TimeCE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to Low Z[7] (7C172)WE LOW to High Z[6, 71 (7C172)WE LOW to Data Valid (7C171)tADV Data Valid to Output Valid (7C171)Notes:5. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IorJ10H and 30 pF load capacitance.6. tHZCE and tHZWE are tested with CL = 5 pF as in Figure 1 b. Transitionis measured ± 500 m V from steady state voltage.7. At any given temperature and voltage condition, tHZ is less than tLZfor any given device.Switching WaveformsRead Cycle No.1 (Notes 9, 10)7C171·25 7C171·35 7C171·457C172·25 7C172·35 7C172·45 UnitsMin. Max. Min. Max. Min. Max.25 35 45 ns25 35 45 ns3 3 3 ns25 35 45 ns5 5 5 ns15 20 20 ns0 0 0 ns25 25 30 ns0 0 0 ns0 0 0 ns25 35 40 ns25 30 35 ns20 30 35 ns0 0 0 ns0 0 0 ns20 25 30 ns10 15 15 ns0 0 3 ns0 0 0 ns10 15 20 ns25 30 35 ns25 30 35 ns8. The internal write time of the memory is defined by the overlap ofCE low and WE low. Both signals must be low to initiate a write andeither signal can terminate a write by going high. The data inputsetup and hold timing should be referenced to the rising edge of thesignal that terminates the write.9. WE is high for read cycle.10. Device is continuously selected, CE = VIL.11. Address valid prior to or coincident with CE transition low.-----*-~~--------------------------tRc--------------------------~1~~ADDRESS_______t_AA __V .. .'~I_:~~~~~~~~_H_A _____DATA OUT PREVIOUS DATA VALID DATA VALID----------------------------------------- 0051-7II2-123

WACY7C171. . CY7C172~~==~~~~~~~~~~~~~~~~~~~==Switching Waveforms (Continued)Read Cycle (Notes 9, 11)~~tRC]1£DATA OUTtACEtLZ:!HIGH IMPEDANCE 1/ / / / ] 1/'\. '\. '\. '\. '\.DATA VALID~tHZ~/HIGHIMPEDANCEVCCSUPPLYCURRENTI---tpu-jll-50%I--tPO---j50%~ ICCISB..:;'f- ")1\i--tRCS !+--tRCH--0051-8Write Cycle No.1 (WE Controlled) (Note 8)-ADDRESS oou- -ltwc-tSCE\\ ,\\~ :1 I I / IIIIIIIIItSAtAW t HA -DATA INDATA OUT(7C172)DATA OUTDATA UNDEFINEDI I---tpWE -1k\\:"ktSDj( DATA-IN VALID TI-tHZW~\-- tAOV-~I..\ tHO\-tLZWE~ HIGH IMPEDANCEII(7C171) _______ D_A_TA_U_ND_E_FI_N_ED _____ 1\. _____I\. "DA_T_A_VA_L_ID ____ _0051-9Write Cycle No.2 (CE Controlled) (Note 8)-ADDRESS-~~ ~ItSA.1 t scE -~,.~DATA INDATA OUT(7C172)tAWI---tpWE -\\ ,\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \"' r!-I I I I I I I I I I I IIDATA UNDEFINED.1tSDI DATA-IN VALID II- tHZWE~~IIt HA -tHOHIGH IMPEDANCE_________________________ -t A_WE~·3~---__ ------DATA OUT DATA UNDEFINED DATA VALID(7C171)Note: If CE goes high simultaneously with WE high, the output remains in a high impedance state (7Cl72).0051-10twc2-124

&iCY7C171. CY7C172~NDU~ ============~~~===================================================Typical DC and AC Characteristics11U~0wN:::i

WnCY7C171. CY7C172~~~~~~~~~~~~~~~~==~~~====~==~================Ordering InformationSpeed Icc Package OperatingOrdering Code(ns) mA Type RangeSpeed Icc Package OperatingOrdering Code(ns) mA Type Range25 70 CY7CI71L-25PC P13 Commercial 25 70 CY7C 172L-25PC P13 CommercialCY7C171L-250C 014 CY7CI72L-250C 014CY7C171 L-25LC L64 CY7CI72L-25LC L6490 CY7C171-25PC P13 90 CY7C 172-25PC P13CY7C171-250C 014 CY7C 172-250C 014CY7C171-25LC L64 CY7C 172-25LC L6435 70 CY7CI71L-35PC P13 Commercial 35 70 CY7CI72L-35PC P13 CommercialCY7C171L-350C 014 CY7CI72L-350C 014CY7CI71L-35LC L64 CY7CI72L-35LC L6490 CY7C171-35PC P13 90 CY7CI72-35PC P13CY7C171-350C 014 CY7CI72-350C 014CY7C171-35LC L64 CY7CI72-35LC L64CY7C171-350MB 014 Military CY7CI72-350MB 014 MilitaryCY7C 171-35LMB L64 CY7CI72-35LMB L6445 70 CY7C171-45PC P13 Commercial 45 70 CY7CI72-45PC P13 CommercialAddress DesignatorsCY7C171-450C 014 CY7C 172-450C 014CY7C171-45LC L64 CY7CI72-45LC L64CY7C171-450MB 014 Military CY7CI72-450MB 014 MilitaryCY7CI71-45LMB L64 CY7CI72-45LMB L64Address Address PinName Function NumberAo Xo 20Al X3 21A2 )4 22A3 Xl 23A4 X2 1As Xs 2A6 X6 3A7 Y3 4As Y4 5A9 Yo 6AlO YI 7All Y2 82-126

MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3ICC 1,2,3ISB! 1,2,3ISB2 1,2,3Switching CharacteristicsParametersREAD CYCLESubgroupstRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tRCS 7,8,9,10,11tRCH 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11tAWE[12] 7,8,9,10,11tADV[12] 7,8,9,10,11Note:12. 7C171 only.Document #: 38-00036-C2-127

Features• Automatic power-down whendeselected• CMOS for optimum speed/power• High speed-2S ns• Low active power- 550 mW• Low standby power-110 mW• TTL compatible inputs andoutputs• Capable of withstanding greaterthan 2001 V electrostaticdischarge• 2V data retention (L version)CYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C185 and CY7C186 are highperformance CMOS static RAMs organizedas 8192 words by 8 bits. Easymemory expansion is provided by anactive LOW chip enable (CE!), an activeHIGH chip enable (CE2), and activeLOW output enable (OE) andthree-state drivers. Both devices havean automatic power-down feature, reducingthe power consumption by 73%when deselected. The CY7C185 is inthe space saving 300 mil wide DIPpackage and leadless chip carrier. TheCY7C186 is in the standard 600 milwide package.An active LOW write enable signal(WE) controls the writing/reading operationof the memory. When CEI andWE inputs are both LOW and CE2 isCY7C185CY7C1868192 X 8 Static R/W RAMHIGH, data on the eight data input/output pins (1/00 through 1/07) iswritten into the memory location addressedby the address present on theaddress pins (Ao through AI2). Readingthe device is accomplished by selectin@edevice and enabling the outputs,CEI and OE active LOW, CE2active HIGH, while (WE) remains inactiveor HIGH. Under these conditions,the contents of the location addressedby the information on addresspins is present on the eight data input/output pins.The input! output pins remain in a highimpedance state unless the chip is selected,outputs are enabled, and writeenable (WE) is HIGH. A die coat isused to ensure alpha immunity.Logic Block DiagramPin Configurations>-+++++11-0+4-1/°0>-+++++11+--1/°11/°21/°3GND0055-2CE 1eE 2WE1/°41/°51/°61/°7J' ",'" ",

fiACY7C185. CY7C186~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Volt~ge to Ground Potential(Pm 28 to Pm 14) .................... -0.5V to +7.0VOperating RangeDC Voltage Applied to OutputsAmbientRangein High Z State ...................... - 0.5V to + 7.0VTemperatureVeeDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto + 70°C 5V ±10%Output Current into Outputs (Low) ............. 20 rnA Military [3] -55°C to + 125°C 5V ±1O%Electrical Characteristics Over Operating Range[4]7C185-25 7C185-35, 45 7C185-55Parameters Description Test Conditions7C186-25 7C186-35, 45 7C186-55Min. Max. Min. Max. Min. Max.UnitsVOH Output HIGH Voltage Vee = Min.,loH = -4.0mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 VVIR Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND S VI S Vee -10 10 -10 10 -10 10 p,AlozOutput Leakage GND S VI S VeeCurrentOutput Disabled-10 +10 -10 +10 -10 +10 fLAlosOutput ShortCircuit Current[l]Vee = Max., VOUT = GND -300 -300 -300 rnAleeVee Operating Vee = Max. Commercial 100 100 80Supply Current lOUT = OmA Military 100 100rnAISBIAutomatic CEIPower Down CurrentMax. Vee,CEI 2 VIH,Commercial 20 20 20Min. DutyCycle = 100% Military 20 20rnAISB2Capacitance [2]Max. Vee, Commercial 20 20 20Automatic CEI CEI 2 Vee-0.3V,Power Down Current VIN 2 Vee-O.3V 20orVIN S 0.3V Military 20Parameters Description Test Conditions Max. UnitsCIN Input Capacitance T A = 25°C, f = 1 MHz 5COUT Output Capacitance Vee = 5.0V7Notes:1. Not more than I output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. Tested initially and after any design or process changes that mayaffect these parameters.AC Test Loads and WaveformsR1481n5VO-------~~ __OUTPUT O--~~----fEquivalent to;I30pFINCLUDING_ JIGAND _ IR2255nR1481115VO-------~~~OUTPUT 0---..... ---..5pF ~~nINCLUDING_JIG AND _- SCOPE - - SCOPE -0055-4Figure laFigure IbTHEVENIN EQUIVALENT16711OUTPUT O~-~·V"V"''''.--''''''o 1.73V 0055-72-129pFrnA3. TA is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.0055-5All Input Pulses3.0 V-----.P~---~GNDs:5nsFigure 2s:5ns0055-6

WnCY7C185. CY7C186~U~==================================================================Switching Characteristics Over Operating Range[4, 5]7C185·25Parameters Description 7C186·25READ CYCLEMin.tRC Read Cycle Time 25tAAAddress to Data ValidtOHA Data Hold from Address Change 3tACEItACE2tOOECEI LOW to Data ValidCE2 HIGH to Data ValidOE LOW to Data ValidtLzOE OE LOW to Low Z 3tHZOEOE HIGH to High Z[6]tLzCEI CEI LOW to Low Z[7] 5tLZCE2 CE2 HIGH to Low Z 3tHZCEtputPDWRITE CYCLE[S]CEI HIGH to High Z[6, 7]CE2 LOW to High ZCEI LOW to Power UpCEI HIGH to Power Downtwc Write Cycle Time 25tSCEI CEI LOW to Write End 25tSCE2 CE2 HIGH to Write End 20tAW Address Set-up to Write End 20tHA Address Hold from Write End 0tSA Address Set-up to Write Start 0tPWE WE Pulse Width 20tSD Data Set-up to Write End 10tHO Data Hold from Write End 0tHZWEWE LOW to High Z[6]tLZWE WE HIGH to Low Z 3Notes:5. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified lorJIOH and 30 pF load capacitance.6. tHZOE, tHZCE and tHzWE are specified with CL = 5 pF as in Figurelb. Transition is measured ± 500 m V from steady state voltage.7. At any given temperature and voltage condition, tHZCE is less thantLZCE for any given device.8. The internal write time of the memory is defined by the overlap ofCEI LOW, CE2 HIGH and m LOW. Both signals must be LOWMax.252525151515020157C185·35 7C185·45 7C185·557C186·35 7C186·45 7C186·55 UnitsMin. Max. Min. Max. Min. Max.35 45 55 ns35 45 55 ns3 3 3 ns35 45 55 ns25 30 40 ns20 20 25 ns3 3 3 ns15 20 25 os5 5 5 ns3 3 3 ns15 20 20 ns0 0 0 ns20 25 25 ns35 45 50 ns30 40 50 os20 25 30 ns30 40 50 ns0 0 0 ns0 0 0 ns20 25 30 ns15 20 25 ns0 0 0 ns15 20 25 ns3 3 3 osto initiate a write and either signal can terminate a write by goingHIGH. The data input setup and hold timing should be referenced tothe rising edge of the signal that terminates the write.9. WE is HIGH for read cycle.10. Device is continuously selected. 00, CE = VIL. CE2 = VIH.11. Address valid prior to or coincident with CE transition LOW.12. Data 1/0 is HIGH impedance if 00 = VIH.2-130

fiACY7C185. CY7C186~NDUcroR ==================================================================~Data Retention Characteristics (L Version only)[4]Parameters Description Test ConditionsVDRVee for Retention of DataIeeDR Data Retention Current Vee = 2.OV,teDRChip Deselect to Data Retention TimeCE ~ Vee - 0.2VVIN ~ Vee - 0.2VtROperation Recovery TimeorVIN ~ 0.2VILlInput Leakage CurrentNote:13. tRC = Read Cycle Time.Data Retention WaveformVee •• J VDATA RETENTIONMODE"'2Vr-teDR~'''''--___ '''''l.= In:R--lIMin.Max.2.0 -- 10000 -tRe[13] -- 2CE """!Z,....,Z,....,Z,....,Z,....,Z,....,Z,....,Z,....,Z,....,Z-1... V ---' I VIH ~\\\\\\\\S\\\IHUnitsV,..,Ansns,..,AII0055-12Switching WaveformsRead Cycle No.1 (Notes 10, 11)MD.,. =tL~~,*-DATA OUT PREVIOUS DATA VAUD ~===============D=A=TA=V=A=L=ID===============0055-82-131

5nCY7C185. CY7C186~~~~~~~~~~~~~~~~~====~====Switching Waveforms (Continued)Read Cycle No.2 (Notes 9, 11)~t RCf---ItACE\:fFt OOE -t HZOE t LZOEtHIGHHZCE-HIGHDATA OUTIMPEDANCEI--tLZCE -DATA VALIDIMPEDANCEf-- tpuI--tpoSUP;~~ ____)~-50-%-.----------------5:1= :~~CURRENTWrite Cycle No.1

5ACY7C185. CY7C186~U~==================================================================Typical DC and AC Characteristics:J.U.!t0wN::;c:EII:0Z1.41.21.00.80.60.4NORMALIZED SUPPLY CURRENTvs SUPPLY VOLTAGE./levV/'0.2Isa0.04.0 4.5 5.0 5.5 6.0SUPPL V VOLTAGE (VIID(IIU.!t0wN::;c:EII:0Z1.21.00.80.60.40.2NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE~~r---IsaVee - 5.0 VVIN = 5.0 V0.0-55 25.0 125.0AMBIENT TEMPERATURE ('C)~!~ZIIIII:II:~(,Jw(,JII::l51~~A-~~012010080604020OUTPUT SOURCE CURRENTvs OUTPUT VOLTAGE~~~Vee =5.0 VTA = 25'C~'"o0.0 1.0 2.0 3.0 4.0OUTPUT VOLTAGE (V)fI1.4NORMALIZED ACCESS TIMEvs SUPPLY VOLTAGE1.6NORMALIZED ACCESS TIMEvs. AMBIENT TEMPERATURE140OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE~ '"SN::;c:EII:0z1.31.21.11.00.9.... .......... ..............TA = 25'C~-0.84.0 4.5 5.0 5.5 6.0~ '"1.4 1-----t------"1S 1.2 t----~I----___:.,.~N::;C~ 1.0 .-------:::I~:...-.---__IoZ0.8 .....".,OC----..-------i0.6 ...... ----...... ------'-55 25 125~!~ZIIIII:II::l(,J:.:Ziii~:lA-~~012010080604020///I/.JII'L V'Vee = 5.0VTA = 25'C0.0 1.0 2.0 3.0 4.0SUPPL V VOLTAGE IVIAMBIENT TEMPERATURE ('CIOUTPUT VOLTAGE (V)3.0TYPICAL POWER·ON CURRENTvs. SUPPLY VOLTAGE30.0TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADINGNORMALIZED IcCvs. CYCLE TIME1.25 ..... --....,.---..,...---.,E2.52.00wN::; 1.5c(:EII:1.0i0.5--- ~0.00.0 1.0 2.0 3.0 4.0 5.0SUPPLY VOLTAGE (VI/25.0:g 20.0'";; 15.0~~ 10.05.00.0//V/"..-TA = 25'C/ vee =4.50V,/Vo 200 400 600 800 1000CAPACITANCE (pF)Vee - 5.0 VTA = 25'CVIN=O.5V0.501·~0---..L20~---30'-----'40CYCLE FREQUENCV (MHz)0055-132-133

· CY7C185~ CY7C186~~~U~==============================================================Truth TableCEi CE2 WE OE Input/Outputs ModeH X X X HighZ Deselect Power DownX L X X HighZ DeselectL H H L Data Out ReadL H L X Data In WriteL H H H HighZ DeselectOrdering InformationSpeedPackage OperatingOrdering Code(ns) Type RangeSpeedPackage OperatingOrdering Code(ns) Type Range25 CY7C185-25PC P21 Commercial 55 CY7C185-55VC V21 CommercialCY7CI85L-25PC P21 CY7CI85L-55VC V21CY7C185-25VC V21 CY7C185-55DC D22CY7CI85L-25VC V21 CY7CI85L-55DC D22CY7C185-25DC D22 CY7C185-55LC L54CY7CI85L-25DC D22 CY7CI85L-55LC L54CY7C185-25LC L54 CY7CI85-55DMB D22 MilitaryCY7CI85L-25LC L54 CY7CI85L-55DMB D2235 CY7C185-35PC P21 Commercial CY7CI85-55LMB L54CY7CI85L-35PC P21 CY7CI85L-55LMB L54CY7C185-35VCCY7CI85L-35VCV21V21SpeedPackage OperatingOrdering Code(ns) Type RangeCY7C185-35DC D22 25 CY7C186-25PC P15 CommercialCY7C 185L-35DC D22 CY7CI86L-25PC P15CY7C185-35LC L54 CY7C186-25DC D16CY7C 185L-35LC L54 CY7C 186L-25DC D16CY7CI85-35DMB D22 Military 35 CY7C186-35PC P15 CommercialCY7CI85L-35DMB D22 CY7CI86L-35PC P15CY7C 185-35LMB L54 CY7C186-35DC D16CY7CI85L-35LMB L54 CY7CI86L-35DC D1645 CY7C185-45PC P21 Commercial CY7CI86-35DMB D16 MilitaryCY7CI85L-45PC P21 CY7CI86L-35DMB D16CY7CI85-45VC V21 45 CY7C186-45PC P15 CommercialCY7CI85L-45VC V21 CY7C 186L-45PC P15CY7C185-45DC D22 CY7C186-45DC D16CY7CI85L-45DC D22 CY7CI86L-45DC D16CY7C185-45LC L54 CY7CI86-45DMB D16 MilitaryCY7CI85L-45LC L54 CY7CI86L-45DMB D16CY7CI85-45DMB D22 Military 55 CY7C186-55PC P15 CommercialCY7CI85L-45DMB D22 CY7CI86L-55PC P15CY7CI85-45LMB L54 CY7C186-55DC D16CY7CI85L-45LMB L54 CY7CI86L-55DC D1655 CY7C185-55PC P21 Commercial CY7CI86-55DMB D16 MilitaryCY7CI85L-55PC P21 CY7CI86L-55DMB D162-134

WACY7C185. CY7C186~~==================================================================BitMapAddress DesignatorsAddress Address PinName Function NumberA4 X3 2AS X4 3A6 X5 4A7 X6 5A8 X7 6A9 Yl 7AlO Y4 8All Y3 9A12 YO 10AO Y2 21Al XO 23A2 Xl 24A3 X2 250055-142-135

&iCY7C185. CYPRFSS CY7C186s~~u~==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3los 1,2,3Icc 1,2,3ISB! 1,2,3ISB2 1,2,3SubgroupsSwitching CharacteristicsParametersREAD CYCLESubgroupstRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACEl 7,8,9,10,11tACE2 7,8,9,10,11tDOE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCEl 7,8,9,10,11tSCE2 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Data Retention Characteristics(L Version only)ParametersVDR 1,2,3ICCDR 1,2,3Document #: 38-00037-BSubgroups2-136

Features• Automatic power-down whendeselected• CMOS for optimum speed/power• High speed-25 ns• Low active power-385 mW• Low standby power-110 mW• TTL compatible inputs andoutputs• Capable of withstanding greaterthan 2000V electrostaticdischarge• 2V data retention (L version)CYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C187 is a high performanceCMOS static RAM organized as65,536 words x 1 bit. Easy memory expansionis provided by an active LOWchip enable (CE) and three-state drivers.The CY7C187 has an automaticpower-down feature, reducing the powerconsumption by 80% when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.Data on the input pin (01) is writteninto the memory location specified onthe address pins (Ao through AlS).CY7C18765,536 x 1 Static R/W RAMReading the device is accomplished bytaking the chip enable (CE) LOW,while write enable (WE) remainsHIGH. Under these conditions thecontents of the memory location specifiedon the address pins will appear onthe data output (DO) pin.The output pin stays in high impedancestate when chip enable (CE) is HIGHor write enable (WE) is LOW.The 7C187 utilizes a Die Coat to en- 1:11sure alpha immunity. iiiLogic Block DiagramPin Configurations..--------c 1------01.>---00U It)- 0 u_«>

~ CY7C187~~~~==============================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............•.. -65°C to + 150°C Static Discharge Voltage ..••....•..•..•...... >2OO1VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied ....••....•.•....•.. - 55°C to + 125°C Latch-up Current ......•......•..........•. > 200 mASupply Voltage to Ground Potential(Pin 22 to Pin 11) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ......•.•............. -0.5Vto +7.0VDC Input Voltage ...•............... - 3.0V to + 7.0VOutput Current into Outputs (Low) ............. 20 mAElectrical Characteristics Over Operating Range(5)Parameters Description Test ConditionsOperating RangeRangeAmbientTemperatureVeeCommercial O°C to +70"C 5V ±1O%Military [4] - 55°C to + 125°C 5V ±1O%7C187-25 7C187-35 7C187-45Min. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min. IOL = 8.0mA Military0.4 0.4 0.4 VI IOL = 12.0 rnA CommercialVIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND:5: VI:5: Vee -10 +10 -10 +10 -10 +10 p.Aloz Output Leakage Current GND :5: Vo :5: Vee, Output Disabled -10 +10 -10 +10 -10 +10 p.AOutput Short Circuitlos Current[l]Vee = Max., VOUT = GND -350 -350 -350 rnAlecISBlISB2Capacitance [3]Vee Operating Vee = Max. Commercial 70 70 50Supply Current lOUT = OmA Military 70 70Automatic Cf:[2] Max. Vee, Commercial 20 20 20Power Down Current CE ~ VIH Military 20 20Automatic CE[2]Max. Vee, CE ~ Vee - 0.3V, Commercial 20 20 20Power Down Current VIN ~ Vee - 0.3Vor Military 20 20VIN:5: 0.3VParameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 5COUT Output Capacitance Vee = 5.0V 7Notes:1. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. A pull-up resistor to Vee on the CE input is required to keep thedevice deselected during Vee power-up, otherwise ISB will exceedvalues given.AC Test Loads and WaveformsR1329r2(480n MIL)5Vo---------~~~R1 329 n(480n MIL)5Vo---------~~~pFUnits3. Tested initially and after any design or process changes that mayaffect these parameters.4. TA is the "instant on" case temperature.5. See the last page ofthis specification for Group A subgroup testinginformation.3.0 V -----_____ ----"'--rnArnArnAOUTPUT 0---..... ----...... OUTPUT 0-----....... ---....Equivalent to:INCLUDINGI 30 pFJIG ANDSCOPEFigure 1aR2202n(255n MIL)THEVENIN EQUIVALENTINCLUDINlJIG ANDSCOPE ':"Figure 1b5pF1670OUTPUT O---~""""'.,.--~O 1.73V 0029-6MilitaryGND-0;; 5 nsFigure 212500029-5OUTPUT O~-~'\N\~--~O 1.90V. 0029-12Commercial2-138

~ CY7C187~~~croR ==================================================================~Switching Characteristics Over Operating Range[S, 6]ParametersREAD CYCLEtRCtAAtOHAtACEtLZCERead Cycle TimeDescriptionAddress to Data ValidOutput Hold from Address ChangeCE LOW to Data ValidCE LOW to Low Z[8]tHZCE CE HIGH to High Z[7, s]tputpDWRITE CYCLE[9]twctSCEtAWtHAtSAtpWEtSDtHDtLZWECE LOW to Power UpCE HIGH to Power DownWrite Cycle TimeCE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to Low Z[S]tHzwE WE LOW to High Z[7, S]Notes:6. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IorJIOH and 30 pF load capacitance.7. tHZCE and tHzwE are specified with CL = 5 pF as in Figure 1 h.Transition is measured ± 500 m V from steady state voltage.S. At any given temperature and voltage condition, tHZCE is less thantLZCE for any given device.7C187-25 7C187-35 7C187-45Min. Max. Min. Max. Min. Max.255500252020002015000Units35 45 ns25 35 45 ns5 5 ns25 35 45 ns5 5 ns15 0 20 0 20 ns0 0 ns20 25 30 ns35 45 ns30 40 ns30 40 ns0 0 ns0 0 ns25 25 ns20 25 ns0 0 ns0 0 ns15 0 20 0 20 ns9. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.10. WE is HIGH for read cycle.11. Device is continuously selected, CE = VIL.12. Address valid prior to or coincident with CE transition LOW.II2-139

~ CY7C187~~~==============================================================Data Retention Characteristics (L Version only)[5]Parameters Description Test ConditionsVDRVee for Retention of DataIeeDR Data Retention Current Vee = 2.0V,teDRChip Deselect to Data Retention TimeCE 2 Vee - 0.2VVIN 2 Vec- 0.2VtR Operation Recovery Time orVIN:;;: 0.2VILlInput Leakage CurrentNote:13. tRC = read cycle time.Data Retention WaveformVee .JI-- tCDR :.I'IDATA RETENTION.,.ODE__ V_DR_~_2v_--,1:SVtR -1V DR'1.=Min.CY7C187Max.2.0 -- 10000 -tRe[l3] -- 2cr IIIIIIIII 1 VIH ' I V1H ~\\\\\\\\\\\\UnitsVp,Ansnsp,A0029-13Switching WaveformsRead Cycle No. 1 [to, 11]~~~~-----------------------tRc------------------------~1~ADO.E~ ~ _____ ~I_;~-_~~--~~~~~~_H-A~~~~~tA~A-_.-I----------.-I-------_________________ ~---------------DATA OUT PREVIOUS DATA VALID DATA VALID---------------------------------------- 0029-72-140

~ CY7C187~~~NDUcrOR =====================================================================)witching Waveforms (Continued)lead Cycle No. 2[10, 12]DATA OUTVcc 1jtRC.SUPPLY ______ 50%CURRENT_Write Cycle No.1 (WE Controlled)[9]~------------------------------twc---------------------------~-----jICCso;,~ IS80029-8fJIADDRESS104------------------tscE------------------tI,..~~~~~~_r~~~~---------------tAw------------------~.---~--------tsA--------I~J'{-tAcetLZce:-iHIGH1--'''''1HIGH IMPEDANCE II I I I I " IMPEDANCEDATA VALIDJ!--tpuI" " " " " 1\r----tpo~~--------~o-------~~-DATA INDATA-IN VALIDDATA OUT -----------------D-AT-A-U-N-D-E-F-IN-E-D---------------tHZWE~»-------------------~~ ____________ __Write Cycle No.2 (CE Controlled)[9]~---------------------------twc-------------------------~0029-9ADDRESS1-------- tsA---------O~----------- tSCE---------~1----------tPWE ----14-+--------tso-------o ....-DATA INDATA-IN VALIDtHzwe---j---------------------~ HIGH IMPEDANCEDATA OUT DATA UNDEFINED ,)--------------------------Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.0029-102-141

~ CY7C187~jr;~~~==================================================================Typical DC and AC Characteristics1.41.2~ 1.0U20 0.8wN:;c( 0.6IEII:0 0.4z0.2NORMALIZEDSUPPLY CURRENTvs SUPPLY VOLTAGEVlev/'"Isa./0.04.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE IV). ...U.!:!0wN 0.8::;:IEa: "'0z1.21.00.80.40.2NORMALIZEDSUPPLY CURRENTvs. AMBIENT TEMPERATURE~~-IsaVee -S.OVV,N - 5.0 V0.0-55 25.0 125.0AMBIENT TEMPERATURE I'CI'i!~~a:a::;)uwua::;)~5:;)== 0120OUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE10080'"6040""Vee"'"20"o0.0 1.0 2.0 3.0OUTPUT VOLTAGE IV)~ 5.0 VTA ~ 2S'C4.0~~Ii!N:;c(:EII:0z1.41.31.21.11.00.9NORMALIZED FREQUENCYvs. SUPPLY VOLTAGE....""-~ TA = 25'C---..... -0.84.0 4.5 5.0 5.5 6.0SUPPL Y VOLTAGE IV)c~1.6NORMALIZED FREQUENCYvs. AMBIENT TEMPERATURE1.4 r----~I------_1S 1.2 r-----I----2f!1A"'--_1N::;~ "' 1.0 r----~....-=------1oz0.8 hotC------1I-------I0.6 ~-----' ..... ------..I-55 25 125AMBIENT TEMPERATURE I· C)'i!t-zwa:a::;)

Truth TableCE WE Input/Outputs ModeH X HighZ Oeselect Power OownL H OataOut ReadL L Oata In WriteOrdering InformationSpeedPackage OperatingOrdering Code(ns) Type RangeAddress DesignatorsAddress Address PinName Function Number25 CY7C187-25PC P9 Commercial AO X3 1CY7CI87L-25PC P9 Al X4 2CY7C187-250C 010A2 X5 3CY7C187L-250C 010A3 X6 4II35 CY7C187-35PC P9 CommercialA4 X7 5CY7C187L-35PC P9 A5 Y7 6CY7C187-350C 010 A6 Y6 7CY7C187L-350C 010 A7 Y2 8CY7C187-35LC L52 A8 Y3 14CY7C187L-35LC L52 A9 Y1 15CY7C187-350MB 010 Military A10 YO 16CY7C187L-350MB 010 All Y4 17CY7C187-35LMB L52 A12 Y5 18CY7C187L-35LMB L52 A13 XO 1945 CY7C187-45PC P9 Commercial A14 Xl 20CY7C 187L-45PC P9 Al5 X2 21CY7C187-450C 010CY7C187L-450C 010. CY7C187-45LC L52CY7C 187L-45LCL52CY7C187-450MB 010 MilitaryCY7C187L-450MB 010CY7CI87-45LMBCY7C187L-45LMBL52L522-143

~~ ====================~C~Y~7~C~18~7BitMap0029-152-144

~ CY7C187'Ir'-~~========================================~MILITARY SPECIFICATIONSGroup A Subgroup Testing[)C CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3los 1,2,3Icc 1,2,3ISB! 1,2,3ISB2 1,2,3fISwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11toHA 7,8,9,10,11tACE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tso 7,8,9,10,11tHO 7,8,9,10,11Document #: 38-00038-CData Retention Characteristics(L Version only)ParametersVOR 1,2,3ICCOR 1,2,3Subgroups2-145

Features• Fully decoded, 16 word x 4-bithigh speed CMOS RAMs• Inverting outputs CY7C189• Non-inverting outputs CY7C190• High speed- 15 ns and 25 ns commercial- 25 ns military• Low power- 303 mW at 25 ns- 495 m W at 15 ns• Power supply 5V ± 10%• Advanced high speed CMOSprocessing for optimumspeed/power product• Capable of withstandinggreater than 2000V staticdischarge• Three-state outputs• TTL compatible interface levelsCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C189 and CY7C190 are extremelyhigh peformance 64-bit staticRAMs organized as 16 words x 4-bits.Easy memory expansion is provided byan active LOW chip select (CS) inputand three-state outputs. The devicesare provided with inverting (CY7CI89)and non-inverting (CY7CI90) outputs.An active LOW write enable (WE) signalcontrols the writing and reading ofthe memory. When the write enable(WE) and chip select (CS) are bothLOW the information on the four datainputs (00-03) is written into the locationaddressed by the information onthe address lines (Ao-A3). The outputsare preconditioned such that the cor-CY7C189CY7C19016 x 4 Static R/W RAMrect data is present at the data outputs(00-03) when the write cycle is complete.This precondition operation insuresminimum write recovery times byeliminating the "write recovery glitch".Reading is accomplished with ~n activeLOW on the chip select line (CS) and aHIGH on the write enable (WE) line.The information stored is read outfrom the addressed location and presentedat the outputs in inverted(CY7CI89) or non-inverted(CY7C190) format.During the write operation or when thechip select line is HIGH the four outputsof the memory go to an inactivehigh impedance state.Logic Block DiagramsCY7C189CY7C190Pin ConfigurationDO010203Do010203AocsWEDOVeeAlA2A3(00) 00 03AoA1A,A300010203AoA1A2A30001020301 03 (03)(01)01 02GNO 02 (02)(7CI89)7C1900011-3cscsWE0011-1WE0011-2Selection GuideMaximum Access Time (ns)Maximum Operating Current (rnA)CommercialMilitaryCommercialMilitary7C189-15 7C189-257C190-15 7C190-2515 252590 55702-146

Maximum RatingsAbove which the useful life may be impaired. For user guidelines, not tested.);torage Temperature ............... - 65°C to + 150°CStatic Discharge Voltage ..................... > 2001 V\mbient Temperature with (per MIL-STD-883 Method 3015)lower Applied .................... - 55°C to + 125°C Latchup Current .......................... > 200 rnA;upply Voltage to Ground PotenialPin 16 to Pin 8) ..................... -0.5V to + 7.0V)C Voltage Applied to Outputsn High Z State ...................... -0.5V to + 7.0VOperating RangeRangeAmbientTemperature)C Input Voltage ................... -3.0V to +7.0V Commercial O°Cto + 70°C 5V ± 10%)utput Current, into Outputs (Low) ............. 20 rnA Military [4] - 55°C to + 125°C 5V ±1O%8:lectrical Characteristics Over the Operating Range[S]7C189-15 7C189-25Parameters Description Test Conditions 7C190-15 7C190-25 UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vec = Min., IOH = - 5.2 mA 2.4 2.4 VVOL Output LOW Voltage Vcc = Min.,IOL = 16.0 mA 0.45 0.45 VVIR Input HIGH Voltage 2.0 Vcc 2.0 Vcc VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 VIIX Input Leakage Current GND::;; VI::;; Vcc -10 + 10 -10 +10 !J-AVCDInput Diode ClampVoltage [1]IOZ Output Leakage Current GND::;; VO::;; VCC -40 +40 -40 +40 !J-AlOSIcc:;apacitance [6]~otes:Output ShortCircuit Current[2]Power Supply CurrentVeeVcc = Max., VOUT = GND -90 -90 mAVcc = Max., I Commercial 90 55 mAlOUT = OmAMilitary 70 mAParameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C,f= 1 MHz 4COUTOutput CapacitanceVCC = 5.0V7. The CMOS process does not provide a clamp diode. However theCY7C189 and CY7C190 are insensitive to -3V dc input levels and- SV undershoot pulses of less than 5 ns (measured at SO% points).~. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.i. Output is preconditioned to data in (inverted or non-inverted) duringwrite to insure correct data is present on all outputs when write isterminated. (No write recovery glitch).I4. T A is the "instant on" case temperature .S. See the last page of this specification for Group A subgroup testinginformation.6. Tested initially and after any design or process changes that mayaffect these parameters.pF2-147

5ACY7C189. CY7C190~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Switching Characteristics Over the Operating Range[5, 7]ParameterREAD CYCLEtRctACStHZCStLZCStOHAtAAWRITE CYCLE[3, 8]twctHZWEtLzwEtAwEtPWEtSDtHDtSARead Cycle TimeDescriptionChip Select to Output ValidChip Select Inactive to High ZChip Select Active to Low ZOutput Hold from Address ChangeAddress Access TimeWrite Cycle TimeWrite Enable Active to High ZWrite Enable Inactive to Low ZWrite Enable Inactive to Output ValidWrite Enable Pulse WidthData Setup to Write EndData Hold from Write EndAddress Setup to Write StarttHAAddress Hold from Write EndNotes:7. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, output loading of the specified IOL /IOHand 30 pF load capacitance.8. The internal write time of the memory is defined by the overlap ofCS LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.BitMapI01l~O·I~I------------COLUMNI 22l!2 3:J33I------------0UTPUTS7C189-15 7C189-25Test 7Cl90-15 7Cl90-25 UnitsConditionsMin. Max. Min. Max.15 25 nsNote 10 12 15 nsNotes 9,11 12 15 ns12 15 ns5 5 nsNote 10 15 25 ns15 20 nsNotes 9,11 12 20 ns12 20Note 10 12 20 nsROW 015 20 ns15 20 ns0 0 ns0 0 ns0 0 ns9. Transition is measured at steady state HIGH level - 500 m V orsteady state LOW level + 500 m V on the output from 1.5V level onthe input.10. tAA, tACS and tA WE are tested with CL = 30 pF as in Figure 1 a.Timing is referenced to 1.5V on the inputs and outputs.11. tHZCS and tHzwE are tested with CL = 5 pF as in Figure 1 h.Address DesignatorsAddressNameAddressFunctionPinNumberAo AXO 1Al AXI 15A2 AYO 14A3 AYI 13ROW 32-1480011-5

I limits5ACY7C189. CY7C190~~================================================================AC Test Loads and WaveformsR123tn5V~--------~~ __ALL INPUT PULSESR1231n5V~--------~~~3.0 V ------;.----_OU~UT~----~-------430pFINCLUDINGI JIG AND-= SCOPE -=Figure laR2150nOU~UT~----~------_1SpFINCLUDINGI _JIGAND _- SCOPE -Figure IbR2160n0011-6GND--~~0;;5 ns 0;;5ns0011-8Equivalent to:Read ModeTHEVENIN EQUIVALENTOUTPUT OO-----jW_-----

5ACY7C189CY7C190• CYPRF.SS~~~~~~~~~~~~~~~~==============~==Typical DC and AC Characteristicsu2cwN:::i"" ~a:0ZNORMALIZED IccVS. SUPPLY VOLTAGE1.21.00.8TA = 25'C0.44.0 4.5 5.0 5.5 6.0SUPPL Y VOLTAGE (V)u2cwN:::i"" :=;a:02NORMALIZED Icc1.4 ;.:.VS:.;,.' .:.;;AM=B:.;;I=E.:..;NT~T:..::E:.:..M:.::P;..:E=R;;::A:.:.T:.;U::;.;R;;::E::..,1.2Vee =5.5 V0.6-55 25 125AMBIENT TEMPERATURE ('C)ctEI-Zwa:a:;:)uwua:;:)0(I)I-~I-;:)0OUTPUT SOURCE CURRENTVS. OUTPUT VOLTAGE605040302010~"'"~o oVee = 5.0 VTA = 25'C",'"1.0 2.0 3.0OUTPUT VOLTAGE (V)4.0«$cwN:::i"" ::IEa:0zNORMALIZED ACCESS TIMEVS. SUPPLY VOLTAGE1.61.41.21.00.80.64.0TA i25'C-4.5 5.0 5.5 6.0SUPPL Y VOLTAGE (V)«$cwN::i~a:NORMALIZED ACCESS TIMEVS. AMBIENT TEMPERATURE1.4....-----.,.--------.1.21------+----~~~ 0.8 jo£-----l-----~Vee =5.0V0.6L.-----.l...--------.l-55 25 125AMBIENT TEMPERATURE ('C)ct!I-2wa:a:;:)u~2iiiI-;:)Q.I-;:)0OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE150"-125100755025/)'~V """"'""/ Vee = 5.0 V _TA =r'cV1.0 2.0 3.0 4.0 5.0OUTPUT VOLTAGE (V)ACCESS TIME CHANGEvs. OUTPUT LOADING30~--~--~--~----~~TA = 25'Cvee =4.5 Vu2cw 1.2N::i:=; ""a:1.102NORMALIZED Iccvs. FREQUENCY1.41.31.0/ VV 17'1/V'~200 400 600 800 1000 00 10 20 30 40 50 60 70CAPACITANCE (pF)FREQUENCY (MHz)0011-112-150

illCY7C189. CY7C190~~==============================================================~rdering InformationSpeed(ns)Ordering Code15 CY7C189-15PCCY7C190-15PCCY7C189-150CCY7C190-150CCY7C189-15LCCY7C190-15LC25 CY7C 189-25PCCY7C190-25PCCY7C189-250CCY7CI90-250CCY7C189-25LCCY7C190-25LCCY7C189-250MBCY7C190-250MBCY7CI89-25LMBCY7CI90-25LMBPackageTypePI02L61PI02L6102L61OperatingRangeCommercialMilitaryPin Configuration...-0 N NOozooz,-...C>,-......- N18, 18,(7C189)7C1900011-4•2-151

1mCY7C189. CY7C19(]~ucr~==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tACS 7,8,9,10,11tOHA 7,8,9,10,11tAA 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tAwE 7,8,9,10,11tpWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11tSA 7,8,9,10,11tHA 7,8,9,10,11Document #: 38-00039-B2-152

8'eatures• Automatic power-down whendeselected• Transparent write (7CI91)• CMOS for optimum speed/power• High speed- 25 ns tAA• Low active power- 385 mW• Low standby power- 110 mW• TTL compatible inputs andoutputsLogic Block DiagramCYPRESSSEMICONDUCTOR• Capable of withstanding greaterthan 2001 V electrostaticdischargeFunctional DescriptionThe CY7C191 and CY7C192 are highperformance CMOS static RAMs organizedas 65,536 x 4 bits with separateI/O. Easy memory expansion is providedby active LOW chip enable (CE)and three-state drivers. They have anautomatic power-down feature, reducingthe power consumption by 71 %when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.PRELIMINARYCY7C191CY7C19265,536 X 4 Static R/W RAMSeparate I/OData on the four input pins (10 through13) is written into the memory locationspecified on the address pins (Aothrough A1S).Reading the device is accomplished bytaking the chip enable (CE) LOW,while the write enable (WE) remainsHIGH. Under these conditions thecontents of the memory location specifiedon the address pins will appear onthe four data output pins.The output pins stay in high impedancestate when write enable (WE) is LOW(7C192 only), or chip enable (CE) isHIGH.A die coat is used to insure alpha immunity.Pin ConfigurationsIII10As 28 VeeAsAI,'213A 10Al1A12A3A2AlAo13AoAlA2A3AI,AsAsA7A8Ag0 0°1°20 3CEWE0108-1'20 3°212 °113 0 014 15 WEco ..... U) () at)""'" < -c >_~Ag" 3 21!J282726 AI,A 10 5 25 A3All 6 24 A2A12 7 23 AlA '3 8 22 AoAll, 9 21 '3A 1S 10 20 '210 11 19 0 3'1 12 18 °213141516 !.?ItJ ~1~8oC>0108-20108-10Selection GuideMaximum Access Time (ns)Maximum OperatingCurrent (mA)Maximum StandbyCurrent (mA)7C191-257C192-2525Commercial 80MilitaryCommercial 20Military2-1537C191-35 7C191-457C192-35 7C192-4535 4580 7090 9020 2020 20

wn. PRELIMINARY CY7C192~NDU~ ~===================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CCY7C191Static Discharge Voltage ..................... >2oo1V(Per MIL-STD-883, Method 3015)Latch-up Current .......................... > 200 mASupply Voltage to Ground Potential(Pin 28 to Pin 14) .................... -0.5V to +Operating Range7.0VDC Voltage Applied to OutputsAmbientRangeVeein High Z State ...................... -0.5V to + 7.0VTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O"C to +70"C 5V ±to%Output Current into Outputs (LOW) ............ 20 rnA Military [2) - 55°C to + 125°C 5V ±to%Electrical Characteristics Over Operating Range[3]7C191-25 7C191-35 7C191-45Parameters Description Test Conditions 7C192·25 7C192·35 7C192·45 UnitsMin. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 VVIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND::;;; VI::;;; Vee -to +to -to +to -to +10 p.Aloz Output Leakage Current GND ::;;; Vo ::;;; Vee, Output Disabled -10 +to -10 +10 -10 +10 p.AOutput Short Circuitlos CurrentVee = Max., VOUT = GND -350 -350 -350 rnA[I)IccISBIISB2Capacitance [4]Vee Operating Vee = Max. Commercial 80 80 70Supply Current lOUT = OmA Military 90 90Automatic CE Max. Vee, CE 2 VIH Commercial 20 20 20Power Down Current Min. Duty Cycle = 100% Military 20 20 20Max. Vee,Commercial 20 20 20Automatic CE CE 2 Vee - 0.3VPower Down Current VIN 2 Vee - 0.3VorVIN::;;; 0.3V Military 20 20Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz, Vee = 5.0V 5 pFCOUT Output Capacitance . TA = 25°C, f = 1 MHz, Vee = 5.0V 7 pFNotes:1. Not more than one output should shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.3. See the last page of this specification for Group A subgroup testinginformation.2. T A is the "instant on" case temperature. 4. Tested initially and after any design or process changes that mayaffect these parameters.AC Test Loads and WaveformsRl481S!5Vo-------~~~OUTPUT o---~~-----tr30PFINCLUDING_ JIGAND _- SCOPE -Figure la~:5nR1481S25VO-------~~~OUTPUT 0---_---..I5 pF R2255S!INCLUDING_JIG AND _- SCOPE -Figure Ib3.0V----_~~--~GNDrnArnArnA0108-3 0108-5Figure 2Equivalent to:THEVENIN EQUIVALENT16mOUTPUT O--.-·Vo .... Vo·\r". ---0 1.73 V0108-42-154

5nCY7C191. PRELIMINAR Y CY7C192~~================================================================Switching Characteristics Over Operating Range[3, s]ParametersREAD CYCLEtRCtAAtOHAtACEtLZCERead Cycle TimeDescriptionAddress to Data ValidOutput Hold from Address ChangeCE LOW to Data ValidCE LOW to LOW Z[7)tHZCE CE HIGH to High Z[6, 7)tputpDWRITE CYCLE[8)twctSCEtAWtHAtSAtpWEtSDtHDtLZWEtHZWEtAwEtADVCE LOW to Power UpCE HIGH to Power DownWrite Cycle TimeCE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to Low Z[7) (7CI92)WE LOW to High Z[6, 7) (7CI92)WE LOW to Data Valid (7CI91)Data Valid to Output Valid (7CI91)Notes:5. Test conditions assume signal transition times ofS ns or less, timingreference levels of I.SV, input pulse levels ofOY to 3.0Y and outputloading of the specified lor/IOH and 30 pF load capacitance.6. tHzCE and tHZWE are specified with CL = 5 pF as in Figure lb.Transition is measured ± SOO m V from steady state voltage.7. At any given temperature and voltage condition, tHZ is less than tLZfor any given device.Switching WaveformsRead Cycle No.1 (Notes 9, to)7C191·25 7C191·35 7C191·457C192·25 7C192·35 7C192·45 UnitsMin.2533020202020201003Max. Min. Max. Min. Max.35 45 ns25 35 45 ns3 3 ns25 35 45 ns3 3 ns10 15 15 ns0 0 ns25 35 45 ns30 40 ns30 35 ns25 35 ns2 2 ns0 0 ns25 35 ns15 20 ns0 0 ns3 3 ns10 10 15 ns25 30 35 ns20 30 35 ns8. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.9. WE is HIGH for read cycle.10. Device is continuously selected. CE = VIL.11. Address valid prior to or coincident with CE transition LOW.----""\~~~--------------------------tRc--------------------------~1.ADDRE~_~ ______ ~I_;~-_~~~~~-_~~-~~H~A~~~~~t_A-A~-_'-'-----------.-,---------------------------~-----------------DATA OUT PREVIOUS DATA VALID DATA VALID---------------------------------------- 0108-6fI2·155

5nCY7C191. PRELIMINARY CY7C192~~R~~~~~~~~~~~~~~~~~~~~~~~~~~====~========Switching Waveforms (Continued)Read Cycle (Notes 9, 11)tACEtRC~~1\]'1-!+-tHZCE-HIGHHIGH IMPEDANCE IMPEDANCEI, I ,', I 1/DATA VALID~DATA OUTJJtLZCE.~ '- '- '- '- I\.f---tpuI---tPO---jICCSUPPLY VCC _____ 50%CURRENT_=t--ISB0108-7Write Cycle No.1 (WE Controlled) (Note 8)-ADDRESS -:if: oliotwctSCE\\ ,\ \\: j'f7TTl 1/11//////tAW t HA -tSA -I I---tpWE -~\'Vir.. if.DATA INtso~ DATA-IN VALID ~-I tHODATA OUT(7C192)I-tHZWE..:1I-tLZWE~ HIGH I~PELlANCEDATA UNDEFINED.II I\.I--- tAOV-DATA OUT -------D-AT-A-U-N-D-EF-IN-E-D---..;.;.;;.~-I,.....---~DA~T~A~V~A~LI~D-----(7C191) ________________ ~0108-8Write Cycle No.2 (CE Controlled) (Note 8)-twc .-tSA t sCE -\:~It-. tAW -tHA -I---tpWE -\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \~r 'f7777111//////ADDRESS 31( 3tDATA INDATA OUT(7C192)DATA UNDEFINEDtso.1-.·1 tHOTDATA-IN VALIDI--- t HZWE -i~ HIGH I~PEDANCEIf-t-AWE ~DATAOUT---------DA-T-A-U-N-DE-F-IN-E-D------------ --DA-T-A-V-AL-ID-----(7C191) __________________ --J. '-. _______ _Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C192 only). 0108-92-156

wn. .. PRELIMINAR Y CY7C192. ~~NDUOOR================================================================~Ordering InformationCY7C191SpeedPackage OperatingSpeedPackage OperatingOrdering CodeOrdering Code(ns) Type Range(ns) Type Range25 CY7C191-25PC P21 Commercial 25 CY7C192-25PC P21 CommercialCY7C191-25VC V21 CY7C192-25VC V21CY7C191-25DC D22 CY7Cl92-25DC D22CY7C191-25LC L54 CY7C192-25LC L5435 CY7C191-35PC P21 Commercial 35 CY7C192-35PC P21 CommercialCY7C191-35VC V21 CY7Cl92-35VC V21CY7C191-35DC D22 CY7Cl92-35DC D22CY7C191-35LC L54 CY7Cl92-35LC L54CY7C191-35DMB D22 Military CY7C192-35DMB D22 MilitaryCY7C191-35LMB L54 CY7C192-35LMB L5445 CY7C191-45PC P21 Commercial 45 CY7C192-45PC P21 CommercialCY7C191-45VC V21 CY7Cl92-45VC V21CY7C191-45DC D22 CY7C 192-45DC D22CY7C191-45LC L54 CY7C192-45LC L54CY7C191-45DMB D22 Military CY7C192-45DMB D22 MilitaryCY7C191-45LMB L54 CY7C192-45LMB L54fJ2-157

5nCY7C191• CYPRESS PRELIMINAR Y CY7C192S~IOO~U~~~~~~====================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3SubgroupsIOZ 1,2,3los 1,2,3ICC 1,2,3ISB! 1,2,3ISB2 1,2,3Switching CharacteristicsParametersREAD CYCLESubgroupstRc 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tPWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11tAWE[l] 7,8,9,10,11tADV[l] 7,8,9,10,11Note:1. 7Cl9l only.Document #: 38-00076-A2-158

Features• Automatic power-down whendeselected• Output Enable (OE) feature(7CI96)• CMOS for optimum speedlpower• High speed- 25 ns tAA• Low active power- 385 mW• Low standby power-110 mW• TTL compatible inputs andoutputsCYPRESSSEMICONDUCTOR• Capable of withstanding greaterthan 2001 V electrostaticdischargeFunctional DescriptionThe CY7C194 and CY7C196 are highperformance CMOS static RAMs organizedas 65,536 x 4 bits. Easy memoryexpansion is provided by active LOWchip enable(s) (CE on the CY7C194,CEI, CE2 on the CY7C196) and threestatedrivers. They have an automaticpower-down feature, reducing the powerconsumption by 71 % when deselected.Writing to the device is accomplishedwhen the chip enable(s) (CE on thePRELIMINAR YCY7C194CY7C19665,536 X 4 Static R/W RAMCY7C194, CEl. CE2 on the CY7C196)and write enable (WE) inputs are bothLOW. Data on the four input pins(1/00 through 1/03) is written into thememory location, specified on the addresspins (Ao through AI5).Reading the device is accomplished bytaking the chip enable(s) (CE on theCY7C194, CEl. CE2 on the CY7C196)LOW, while write enable (WE) remainsHIGH. Under these conditionsthe contents of the memory locationspecified on the address pins will appearon the four data output pins. Adie coat is used to insure alpha immunity.fILogic Block DiagramPin Configurations_110,1/00........ ~ GE2(7CI960NLY)GE,WE-~--(oE:)(7C196 ONLY)0109-1A '5CEGNDAsA9A '0A"A'2A '3A'4A,SeEVeeAsA4A3A2AIAo1/°31/°21/°11/°0WE,... (DU 0(,)«z>z3 2 [iJ2827 ,4 26 As25 A424 A37 23 A27C194822 A,9 21 Ao10 20 1/°311 19 1/°212 18 1/°1",314151617 j0109-2VeeAsA4AsA3AsA2A '0A,Al1AoNCCE21/°31/°21/°11/°0GNDWE.t.:'~~.f0109-33 2l!J28 27 ,As 4 26 A4A9 5 25 A3A '0 24 A2A"23 A,7C196A'2 8 22 AoA '3 9 21 NCA'4 10 20 eE 2A,S 11 19 1/°3eE, 12 18 1/°2" 13141516170109-110109-12Selection GuideMaximum Access Time (ns)Maximum OperatingCurrent (rnA)Maximum StandbyCurrent (rnA)CommercialMilitaryCommercialMilitary7C194-257C196-252580207C194-357C196-3535809020207C194-457C196-4545709020202-159

WiiCY7C194. PRELIMINARY CY7C196~~==================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential .... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VStatic Discharge Voltage ..................... > 2OO1V(Per MIL-STD-883 Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0VCommercial O°Cto + 70°COutput Current into Outputs (Low) ............. 20 rnA Military [3] - 55°C to + 125°CElectrical Characteristics Over Operating Range[4]7C194-25 7C194-35Parameters Description Test Conditions 7C196-25 7C196-35Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 mA 2.4 2.4VOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 0.4VIH Input HIGH Voltage 2.2 Vee 2.2 VeeVIL Input LOW Voltage -3.0 0.8 -3.0 0.8IIX Input Load Current GND ~ VI ~ Vee -10 +10 -10 +10loz Output Leakage Current GND ~ Vo ~ Vee, Output Disabled -10 +10 -10 +10losOutput Short CircuitCurrent [I]Vee = Max., VOUT = GND -350 -350leeVee Operating Vee = Max. Commercial 80 80Supply Current lOUT = OmA Military 90ISB}Automatic CE[2] Max. Vee, CE ~ VIH Commercial 20 20Power Down Current Min. Duty Cycle = 100% Military 20ISB2Capacitance [5]Automatic CE[2]Power Down CurrentMax. Vee,CE;;:: Vee - 0.3VCommercial 20 20VIN ~ Vee -;-0.3V orVIN ~ 0.3V Military 20Parameters Description Test Conditions Max.CIN Input Capacitance TA = 25°C, f = 1 MHz, 5COUT Output Capacitance Vee = 5.0V 7Notes:1. Not more than} output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. A pull-up resistor to Vee on the CE input is required to keep thedevice deselected during Vee power-up, otherwise ISB will exceedvalues given.AC Test Loads and WaveformsRl481S!5 v 0-----#\""'.--,OUTPUT 0----.---..30PFINCLUOINGr_JIGANO_- SCOPE -Figure la~:5nRl481l!5 v o----~'\_..,OUTPUT C>----.---...I5 pF R2255!!INCLUDING,:"~~~DFigure Ib':"Vee5V ±10%5V ± 10%7C194-457C196-45 UnitsMin. Max.2.4 V0.4 V2.2 Vee V-3.0 0.8 V-10 +10 p,A-10 +10 p,A-350 mA709020203. TA is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.5. Tested initially and after any design or process changes that mayaffect these parameters.3.0V----.~~--_i..GND0109-4 Figure 22020UnitspFmAmAmA0109-5Equivalent to: THEVENIN EQUIVALENT16mOUTPUT O~-~·.., . ..,",",.--~O 1.7lV0109-62-160

WACY7C194. PRELIMINARY CY7C196~~================~~~====================Switching Characteristics Over Operating Range[4, 6]ParametersREAD CYCLEtRCtAAtoHAtACEl,ACE2Read Cycle TimeDescriptionAddress to Data ValidOutput Hold from Address ChangeCE LOW to Data ValidtDOE OE LOW to Data Valid 7C196tLZOE OE LOW to LOW Z 7C196tHZOE OE HIGH to HIGH Z 7C196tLZCEl' CE2CE LOW to LOW Z[S]tHZCEl,CE2 CE HIGH to High Z[7, s]tputpDWRITE CYCLE[9]twctSCEtAWtHAtSAtPWEtSDtHDtLZWECE LOW to Power UpCE HIGH to Power DownWrite Cycle TimeCE LOW to Write EndAddress Set·up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to LOW Z(s]tHZWE WE LOW to HIGH Z(7, S]Notes:6. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input pulse levels of 0 to 3.0V and outputloading of the specified IoVIoH and 30 pF load capacitance.7. tHzCE and tHzwE are specified with CL = 5 pF as in Figure lb.Transition is measured ± 500 m V from steady state voltage.S. At any given temperature and voltage condition, tHZCE is less thantLZCE for any given device.Switching Waveforms7C194-25 7C194-35 7C194-457C196·25 7C196·35 7C196-45 UnitsMin. Max. Min. Max. Min. Max.25333020202020201003035 45 ns25 35 45 ns3 3 ns25 35 45 ns15 25 30 ns3 3 ns15 15 15 ns3 3 ns10 15 15 ns0 0 ns25 35 45 ns30 40 ns30 35 ns25 35 ns2 2 ns0 0 ns25 35 ns15 20 ns0 5 ns3 3 ns10 0 10 0 15 ns9. The internal write time of the memory is defined by the overlap ofCEI LOW, CE2 LOW and WE LOW. Both signals must be LOW toinitiate a write and either signal can terminate a write by goingHIGH. The data input setup and hold timing should be referenced tothe rising edge of the signal that terminates the write.10. WE is HIGH for read cycle.11. Device is continuous.!r.§elected, CEI = VII/CE2 = VIL.(7CI96: OE = VIL, CE2 = VIL also.)12. Address valid prior to or coincident with CEI and CE2 transitionLOW.13. 7C196 only: Data 110 will be high impedance ifOE = V!H.Read Cycle No.1 (Notes to, 11)~~~~--------------------------tRc--------------------------~1~.ADDRE~_~ _______ ~I_;~-':-~':-':-~':-':-~':-_~~H~A~~~~~tA~A~-_.-'----------.----.-'------------------------------~-------------------...DATA OUT PREVIOUS DATA VALID DATA VALID------------------------------------------------------------------0109-7II2-161

(;nCY7C194. PRELIMINARY CY7C196~~u~========================~~~~~~~============================Switching Waveforms (Continued)Read Cycle No.2 (Notes 10, 12)~,/~2 Jk- KDE(7Cl96 )~~tACEtRC]"1-tOOEf..--tLZOEiDATA OUT! HIGH IMPEDANCE I, , , , ,J[tLZCE~tPuSUPPL Vec Y _____ 50%CURRENT_I' , , , , 1\DATA VALID,HIGHIMPEDANCEI---tpo-j ICCS:C'SB0109-8Write Cycle No.1 (WE Controlled) (Notes 9, 13)~----------------------------twe--------------------------~ADDRESS140-----------------!sce---------------I~,/~2~----------------------tAw--------------------~~--~--------t5A---------...!~------t~E-----~DATA INDATA-IN VALIDtHzwE~DATA 1/0 ---------D-A-T-A-U-N-DE-F-,N-E-D------- >,"--"';';;';';';"';';;';';"';;';;;';;';;;;':"---iI "'______0109-9Write Cycle No.2 (CE Controlled) (Notes 9, 13)~------------------------'wc-----------------------~------1-----------tsce-------l~------IME-----------~L!--tHZCE- ~'~~1---=--------t50-------.-.-1-4----------·50.-------'"-DATA-IN VALIDtHzwE~-------------.;...---~ HIGH IMPEDANCEDATA I/O DATA UNDEFINED l)o----------...;;;..;..;.,;.~~.;.;;..------Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.0109-102-162

~CY7C194. PRELIMINARY CY7C196~~uaoR================================================================~7C194 Truth Table7C196 Truth TableCE WE Input/Outputs Mode CEI CE2 WE OE Inputs/Outputs ModeH X HighZ Deselect/Power Down H X X XHighZ Deselect/Power DownL H Data Out Read X H X XL L Data In Write L L H L Data Out ReadL L L X Data In WriteL L H H HighZ DeselectOrdering InformationSpeedPackage OperatingSpeedPackage OperatingOrdering Code(ns)Ordering CodeType Range(ns) Type Range25 CY7C194-25PC Pl3 Commercial25 CY7C196-25PC P21 CommercialCY7C194-25VC V13CY7C196-25VC V21IICY7C194-25DC DI4CY7C196-25DC D22CY7C194-25LC L54 CY7C196-25LC L5435 CY7C194-35PC P13 Commercial 35 CY7C196-35PC P21 CommercialCY7C194-35VC VI3 CY7C196-35VC V21CY7C194-35DC DI4 CY7C196-35DC D22CY7C194-35LC L54 CY7C196-35LC L54CY7CI94-35DMB DI4 Military CY7CI96-35DMB D22 MilitaryCY7CI94-35LMB L54 CY7CI96-35LMB L5445 CY7C194-45PC P13 Commercial 45 CY7C 196-45PC P21 CommercialCY7C194-45VC V13 CY7C196-45VC V21CY7C194-45DC DI4 CY7C196-45DC D22CY7C194-45LC L54 CY7C196-45LC L54CY7CI94-45DMB DI4 Military CY7CI96-45DMB D22 MilitaryCY7CI94-45LMB L54 CY7C196-45LMB L542-163

~CY7C194. PRELIMINARY CY7C196~~u~~~~~~~~================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3los 1,2,3Icc 1,2,3ISBI 1,2,3ISB2 1,2,3Switching CharacteristicsParametersREAD CYCLESubgroupstRc 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACEl,ACE2 7,8,9,10,11tOOE[l] 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAw 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tPWE 7,8,9,10,11tso 7,8,9,10,11tHO 7,8,9,10,11tAwE 7,8,9,10,11tAOV 7,8,9,10,11Note:1. 7C196 only.Document #: 38-000812-164

Features• Automatic power-down whendeselected• CMOS for optimum speed/power• High speed-25 ns• Low active power-330 mW• Low standby power-110 mW• TTL compatible inputs andoutputs• Capable of withstanding greaterthan 2001 V electrostaticdischargeCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C197 is a high performanceCMOS static RAM organized as262,144 words x 1 bit. Easy memoryexpansion is provided by an activeLOW chip enable (CE) and three-statedrivers. The CY7C197 has an automaticpower-down feature, reducing thepower consumption by 67% when deselected.Writing to the device is accomplishedwhen the chip enable (CE) and writeenable (WE) inputs are both LOW.Data on the input pin (DIN) is writteninto the memory location specified onthe address pins (Ao through A 17).PRELIMINARYCY7C197262,144 X 1 Static R/W RAMReading the device is accomplished bytaking the chip enable (CE) LOW,while write enable (WE) remainsHIGH. Under these conditions thecontents of the memory location specifiedon the address pins will appear onthe data output (DOUT) pin.The output pin stays in ~h impedancestate when chip enable (CE) is HIGHor write enable (WE) is LOW.The 7C197 utilizes a Die Coat to ensurealpha immunity.EILogic Block DiagramA13A14A15A16A17AoAIA2A3~OfDOCEWE0110-1Pin Configurations"0 Vee"1 "17"2 "16"3 "15"4 "14"5 "13"6 "12"7 "11"8 "10DOUT"9WEDINGHDCE0 ...

~ PRELIMINARY CY7C197~~~NDUcroR ==~~~~~~~~~~~~===========================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CStatic Discharge Voltage ..................... > 2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to +Operating Range7.0VDC Voltage Applied to OutputsAmbientRangeVeein High Z State ...... , .. , ............ -0.5V to + 7.0VTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°C to +7rJ'C 5V ±1O%Output Current into Outputs (Low) ............. 20 rnA Military [4] - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over Operating Range[5]Parameters Description Test Conditions7C197-25 7C197-35 7C197-45Min. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,IOH = -4.0 mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min. llOL = S.OmA Military0.4 0.4 0.4 VI IOL = 12.0 mA CommercialVIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 O.S -3.0 O.S -3.0 O.S VIIX Input Load Current GND:5: VI:5: Vee -10 +10 -10 +10 -10 +10 ftAloz Output Leakage Current GND :5: Vo :5: Vee, Output Disabled -50 +50 -50 +50 -50 +50 ftAOutput Short Circuitlos Current[l]Vee = Max., VOUT = GND -350 -350 -350 mAVee Operating Vee = Max. Commercial 70 70 60lee Supply Current lOUT = OmA Military SO SOUnitsmAISBlAutomatic CE[2) Max. Vee, Commercial 20 20 20Power Down Current CE 2 VIHMilitary 20 20ISB2Automatic CE[2)Max. Vee, CE 2 Vee - 0.3V, Commercial 20 20 20VIN 2 Vee - 0.3VorPower Down CurrentVIN:5: 0.3VMilitary 20 20rnArnACapacitance [3]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 5COUT Output Capacitance Vee = 5.0V 7Notes:1. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. A pull-up resistor to Vee on the CE input is required to keep thedevice deselected during Vee power-up, otherwise ISB will exceedvalues given.AC Test Loads and WaveformsR1 329 n(480n MIL)R1 329 n(480n MIL)5 v o-----~M~ 5Vo-----JV~~OUTPUT 0----.------. OUTPUT 0-----1....-------.Equivalent to:INCLUDINGI 30 pFJIG ANDSCOPEFigure laR2202n(255n MIL)THEVENIN EQUIVALENT5 pFINCLUDINGfJIG AND 1-SCOPE ":"Figure Ib1250OUTPUT O----"-\N"-"'.---O 1.90 VCommercial 0110-52-1663. Tested initially and after any design or process changes that mayaffect these parameters.4. TA is the "instant on" case temperature.5. See the last page of this specification for Group A subgroup testinginformation.R2202n(255n MIL)0110-33.0 V -------~-----...GNDpF.;; 5 ns -.;; 5 nsFigure 21670OUTPUT ~ 1.73V0110-4Military 0110-6

C:z PRELIMINARY CY7C197~~~UcrOR==~~~~~~~~~~~~~~=======================================Switching Characteristics Over Operating Range[S, 6]ParametersREAD CYCLEtRCtAAloHAtACEtLZCERead Cycle TimeDescriptionAddress to Data ValidOutput Hold from Address ChangeCE LOW to Data ValidCE LOW to Low Z[s)tHZCE CE HIGH to High Z[7, S)tputpDWRITE CYCLE[9]twctSCEtAWtHAtSAtpwEtSDtHDtLZWECE LOW to Power UpCE HIGH to Power DownWrite Cycle TimeCE LOW to Write EndAddress Set-up to Write EndAddress Hold from Write EndAddress Set-up to Write StartWE Pulse WidthData Set-up to Write EndData Hold from Write EndWE HIGH to Low Z[S]tHZWE WE LOW to High Z[7, S]Notes:6. Test conditions assume signal transition times of S ns or less, timingreference levels of I.SV, input pulse levels of 0 to 3.0V and outputloading of the specified 100/loH and 30 pF load capacitance.7. tHZCE and tHZWE are specified with CL = S pF as in Figure 1 h.Transition is increased ± 500 mV from steady state voltage.S. At any given temperature and voltage condition, tHZCE is less thantLzcE for any given device.Switching WaveformsRead Cycle No. 1[10,11]7C197·25 7C197·35 7C197·45Min. Max. Min. Max. Min. Max.253300252020202015000Units35 45 ns25 35 45 ns3 3 ns25 35 45 ns3 3 ns15 0 20 0 20 ns0 0 ns20 25 30 ns35 45 ns30 40 ns30 40 ns2 2 ns0 0 ns25 25 ns20 25 ns0 0 ns0 0 ns15 0 20 0 20 ns9. The internal write time ofthe memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate awrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.10. WE is HIGH for read cycle.11. Device is continuously selected, CE = VIL.12. Address valid prior to or coincident with CE transition LOW.---"""\t::~~--------------------------tRc--------------------------~1~.ADDRESS--1____ ""I_:~--~~--~~--~~-to~_H-A~~~~~t_A-A~-_.-!------.-,--------------*---------DATA OUT PREVIOUS DATA VALID DATA VALID----------------------------------- 0110-72·167

~ PRELIMINARY CY7C197~~~~~UaoR======================~====================~~==================Switching Waveforms (Continued)Read Cycle No. 2[11]DATA OUTVcc 1tRC)~1\tAce .J~!+--tput Lzce ;:-1 ~tHzce~1HIGHSUPPLY ______ 50%CURRENT_Write Cycle No.1 (WE Controlled)[lO]HIGH IMPEDANCE 1/ / / / / ~I" " " " " 1\ DATA VALID~-------------------------------twc------------------------------~fI----tpo--jIMPEDANCEICC=t--IS80110-8ADDRESS1+------------tsce---------------------+j~---------------------tAw----------------------+~---..... -------tsA--------~ ~----t~e-----~DATA INDATA-IN VALIDtHzwe---!tLzwe---!------------------------\! HIGH IMPEDANCE It'-------DATA OUT DATA UNDEFINED /)o------------i\\.. ______ _Write Cycle No.2 (CE Controlled)[lO]~---------------------------~c----------------------------~0110-9ADDRESS14------- tSA----------~---------- tsce----------.t1+---.:.-------tso-----~-~--------------------tAW------------------~~-~------t~E------------~I+--+------------tso-----.... -DATA INDATA-IN VALIDtHzwe----1-------------------~ HIGH IMPEDANCEDATA OUT DATA UNDEFINED /)0------------------------0110-10Note: IfeE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.2-168

~ PRELIMINARY CY7C197~~~UcrOR~~~~~~~~~~~==~========================================Truth TableCE WE Input/Outputs ModeH X HighZ Deselect/Power DownL H Data Out ReadL L Data In WriteOrdering InformationSpeedPackageOperatingOrdering Code(ns) Type Range25 CY7C197-25PC P13 CommercialCY7C197-25VCV13CY7C197-25DCD14CY7C197-25LCL5435 CY7C197-35PC P13 Commercial IICY7C197-35VCV13CY7C197-35DCCY7C197-35LCD14L54CY7C197-35DMB D14 MilitaryCY7C197-35LMBL5445 CY7C197-45PC P13 CommercialCY7C197-45VCCY7C197-45DCCY7C197-45LCV13D14L54CY7C197-45DMB D14 MilitaryCY7C197-45LMBL542-169

~ PRELIMINARY CY7C197~~~~~==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3loz 1,2,3loS 1,2,3Icc 1,2,3ISBI 1,2,3ISB2 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpwE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00078-A2-170

Features• Automatic power-down whendeselected• CMOS for optimum speed/power• High speed-3S ns• Low active power-SSO mW• Low standby power-ll0 mW• TIL compatible inputs andoutputs• Capable of withstanding greaterthan 2001 V electrostaticdischargeCYPRESSSEMICONDUCTORFunctional DescriptionThe CY7C198 and CY7C199 are highperformance CMOS static RAMs organizedas 32,768 words by 8 bits. Easymemory expansion is provided by anactive LOW chip enable (CE) and activeLOW output enable (OE) andthree-state drivers. Both devices havean automatic power-down feature, reducingthe power consumption by 80%when deselected. The CY7C199 is inthe space saving 300 mil wide DIPpackage and leadless chip carrier. TheCY7C198 is in the standard 600 milwide package.An active LOW write enable signal(WE) controls the writing/reading operationof the memory. When CE andWE inputs are both LOW, data onPRELIMINARYCY7C198CY7C19932,768 x 8 Static R/W RAMthe eight data input/output pins (1/00through I/07) is written into the memorylocation addressed by the addresspresent on the address pins (Aothrough A14). Reading the device is accomplishedby selecting the device andenabling the outputs, CE and OE activeLOW, while (WE) remains inactiveor HIGH. Under these conditions,the contents of the location addressedby the information on address pins ispresent on the eight data input/outputpins.The input/output pins remain in a highimpedance state unless the chip is selected,~uts are enabled, and writeenable (WE) is HIGH. A die coat isused to ensure alpha immunity.IILogic Block DiagramPin ConfigurationsASAsVeeWEA4A3A2A '0A,AllOESelection GuideMaximum Access Time (ns)Maximum OperatingCurrent (rnA)Maximum StandbyCurrent (mA)>-t;+---I/os>-t..----I/os7C198-357C199-3535Commercial 110MilitaryCommercial 20/20Military2-1710111-10111-2"(

finPRELIMINARYCY7C198CY7C199~~NDUCTOR =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2oo1VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential(Pin 28 to Pin 14) .................... -0.5V to + 7.0VOperating RangeDC Voltage Applied to OutputsRangeAmbientinHighZState ...................... -0.5Vto +7.0VTemperatureVeeDC Input Voltage ................... - 3.0V to + 7.0V Commercial (fC to + 70°C 5V ± 10%Output Current into Outputs (Low) ............. 20 rnA Military [3] - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over Operating Range[4]7C198·35 7C198·45 7C198·55Parameters Description Test Conditions7C199·35 7CI99·45 7CI99·55Min. Max. Min. Max. Min. Max.UnitsVOH Output HIGH Voltage Vee = Min.,IOH = -4.0mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 0.4 0.4 VVIH Input HIGH Voltage 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Load Current GND::;; VI::;; Vee -10 10 -10 10 -10 +10 p,AIoz Output Leakage CurrentGND::;; VI::;; VeeOutput Disabled-10 +10 -10 +10 -10 +10 p,AloSOutput Short CircuitCurrent[l1 Vee = Max., VOUT = GND -300 -300 -300 mAleeVee Operating Vee = Max. Commercial 110 110 100Supply Current lOUT = OmA Military 120 120mAIISBIMax. Vee, Commercial 20 20 20Automatic CE CE 2 VIH, mAPower Down Current Min. DutyCycle = 100% Military 20 20Max. Vee, Commercial 20 20 20ISB2 Automatic CE CE 2 Vee - 0.3V, mAPower Down Current VIN 2 Vee - 0.3VorVIN::;; 0.3V Military 20 20Capacitance [2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance T A = 25°C, f = 1 MHz 5pFCOUTOutput CapacitanceVee = 5.0V 7Notes:1. Not more than I output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. Tested initially and after any design or process changes that mayaffect these parameters.AC Test Loads and WaveformsRI481n5 V o-----'w'-"-.,OUTPUT 0---.---'"Equivalent to:I30 pF R2255flINCLUDING_ JIG AND _- SCOPE -Figure la0111-3THEVENIN EQUIVALENT167nOUTPUT O---·~"~"~. ---.0 1.73 V3. TA is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.RI481n5Vo----~""""...,All Input Pulses3.0V~OUTPUT 0---.---.... 90% 90%0111-6GND 10% ·10%,;5 ns I--- ,;5 nsI 5pF~:SflINCLUDING_JIG AND _- SCOPE - 0111-5Figure Ib2-1720111-4 Figure 2

finCY7C198PRELIMINARY CY7C199~~NDUcrOR ======~~~~====~~~~==~~~~~~~~~~=====================Switching Characteristics Over Operating Range[4, 5]7C198-35 7C198-45 7C198-55Parameters Description 7C199-35 7C199-45 7C199-55 UnitsREAD CYCLEtRC Read Cycle Time 35tAAAddress to Data ValidtOHA Data Hold from Address Change 3tACEtDOECE LOW to Data ValidOE LOW to Data ValidtLZOE OE LOW to Low Z 3tHZOEOE HIGH to High Z[6]tLZCE CE LOW to Low Z[7] 3tHZCE CE HIGH to High Z[6, 7]tpu CE LOW to Power Up 0tpDWRITE CYCLErS]CE HIGH to Power Downtwc Write Cycle Time 35tSCE CE LOW to Write End 30tAw Address Set-up to Write End 30tHA Address Hold from Write End 2tSA Address Set-up to Write Start 0tpwE WE Pulse Width 20tSD Data Set-up to Write End 15tHD Data Hold from Write End 0tHZWEWE LOW to High Z[6]tLzwE WE HIGH to Low Z 3Notes:5. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, input levels of 0 to 3.0V and output loadingof the specified lor/IOH and 30 pF load capacitance.6. tHZOE, tHzCE and tHzWE are specified with CL = 5 pF as in Figure1 b. Transition is measured ± 500 m V from steady state voltage.7. At any given temperature and voltage condition, tHZCE is less thantLZCE for any given device.8. The internal write time of the memory is defined by the overlap ofCE LOW and WE LOW. Both signals must be LOW to initiate aSwitching WaveformsRead Cycle No.1 (Notes 10, 11)Min. Max. Min. Max. Min. Max.45 55 ns35 45 55 ns3 3 ns35 45 55 ns20 20 25 ns3 3 ns20 25 30 ns3 3 ns15 20 20 ns0 0 ns20 25 25 ns45 50 ns40 50 ns40 50 ns2 2 ns0 0 ns25 30 ns20 25 ns0 0 ns15 20 25 ns3 3 nswrite and either signal can terminate a write by going HIGH. Thedata input setup and hold timing should be referenced to the risingedge of the signal that terminates the write.9. WE is HIGH for read cycle.10. Device is continuously selected. OE, CE = VIL.11. Address valid prior to or coincident with CE transition LOW.12. Data I/O is high impedance ifOE = VIR.------l;~~-------------------------tRc---------------------------1~MADDRE~_~ ______ ~I_::~~:_-~~ __ ~~~~H~A~~~~~tA~A-_-.I------------.-!--------------------------~-----------------DATA OUT PREVIOUS DATA VALID DATA VALID--------------------------------------- 0111-7fI2-173

(inCY7C198. PRELIMINARY CY7C199~DUcrOR================================================================Switching Waveforms (Continued)Read Cycle No.2 (Notes 9, 11)~ ... ..,~t RCDATA OUT.l(t AcEI---tOOE - tHZOE -t LZOEt HzCE I----HIGHHIGHIMPEDANCE / IMPEDANCEDATA VALID'\--tLZCE -- tpu I--tpoSUP~~~ ____) ... -5-0%-.------------------5~:CURRENT-f-0111-8Write Cycle No.1 (WE Controlled) (Notes 8, 12)-\\ ."'-\1 ·'f-I I I / IIIIIIIIItwc .ADDRESS -n- -it--LtSCEtAW t HA -tSA ~tpwE-"1~\ \-'1( .....tsoIDATA IN )( DATA-IN VALID )(DATA I/ODATA UNDEFINED-tHZWE=!1\ "I tHO~tLZWEHIGH IMPEDANCE .,""0111-9Write Cycle No.2 (CE Controlled) (Notes 8, 12)-twc1DATA INADDRESS -it- jftSA.1 t sCE -\: 1rtAWI---tpWE- -- t HA -\ \ \ \ \ \ \ \ \ \ \ \\\ \ \\\ \~~ .'f-I I I I I I I I I I I I ItsoI"I tHOl(' DATA-IN VALID )(I-- t HZWE -HIGH IMPEDANCEDATA I/o DATA UNDEFINED ~JoI--........ -------------------'~0111-10Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.2-174

(;jiCY7C198. PRELIMINARY CY7C199~ucr~==================================================================Truth TableCE WE OE Input/Outputs ModeH X X HighZ Deselect Power DownL H L Data Out ReadL L X Data In WriteL H H HighZ DeselectOrdering InformationSpeedPackage OperatingSpeedPackage OperatingOrdering CodeOrdering Code(ns) Type Range(ns) Type Range35 CY7C198-35PC P15 Commercial 35 CY7C199-35PC P21 CommercialCY7C198-35DC D16 CY7C199-35VC V2145 CY7C198-45PC P15 Commercial CY7C199-35DC D22CY7C198-45DC D16 CY7C199-35LC L54CY7CI98-45DMB D16 Military 45 CY7C199-45PC P21 Commercial55 CY7C198-55PC P15 Commercial CY7C199-45VC V21CY7C198-55DC D16 CY7C199-45DC D22CY7CI98-55DMB D16 Military CY7C199-45LC L54CY7CI99-45DMB D22 MilitaryCY7CI99-45LMB L5455 CY7C199-55PC P21 CommercialCY7C199-55VC V21CY7C199-55DC D22CY7C199-55LC L54CY7CI99-55DMB D22 MilitaryCY7CI99-55LMB L54II2-175

~CY7C198• CYPRESS PRELIMINAR Y CY7C199s~~u~~~~~~~~~~~~~~~====================~============MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIR 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3loS 1,2,3ICC 1,2,3ISB! 1,2,3ISB2 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tOHA 7,8,9,10,11tACE 7,8,9,10,11tDoE 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSCE 7,8,9,10,11tAW 7,8,9,10,11tHA 7,8,9,10,11tSA 7,8,9,10,11tpWE 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11Document #: 38-00077-A2-176

Features• Fully decoded, 16 word x 4-bithigh speed CMOS RAMs• Inverting outputs 27S03,27LS03,74S189• Non-inverting outputs 27S07• High speed- 25 ns• Low power- 210 mW (27LS03)• Power supply 5V ± 10%• Advanced high speed CMOSprocessing for optimum speed/power product• Capable of withstanding greaterthan 2001 V static discharge• Three-state outputs• TTL compatible interface levelsCYPRESSSEMICONDUCTORFunctional DescriptionThese devices are high performance64-bit static RAMs organized as 16words x 4-bits. Easy memory expansionis provided by an active LOW chipselect (CS) input and three-state outputs.The devices are provided with invertingand non-inverting outputs.An active LOW write enable (WE) signalcontrols the writing and reading ofthe memory. When the write enable(WE) and chip select (CS) are bothLOW the information on the four datainputs (Do-D3) is written into the locationaddressed by the information onthe address lines (Ao-A3). The outputsare preconditioned such that the correctdata is present at the data outputs(00-03) when the write cycle is complete.This preconditioning operationCY74S189, CY27LS03CY27S03, CY27S0716 x 4 Static R/W RAMinsures minimum write recovery timesby eliminating the "write recoveryglitch".Reading is accomplished with an activeLOW on the chip select line (CS) and aHIGH on the write enable (WE) line.The information stored is read outfrom the addressed location and presentedat the outputs in inverted ornon-inverted format.During the write operation or when the 2chip select line is HIGH the four outputsof the memory go to an inactivehigh impedance state.Logic Block Diagrams27S03,27LS03, 74S189.--------

QCY74S189, CY27LS03.. CY27S03, CY27S07~ucr~==================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower applied ..................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 16 to 8) ........................ -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current, into Outputs (Low) ............. 20 mAElectrical Characteristics Over the Operating Rangd6]Static Discharge Voltage ..................... >2001 V(per MIL-STD-883 Method 3015)Latchup Current .......................... ::> 200 mAOperating RangeRangeAmbientTemperatureVeeCommercial O°C to + 70°C 5V ± 10%Military [5] - 55°C to + 125°C 5V ±1O%748189,27L803Parameters Description Test Conditions 27803,27807 UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = -5.2mA 2.4 2.4 VVOL Output LOW Voltage Vee = Min.,IOL = 16.0mA 0.45 VVee = Min., IOL = 8.0 rnA 0.45 VVIR Input HIGH Voltage 2.0 Vee 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 VIIX Input Leakage Current GND::;: VI::;: Vee -10 +10 -10 +10 p,AVeDInput Diode Clamp Voltage[l]Ioz Output Leakage Current GND::;: Vo::;: Vee -40 +40 -40 +40 p,Alos Output Short Circuit Current [2] Vee = Max., VOUT = GND -90 -90 rnAIceCapacitance [4]Power Supply CurrentVee = Max., I Commercial 90 rnAlOUT = OmA I Military 100 38 rnAParameters Description Test Conditions Max. UnitsCIN Input Capacitance T A = 25°C, f = 1 MHz 4pFCOUT Output Capacitance Vee = 5.0V 7Notes:1. The eMOS process does not provide a clamp diode. However these4. Tested initially and after any design or process changes that maydevices are insensitive to - 3V dc input levels and - 5V undershootaffect these parameters.pulses ofJess than 5 ns (measured at 50% points).5. TA is the "instant on" case temperature.2. Not more than I output should be shorted at one time. Duration of6. See the last page of this specification for Group A subgroup testingthe short circuit should not exceed 30 seconds.information.3. Output is precoditioned to data in (inverted or non-inverted) duringwrite to insure correct data is present on all outputs when write isterminated. (No write recovery glitch.)2~178

~CY74S189, CY27LS03. CY27S03, CY27S07~NDUcroR =====================================================================Switching Characteristics Over the Operating Range[6, 7]27S03AParameters Description 27S07AREAD CYCLEMin.tRC Read Cycle Time 25Max.tAA Address to Data Valid[lO] 25tACS CS Low to Data Valid[lO] 15tHZCS CS HIGH to High Z[9, 11, 12] 15WRITE CYCLE[3, 7, 8]twc Write Cycle Time 25tSA Address Set-up to Write Start 0tHA Address Hold from Write End 0tscstHCSCS Set-up to Write StartCS Hold from Write EndtSD Data Set-up to Write End 20tHD Data Hold from Write End 0tPWE WE Pulse Width 20tHzwE WE LOW to High Z[9, II, 12] 20tAwE WE HIGH to Output Valid[lO] 20Notes:7. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, output loading of the specified lor/IOH and30 pF load capacitance.8. The internal write time of the memory is defined by the overlap ofCSLOW and WE LOW. Both signals must be LOW to intiate a writeand either signal can terminate a write by going HIGH. The datainput setup and hold timing should be referenced to the rising edge ofthe signal that terminates the write.BitMap27S0327S071~123 a12~11~.123 a1~~I. COLUMN~ooo 111~~222 333~f-o ..-------OUTPUTS74S18927LS03Min. Max. Min. Max. Min. Max.Units35 35 65 ns35 35 65 ns17 22 35 ns20 17 35 ns35 35 65 ns0 0 0 ns0 0 0 ns0 ns0 ns25 20 55 ns0 0 0 ns25 20 55 ns25 20 35 ns35 30 35 ns9. Transition is measured at steady state HIGH level - 500 m V orsteady state LOW level + 500 mV on the output from 1.5V level onthe input.10. tAA, tACS and tAWE are tested with CL = 30 pF as in Figure laoTiming is referenced to 1.5V on the inputs and outputs.II. tHzCS and tHzwE are tested with CL = 5 pF as in Figure 1 b.12. At any given temperature and voltage condition, tHZCS is less thantLZCS for any given device.RowaAddress DesignatorsAddressNameAddressFunctionPinNumberAo AXO 1Al AXI 15A2 AYO 14A3 AYI 13fIROW 30006-92-179

(inCY74S189, CY27LS03CY27S03, CY27S07~~MOOCTOR =====================================================================AC Test Loads and WaveformsR123tflR123tfl5 V O-----'V'-\l\r---.ALL INPUT PULSES3.0V----"1r~!"'""--~OUTPUT~--~----' OUTPUT ~--~---......30pF,NCLUD,NGI JIG AND':" SCOPEFigure la':"R2150125pFINCLUDINGI _ JIG AND _- SCOPE -Figure IbR2150120006-4GND---"'I.;5ns

fin• CYPRFSSCY74S189, CY27LS03CY27S03, CY27S07S~~crOR================================================================Ordering InformationfISpeedPackage OperatingOrdering Code(ns) Type Range25 CY27S03APC PI CommercialCY27S07APCCY27S03ADC D2CY27S07ADCCY27S03ALMB L6I MilitaryCY27S07 ALMBCY27S03ADMB D2CY27S07 ADMB35 CY27S03PC PI CommercialCY27S07PCCY74SI89PCCY27S03DC D2CY27S07DCCY74SI89DCCY27S03LC L6ICY27S07LCCY27S03LMB L6I MilitaryCY27S07LMBCY27S03DMB D2CY27S07DMB65 CY27LS03LMB L6I MilitaryCY27LS03DMB D22-181

(;IiCY74S189, CY27LS03• CYPRESSCY27S03, CY27~07S~IOO~UaDR==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsREAD CYCLEtRC 7,8,9,10,11tAA 7,8,9,10,11tACS 7,8,9,10,11WRITE CYCLEtwc 7,8,9,10,11tSA 7,8,9,10,11tHA 7,8,9,10,11tscs 7,8,9,10,11tHCS 7,8,9,10,11tSD 7,8,9,10,11tHD 7,8,9,10,11tpwE 7,8,9,10,11tAwE 7,8,9,10,11Document #: 38-00041-C2-182

l?eatures• 256 x 4 static RAM for controlstores in high speed computer• Processed with high speedCMOS for optimumspeed/power• Separate inputs and outputs• Low power- Standard power:660 mW (commercial)715 mW (military)- Low power:440 mW (commercial)495 mW (military)• 5 volt power supply ± 10%tolerance both commercial andmilitary• Capable of withstanding greaterthan 2001 V static dischargeCYPRESSSEMICONDUCTORFunctional DescriptionThe CY93422 is a high performanceCMOS static RAM organized as256 x 4 bits. Easy memory expansion isprovided by an active LOW chip selectone (CS}) input, an active HIGH chipselect two (CS2) input, and three-stateoutputs.An active LOW write enable input(WE) controls the writing/reading operationof the memory. When the chipselect one (CS}) and write enable (WE)inputs are LOW and the chip selecttwo (CS2) input is HIGH, the informationon the four data inputs Do to D3 iswritten into the addressed memoryword and the output circuitry is preconditionedso that the correct data ispresent at the outputs when the writecycle is complete. This preconditioningCY93422A/93L422ACY93422/93L422256 X 4 Static R/W RAMoperation insures minimum write recoverytimes by eliminating the "writerecovery glitch."Reading is performed with the chip selectone (CS}) input LOW, the chip selecttwo input (CS2) and write enable(WE) inputs HIGH, and the output enableinput (OE) LOW. The informationstored in the addressed word is readout on the four non-inverting outputs00 to 03.The outputs of the memory go to anactive high impedance state wheneverchip select one (CS}) is HIGH, chip selecttwo (CS2) is LOW, output enable(OE) is HIGH, or during the writingoperation when write enable (WE) isLOW.tilLogic Block DiagramPin ConfigurationsVeeWECS1OE030302f') 0 (,) ~..,.« z z >

5ACY93422A/93L422A. CY93422/93L422~UaoR==================================================================Maximum Ratings(Above which the useful life may be impaired. For userguidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 22 to Pin 8) ..................... -O.SV to + 7.0VDC Voltage Applied to Outputsfor High Output State .............. -O.SV to VCC MaxDC Input Voltage ................... -O.SV to + S.SVOutput Current, into Outputs (Low) ............. 20 rnADC Input Current ............... - 30 rnA to + 5.0 rnAStatic Discharge Voltage ..................... > 200 1 V(per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 rnAOperating RangeRangeVeeAmbientTemperatureCommercial SV ± 10% O°C to +7SoCMilitary [6] SV ±10% - SsoC to + 12SoCDC Electrical Characteristics Over Operating Range[S]Function TableInputsOutputsCS2 CSt WE OE Dn OnModeL X X X X *HIGHZ Not SelectX H X X X *HIGHZ Not SelectH L H H X *HIGHZ Output DisableH L H L XSelectedDataRead DataH L L X L *HIGHZ Write "0"H L L X H *HIGHZ Write "1"H = High Voltage Level L = Low Voltage Level X = Don't Care"HIGH Z implies outputs are disabled or off. This condition is definedas a high impedance state for the CY93422.93422 93L422Parameters Description Test Conditions 93422A 93L422A UnitsMin. Max. Min. Max.VOHVOLVIHVILOutput HIGH VoltageOutput LOW VoltageInput HIGH Level[l]Input LOW Level[l]Vee = Min.,VIN = VIH or VILVee = Min.,VIN = VIH or VILGuaranteed Input Logical HIGHVoltage for all InputsGuaranteed Input Logical LOWVoltage for all InputsIOH = -S.2mA 2.4 2.4 VIOL = S.OmA O.4S 0.4S V2.1 2.1 VO.S 0.8 VIlL Input LOW Current Vee = Max., VIN = O.40V -300 -300 p.AIIH Input HIGH Current V CC = Max., VIN = 4.SV 40 40 p.AIseOutput ShortCircuit CurrentVee = Max., VOUT = 0.OV[2) -90 -90 mATA = 12SoC 110 70All Inputs = GND, TA = 7SoC 110 70IcC Power Supply Current mAVce = Max. TA = O°C 120 SOTA = -SsoC 130 90VCL Input Clamp Voltage See Note 4 See Note 4ICEXOutput Leakage CurrentVOUT = 2.4V SO SOVOUT = O.SV, VCC = Max. -SO -SOCIN Input Pin Capacitance See Note 3 4 4 pFCOUT Output Pin Capacitance See Note 3 7 7 pFNotes:1. These are absolute voltages with respect to device ground pin and4. The CMOS process does not provide a clamp diode. However, theinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment.pulses ofless than 10 ns (measured at 50%CY93422 is insensitive to - 3V dc input levels and - 5V undershootpoint).2. Not more than one output should be shorted at a time. Duration ofthe short circuit should not be more than one second.3. Tested initially and after any design or process changes that mayaffect these parameters.5. See the last page ofthis specification for Group A subgroup testinginformation.6. T A is the "instant on" case temperature.p.A2-184

5nCY93422A/93L422A. CY93422/93L422~~UaoR================================================================~Commercial Switching Characteristics vcc = 5V ± 10%. TA = ooe to +75°e (Unless Otherwise Noted)ParametersDescriptiontpLH(A) [11 Delay from Address to OutputtPHL(A) [11 (Address Access Time) (See Figure 2)tpzH (CSI. CS2) Delay from Chip Select to ActivetPZL (CSt, CS2) Output and Correct Data (See Figure 2)tpzH(WE)tPZL(WE)Delay from Write Enable toActive Output and Correct Data(Write Recovery) (See Figure 1)tPZH (OE) Delay from Output Enable to ActivetpzL(OE) Output and Correct Data (See Figure 2)ts(A)th (A)ts (DI)th (DI)ts (CSt, CS2)th (CSI. CS2)tpw (WE)Setup Time Address (Prior toInitiation of Write) (See Figure 1)Hold Time Address (AfterTermination of Write) (See Figure 1)Setup Time Data Input (Prior toInitiation of Write) (See Figure 1)Hold Time Data Input (AfterTermination of Write) (See Figure 1)Setup Time Chip Select (Prior toInitiation of Write) (See Figure 1)Hold Time Chip Select (AfterTermination of Write) (See Figure 1)Minimum Write Enable Pulse Widthto Insure Write (See Figure 1)tpHZ (CSt, CS2) Delay from Chip Select to InactivetpLZ (CSI. eS2) Output (HIGH Z) (See Figure 2)tPHZ(WE) Delay from Write Enable to InactivetPLZ(WE) Output (HIGH Z) (See Figure 1)tpHZ (OE) Delay from Output Enable to InactivetpLZ(OE) Output (HIGH Z) (See Figure 2)~otes:. tpLH (A) and tpHL (A) are tested with S, closed and CL = 15 pFwith both input and output timing referenced to 1.5V.:. tpzH (WE), tPZH (CS" CS2) and tPZH (OE) are measured with S,open, CL = 15 pF and with both the input and output timing referencedto 1.5V. tPZL (WE), tpzL (CS" CS2) and tPZL (OE) are measuredwith S, closed, CL = 15 pF and with both the input and output93422A 93IA22A 93422 93L422UnitsMin. Max. Min. Max. Min. Max. Min. Max.35 45 45 60 ns5555552025 30 30 35 ns25 40 40 45 ns25 30 30 35 ns5 10 10 ns5 5 5 ns5 5 5 ns5 5 5 ns5 5 5 ns5 5 5 ns40 30 45 ns30 40 30 45 ns30 40 35 45 ns30 40 30 45 nstiming referenced to 1.5V. tPHZ (WE), tpHZ (CS" CS2) and tpHZ(OE) are measured with S, open, CL S 5 pF and are measured betweenthe 1.5V level on the input to the V OH - 500 m V level on theoutput. tpLZ (WE), tpLZ (CS" CS2) and tPLZ (OE) are measured withS, closed and CL S 5 pF and are measured between the 1.5V level onthe input and the VOL + 500 m V level on the output.til2-185

WACY93422A/93L422A. CY93422/93L422~NDUcrOR==================================================================Military Switching Characteristics Vee = 5V ± 10%, TA = - 55°C to + 125°C (Unless Otherwise Noted)[5]ParametersDescriptiontPLH(A) [11 Delay from Address to OutputtPHL(A)[l] (Address Access Time) (See Figure 2)tPZH (CSt. CS2) Delay from Chip Select to ActivetPZL (CSt. CS2) Output and Correct Data (See Figure 2)tpzH(WE)tPZL (WE)Delay from Write Enable toActive Output and Correct Data(Write Recovery) (See Figure 1)tPZH (OE) Delay from Output Enable to ActivetPZL (OE) Output and Correct Data (See Figure 2)ts (A)th (A)ts (DI)th (DI)ts (CSt. CS2)th (CSt. CS2)tpw (WE)Setup Time Address (Prior toInitiation of Write) (See Figure 1)Hold Time Address (AfterTermination of Write) (See Figure 1)Setup Time Data Input (Prior toInitiation of Write) (See Figure 1)Hold Time Data Input (AfterTermination of Write) (See Figure 1)Setup Time Chip Select (Prior toInitiation of Write) (See Figure 1)Hold Time Chip Select (AfterTermination of Write) (See Figure 1)Minimum Write Enable Pulse Widthto Insure Write (See Figure 1)tpHZ (CS t. CS2) Delay from Chip Select to InactivetPLZ (CSt. CS2) Output (HIGH Z) (See Figure 2)tpHZ (WE) Delay from Write Enable to InactivetPLZ (WE) Output (HIGH Z) (See Figure 1)tPHZ(OE) Delay from Output Enable to InactivetPLZ (OE) Output (HIGH Z) (See Figure 2)Notes:1. tpLH (A) and tPHL (A) are tested with SI closed and CL = 15 pFwith both input and output timing referenced to 1.5V.2. tPZH (WE), tPZH (CSb CS2) and tpzH (OE) are measured with SIopen, CL = 15 pF and with both the input and output timing referencedto l.5V. tPZL (WE), tpZL (CS1, CS2) and tPZL (00) are measuredwith SI closed, CL = 15 pF and with both the input and output93422A 93IA22A 93422 93IA22UnitsMin. Max. Min. Max. Min. Max. Min. Max.45 55 60 75 ns5555553535 40 45 45 ns40 45 50 50 ns35 40 45 45 ns10 10 10 ns5 5 10 ns5 5 5 ns5 5 5 ns5 5 5 ns5 5 10 ns40 40 45 ns35 40 45 45 ns40 40 45 45 ns35 40 45 45 nstiming referenced to l.5V. tPHZ (WE), tpHZ (CS1, CS2) and tpHZ(OE) are measured with SI open, CL S; 5 pF and are measured betweenthe 1.5V level on the input to the VOH - 500m V level on theoutput. tpLz (WE), tpLz (CS1, CS2) and tPLZ (OE) are measured withSI closed and CL S; 5 pF and are measured between the 1.5V level onthe input and the VOL + 500 m V level on the output.2-186

finCY93422A/93L422A. CY93422/93L422~UcroR ==================================================================~Switching WaveformsWrite Mode (with OE = Low)Key to Timing DiagramCHIPSELECTCS,CS2AO-A7 --~~1IIaADDRESSINPUTS __-+_l1li'1'-_____________..J l'aA~DATAINPUT Ox ~==I=~I~iWE ---1---+----""WRITEENABLEOxDATA ---+~F+

finCY93422A/93L422A. CY93422/93L422~~u~======================================~~~~~~~~~~~~~Ordering InformationSpeed Ordering Code Package Operating(ns) Std. Power Low Power Type Range35 CY93422APC P7 CommercialCY93422ADCD8CY93422ALCL5445 CY93422PC CY93L422APC P7 CommercialCY93422DC CY93L422ADC D8CY93422LC CY93L422ALC L54CY93422ADMB D8 MilitaryCY93422ALMBL5455 CY93L422ADMB D8 MilitaryCY93L422ALMB L5460 CY93422DMB D8 MilitaryCY93422LMBL54CY93L422PC P7 CommercialCY93L422DCD8CY93L422LCL5475 CY93L422DMB D8 MilitaryCY93L422LMBL542-188

5ACY93422A/93L422ACY93422/93L422• CYPRESSs~~O~UcrOR============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IlL 1,2,3IIH 1,2,3Icc 1,2,3IcEx 1,2,3SubgroupsEISwitching CharacteristicsParameters SubgroupstPLH(A) 7,8,9,10,11tPHL(A) 7,8,9,10,11tpZH (CSt.CS2) 7,8,9,10,11tpzL (CSt,CS2) 7,8,9,10,11tPZH(WE) 7,8,9,10,11tPZL(WE) 7,8,9,10,11tPZH (OE) 7,8,9,10,11tpzL(OE) 7,8,9,10,11is (A) 7,8,9,10,11th (A) 7,8,9,10,11ts (DI) 7,8,9,10,11th (DI) 7,8,9,10,11ts (CSt, CS2) 7,8,9,10,11th (CSt, CS2) 7,8,9,10,11tpw (WE) 7,8,9,10,11Document #: 38-00022-C2-189

PRODUCTINFORMATION•STATIC RAMS'II=- ~PROMS•-"EPLDSLOGICRISCBRIDGEMOS ..QUICKPRO•[IIIIQUALITY ANDRELIABILITYAPPLICATION BRIEFSPACKAGESDJIII

~ Section Contents~~~~u~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==PROMs (Programmable Read Only Memory)Page NumberIntroduction to PROMs .................................................................................. 3-1Device Number DescriptionCY7C225 512 x 8 Registered PROM .................................................. 3-4CY7C235 1024 x 8 Registered PROM ................................................. 3-15CY7C245 2048 x 8 Reprogrammable Registered PROM .................................. 3-26CY7C245A 2048 x 8 Reprogrammable Registered PROM .................................. 3-38CY7C251 16,384 x 8 Reprogrammable Power Switched PROM ............................. 3-50CY7C254 16,384 x 8 Reprogrammable PROM ........................................... 3-50CY7C261 8192 x 8 Reprogrammable Power Switched PROM ............................. 3-60CY7C263 8192 x 8 Reprogrammable PROM ........................................... 3-60CY7C264 8192 x 8 Reprogrammable PROM ........................................... 3-60CY7C268 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-71CY7C269 8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-71CY7C271 32,768 x 8 Reprogrammable Power Switched PROM ............................. 3-84CY7C281 1024 x 8 PROM .......................................................... 3-90CY7C282 1024 x 8 PROM .......................................................... 3-90CY7C291 2048 x 8 Reprogrammable PROM ........................................... 3-99CY7C291A 2048 x 8 Reprogrammable PROM .......................................... 3-108CY7C292 2048 x 8 PROM .......................................................... 3-99CY7C292A 2048 x 8 Reprogrammable PROM .......................................... 3-108CY7C293A 2048 x 8 Reprogrammable PROM .......................................... 3-108PROM Programming Information ....................................................................... 3-117

~ Introduction to CMOS PROMs~~~~UaoR================================================================~1: Product Line OverviewThe Cypress CMOS family of PROMs span 4K to 256Kbit densities, three functional configurations, and are allbyte-wide. The product line is available in both 0.3 and 0.6inch wide dual-in-line plastic and CERDIP as well as LCCand PLCC packages. The programming technology isEPROM and therefore windowed packages are available inboth dual-in-line and LCC configurations, providing erasableproducts. These byte-wide products are available inregistered versions at the 512, lK, 2K, and 8K by 8 densities,and in non-registered versions at the lK, 2K, 8K, 16Kand 32K by 8 densities. The registered devices operate ineither synchronous or asynchronous output enable modesand may have an initialize feature to preload the pipelineregister. The 8K by 8 registered devices feature a diagnosticshadow register which allows the pipeline register to beloaded or examined via a serial path.Cypress PROMs perform at the level of their bipolar equivalentsor beyond with reduced power levels of CMOS technology.They are capable of 2001 volts of ESD and operatewith 10% power supply tolerances.2: Technology IntroductionCypress PROMs are executed in an "N" well CMOSEPROM process. Densities of 128K and under with theexception of the "A" series devices use the 1.2 micronPROM I technology. The 16K "A" series devices and thefuture 256K PROMs use the 0.8 micron PROM II technologywith a single ended memory cell. The process providesbasic gate delays of 235 picoseconds for a fanout ofone at a power consumption of 45 femto joules. The processprovides the basis for the development of LSI productsthat outperform the fastest bipolar products currentlyavailable.Although CMOS static RAMs have challenged bipolarRAMs for speed, CMOS EPROMs have always been afactor of three to ten times slower than bipolar fusePROMs. There have been two major limitations on CMOSEPROM speed; 1) the single transistor EPROM cell is inherentlyslower than the bipolar fuse element, and 2)CMOS EPROM technologies have been optimized for cellprogrammability and density, almost always at the expenseof speed. In the Cypress CMOS EPROM technology, bothof the aformentioned limitations have been overcome tocreate CMOS PROMs with performance superior toPROMs implemented in bipolar technology.In all Cypress PROMs, speed and programmability are optimizedindependently by separating the read and writetransistor functions. Also, for the first time a substrate biasgenerator is employed in an EPROM technology to im~prove performance and raise latchup immunity to greaterthan 200 mA. The result is a CMOS EPROM technologythat challenges bipolar fuse technology for both densityand speed. In addition, at higher densities, performanceand density surpasses the best that bipolar can provide.Limitations of devices implemented in the bipolar fusetechnology such as PROGRAMMING YIELD, POWERDISSIPATION and HIGHER DENSITY PERFORM­ANCE are eliminated or greatly reduced using CypressCMOS EPROM technology.3: Design ApproachA. Four Transistor Differential Memory CellThe 4K, 8K, and 16K PROM (except "A" version) use anN-Well CMOS technology along with a new differentialfour transistor EPROM cell that is optimized for speed.The area of the four transistor cell is 0.43 square mils andthe die size is 19,321 square mils for the 2K by 8 PROM(Figure 1). The floating gate cell is optimized for high readcurrent and fast programmability. This is accomplished byseparating the read and program transistors (Figure 2). Theprogram transistor has a separate implant to maximize thegeneration and collection of hot electrons while the readtransistor implant dose is chosen to provide a large readcurrent. Both the nand p channel peripheral transistorshave self-aligned, shallow, lightly doped drain (LDD) junctions.The LDD structure reduces overlap capacitance forspeed improvement and minimizes hot electron injectionfor improved reliability. Although common for NMOSstatic and dynamic RAMs, an on-chip substrate bias generatoris used for the first time in an EPROM technology.The results are improved speed, greater than 200 mA 3latch-up immunity and high parasitic field inversion voltagesduring programming.Figure 10034-10034-2Figure 2. Non-volatile cell optimizedfor speed and programmabilityAccess times ofless than 35 ns at 16K densities and 30 nsat 4K and 8K densities over the full operating range areachieved by using differential design techniques and by to-3-1

~ Introduction to CMOS PROMs (Continued)~,-~==========================================,----------------,I OPERATIONAL At.lPLIF"IER IIIr--------"CASCODE At.lPYR~r--IIIIIIII!S1III~-------------------.SAFigure 3. Differential sensing0034-3tally separating the read and program paths. This allowsthe read path to be optimized for speed. The X and Ydecoding paths are predecoded to optimize the power-delayproduct. A differentail sensing scheme and the four transistorcell are used to sense bit-line swings as low as 100 m Vat high speed. The sense amplifier (Figure 3) consists ofthree stages of equal gain. A gain of 4 per stage was foundto be optimum. The Cascode stage amplifies the bit lineswings and feeds them into a differential amplifier. Theoutput of the differential amplifier is further amplified andvoltages shifted by a level shifter and latch. This signal isthen fed into an output buffer having a TTL fan-out of ten.B. Two Transistor Memory CellThe Cypress 64K and greater density PROMs. use a twotransistor memory cell. This cell uses a single ended sensingscheme with the exception of the 256K device whichuses a differential sensing circuit. This combination allowsfor a more compact design and reduced manufacturingcosts. This is an excellent compromise between performanceand high density, allowing the development of deviceswith performance of 35 ns and 45 ns access times at densitiesfrom 64K to 256K bits and 25 ns for the "A" series16K using the PROM II technology. This two transistorcell still uses the high speed read transistor and the optimizedEPROM transistor for performance and reliableprogramming. The sense amplifier uses a reference voltageon one input and the read transistor on the other, insteadof two read transistors. This single ended sensing is a moreconventional technique and has the effect of causing anerased device to contain all "O"s.4: ProgrammingA. Differential Memory CellsCypress PROMs are programmed a BYTE at a time byapplying 12 to 14 volts on one pin and the desired logiclevels to input pins. Both logic "ONE" and logic "ZERO"are programmed into the differential cell. A BIT is programmedby applying 12 to 14 volts on the control gateand 9 volts on the drain of the floating gate write transistor.This causes hot electrons from the channel to be injectedonto the floating gate thereby raising the threshold voltage.Because the read transistor shares a common floatinggate with the program transistor, the threshold of the readtransistor is raised from about 1 volt to greater than 5 voltsresulting in a transistor that is turned "OFF" when selectedin a read mode of operation. Since both sides of thedifferential cell are at equal potential. before programming,a threshold shift of 100m V is enough to be determined asthe correct logic state. Because an unprogrammed cell hasneither a ONE nor a ZERO in it before programming, aspecial BLANK CHECK mode of operation is implemented.In this mode the output of each half of the cell is comparedagainst a fixed reference which allows distinction ofa programmed or unprogrammed cell. A MARGIN modeis also provided to monitor the thresholds of the individualBITs allowing the monitoring of the quality of programmingduring the manufacturing operation.B. Single Ended Memory CellsThe programming mechanism of the EPROM transistor ina single ended memory cell is the same as its counterpart ina double ended memory cell. The difference is that onlyones "1"s are programmed in a single ended cell. A "I"applied to the I/O pin during programming causes anerased EPROM transistor to be programmed while a "0"allows the EPROM transistor to remain unprogrammed.5: ErasabilityFor the first time at PROM speeds, Cypress PROMs usingCMOS EPROM technology offer reprogrammability whenpackaged in windowed CERDIP. This is available at densitiesof 16K and larger, both registered and non-registered.3-2

~ Introduction to CMOS PROMs(Continued)~~~NDUcrOR ==================================================================~Wavelengths of light less than 4000 Angstroms begin toerase Cypress PROMs. For this reason, an opaque labelshould be placed over the window if the PROM is exposedto sunlight or fluorescent lighting for extended periods oftime.The recommended dose of ultraviolet light for erasure is awavelength of 2537 Angstroms for a minimum dose (UVintensity X exposure time) of 25 Wsec/cm2. For an ultravioletlamp with a 12 mW/cm2 power rating the exposuretime would be approximately 30-35 minutes. The industryEPROM erasure standard is 15 Wsec/cm 2 .EPROMs require 1% longer erase times.CypressThe PROM needs to be within 1 inch of the lamp duringerasure. Permanent damage may result if the PROM isexposed to high intensity light for an extended period oftime. 7258 Wsec/cm2 is the recommended maximum dosage.Some devices are sensitive to photo-electric effects duringprogramming. Cypress recommends covering the windowsof reprogrammable devices during programming.6: ReliabilityThe CMOS EPROM approach to PROMs has some significantbenefits to the user in the area of programming andfunctional yield. Since a cell may be programmed anderased multiple times, CMOS PROMs from Cypress can betested 100% for programmability during the manufacturingprocess. Because each CMOS PROM contains aPHANTOM array, both the functionality and performanceof the devices may be tested after they are packaged thusassuring the user that not only will every cell program, butthat the product performs to the specification.3-3

CYPRESSSEMICONDUCTORCY7C225512 X 8 Registered PROMFeatures• CMOS for optimumspeed/power• High speed- 25 ns max set-up- 12 ns clock to output• Low power- 495 mW (commercial)- 660 mW (military)• Synchronous and asynchronousoutput enables• On-chip edge-triggeredregisters• Buffered Common PRESET andCLEAR inputs• EPROM technology, 100%programmableLogic Block Diagram• Slim, 300 mil, 24 pin plastic orhermetic DIP, or 28 pin LCC• 5V ± 10% V cc, commercial andmilitary• TTL compatible I/O• Direct replacement forbipolar PROMs• Capable of withstandinggreater than 1500V staticdischargeProduct CharacteristicsThe CY7C225 is a high performance512 word by 8 bit electrically ProgrammableRead Only Memory packaged ina slim 300 mil plastic or hermetic DIPand 28 pin Leadless Chip Carrier. Thememory cells utilize proven EPROMfloating gate technology and byte-wideintelligent programming algorithms.The CY7C225 replaces bipolar devicesand offers the advantages oflowerpower, superior performance and highprogramming yield. The EPROM cellrequires only 13.5V for the supervoltageand low current requirements allowfor gang programming. The EPROMcells allow for each memory location tobe tested 100%, as each location iswritten into, erased, and repeatedly exercizedprior to encapsulation. EachPROM is also tested for AC performanceto guarantee that after customerprogramming the product will meetAC specification limits.The CY7C225 has asynchronous PRE­SET and CLEAR functions.Pin ConfigurationsA7VeeA3A2A,Ao~CI:A"CPESROWDECODER1 OF 32COLUMNDECODER1 OF 1632 x 128PROGRAMMABLEARRAY070605SBIT 04EDGE-TRIGGEREDREGISTER 03020,000020-1A6A5A4A3A2AlAo000,02GND.r:t~~ ~:tl~4 3 2l!]282726A4 5 25A3 6 24A2 23AI 22Ao 9 21NC 10As'PS"mEsCP0706050403ECLREsCPNC°700 11 19 06121314151617180020-2- NO 0 tt) ... I/)OOZ%OOO(!) 0020-11Selection GuideMaximum Set-up Time (ns)Maximum Clock to Ouput (ns)Maximum OperatingCurrent (rnA)II7C225-25 7C225-30 7C225-35 7C225-4025 30 35 4012 15 20 25Commercial 90 90 90Military 120 120 1203-4

~ CY7C225~~~NDUcrOR ~~~~~~~~~====================================================~Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VStatic Discharge Voltage ..................... > 1500V(Per MIL-STD-883 Method 3015)Latch-up Current .......................... > 200 mAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto +7(J'C SV ±1O%DC Program Voltage (Pins 7, 18,20) ............. 14.0V Military [6] - SsoC to + 12SoC SV ±1O%VeeElectrical Characteristics Over Operating Range[7]Parameters Description Test Conditions Min. Max. UnitsVOHOutput HIGH VoltageVee = Min.,IOH = -4.0mAVIN = VIH or VIL2.4 VVOLOutput LOW VoltageVec = Min.,IoL = -16 rnAVIN = VIH or VIL0.4 VVIHInput HIGH LevelGuaranteed Input Logical HIGHVoltage for All Inputs[2]2.0 VVILInput LOW LevelGuaranteed Input Logical LOWVoltage for All inputs[2]0.8 VIIX Input Leakage Current GND:::;: VIN :::;: Vec -10 +10 p.AVCDInput Clamp DiodeVoltageNote 1Ioz Output Leakage Current GND :::;: Vo :::;: Vee Output Disabled[4] -40 +40 p.Alos Output Short Circuit Current VCC = Max., VOUT = 0.OV[3] -20 -90 rnAGND :::;: VIN :::;: Vec I Commercial 90IcCPower Supply CurrentrnAVce = Max.Military 120IIICapacitance [5]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 2SoC, f = 1 MHz, Vee = S.OV S pFCoUT Output Capacitance TA = 25°C, f = 1 MHz, Vcc = S.OV 8 pFNotes:1. The CMOS process does not provide a clamp diode. However, theCY7C225 is insensitive to - 3V dc input levels and - 5V undershootpulses ofless than 10 ns (measured at 50% point).2. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment (see Notes onTesting).3. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.4. For devices using the synchronous enable, the device must be clockedafter applying these voltages to perform this measurement.5. Tested initially and after any design or process changes that mayaffect these parameters.6. T A is the "instant on" case temperature.7. See the last page of this specification for Group A subgroup testinginformation.3-5

~ CY7C225~~~~UaoR==~~~~~~~~~~~~~~================================~==Switching Characteristics Over Operating Range[7, s]ParameterstSAtHAteotpwetSEstHEStop, toetRP, tReDescriptionAddress Setup to Clock HIGHAddress Hold from Clock HIGHClock HIGH to Valid OutputClock Pulse WidthEs Setup to Clock HIGHEs Hold from Clock HIGHDelay from PRESET or CLEAR to Valid OutputPRESET or CLEAR Recovery to Clock HIGHtpwP, tpwe PRESET or CLEAR Pulse WidthteosValid Output fromClock HIGH[l]tHze Inactive Output from Clock HIGH[1, 3]tOOEtHZEValid Output from E LOW[2]Inactive Output fromEHIGH[2,3]Notes:1. Applies only when the synchronous (ES) function is used.2. Applies only when the asynchronous (E) function is used.3. Transition is measured at steady state HIGH level - SOO m V orsteady state LOW level + SOO m V on the output from the 1.SV levelon the input with loads shown in Figure lb.4. Tests are performed with rise and fall times of S ns or less.AC Test Loads and Waveforms[5, 6, 7]Rl 250 nThe CY7C225 is a CMOS electrically Programmable ReadOnly Memory organized as 512 words x 8·bits and is a pinfor-pinreplacement for bipolar TTL fusible link PROMs.The CY7C225 incorporates a D-type, master-slave registeron chip, reducing the cost and size of pipelined microprogrammedsystems and applications where accessed PROMdata is stored temporarily in a register. Additional flexibilityis provided with synchronous (ES) and asynchronous(E) output enables, and CLEAR and PRESET inputs.Upon power-up, the synchronous enable (Es) flip-flop willbe in the set condition causing the outputs (00-07) to bein the OFF or high impedance state. Data is read byR1250n7C225·25 7C225·30 7C225·35 7C225·40Min. Max. Min. Max. Min. Max. Min. Max.Units2530 35 40 ns00 0 0 ns12 15 20 25 ns1015 20 20 ns1010 10 10 ns05 5 5 ns20 20 20 20 ns1520 20 20 ns1520 20 20 ns20 20 25 30 ns20 20 25 30 ns20 20 25 30 ns20 20 25 30 nsS. See Figure 1 a for all switching characteristics except tHZ.6. See Figure 1 b for tHZ.7. All device test loads should be located within 2" of device outputs.S. See the last page of this specification for Group A subgroup testinginformation.ALL INPUT PULSESOUTPUT 0---...... ---.... OUTPUT 0,.--_---....3.0 V--------'-----'IL5pF R250 pF ~:7 12l67S! GND --....;~INCLUDINGINCLUDING.;;5nsI JIG AND I _ JIG AND _-= SCOPE -=- SCOPE -0020-3Figure laFigure IbFigure 2Equivalent to:THEVENIN EQUIVALENTloonOUTPUT ~2.0V0020-4Functional Description.;5ns0020-5applying the memory location to the address inputs (Ao­As) and a logic LOW to the enable (Es) input. The storeddata is accessed and loaded into the master flip-flops of thedata register during the address set-up time. At the nextLOW-to-HIGH transition of the clock (CP), data is trans·ferred to the slave flip-flops, which drive the output buffers,and the accessed data will appear at the outputs (00-07) provided the asynchronous enable (E) is also LOW.The outputs may be disabled at any time by switching theasynchronous enable (E) to a logic HIGH, and may bereturned to the active state by switching the enable to alogic LOW.3-6

~ CY7C225~~~~UcrOR======~~====~======~=============================================Functional Description (Continued)Regardless of the condition ofE, the outputs will go to theOFF or high impedance state upon the next positive clockedge after the synchronous enable (Es) input is switched toa HIGH level. If the synchronous enable pin is switched toa logic LOW, the subsequent positive clock edge will returnthe output to the active state ifE is LOW. Following apositive clock edge, the address and synchronous enableinputs are free to change since no change in the output willoccur until the next low to high transition of the clock.This unique feature allows the CY7C225 decoders andsense amplifiers to access the next location while previouslyaddressed data remains stable on the outputs.System timing is simplified in that the on-chip edge triggeredregister allows the PROM clock to be derived directlyfrom the system clock without introducing race conditions.The on-chip register timing requirements are similarto those of discrete registers available in the market.Switching WaveformsThe CY7C225 has buffered asynchronous CLEAR andPRESET input (INIT). The initialize function is usefulduring power-up and time-out sequences.Applying a LOW to the PRESET input causes an immediateload of all ones into the master and slave flip-flops ofthe register, independent of all other inputs, including theclock (CP). Applying a LOW to the CLEAR input, resetsthe flip-flops to all zeros. The initialize data will appear atthe device outputs after the outputs are enabled by bringingthe asynchronous enable (E) LOW.When power is applied the (internal) synchronous enableflip-flop will be in a state such that the outputs will be inthe high impedance state. In order to enable the outputs aclock must occur and the Es input pin must be LOW atleast a setup time prior to the clock LOW to HIGH transition.The E input may then be used to enable the outputs.AO-Al0 ----------------__________________ ~----~~~l-----+_----~~~~~Q£Wl---------------------IIESCP~orQRNotes on TestingIncoming test procedures on these devices should be carefully planned,taking into account the high performance and output drive capabilities ofthe parts. The following notes may be useful.1. Ensure that adequate decoupling capacitance is employed across thedevice Vee and ground terminals. Multiple capacitors are recommended,including a 0.1 ,..,F or larger capacitor and a 0.01 ,..,F orsmaller capacitor placed as close to the device terminals as possible.Inadequate decoupling may result in large variations of power supplyvoltage, creating erroneous function or transient performance failures.2. Do not leave any inputs disconnected (floating) during any tests.0020-63. Do not attempt to perform threshold tests under AC conditions.Large amplitude, fast ground current transients normally occur as thedevice outputs discharge the load capacitances. These transients flowingthrough the parasitic inductance between the device ground pinand the test system ground can create significant reductions in observableinput noise immunity.4. Output levels are measured at 1.5V reference levels.5. Transition is measured at steady state HIGH level - 500 m V orsteady state LOW level + 500 mV on the output from the 1.5V levelon inputs with load shown in Figure J b.3-7

Typical DC and AC CharacteristicstJ.::cwN::i

~ CY7C225~~~~~UcrOR=======================================================================Device ProgrammingOverview:There is a programmable function contained in the 7C225CMOS 512 x 8 Registered PROM; the 512 x 8 array. All ofthe programming elements are "EPROM" cells, and are inan erased state when the device is shipped.The 512 x 8 array uses a differential memory cell, withdifferential sensing techniques. In the erased state the cellcontains neither a one nor a zero. The erased state of thisarray may be verified by using the "BLANK CHECKONES" and "BLANK CHECK ZEROS" function, seeTable 3.DC Programming Parameters TA = 25°CTable 1Parameter Description Min. Max. UnitsVpp[1] Programming Voltage 13.0 14.0 VVccp Supply Voltage 4.75 5.25 VVIHP Input High Voltage 3.0 VVILP Input Low Voltage 0.4 VVOH[2] Output High Voltage 2.4 VVOL[2] Output Low Voltage 0.4 VIpp Programming Supply Current 50 rnAAC Programming Parameters TA = 25°CTable 2Parameter Description Min. Max. Unitstpp Programming Pulse Width 100 10,000 J.LstAS Address Setup Time 1.0 J.LstDS Data Setup Time 1.0 J.LstAH Address Hold Time 1.0 J.LStDH Data Hold Time 1.0 J.LstR, tF[3] Vpp Rise and Fall Time 50 nstVD Delay to Verify 1.0 J.Lstvp Verify Pulse Width 2.0 J.LstDV Verify Data Valid 1.0 J.LstDZ Verify HIGH to High Z 1.0 J.LsNotes:1. V ccp must be applied prior to Vpp. 3. Measured 10% and 90% points.2. During verify operation.II3-9

~ CY7C225~~~NDUcroR =====================================================================Mode SelectionModeRead[2,3]Output Disable£5]Output DisableCLEARPRESETProgram [4]Program Verify[4]Program Inhibit[4]Intelligent Program[4]Blank Check Ones[4]Blank Check Zeros[4]Read or Output DisableOtherCPPGMPin (18)XXXXXVILPVIHPVIHPVILPVppVppNotes:1. X = Don't care but not to exceed Vpp.2. During read operation, the output latches are loaded on a "0" to "1"transition ofCP.3. Pin 19 must be LOW prior to the "0" to "I" transition on CP (18)that loads the register.Table 3ESVFY(19)VILVIHXVILVILVIHPVILPVIHPVIHPVILPVIHPPin Function[t]CLR E PSOutputsVpp E PS (9-11,13-17)(20) (21) (22)VIH VIL VIH Data OutVIH X VIH HighZVIH VIH VIH HighZVIL VIL VIH ZerosVIH VIL VIL OnesVpp VIHP VIHP Data InVpp VIHP VIHP Data OutVpp VIHP VIHP HighZVpp VIHP VIHP Data InVILP VILP VIHP OnesVILP VILP VIHP Zeros4. During programming and verification, all unspecified pins to be atVILP·5. Pin 19 must be HIGH prior to the "0" to "I" transition on CP (18)that loads the register.A7VeeA6A8As ~A4A3A2A1EAo 07Do 0 601 Os0 2 04Vss 03VPP(CLR)VFY (Es)PGM (CP)Figure 3. Programming Pinouts0020-8The CY7C225 programming algorithm allows significantlyfaster programming than the "worst case" specification of10 msec.Typical programming time for a byte is less than 2.5 msec.The use of EPROM cells allows factory testing of programmedcells, measurement of data retention and erasureto ensure reliable data retention and functional performance.A flowchart of the algorithm is shown in Figure 4.The algorithm utilizes two different pulse types: initial andoverprogram. The duration of the PG M pulse (tpp) is 0.1msec which will then be followed by a longer overprogrampulse of 24 (0.1) (X) msec. X is an iteration counter and isequal to the NUMBER of the initial 0.1 msec pulses appliedbefore verification occurs. Up to four 0.1 msec pulsesare provided before the overprogram pulse is applied.The entire sequence of program pulses and byte verificationsis performed at V ccp = 5.0V. When all bytes havebeen programmed all bytes should be compared (Readmode) to original data with V cc = 5.0V.3-10

STARTVccp K S.OV. Vpp = 13.SVPROGRAM ONE PULSEOF 0.1 msecIIYESFAILPROGRAM ONE PULSEOF 24 (0.1) (X) msecDEVICE BADREAD ALL BYTES?Vee =5.0VFAILt----.....'"-----..Figure 4. Programming Flowchart0020-93-11

~ CY7C225~~~NDUcroR ================================================================~~Programming Sequence 512 x 8 ArrayPower the device for normal read mode operation with pin18,19,20 and 21 at VIH. Per Figure 5 take pin 20 to Vpp.The device is now in the program inhibit mode of operationwith the output lines in a high impedance state; see Figure5. Again per Figure 5 address, program, and verify onebyte of data. Repeat this for each location to be programmed.If the brute force programming method is used, the pulsewidth of the program pulse should be 10 ms, and eachlocation is programmed with a single pulse. Any locationthat fails to verify causes the device to be rejected.If the intelligent programming technique is used, the programpulse width should be 100 JLs. Each location is ultimatelyprogrammed and verified until it verifies correctlyup to and including 4 times. When the location verifies, oneadditional programming pulse should be applied of duration24X the sum ofthe previous programming pulses beforeadvancing to the next address to repeat the process.Blank CheckA virgin device contains neither one's nor zero's because ofthe differential cell used for high speed. To verify that aPROM is unprogrammed, use the two blank check modesprovided in Table 3. In both of these modes, address andread locations 0 thru 511. A device is considered virgin ifall locations are respectively "l's" and "O's" when addressedin the "BLANK ONES AND ZEROS" modes.Because a virgin device contains neither ones nor zeros, itis necessary to program both one's and zero's. It is recommendedthat all locations be programmed to ensure thatambiguous states do not exist.PROGRAM1------PROGRAM----~I4_---VERIFY ___ ",,*o--_OT_H~ER ~BYTES_____VllP - - - I C _.VIHP ~:~RESS ____ "" I"_~ __ T-" __ A_D_D_R_ES_S_S_TA_B_L_E~I-________ --'I __ ~VllP - --Vpp---DATA -------(PROGRAMMINGVOLTAGE (PIN 20)~--~--~J~-----------~Ir-------~----~------------~)~-----------Figure 5. PROM Programming Waveforms0020-103-12

~ CY7C225~~~NDUcrOR ==================================================================~Ordering InformationSpeednsOrdering Package OperatingCode Type RangetSA teo25 12 CY7C225-25PC P13 CommercialCY7C225-250C 014CY7C225-25LC L6430 15 CY7C225-30PC P13 CommercialCY7C225-300C 014CY7C225-30LC L64CY7C225-300MB 014 MilitaryCY7C225-30LMB L6435 20 CY7C225-350MB 014 MilitaryCY7C225-35LMB L6440 25 CY7C225-40PC P13 CommercialCY7C225-400C 014CY7C225-40LC L64CY7C225-400MB 014 MilitaryCY7C225-40LMB L643-13

~ CY7C225~~~DU~~~~~~~~~~~~~~~~~~~~~~~~~~~====~====MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIR 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstSA 7,8,9,10,11tHA 7,8,9,10,11teo 7,8,9,10,11tDP 7,8,9,10,11tRP 7,8,9,10,11Document #: 38-00002-B3-14

Features• CMOS for optimumspeed/power• High speed- 25 ns max set-up- 12 ns clock to output• Low power- 495 mW (commercial)- 660 mW (military)• Synchronous and asynchronousoutput enables• On-chip edge-triggered registers• Programmable asynchronousregister (lNIT)• EPROM technology, 100%programmable• Slim, 300 mil, 24 pin plastic orhermetic DIP or 28 pin LCCLogic Block DiagramCYPRESSSEMICONDUCTOR• 5V ± 10% Vee, commercial andmilitary• TIL compatible I/O• Direct replacement for bipolarPROMs• Capable of withstanding greaterthan 1500V static dischargeProduct CharacteristicsThe CY7C235 is a high performance1024 word by 8 bit electrically ProgrammableRead Only Memory packagedin a slim 300 mil plastic or hermeticDIP or 28-pin Leadless Chip carrier.The memory cells utilize provenEPROM floating gate technology andbyte-wide intelligent programming algorithms.The CY7C235 replaces bipolar devicesand offers the advantages of lowerCY7C2351024 X 8 Registered PROMpower, superior performance and highprogramming yield. The EPROM cellrequires only 13.5V for the supervoltageand low current requirements allowfor gang programming. The EPROMcells allow for each memory location tobe tested 100%, as each location iswritten into, erased, and repeatedlyexercised prior to encapsulation. EachPROM is also tested for AC performanceto guarantee that after customerprogramming the product will meetAC specification limits.The CY7C235 has an asynchronousinitialize function (INIT). This functionacts as a 1025th 8-bit word loadedinto the on-chip register. It is user programmablewith any desired word ormay be used as a PRESET or CLEARfunction on the outputs.Pin ConfigurationsIIINIT----~~------------------------~64 .128PROGRAMMA8LEARRAY0005-2cp----~_t~~----------------------------~ES-----~01000005-14 3 2111282726A4 5 '-' 25A3 6 24A2 7 23AI 8 22Ao 9 21NC 10 20INITEsCPNC°70 0 11 19 Os12131415161718--NOO ~~Il)00%2000~ 0005-12Selection GuideMaximum Set-up Time (ns)Maximum Clock to Output (ns)Maximum Operating I CommercialCurrent (mA)MilitaryI7C23S-2S2512907C23S-30 7C23S-4030 4015 2090 90120 1203-15

~ CY7C235~~~NDUcrOR ~~~~~=============================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 24 to Pin 12 for DIP) ............. -0.5Vto +7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to +7.0VStatic Discharge Volume ..................... > 1500V(Per MIL-STD-883 Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°C to + 70°C 5V ±1O%DC Program Voltage(Pins 7, 18,20 for DIP) ........................ 14.0VElectrical Characteristics Over Operating Rangel7]VeeMilitary [6] - 55°C to + 125°C 5V ± 10%Parameters Description Test Conditions Min. Max. UnitsVOHVOLVIHVILOutput HIGH VoltageOutput LOW VoltageInput HIGH LevelInput LOW LevelVee = Min., IOH = - 4.0 rnAVIN = VIH or VILVee = Min.,loL = 16 rnAVIN = VIH or VILGuaranteed Input Logical HIGHVoltage for All Inputs[2]Guaranteed Input Logical LOWVoltage for All Inputs[2]2.4 V0.4 V2.0 V0.8 VIIX Input Leakage Current GND:5: VIN:5: Vee -10 +10 p,AVCDInput Clamp DiodeVoltageNote 1loz Output Leakage Current GND :5: Vo :5: Vee Output Disabled[4] -40 +40 p,AOutput Short CircuitlosVee = Max., VOUT = 0.OV[3] -20 -90 rnACurrentGND :5: VIN:5: Vce lCommercial 90Icc Power Supply Current rnAVec = Max.1Military 120Capacitance [5]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C,f = 1 MHz 5COUT Output Capacitance VCC = 5.0V 8Notes:1. The CMOS process does not provide a clamp diode. However, theCY7C23S is insensitive to - 3V dc input levels and - SV undershootpulses ofless than 10 ns (measured at SO% point).2. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment (see Notes onTesting).3. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.4. For devices using the synchronous enable, the device must be clockedafter applying these voltages to perform this measurement.S. Tested initially and after any design or process changes that mayaffect these parameters.6. TA is the "instant on" case temperature.7. See the last page of this specification for Group A subgroup testinginformation.pF3-16

IfJ:':z-CY7C235~~~NDUcrOR======================================================================~Switching Characteristics Over Operating Rangd4, 8]7C235-25 7C235-30 7C235-40Parameters Description UnitsMin. Max. Min. Max. Min. Max.tSAtHAteotpwctSEstHEStmtRItPWIteasAddress Setup to Clock HIGHAddress Hold from Clock HIGHClock HIGH to Valid OutputClock Pulse WidthES Setup to Clock HIGHES Hold from Clock HIGHDelay from INIT to Valid OutputINIT Recovery to Clock HIGHINIT Pulse WidthInactive to Valid Output from Clock HIGH[I]tHZC Inactive Output from Clock HIGH[l, 3]tDOEValid Output from E LOW[2]tHZE Inactive Output from E HIGH[2, 3]Notes:I. Applies only when the synchronous (Es) function is used.2. Applies only when the asynchronous (E) function is used.3. Transition is measured at steady state High level - 500 m V or steadystate Low level + 500 m V on the output from the 1.5V level on theinput with loads shown in Figure lb.AC Test Loads and Waveforms [5,6,7]R1 250 nR1 250 n5 V Q----.JVV\r--. 5Vo-------~~~~OUTPUT Q----_----t OUTPUT 0-----..-------....Equivalent to:50 pF '::7 HINCLUDINGI JIG AND-= SCOPE -=Figure 18I5 pF R2167HINCLUDING25 30 40 ns0 0 0 ns12 15 20 ns12 15 20 ns10 10 15 ns5 5 5 ns25 25 35 ns20 20 20 ns20 20 25 ns20 20 25 ns20 20 25 ns20 20 25 ns20 20 25 ns4. Tests are performed with rise and fall times of 5 ns or less.5. See Figure la for all switching characteristics except tHZ.6. See Figure 1 b for tHZ.7. All device test loads should be located within 2" of device outputs.8. See the last page of this specification for Group A subgroup testinginformation.ALL INPUT PULSES3.0V-----...P .... ---~GND.;5 ns

~ CY7C235~~~UcroR =====================================================================Functional Description (Continued)Regardless of the condition of E, the outputs will go to theOFF or high impedance state upon the next positive clockedge after the synchronous enable (Es) input is switched toa HIGH level. If the synchronous enable pin is switched toa logic LOW, the subsequent positive clock edge will returnthe output to the active state ifE is LOW. Following apositive clock edge, the address and synchronous enableinputs are free to change since no change in the output willoccur until the next low to high transition of the clock.This unique feature allows the CY7C235 decoders andsense amplifiers to access the next location while previouslyaddressed data remains stable on the outputs.System timing is simplified in that the on-chip edge triggeredregister allows the PROM clock to be derived directlyfrom the system clock without introducing race conditions.The on-chip register timing requirements are similarto those of discrete registers available in the market.The CY7C235 has an asynchronous initialize input (INIT).The initialize function is useful during power-up and timeoutsequences and can facilitate implementation of othersophisticated functions such as a built-in "jump start" address.When activated the initialize control input causes thecontents of a user programmed 1025th 8-bit word to beloaded into the on-chip register. Each bit is programmableSwitching Waveformsand the initialize function can be used to load any desiredcombination of"I"s and "O"s into the register. In the unprogrammedstate, activating INIT will generate a registerCLEAR (all outputs LOW). If all the bits of the initializeword are programmed, activating INIT performs a registerPRESET (all outputs HIGH).Applying a LOW to the INIT input causes an immediateload of the programmed initialize word into the master andslave flip-flops of the register, independent of all other inputs,including the clock (CP). The initialize data will appearat the device outputs after the outputs are enabled bybringing the asynchronous enable (E) LOW.When power is applied the (internal) synchronous enableflip-flop will be in a state such that the outputs will be inthe high impedance state. In order to enable the outputs, aclock must occur and the ES input pin must be LOW atleast a setup time prior to the clock LOW to HIGH transition.The E input may then be used to enable the outputs.When the asynchronous initialize input, INIT, is LOW,the data in the initialize byte will be asynchronously loadedinto the output register. It will not, however, appear on theoutput pins until they are enabled, as described in the precedingparagraph.AO-Al0 __________________________________ ~---J~~~----+----J~~~~~~~-------------------CPNotes on TestingIncoming test procedures on these devices should be carefully planned,taking into account the high performance and output drive capabilities ofthe parts. The following notes may be useful.1. Ensure that adequate decoupling capacitance is employed across thedevice Vee and ground terminals. Multiple capacitors are recommended,including a 0.1 ,..,F or larger capacitor and a 0.01 ,..,F orsmaller capacitor placed as close to the device terminals as possible.Inadequate decoupling may result in large variations of power supplyvoltage, creating erroneous function or transient performance failures.2. Do not leave any inputs disconnected (floating) during any tests.3. Do not attempt to perform threshold tests under AC conditions.Large amplitude, fast ground current transients normally occur as thedevice outputs discharge the load capacitances. These transients flowingthrough the parasitic inductance between the device ground pinand the test system ground can create significant reductions in observableinput noise immunity.4. Output levels are measured at l.SV reference levels.S. Transition is measured at steady state HIGH level - SOO m V orsteady state LOW level + SOO mV on the output from the l.SV levelon inputs with load shown in Figure 1 h.3-18

~ CY7C235~~~~~~~~~~~~~~~~~~~~~~~~====~==~~~~~==~==~~==Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.61.41.21.00.8VV//TA" 25'Cf-MAX.O. 6 4.0 4.5 5.0 5.5 6.011o.WN:::ic(:Ea:iNORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.2...-----.....-------.0.80L.-____ -'--_____...J-55 25 125w:Ei=5 1.4~:;)o 1.2~:00:-I~ 1.0wN:::ic( 0.8:Ea:iNORMALIZED CLOCK TO OUTPUTTIMEvs. Vee1.60.64.0~"- ~--- r---TA j25'C4.5 5.0 5.56.0SUPPLY VOLTAGE (VIAMBIENT TEMPERATURE rCISUPPL Y VOLTAGE (VIw:!;t=I­ :;)CLI­ :;)o:::00:9NORMALIZED CLOCK TO OUTPUTTIME vs. TEMPERATURE1.6,.-----,-------...,1.41-----+------_11.2 t-----+----~~_fCJ 1.0 I-----:::;~~----_IowN~ 0.81-----+-------1:EIE:~0.6 '------.......-----~-55 25125w:Ei= 1.0Q.~IIIo 0.8wN:::i~a: 0.6iNORMALIZED SETUP TIMEvs. SUPPLY VOLTAGE1.2~ ~~'"0.44.0 4.5 5.0TA i 2S'C5.5 6.0Q.:;)I-Wen0wN:::ic(:Ea:0zNORMALIZED SETUP TIMEvs. TEMPERATURE1.61.41.21.0 ....-0.80.6 -55 25-125IIAMBI ENT TEMPERA TUR E ('CISUPPL Y VOLTAGE (VIAMBIENT TEMPERATURE ('CI60OUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE30.0TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADINGOUTPUT SINK CURRENTvs. OUTPUT VOLTAGE175C(.§I- Zwa:a::;)CJwCJa::;)0enI- :;)CLI- :;)05040302010~"-~"'"o o~1.0 2.0 3.0 4.0OUTPUT VOLTAGE (VI25.0] 20.0«~ 15.0~wo 10.05.00.0.IV//v/~TA = 25'CVee" 4.5 VVo 200 400 600 800 1000CAPACITANCE (pFIC(.§I-zwa:a::;)CJ:00:ziiiI- :;)CLI- :;)01501251007550/2517o0.0// V17~ ~Vee =5.0 VTA = 25'C1.0 2.0 3.0 4.0OUTPUT VOLTAGE (VI0005-73-19

~ CY7C235~~~~UcrOR====================================================================~=Device ProgrammingOverview:There are two independent programmable functions containedin the 7C235 CMOS lK x 8 Registered PROM; thelK x 8 array, and the INITIAL BYTE. All of the programmingelements are "EPROM" cells, and are in anerased state when the device is shipped. The erased statefor the "INITIAL BYTE" is all "O's" or "LOW". The"INITIAL BYTE" may be accessed operationally throughDC Programming Parameters TA = 25°CParameterVpp[llVccpVIHPVILPVOH[2]VOL [2]DescriptionProgramming VoltageSupply VoltageInput High VoltageInput Low VoltageOutput High VoltageOutput Low VoltageTable 1the use of the initialize function. The 1 K x 8 array uses adifferential memory cell, with differential sensing techniques.In the erased state the cell contains neither a onenor a zero. The erased state of this array may be verified byusing the "BLANK CHECK ONES" and "BLANKCHECK ZEROS" function, see Table 3.Min. Max. Units13.0 14.0 V4.75 5.25 V3.0 V0.4 V2.4 V0.4 VIpp Programming Supply Current 50 rnAAC Programming Parameters TA = 25°CTable 2Parameter Description Min. Max. Unitstpp Programming Pulse Width 100 10,000 J.LstAS Address Setup Time 1.0 J.LstDS Data Setup Time 1.0 J.LstAH Address Hold Time 1.0 J.LstDH Data Hold Time 1.0 J.LstR,tF[3] Vpp Rise and Fall Time 1.0 J.LstVD Delay to Verify 1.0 J.Lstvp Verify Pulse Width 2.0 J.LstDV Verify Data Valid 1.0 J.LstDZ Verify HIGH to High Z 1.0 J.LsNotes:1. V ccp must be applied prior to V pp.2. During verify operation.3. Measured 10% and 90% points.3-20

~ CY7C235~~~UcrOR=====================================================================Mode SelectionRead or Output Disable A2 CPMode Other A2 PGM(DIP) Pin (6) (18)Read[2,3] X XOutput Disable[5] X XOutput Disable X XInitialize [6] X XProgram [1,4] X VILPProgram Verify[l,4] X VIHPProgram Inhibit[I,4] X VIHPIntelligent Program[l,4] X VILPProgram Initial Byte[4] VILP VILPBlank Check Ones[l,4] X VppBlank Check Zeros[I,4] X VppNotes:1. X = Don't care but not to exceed Vpp.2. During read operation, the output latches are loaded on a "0" to "1"transition ofCP.3. Pin 19 must be LOW prior to the "0" to "I" transition on CP (18)that loads the register.Table 3Pin FunctionEs INIT E At OutputsVFY Vpp E At (9-11,13-17)(19) (20) (21) (7)DIPVIL VIH VIL X Data OutVIH VIH X X HighZX VIH VIH X HighZX VIL VIL X 1025th wordVIHP Vpp VIHP X Data InVILP Vpp VIHP X Data OutVIHP Vpp VIHP X HighZVIHP Vpp VIHP X Data InVIHP Vpp VIHP Vpp Data InVILP VILP VILP X OnesVIHP VILP VILP X Zeros4. During programming and verification, all unspecified pins to be atVILP·5. Pin 19 must be HIGH prior to the "0" to "1" transition on CP (18)that loads the register.6. LOW to HIGH clock transition required to enable outputs.A7veeA6AsA5AsA4EA3Vpp (lNIT)A2VFY (Es)AlPGM (CP)Ao 07Do 06DI 05D2 04Vss 03Figure 3. Programming Pinouts0005-8The CY7C235 programming algorithm allows significantlyfaster programming than the "worst case" specification oflOmsec.Typical programming time for a byte is less than 2.5 msec.The use of EPROM cells allows factory testing of programmedcells, measurement of data retention and erasureto ensure reliable data retention and functional performance.A flowchart of the algorithm is shown in Figure 4.The algorithm utilizes two different pulse types: initial andoverprogram. The duration of the PGM pulse (tpp) is 0.1msec which will then be followed by a longer overprogrampulse of 24 (0.1) (X) msec. X is an iteration counter and isequal to the NUMBER of the initial 0.1 msec pulses appliedbefore verification occurs. Up to four 0.1 msec pulsesare provided before the overprogram pulse is applied.The entire sequence of program pulses and byte verificationsis performed at Veep = S.OV. When all bytes havebeen programmed all bytes should be compared (Readmode) to original data with Vec = 5.0V.3-21

~ CiPRFSSCY7C235~~I~U~======~==================~====================================STARTVCCf' - 5.0V. Vpp = 13.5VPROGRAM ONE PULSEOF 0.1 msecYESFAILPROGRAM ONE PULSEOF 24 (0.11 (XI msecDEVICE BADREAD ALL BYTES? FAILVee =5.0V 1------+1 10-. ___..1Figure 4. Programming Flowchart0005-93-22

CY7C235Programming Sequence lK x 8 ArrayPower the device for normal read mode operation with pin18,19,20 and 21 at VIH. Per Figure 6 take pin 20 to Vpp.The device is now in the program inhibit mode of operationwith the output lines in a high impedance state; see Figures5 and 6. Again per Figure 6 address program and verifyone byte of data. Repeat this for each location to be programmed.If the brute force programming method is used, the pulsewidth of the program pulse should be 10 ms, and eachlocation is programmed with a single pulse. Any locationthat fails to verify causes the device to be rejected.If the intelligent programming technique is used, the programpulse width should be 100 IJ-S. Each location is ultimatelyprogrammed and verified until it verifies correctlyup to and including 4 times. When the location verifies, oneadditional programming pulse should be applied of duration24X the sum of the previous programming pulses beforeadvancing to the next address to repeat the process.1+----PROGRAM-------., .....---VERIFY___.....__O_TH ......PROGRAMER ~BYTESVIHP -A:~RESS ___......., I':-~~--::"'I'""" __ A_D_D_RE_S_S S_T_AB_L_E -+________-'11__---:\VILP ---VIHP - --VllP ---Vpp - --DATA -----....(PROGRAMMINGVOLTAGE (PIN 20, DIP)VIHP - --~-~--~ j~-------~VILP ---VIHP - --VILP---PGMVILP ---0005-10Figure 5. PROM Programming WaveformsVIHP---A2~---------------PROGRAM--------------~1_---Vpp---VIHP - --VILP ---VIHP --­VILP ---Vpp--­DATAPROGRAMMINGVOLTAGE (PIN 20, DIP)~---------------tAH----------------~VIHP---VILP ---VIHP---VILP---PGM0005-11Figure 6. Initial Byte Programming Waveforms3-23

~ CY7C235~~~NDUcroR =====================================================================Programming the Initial ByteThe CY7C235 registered PROM has a 1025th byte of dataused to initialize the value of the register. This initial byteis value "0" when the part is received. If the user desires tohave a value other than "0" for register initialization, thismust be programmed into the 1025th byte. This byte isprogrammed in a similar manner to the 1024 normal bytesin the array except for two considerations. First, since all ofthe normal addresses of the part are used up, a super voltagewill be used to create additional effective addresses.The actual address has Vpp on Al pin 7, and VILP on A2,pin 6, per Table 3. The programming and verification of"INITIAL BYTE" is accomplished operationally by performingan initialize function.Blank CheckA virgin device contains neither one's nor zero's because ofthe differential cell used for high speed. To verify that aPROM is unprogrammed, use the two blank check modesprovided in Table 3. In both of these modes, address andread locations 0 thru 1023. A device is considered virgin ifall locations are respectively" 1 's" and "O's" when addressesin the "BLANK ONES AND ZEROS" modes.Because a virgin device contains neither ones nor zeros, itis necessary to program both one's and zero's. It is recommendedthat all locations be programmed to ensure thatambiguous states do not exist.BitMap DataProgrammer AddressRAM DataDecimal Hex Contents0 0 Data• • • •1023 3FF Data1024 400 Init ByteOrdering InformationSpeednstSAteoOrdering Package OperatingCode Type Range25 12 CY7C235-25PC P13 CommercialCY7C235-25DC D1430 15 CY7C235-30PC Pl3CY7C23~-30DC D14CY7C235-30JC J64CY7C235-30DMB D14 MilitaryCY7C235-30LMB L6440 20 CY7C235-40PC Pl3 CommercialCY7C235-40DC D14CY7C235-40DMB D14 MilitaryCY7C235-40LMB L643-24

~ CY7C235~~~ucr~==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstSA 7,8,9,10,11tHA 7,8,9,10,11teo 7,8,9,10,11Document #: 38-00003-B3-25

CY7C245CYPRESSSEMICONDUCTOR Reprogrammable 2048 X 8Registered PROMFeatures• Windowed for reprogrammability• CMOS for optimumspeed/power• High speed- 25 ns max set-up- 12 ns clock to output• Low power- 330 mW (commercial) for-35 ns, -45 ns- 660 mW (military)• Programmable synchronous orasynchronous output enable• On-chip edge-triggered registers• Programmable asynchronousregister (lNIT)• EPROM technology, 100%programmable• Slim, 300 mil, 24 pin plastic orhermetic DIP• 5V ± 10% Vee, commercial andmilitary• TTL compatible I/O• Direct replacement for bipolarPROMs• Capable of withstanding greaterthan 2000V static dischargeLogic Block DiagramPin ConfigurationsINIT----I >0--------------,ROWDECODER1 OF 128128 x 128PROGRAMMABLEARRAYA7AsA5A4A3A2A1Ao000102GNDVCCAsAgA10INITE/EsCP0706050403COLUMN t---------.JDECODER1 OF 16 t------------'010016-2000016-1... C'oIC U tot) ..... It)0 Ozzooo(!)0016-13Selection GuideMaximum Setup Time (ns)Maximum Clock to Output (ns)Maximum Operating STnCurrent (mA)L7C245-252512Commercial 90MilitaryCommercial7C245-35 7C245-4535 4515 2590 90120 12060 603-26

~p£ssCY7C245.nEMICONDUcrOR ====================================================================Product CharacteristicsThe CY7C245 is a high performance 2048 word by 8 bitelectrically Programmable Read Only Memory packagedin a slim 300 mil plastic or hermetic DIP. The ceramicpackage may be equipped with an erasure window; whenexposed to UV light the PROM is erased and can then bereprogrammed. The memory cells utilize proven EPROMfloating gate technology and byte-wide intelligent programmingalgorithms.The CY7C245 replaces bipolar devices and offers the advantagesof lower power, reprogrammability, superior performanceand high programming yield. The EPROM cellrequires only 13.5V for the supervoltage and low currentrequirements allow for gang programming. The EPROMcells allow for each memory location to be tested 100%, aseach location is written into, erased, and repeatedly exercizedprior to encapsulation. Each PROM is also tested forAC performance to guarantee that after customer programmingthe product will meet AC specification limits.The CY7C245 has an asynchronous initialize function(INIT). This function acts as a 2049th 8-bit word loadedinto the on-chip register. It is user programmable with anydesired word or may be used as a PRESET or CLEARfunction on the outputs.Electrical Characteristics Over Operating Rangd6]Parameters Description Test ConditionsVOHVOLVIRVILOutput HIGH VoltageOutput LOW VoltageInput HIGH LevelInput LOW LevelVec = Min.,IOH = -4.0mAVIN = VIR or VILVcc = Min.,IOL = 16 mAVIN = VIR or VILGuaranteed Input Lo~ical HIGHVoltage for All Inputs 1]Guaranteed Input Lo~ical LOWVoltage for All Inputs 1]Maximum Ratings(Above which the useful life may be impaired. For userguidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VDC Program Voltage (Pins 7, 18,20) ............. 14.0VUV Erasure .......................... 7258 Wsec/cm2Static Discharge Voltage ..................... >2001V(Per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureVeeCommercial O°C to + 70°C 5V ± 10%Military [7] - 5SOC to + 125°C 5V ±1O%7C245L·35, 45 7C245·25 7C245·35, 45Min. Max. Min. Max. Min. Max.Units2.4 2.4 2.4 V0.4 0.4 0.4 V2.0 Vec 2.0 Vec 2.0 Vee V0.8 0.8 0.8 VIIX Input Leakage Current GND s VIN s Vcc -10 +10 -10 +10 -10 +10 p,AVeDlozlosIccCapacitance [4]ParametersCINInput Clamp DiodeVoltageOutput Leakage CurrentOutput Short CircuitCurrentPower Supply CurrentNote 5 Note 5GND s Vo S VncOutput Disabled[3-40 +40 -40 +40 -40 +40 p,AVee = Max., VOUT = 0.OV[2] -20 -90 -20 -90 -20 -90 mAGND S VIN s Vec I Commercial 60 90 90mAVee = Max.I Military 120DescriptionInput CapacitanceCOUTOutput CapacitanceNotes:1. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment (see Notes onTesting).2. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.3. For devices using the synchronous enable, the device must be clockedafter applying these voltages to perform this measurement.Test Conditions Max. UnitsTA = 25°C, f = 1 MHz 5Vec = 5.0V84. Tested initially and after any design or process changes that mayaffect these parameters.5. The CMOS process does not provide a clamp diode. However, theeY7e245 is insensitive to - 3V dc input levels and - 5V undershootpulses ofless than 10 ns (measured at 50% point).6. See the last page of this specification for Group A subgroup testinginformation.7. TA is the "instant on" case temperature.pF3-27

~ CY7C245~~~ND~=====================================================================Switching Characteristics Over Operating Range[8]ParameterstSAtHAteotpwctSEgtHEStmtRItPWIteosDescriptionAddress Setup to Clock HIGHAddress Hold from Clock HIGHClock HIGH to Valid OutputClock Pulse WidthEs Setup to Clock HIGHES Hold from Clock HIGHDelay from INIT to Valid OutputINIT Recovery to Clock HIGHINIT Pulse WidthValid Output fromClock HIGH[I]tHZC Ioactive Output from Clock HIGH[l, 3]tOOEtHZEValid Output from E LOW[2]Inactive Output fromEHIGH[2,3]Notes:I. Applies only when the synchronous (Es) function is used.2. Applies only when the asynchronous (E) function is used.3. Transition is measured at steady state High level - 500 m V or steadystate Low level + 500 m V on the output from the 1.5V level on theinput with loads shown in Figure 1 b.4. Tests are performed with rise and fall times of 5 ns or less.Min.2501512515157C245-25 7C245-35 7C245-45Max. Min. Max. Min. Max.Units35 45 os0 0 os12 15 25 os20 20 os15 15 os5 5 os20 20 35 os20 20 os20 25 os15 20 30 os15 20 30 os15 20 30 os15 20 30 os5. See Figure 1a for all switching characteristics except tHZ.6. See Figure 1 b for tHZ.7. All device test loads should be located within 2" of device outputs.8. See the last page of this specification for Group A subgroup testinginformation.AC Test Loads and Waveforms [5, 6, 7]R125012R1250n5 v o-----'\M--, 5 v o-----"M--.OUTPUTo--__ ---i60PFR216711INCLUDINGrJIG ANDEquivalent to:-= SCOPE -=Figure laTHEVENIN EQUIVALENTOUTPUT Q--........ ---iI5pFR2167nINCLUDING_ JIG AND _- SCOPE -0016-3Figure lb100nOUTPUT ~2.0V 0016-4Functional DescriptionThe CY7C245 is a CMOS electrically Programmable ReadOnly Memory organized as 2048 words x 8-bits and is apin-for-pin replacement for bipolar TTL fusible linkPROMs. The CY7C245 incorporates aD-type, masterslaveregister on chip, reducing the cost and size of pipelinedmicroprogrammed systems and applications whereaccessed PROM data is stored temporarily in a register.Additional flexibility is provided with a programmablesynchronous (Es) or asynchronous (E) output enable andasynchronous initialization (INIT).Upon power-up the state of the outputs will depend on theprogrammed state of the enable function (Es or E). If thesynchronous enable (Es) has been programmed, the registerwill be in the set condition causing the outputsALL INPUT PULSES3.0V-----jo----""""'ILGND.. Sns .;;5 nsFigure 20016-5(00-07) to be in the OFF or high impedance state. If theasynchronous enable (E) is being used, the outputs willcome up in the OFF or high impedance state only iftheenable (E) input is at a HIGH logic level. Data is read byapplying the memory location to the address inputs(Ao-AlO) and a logic LOW to the enable input. The storeddata is accessed and loaded into the master flip-flops of thedata register during the address set-up time. At the nextLOW-to-HIGH transition of the clock (CP), data is transferredto the slave flip-flops, which drive the output buffers,and the accessed data will appear at the outputs(00-0 7).If the asynchronous enable (E) is being used, the outputsmay be disabled at any time by switching the enable to a3-28

Functional Description (Continued)logic HIGH, and may be returned to the active state byswitching the enable to a logic LOW.If the synchronous enable (Es) is being used, the outputswill go to the OFF or high impedance state upon the nextpo~itive clock edge after the synchronous enable input issWltched to a HIGH level. If the synchronous enable pin isswitched to a logic LOW, the subsequent positive clockedge will return the output to the active state. Following apositive clock edge, the address and synchronous enableinputs are free to change since no change in the output willoccur until the next low to high transition of the clock.This unique feature allows the CY7C245 decoders andsense amplifiers to access the next location while previouslyaddressed data remains stable on the outputs.System timing is simplified in that the on-chip edge triggeredregister allows the PROM clock to be derived directlyfrom the system clock without introducing race conditions.The on-chip register timing requirements are similarto those of discrete registers available in the market.The CY7C245 has an asynchronous initialize input (INIT).The initialize function is useful during power-up and timeoutsequences and can facilitate implementation of othersophisticated functions such as a built-in "jump start" address.When activated the initialize control input causes thecontents of a user programmed 2049th 8-bit word to beloaded into the on-chip register. Each bit is programmableand the initialize function can be used to load any desiredcombination of"l"s and "O"s into the register. In the unprogrammedstate, activating INIT will generate a registerCLEAR (all outputs LOW). If all the bits of the initializeword are programmed, activating INIT performs a registerPRESET (all outputs HIGH).Applying a LOW to the INIT input causes an immediateload of the programmed initialize word into the master andslave flip-flops of the register, independent of all other inputs,including the clock (CP). The initialize data will appearat the device outputs after the outputs are enabled bybringing the asynchronous enable (E) LOW.Switching WaveformsAO-Al0 ------------------------------------t-----~~~----_1----~~~~~~~cr---------------------EsCPNotes on TestingInc?mi!lg test procedure~ on these devices should be carefully planned,takmg mto account the hIgh performance and output drive capabilities ofthe parts. The following notes may be useful.1. Ens.UTe that adequate decoupling capacitance is employed across thedeVIce Vee and ground terminals. Multiple capacitors are recommended,including a 0.1 p,F or larger capacitor and a 0.01 p,F orsmaller capacitor placed as close to the device terminals as possible.Inadequate decoupling may result in large variations of power supplyvoltage, creating erroneous function or transient performance failures.2. Do not leave any inputs disconnected (floating) during any tests.0016-63. Do not attempt to perform threshold tests under AC conditions.Large amplitude, fast ground current transients normally occur as thedevice outputs discharge the load capacitances. These transients flowingthrough the parasitic inductance between the device ground pinand the test system ground can create significant reductions in observableinput noise immunity.4. Output levels are measured at 1.5V reference levels.5. Transition is measured at steady state HIGH level - 500 m V orsteady state LOW level + 500 m Von the output from the 1.5V levelon inputs with load shown in Figure 1 h.3-29

Typical DC and AC Characteristicsu.P0IIIN:::i

~ CY7C245~~~~UcrOR;=================================================================Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the 7C245. For this reason, an opaque label should beplaced over the window if the PROM is exposed to sunlightor fluorescent lighting for extended periods of time.The recommended dose for erasure is ultraviolet light witha wavelength of 2537 Angstroms for a minimum dose (UVintensity X exposure time) of25 Wsec/cm2. For an ultravioletlamp with a 12 m W / cm2 power rating the exposuretime would be approximately 30-35 minutes. The 7C245needs to be within 1 inch of the lamp during erasure. Permanentdamage may result if the PROM is exposed to highintensity UV light for an extended period of time. 7258Wsec/cm2 is the recommended maximum dosage.DC Programming Parameters TA = 25°CParameterVppU]VccpVIHPVILPVOH[2]VOL [2]DescriptionProgramming VoltageSupply VoltageInput High VoltageInput Low VoltageOutput High VoltageOutput Low VoltageTable 1Device ProgrammingOVERVIEW:There are three independent programmable functions containedin the 7C245 CMOS 2K x 8 Registered PROM; the2K x 8 array, the initial byte, and the synchronous enablebit. All of the programming elements are "EPROM" cells,and are in an erased state when the device is shipped. Thiserased state manifests itself differently in each case. Theerased state for ENABLE bit is the "ASYNCHRONOUSENABLE" mode. The erased state for the "INITIALBYTE" is all "O's" or "LOW". The "INITIAL BYTE"may be accessed operationally thru the use of the initializefunction. The 2K x 8 array uses a differential memory cell,with differential sensing techniques. In the erased state thecell contains neither a one nor a zero. The erased state ofthis array may be verified by using the "BLANK CHECKONES" and "BLANK CHECK ZEROS" function, seeTable 3.Min. Max. Units13.0 14.0 V4.75 5.25 V3.0 V0.4 V2.4 V0.4 VIpp Programming Supply Current 50 mAAC Programming Parameters TA = 25°CTable 2Parameter Description Min. Max. Unitstpp Programming Pulse Width 100 10,000 ,..,StAS Address Setup Time 1.0 ,..,StDS Data Setup Time 1.0 ,..,StAR Address Hold Time 1.0 ,..,StDR Data Hold Time 1.0 ,..,StR, tF[3] Vpp Rise and Fall Time 1.0 ,..,StVD Delay to Verify 1.0 ,..,Stvp Verify Pulse Width 2.0 ,..,StDv Verify Data Valid 1.0 ,..,StDZ Verify HIGH to High Z 1.0 ,..,SNotes:1. V ccp must be applied prior to Vpp.2. During verify operation.3. Measured 10% and 90% points.3-31

~ CY7C245~~~~~~~~~~~~~==~~====~==~~========~~==~~==~~==~==Mode SelectionModeRead [2,3]Output Disable[5]Read or Output DisableOtherAlAlPin (6)Program [1,4]X VILPProgram Verify[1,4]X VIHPProgram Inhibit[I,4]X VIHPIntelligent Program [1,4]X VILPProgram Synch Enable[4]VIHP VILPProgram Initial Byte[4]VILP VILPNotes:1. X = Don't care but not to exceed Vpp.2. During read operation, the output latches are loaded on a "0" to "1"transition of CPo3. If the registered device is being operated in a synchronous mode, pin19 must be LOW prior to the "0" to "1" transition on CP (18) thatloads the register.A7A6A5A4A3AzAlBitMap DataVecAsAsAo 07Do 060, 05Oz 04Vss 03A,OVpp (iNfi')m(E/E's)PGM(CP)Figure 3. Programming PinoutsXXProgrammerDecimal0016-8Table 3CPPGM(18)XXAddressHex0 0• •2047 7FF2048 8002049 801Control BytePin FunctionE/Es INIT AlOutputsVFY Vpp Al (9-11,13-17)(19) 20 (7)VIL VIH X Data OutVIH VIH X HighZVIHP Vpp X Data InVILP Vpp X Data OutVIHP Vpp X HighZVIHP Vpp X Data InVIHP Vpp Vpp HighZVIHP Vpp Vpp Data In4. During programming and verification, all unspecified pins to be atVILP.5. Ifthe registered device is being operated in a synchronous mode, pin19 must be HIGH prior to the "0" to "1" transition on CP (18) thatloads the register.The CY7C245 programming algorithm allows significantlyfaster programming than the "worst case" specification ofIOmsec.Typical programming time for a byte is less than 2.5 msec.The use of EPROM cells allows factory testing of programmedcells, measurement of data retention and erasureto ensure reliable data retention and functional performance.A flowchart of the algorithm is shown in Figure 4.The algorithm utilizes two different pulse types: initial andoverprogram. The duration of the PGM pulse (tpp) is 0.1msec which will then be followed by a longer overprogrampulse of 24 (0.1) (X) msec. X is an iteration counter and isequal to the NUMBER of the initial 0.1 msec pulses appliedbefore verification occurs. Up to four 0.1 msec pulsesare provided before the overprogram pulse is applied.The entire sequence of program pulses and byte verificationsis performed at V CCP = 5.0V. When all bytes havebeen programmed all bytes should be compared (Readmode) to original data with VCC = 5.0V.RAM DataContentsDATA•DATAINITBYTECONTROL BYTE00 Asynchronous output enable (default state)01 Synchronous output enable3-32

STARTVccp = 5.0V. Vpp = 13.5VPROGRAM ONE PULSEOF 0.1 msecIIDEVICE BADREAD ALL BYTES? FAILVee - 5.0 1----....Figure 4. Programming Flowchart0016-093-33

Programming Sequence 2K x 8 ArrayPower the device for normal read mode operation with pin18,19 and 20 at VIR. Per Figure 5 take pin 20 to Vpp. Thedevice is now in the program inhibit mode of operationwith the output lines in a high impedance state; see Figures5 and 6. Again per Figure 5 address program and verifyone byte of data. Repeat this for each location to be programmed.If the brute force programming method is used, the pulsewidth ofthe program pulse should be 10 ms, and eachlocation is programmed with a single pulse. Any locationthat fails to verify causes the device to be rejected.If the intelligent programming technique is used, the programpulse width should be 100 ILs. Each location is ultimatelyprogrammed and verified until it verifies correctlyup to and including 4 times. When the location verifies, oneadditional programming pulse should be applied of duration24X the sum of the previous programming pulses beforeadvancing to the next address to repeat the process.VIHP - --ADDRESSVILP ---VIHP - --VILP - --Vpp - --DATA -----------00(PROGRAMMINGVOLTAGE (PIN 20)VIHP - --PRoGRAM-----+i~---VERIFY---~I---OT-H .....PROGRAMER ~.ADDRESS STABLE ~.----+----~ )p---------------~VILP - --1r-----~------~----------~5~--------------VILP - --VIHP - --VILP - --Figure 5. PROM Programming Waveforms0016-10~--------------------------PROGRAM-----------------------~VIHP - -- -----~I 1.------A2VILP ---Vpp ---VIHP - --VILP ---VIHP --­VILP ---Vpp--­DATA~------------tAH-------------~PROGRAMMINGVOLTAGE (PIN 20)VIHP ---VllP ---tppVIHP ---VllP - --Figure 6. Initial Byte Programming Waveforms0016-113-34

Programming the Initialization ByteThe CY7C245 registered PROM has a 2049th byte of dataused to initialize the value of the register. This initial byteis value "0" when the part is received. If the user desires tohave a value other than "0" for register initialization, thismust be programmed into the 2049th byte. This byte isprogrammed in a similar manner to the 2048 normal bytesin the array except for two considerations. First, since all ofthe normal addresses of the part are used up, a super voltagewill be used to create additional effective addresses.The actual address has Vpp on Al pin 7, and VILP on A2,pin 6, per Table 3. The programming and verification of"INITIAL BYTE" is accomplished operationally by performingan initialize function.Programming Synchronous EnableThe CY7C245 provides for both a synchronous and asynchronousenable function. The device is delivered in anasynchronous mode of operation and only requires that theuser alter the device if synchronous operation is required.The determination of the option is accomplished thru theuse of an EPROM cell which is programmed only if synchronousoperation is required. As with the INITIAL byte,this function is addressed thru the use of a supervoltage.Per Table 3, Vpp is applied to pin 7 (AI) with pin 6 (A2) atV IHP. This addresses the cell that programs synchronousenable. Programming the cell is accomplished with a 10 msprogram pulse on pin 18 (PGM) but does not require anydata as there is no choice as to how synchronous enablemay be programmed, only if it is to be programmed.VILP - --VIHP - -­PGMVILP - --VIHP --­VFVVILP - --~---tAS ---t-------tpP-----~Vpp ---VIHP ---VILP---Vpp ---PROGRAMMINGVOLTAGE (PIN 20)VIHP ---Verification of Synchronous EnableVerification of the synchronous enable function is accomplishedoperationally. Power the device for read operationwith pin 20 at V IH, cause clock pin 18 to transition fromVIL to VIH. The output should be in a High Z state. Takepin 20, ENABLE, to VIL. The outputs should remain in ahigh Z state. Transition the clock from V IL to V IH, theoutputs should now contain the data that is present. Againset pin 19 to VIH. The output should remain driven. Clockingpin 18 once more from VIL to VIH should place theoutputs again in a High Z state.Figure 7. Program Synchronous EnableBlank Check0016-12A virgin device contains neither one's nor zero's because ofthe differential cell used for high speed. To verify that aPROM is unprogrammed, use the two blank check modesprovided in Table 3. In both of these modes, address andread locations 0 thru 2047. A device is considered virgin ifall locations are respectively" I's" and "O's" when addressedin the "BLANK ONES AND ZEROS" modes.Because a virgin device contains neither ones nor zeros, itis necessary to program both one's and zero's. It is recommendedthat all locations be programmed to ensure thatambiguous states do not exist.3-35

Ordering InformationSpeed (ns) Icc Ordering Package Operating Speed (ns) IcC Ordering Package OperatingrnA Code Type RangetSA teo rnA Code Type Range tSA teo25 12 90 CY7C245-25PC P13 Commercial 45 25 60 CY7C245L-45PC P13 CommercialCY7C245-25WC W14 CY7C245L-45WC W1435 15 60 CY7C245L-35PC P13 Commercial 90 CY7C245-45PC P13CY7C245L-35WC W14 CY7C245-45SC S1390 CY7C245-35PC P13 CY7C245-45WC W14CY7C245-35SC S13 CY7C245-45LC L64CY7C245-35WC W14 120 CY7C245-45WMB W14 MilitaryCY7C245-35LC L64 CY7C245-45LMB L64120 CY7C245-35DMB D14 Military CY7C245-45DMB D14CY7C245-35QMB Q64 CY7C245-45QMB Q64CY7C245-35WMB W14CY7C245-35LMB L643-36

~ CYPRESSCY7C245~~~~u~==================================================~~~~~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3IcC 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstSA 7,8,9,10,11tHA 7,8,9,10,11teo 7,8,9,10,11Document #: 38-00004-CII3-37

CY7C245ACYPRESSSEMICONDUCTOR Reprogrammable 2048 X 8Registered PROMFeatures• Windowed for reprogrammabiIity• CMOS for optimumspeed/power• High speed- 18 ns max set-up- 12 ns clock to output• Low power- 330 mW (commercial) for-35 ns- 660 mW (military)• Programmable synchronous orasynchronous output enable• On-chip edge-triggered registers• Programmable asynchronousregister (lNIT)• EPROM technology, 100%programmable• Slim, 300 mil, 24 pin plastic orhermetic DIP• 5V ± 10% Vee, commercial andmilitary• TTL compatible I/O• Direct replacement for bipolarPROMs• Capable of withstanding greaterthan 2000V static dischargeLogic Block DiagramPin Configurations0121-2°0(.)II') U) "'U U GO 0)««4 3 2 :~! 28 27 265 25 A 1024 INIT2322 CP0 21 NC20 °711 19 06121314151617180' NO U '" ~ II)OzzOOOco0121-3Selection GuideMaximum Setup Time (ns)Maximum Clock to Output (ns)Maximum Operating STDCurrent (rnA)L7C245A-181812Commercial 120MilitaryCommercial7C245A-25 7C245A-3525 3515 2090 90120 120603-38

~crPRESSCY7C245AWnEMICONDUcroR ====================================================================Product CharacteristicsThe CY7C245A is a high performance 2048 word by 8 bitelectrically Programmable Read Only Memory packagedin a slim 300 mil plastic or hermetic DIP. The ceramicpackage may be equipped with an erasure window; whenexposed to UV light the PROM is erased and can then bereprogrammed. The memory cells utilize proven EPROMfloating gate technology and byte-wide intelligent programmingalgorithms.The CY7C245A replaces bipolar devices and offers the advantagesoflower power, reprogrammability, superior performanceand high programming yield. The EPROM cellrequires only 12.5V for the supervoltage and low currentrequirements allow for gang programming. The EPROMcells allow for each memory location to be tested 100%, aseach location is written into, erased, and repeatedly exercizedprior to encapsulation. Each PROM is also tested forAC performance to guarantee that after customer programmingthe product will meet AC specification limits.The CY7C245A has an asynchronous initialize function(INIT). This function acts as a 2049th 8-bit word loadedinto the on-chip register. It is user programmable with anydesired word or may be used as a PRESET or CLEARfunction on the outputs.Electrical Characteristics Over Operating Range[7]Parameters Description Test ConditionsVOHVOLVIRVILOutput HIGH VoltageOutput LOW VoltageInput HIGH LevelInput LOW LevelVee = Min.,loH = -4.0mAVIN = VIR or VILVee = Min.,IOL = 16 rnAVIN = VIR or VILGuaranteed Input Lo~ical HIGHVoltage for All Inputs 1]Guaranteed Input Lo~ical LOWVoltage for All Inputs 1]Maximum Ratings(Above which the useful life may be impaired. For userguidelines, not tested.)Storage Temperature ............ '" -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 24 to Pin 12) ................ " .. -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State .................. " .. -0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VDC Program Voltage (Pins 7, 18,20) ............. 13.0VUV Erasure .......................... 7258 Wsec/cm2Static Discharge Voltage ..................... > 2001 V(Per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureVeeCommercial O°Cto + 70°C SV ±1O%Military [4] - SsoC to + 12SoC SV ± 10%7C245A-18 7C245A-25, 35 7C245AL-35UnitsMin. Max. Min. Max. Min. Max.2.4 2.4 2.4 V0.4 0.4 0.4 V2.0 Vee 2.0 Vee 2.0 Vee V0.8 0.8 0.8 VIIX Input Leakage Current GND s VIN s Vee -10 +10 -10 +10 -10 +10 ).LAVeDlozlosleeCapacitance [6]ParametersInput Clamp DiodeVoltageOutput Leakage CurrentOutput Short CircuitCurrentPower Supply CurrentNote SGND s Vo s V~eOutput Disabled[3Note S-40 +40 -40 +40 -40 +40 ).LAVee = Max., VOUT = 0.OV[2] -20 -90 -20 -90 -20 -90 rnAGND s VIN s Vee I Commercial 120 90 60rnAVee = Max.I Military 120DescriptionCINInput CapacitanceCOUTOutput CapacitanceNotes:1. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment (see Notes onTesting).2. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.3. For devices using the synchronous enable, the device must be clockedafter applying these voltages to perform this measurement.Test Conditions Max. UnitsTA = 2SoC, f = 1 MHzSpFVee = S.OV84. T A is the "instant on" case temperature.5. The eMOS process does not provide a clamp diode. However, theeY7e245A is insensitive to - 3V dc input levels and - 5V undershootpulses ofless than 10 ns (measured at 50% point).6. Tested initially and after any design or process changes that mayaffect these parameters.7. See the last page of this specification for Group A subgroup testinginformation.3-39

~ CY7C245A~~~U~================================================================Switching Characteristics Over Operating Range[S]ParameterstSAtHAteotpwetSEgtHEStOltRItPWIteosDescriptionAddress Setup to Clock HIGHAddress Hold from Clock HIGHClock HIGH to Valid OutputClock Pulse WidthES Setup to Clock HIGHEs Hold from Clock HIGHDelay from INIT to Valid OutputINIT Recovery to Clock HIGHINIT Pulse WidthValid Output fromClock HIGH[l]tHze Inactive Output from Clock HIGH[1, 3]tOOE Valid Output from E LOW[2]tHZEInactive Output fromEHIGH[2,3]Notes:1. Applies only when the synchronous (ES) function is used.2. Applies only when the asynchronous --..... ---+I6pF R2167nINCLUDING_JIG AND _- SCOPE -0121-4Figure IbTHEVENIN EQUIVALENTloonOUTPUT ~2.0V 0121-6Functional DescriptionThe CY7C245A is a CMOS electrically ProgrammableRead Only Memory organized as 2048 words x 8·bits andis a pin-for-pin replacement for bipolar TTL fusible linkPROMs. The CY7C245A incorporates aD-type, masterslaveregister on chip, reducing the cost and size of pipelinedmicroprogrammed systems and applications whereaccessed PROM data is stored temporarily in a register.Additional flexibility is provided with a programmablesynchronous (Es) or asynchronous (E) output enable andasynchronous initialization (INIT).Upon power-up the state of the outputs will depend on theprogrammed state of the enable function (Es or E). If thesynchronous enable (Es) has been programmed, the registerwill be in the set condition causing the outputsALL INPUT PULSES3.0V-----.----......tGND --.....;~":5"1 ..:6"sFigure 20121-5(00-07) to be in the OFF or high impedance state. If theasynchronous enable (E) is being used, the outputs willcome up in the OFF or high impedance state only if theenable (E) input is at a HIGH logic level. Data is read byapplying the memory location to the address inputs(Ao-AlO) and a logic LOW to the enable input. The storeddata is accessed and loaded into the master flip-flops of thedata register during the address set-up time. At the nextLOW-to-HIGH transition of the clock (CP), data is transferredto the slave flip-flops, which drive the output buffers,and the accessed data will appear at the outputs(00-0 7).If the asynchronous enable (E) is being used, the outputsmay be disabled at any time by switching the enable to a3-40

~ CYPRESSCY7C245A~~~I~UaoR======================================================~~~~~8'unctional Description (Continued)ogic HIGH, and may be returned to the active state by.witching the enable to a logic LOW.[f the synchronous enable (Es) is being used, the outputs/'Iill. ~o to the OFF or high impedance state upon the next)O~lttve clock edge after the synchronous enable input isiw~tched to a HI~H level. If the synchronous enable pin isiWltched to a loglc LOW, the subsequent positive clock~dge will return the output to the active state. Following a)ositive clock edge, the address and synchronous enable.nputs are. free to change since no change in the output will)ccur untll the next low to high transition of the clock.fhis unique feature allows the CY7C245A decoders and~ense amplifiers to access the next location while previouslyilddressed data remains stable on the outputs.System ti!Ding is simplified in that the on-chip edge triggeredreglster allows the PROM clock to be derived directlyfrom the system clock without introducing race conditions.The on-chip register timing requirements are similarto those of discrete registers available in the market.Switching WaveformsThe CY7C245A has an asynchronous initialize input(INI~). The initialize function is useful during power-upand ttme-out sequences and can facilitate implementationof other sophisticated functions such as a built-in "jumpstart" address. When activated the initialize control inputcauses the contents of a user programmed 2049th 8-bitword to be loaded into the on-chip register. Each bit isprogrammable and the initialize function can be used toload any desired combination of" 1 "s and "O"s into theregister. In the unprogrammed state, activating INIT willgenerate a register CLEAR (all outputs LOW). If all thebits of the initialize word are programmed, activating INITperforms a register PRESET (all outputs HIGH).Applying a LOW to the INIT input causes an immediateload of the programmed initialize word into the master andslave flip-flops of the register, independent of all other inputs,including the clock (CP). The initialize data will appearat the device outputs after the outputs are enabled bybrir.ging the asynchronous enable (E) LOW.Au-AID______________ ~--~L--+~~~~~-------CPNotes on TestingInc~mi?g test procedures. on these devices should be carefully planned,takmg mto account the hIgh performance and output drive capabilities ofthe parts. The following notes may be useful.1. Ens.ure that adequate decoupling capacitance is employed across thedeVIce Vee and ground terminals. Multiple capacitors are recommended,incl~ding a 0.1 /l-F or larger capacitor and a 0.01 /l-F orsmaller capaCItor placed as close to the device terminals as possible.Inadequate d~coupling may resul.t in large v~riations of power supplyvoltage, ?reatmg erroneous functIOn or tranSIent performance failures.2. Do not leave any inputs disconnected (floating) during any tests.0121-73. Do not attempt to perform threshold tests under AC conditions.Lar~e amplitude! fast ground current tr~nsients normally occur as thedeVIce outputs dIscharge the load capaCItances. These transients flowingthrough the parasitic inductance between the device ground pinand the test system ground can create significant reductions in observableinput noise immunity.4. Output levels are measured at l.SV reference levels.S. Transition is measured at steady state HIGH level - SOO mV orsteady state LOW level + sao m Von the output from the l.SV levelon inputs with load shown in Figure 1 h.3-41

~ CY7C245A~~~NDUcroR =====================================================================Typical DC and AC Characteristicsu.::owN:;j«::ea:ozNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.61.41.21.0V//O.sTA = 25°CV f=MAX.O. 64.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (V)J~owN:;j«::ea:oZNORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.2,..-----.....,....-------,O.SOL-. ____ ..l-_____ --'-55 25 125AMBIENT TEMPERATURE rc)w::ei=... 1.4~...:lo 1.2E! :.:...JufilN:;j« O.S::ea:oZCLOCK TO OUTPUT TIMEvs. Vee1.6""- "-i'-......1.0---.. r--0.64.0TA = 25°CI4.5 5.0 5.5SUPPLY VOLTAGE (VI6.0w::ei=...:l~...:loE!:.:uo...JUfilN:;j«::ea:oZCLOCK TO OUTPUT TIMEvs. TEMPERATURE1.6,.------r--------,1.41-------+--------11.01--------:""""'::::.-------1O.s t-----+-------I0.6 ..... -----1...-------'-55 25125w::ei=...~:lwII)0wN:;j«::ea:0ZNORMALIZED SETUP TIMEvs. SUPPLY VOLTAGE1.21.0O.s0.6~ ~~ ~0.44.0 4.5 5.0TA i 2SoC5.5 6.0...~:lwII)0wN:;j«::ea:0ZNORMALIZED SETUP TIMEvs. TEMPERATURE1.61.41.21.0~O.S0.6-55 25--125AMBIENT TEMPERATURE (OC)SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE (OC)~E...~a:a::luwua::l0II)...:l~...:l0OUTPUT SOURCE CURRENTvs. VOLTAGE605040302010o o~"-~'"'" '"1.0 2.0 3.0 4.0OUTPUT VOLTAGE (V)30.025.0! 20.0"; 15.0~~ 10.05.0TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADINGV/"Vv//.--TA = 25°CVee =4.5 V0.0o 200 400 600 SOO 1000CAPACITANCE (pF)~E...Zwa:a::lU:.:Ziii...:l~...:l0OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE17515012510075I/50/L25[1o0.0 1.0.".,.. ~/ V- Vee =5.0 VTA = 25°C2.0 3.0 4.0OUTPUT VOLTAGE (V)0121-93-42

~ CY7C245A~~~NDUcrOR=====================================================================Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the 7C245A. For this reason, an opaque label shouldbe placed over the window if the PROM is exposed tosunlight or fluorescent lighting for extended periods oftime.The recommended dose for erasure is ultraviolet light witha wavelength of2537 Angstroms for a minimum dose (UVintensity X exposure time) of25 Wsec/cm2. For an ultravioletlamp with a 12 m W I cm2 power rating the exposuretime would be approximately 30-35 minutes. The 7C245Aneeds to be within 1 inch of the lamp during erasure. Permanentdamage may result if the PROM is exposed to highintensity UV light for an extended period of time. 7258Wsec/cm2 is the recommended maximum dosage.DC Programming Parameters TA = 25°CParameterVpp[1]VccpVIHPVILPVOR[2]VOL[2]DescriptionProgramming VoltageSupply VoltageInput High VoltageInput Low VoltageOutput High VoltageOutput Low VoltageTable 1Device ProgrammingOVERVIEW:There are three independent programmable functions containedin the 7C245A CMOS 2K x 8 Registered PROM;the 2K x 8 array, the initial byte, and the synchronousenable bit. All of the programming elements are"EPROM" cells, and are in an erased state when the deviceis shipped. This erased state manifests itself differentlyin each case. The erased state for ENABLE bit is the"ASYNCHRONOUS ENABLE" mode. The erased statefor the "INITIAL BYTE" is all "O's" or "LOW". The"INITIAL BYTE" may be accessed operationally thru theuse of the initialize function.Min. Max. Units12.0 13.0 V4.75 5.25 V3.0 V0.4 V2.4 V0.4 VIpp Programming Supply Current 50 mAAC Programming Parameters TA = 25°CTable 2Parameter Description Min. Max. Unitstpp Programming Pulse Width 200 10,000 fJ-stAS Address Setup Time 1.0 fJ-stos Data Setup Time 1.0 fJ-stAR Address Hold Time 1.0 fJ-stOR Data Hold Time 1.0 fJ-stR, tF[3] Vpp Rise and Fall Time 1.0 fJ-stvo Delay to Verify 1.0 fJ-stvp Verify Pulse Width 2.0 fJ-stov Verify Data Valid 1.0 fJ-stoz Verify HIGH to High Z 1.0 fJ-sNotes:1. V ccp must be applied prior to V pp.2. Ouring verify operation.3. Measured 10% and 90% points.3-43

~ CY7C245A~~~NDUcrOR =======================================================================Mode SelectionModeRead[2,3]Output Disable[5]Program [4]Program Verify[4]Program Inhibit[4]Read or Output DisableOtherA3A3Pin (5)Intelligent Program[4]X VILPProgram Synch Enable[4]VIHP VILPProgram Initial Byte[4]VILP VILPNotes:1. X = Don't care but not to exceed Vpp.2. During read operation, the output latches are loaded on a "0" to "1"transition of CPo3. If the registered device is being operated in a synchronous mode, pin19 must be LOW prior to the "0" to "1" transition on CP (18) thatloads the register.A7A6A5A4A3A2AlBitMap DatavceAsAgAl0Ao 0 7Do 0 60 1 0 50 2 04Vss 0 3Vpp (lNIT)VFY fE/Es)PGM (CP)Figure 3. Programming PinoutsXXXXX0121-10Programmer AddressDecimal Hex0 0• ••• •2047 7FF2048 8002049 801Table 3Pin Function[l]CP E/Es INIT AOOutputsPGM VFY Vpp Ao (9-11,13-17)(18) (19) 20 (8)XXVILPVIHPVIHPControl Byte00 Asynchronous output enable (default state)01 Synchronous output enable3-44VIL VIH X Data OutVIH VIH X HighZVIHP Vpp X Data InVILP Vpp X Data OutVIHP Vpp X HighZVIHP Vpp X Data InVIHP Vpp Vpp HighZVIHP Vpp Vpp Data In4. During programming and verification, all unspecified pins to be atVILP·5. If the registered device is being operated in a synchronous mode, pin19 must be HIGH prior to the "0" to "I" transition on CP (18) thatloads the register.The CY7C245A programming algorithm allows significantlyfaster programming than the "worst case" specificationof 10 msec. .Typical programming time for a byte is less than 2.5 msec.The use of EPROM cells allows factory testing of programmedcells, measurement of data retention and erasureto ensure reliable data retention and functional performance.A flowchart of the algorithm is shown in Figure 4.The algorithm utilizes two different pulse types: initial andoverprogram. The duration of the PGM pulse (tpp) is 0.2msec which will then be followed by a longer overprogrampulse of 4 (0.1) (X) msec. X is an iteration counter and isequal to the NUMBER of the initial 0.2 msec pulses appliedbefore verification occurs. Up to ten 0.2 msec pulsesare provided before the overprogram pulse is applied.The entire sequence of program pulses and byte verificationsis performed at V ccp = 5.0V. When all bytes havebeen programmed all bytes should be compared (Readmode) to original data with Vcc = 5.0V.RAM DataContentsDATA••DATAINITBYTECONTROL BYTE

IIFigure 4. Programming Flowchart3-45

~ CY7C245A~~~UaoR~==============================~====~~==~~====~==========~Programming Sequence 2K x 8 ArrayPower the device for normal read mode operation with pin18,19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. Thedevice is now in the program inhibit mode of operationwith the output lines in a high impedance state; see Figures5 and 6. Again per Figure 5 address program and verifyone byte of data. Repeat this for each location to be programmed.If the brute force programming method is used, the pulsewidth of the program pulse should be 10 ms, and eachlocation is programmed with a single pulse. Any locationthat fails to verify causes the device to be rejected.If the intelligent programming technique is used, the programpulse width should be 200 J.Ls. Each location is ultimatelyprogrammed and verified until it verifies correctlyup to and including 10 times. When the location verifies,one additional programming pulse should be applied of duration4X the sum of the previous programming pulsesbefore advancing to the next address to repeat the process.VIHP -A:~RESS14----- PROGRAM------

Programming the Initialization ByteThe CY7C245A registered PROM has a 2049th byte ofdata used to initialize the value of the register. This initialbyte is value "0" when the part is received. If the userdesires to have a value other than "0" for register initialization,this must be programmed into the 2049th byte. Thisbyte is programmed in a similar manner to the 2048 normalbytes in the array except for two considerations. First,since all of the normal addresses of the part are used up, asuper voltage will be used to create additional effective addresses.The actual address has Vpp on Ao pin 8, and VILPon A3, pin 5, per Table 3. The programming and verificationof "INITIAL BYTE" is accomplished operationallyby performing an initialize function.Programming Synchronous EnableThe CY7C245A provides for both a synchronous and asynchronousenable function. The device is delivered in anasynchronous mode of operation and only requires that theuser alter the device if synchronous operation is required.The determination of the option is accomplished thru theuse of an EPROM cell which is programmed only if synchronousoperation is required. As with the INITIAL byte,this function is addressed thru the use of a supervoltage.Per Table 3, Vpp is applied to pin 8 (Ao) with pin 5 (A3) atV IHp. This addresses the cell that programs synchronousenable. Programming the cell is accomplished with a 10 msprogram pulse on pin 18 (PGM) but does not require anydata as there is no choice as to how synchronous enablemay be programmed, only if it is to be programmed.VILP ---VIHP ---PGMVILP---VIHP ---VFvVILP - --....... ---tAs ___ +-------Ipp-----~Vpp---AoVIHP---VILP ---Vpp---PROGRAMMINGVOLTAGE (PIN 201VIHP ---VILP ---Verification of Synchronous EnableVerification of the synchronous enable function is accomplishedoperationally. Power the device for read operationwith pin 20 at V IH, cause clock pin 18 to transition fromVIL to VIH. The output should be in a High Z state. Takepin 20, ENABLE, to VIL. The outputs should remain in ahigh Z state. Transition the clock from VIL to VIH, theoutputs should now contain the data that is present. Againset pin 19 to VIH. The output should remain driven. Clockingpin 18 once more from VIL to VIH should place theoutputs again in a High Z state.IFigure 7. Program Synchronous EnableBlank Check0121-13A virgin device contains all zeros. To blank check thisPROM, use the verify mode to read locations 0 thru 2047.A device is considered virgin if all locations are "O's" whenaddressed.3-47

~ CY7C245A~~~NDU~ ===================================================================Ordering InformationSpeed (ns) Icc Ordering Package Operating Speed (ns) Icc Ordering Package OperatingtSA teo mA Code Type Range mA Code Type RangetSA teo18 12 120 CY7C245A-18PC P13 Commercial 35 20 60 CY7C245AL-35PC P13 CommercialCY7C245A-18WC W14 CY7C245AL-35WC W1425 15 90 CY7C245A-25PC P13 Commercial 90 CY7C245A-35PC P13CY7C245A-25SC S13 CY7C245A-35SC S13CY7C245A-25WC W14 CY7C245A-35WC W14CY7C245A-25LC L64 CY7C245A-35LC L64120 CY7C245A-250MB 014 Military 120 CY7C245A-35WMB W14 MilitaryCY7C245A-25QMB Q64 CY7C245A-35LMB L64CY7C245A-25WMB W14 CY7C245A-350MB 014CY7C245A-25LMB L64 CY7C245A-35QMB Q643-48

~ CYPREI3SCY7C245A~~IOO~UaDR==================================================~~~~~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstSA 7,8,9,10,11tHA 7,8,9,10,11teo 7,8,9,10,11Document #: 38-00004-AIII3-49

Features• CMOS for optimumspeed/power• Windowed for reprogrammability• High speed- 45 ns (commercial)- 55 ns (military)• Low power- 550 mW (commercial)- 660 mW (military)• Super low standby power(7C251)- Less than 165 mW whendeselected- Fast access: 50 ns• EPROM technology 100%programmable• Slim 300 mil or standard 600mil packaging available• 5V ± 10% V CC, commercial andmilitary• TTL compatible I/OCYPRESSSEMICONDUCTOR• Direct replacement for bipolarPROMs• Capable of withstanding > 2001 Vstatic dischargeProduct CharacteristicsThe CY7C251 and CY7C254 are highperformance 16,384 word by 8 bitCMOS PROMs. When deselected, the7C251 automatically powers down intoa low power stand-by mode. It is packagedin the 300 mil wide package. The7C254 is packaged in 600 mil widepackages and does not power downwhen deselected. The 7C251 and7C254 reprogrammable CERDIPpackages are equipped with an erasurewindow; when exposed to UV light,these PROMs are erased and can thenbe reprogrammed. The memory cellsutilize proven EPROM floating gatetechnology and byte-wide intelligentprogramming algorithms.CY7C251CY7C25416,384 X 8 PROMPower Switched andReprogrammableThe CY7C251 and CY7C254 are pluginreplacements for bipolar devices andoffer the advantages of lower power,superior performance and programmingyield. The EPROM cell requiresonly 12.5V for the supervoltage andlow current requirements allow forgang programming. The EPROM cellsallow for each memory location to betested 100%, as each location is writteninto, erased, and repeatedly exercisedprior to encapsulation. Each PROM isalso tested for AC performance toguarantee that after customer programmingthe product will meet DC andAC specification limits.Reading is accomplished by placing allfour chip selects in their active states.The contents of the memory locationaddressed by the address lines (Ao­A13) will become available on the outputlines (00-07).Logic Block DiagramPin Configurations0 7A6 A7 As Ag V cc A,oAA.A3COLUMNA2 DECODERA, ' OF 32Ao0 6OsO.AsA.0 3O 20 00,VeeA,o~~! ~~! ~ ~!i:j !3_~ t:'! ~A5 :S:1"n! A'2Au A. I1 ~~! A'3A'2 A3 7' ~~! cs,AUA2 I} cs, ~~! cs02CS 2A, .- ~~~ CS 3CS 3 Ao H1 -2. cs.CS. NC ,,- t~! NCQ o 1~! ~~~ Q7Q, 13- ~~I Q 6:,,1 h~: :1': :,71 :18: :19: ~o:Q 2 NC GND Q 3 NC Q. Q50 0 0086-20086-11Top ViewSelection Guide0086-17C251-45 7C251-55 7C251-657C254-45 7C254-55 7C254-65Maximum Access Time (ns) 45 55 65Maximum Operating Commercial 100 100 100Current (rnA)Military 120 120Standby Current (rnA) Commercial 30 30 30(7C251 only)Military 35 35-3-50

wnCY7C251~. ~~~ ~~~UcrOR=====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... > 2001VAmbient Temperature with (per MIL-STD-883, Method 3015)Power Applied .................... - 55°C to + 125°C Latchup Current .......................... > 200 rnASupply Voltage to Ground PotentialUV Exposure ........................ 7258 Wsec/cm2(Pin 28 to Pin 14) .................... -O.5V to + 7.0VDC Voltage Applied to OutputsOperating Rangein High Z State ...................... -O.5V to +7.0VAmbientRangeDC Input Voltage ................... - 3.0V to + 7.0VTemperatureVeeDC Program Voltage (Pin 22) ................... 13.5VCommercial O°C to + 70°C 5V ±lO%Military [5] - 55°C to + 125°C 5V ±lO%Electrical Characteristics Over the Operating Range[6]7C251-45 7C251-55,65Parameters Description Test Conditions 7C254-45 7C254-55,65 UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = -4.0 rnA 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 16.0 rnA 0.5 0.5 VVIR Input HIGH Level[ll 2.0 2.0 VVIL Input LOW Leve1U] 0.8 0.8 VIIX Input Current GND ~ VIN ~ Vee -lO +lO -10 +lO fLAVeDInput Diode ClampVoltageNote 2 Note 2loz Output Leakage Current VOL ~ VOUT ~ VOH, Output Disabled -40 +40 -40 +40 fLAlosleeISBCapacitance [4]Output ShortCircuit Current[3]Vee = Max., VOUT = GND -20 -90 -20 -90 rnAPower Supply Vee = Max., VIN = 2.0V Commercial 100 100 rnACurrent lOUT = OmA Military 120 rnAStandby Supply Vee = Max., CS ~ VIR Commercial 30 30 rnACurrent (7C251) lOUT = OmA Military 35 rnAParameters Description Test Conditions Max. UnitsCINInput CapacitanceCOUTOutput CapacitanceNotes:1. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment.Z. The CMOS process does not provide a clamp diode. However, theCY7C251 and CY7C254 are insensitive to - 3V dc input levels and- 5V undershoot pulses ofless than 10 ns (measured at 50% point).TA = 25°C, f = 1 MHz 10Vee = 5.0V 103. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.4. Tested initially and after any design or process changes that mayaffect these parameters.5. TA is the "instant on" case temperature.6. See the last page of this specification for Group A subgroup testinginformation.pF3-51

Switching Characteristics Over the Operating Rangef6, 717C251·45 7C251·55 7C251·65Parameters Description 7C254·45 7C254-55 7C254-65 UnitsMin. Max. Min. Max. Min. Max.tAA Address to Output Valid 45 55 65 nstHZCSl Chip Select Inactive to High Z[S, 9] 25 30 35 nstHZCS2 Chip Select Inactive to High Z (7C251, CSI Only)[S] 50 60 70 nstAcsl Chip Select Active to Output Valid[9] 25 30 35 nstACS2 Chip Select Active to Output Valid (7C251, CSI Only) 50 60 70 nstpu Chip Select Active to Power Up (7C251) 0 0 0 nstpD Chip Select Inactive to Power Down (7C25I) 50 60 70 nsAC Test Loads and WaveformsR1 23S.nOUTPUT SVFl30 f R2INCLUDING I P 1S9.nJIG ANDSVHR1 23S.nOUTPUT5 f R2INCLUDING I P 1S9.nJIG AND0086-43.0 v-----=.I!~~---~GND---:rSCOPE -= SCOPE -= Figure 2. Input PulsesFigure laFigure Ib" 5n8" 5n80086-6Equivalent to:THEVENIN EQUIVALENT9S.nOUTPUT ~ 2.02V 0086-5VeeSUPPLYCURRENTAo- A 13ADDRESS-_tPDjtpu I Note: Power Down controlled by CSJ,only."\50% 50%ICS 3CS 1 ,CS Z·CS 4K_t AA _tHzes -I- tAesNotes:7. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, output loading of the specified IOL/loH andloads shown in Figure la, lb.Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the 7C251 and 7C254 in the windowed package. Forthis reason, an opaque label should be placed over the windowif the PROM is exposed to sunlight or fluorescentlighting for extended periods of time.The recommended dose of ultraviolet light for erasure is awavelength of 2537 Angstroms for a minimum dose (UV0086-7S. tHZCS is tested with load shown in Figure lb. Transition is measuredat steady state High level - 500 m V or steady state Low level + 500m V on the output from the 1.5V level on the input.9. tHZCS! and tACS! refers to 7C253 and 7C254 (all chip selects); and7C251 (CS2, CS3 and CS4 only).intensity X exposure time) or 25 Wsec/cm 2 , For an ultravioletlamp with a 12 m W I cm2 power rating the exposuretime would be approximately 45 minutes. The 7C251 or7C254 needs to be within 1 inch of the lamp during erasure.Permanent damage may result if the PROM is exposedto high intensity UV light for an extended period oftime. 7258WXsec/cm2 is the recommended maximumdosage.3-52

CY7C251~ CY7C254~)r;~~ucr~================================================================~Device ProgrammingThe CY7C251 and CY7C254 all program identically. Theyutilize an intelligent programming algorithm to assure consistentprogramming quality. These 128K PROMS use asingle ended memory cell design. In an unprogrammedstate, the memory contains all "O"s. During programming,a "1" on a data-in pin causes the addressed location to beprogrammed, and a "0" causes the location to remain unprogrammed.Programming PinoutThe Programming Pinout of all three devices are shown inFigure 3 below, and are identical. The programming modeis entered by raising the pin 22 to V pp. The addressedlocation is programmed and verified with the application ofa PGM and VFYpulse applied to pins 23 and 21 respectively.Entering and exiting the programming mode shouldbe done with care. Proper sequencing as described in thedialog on the programming algorithm and shown in thetiming diagram and programming flow chart must be implemented.Programming And BlankcheckBlankcheck8lankcheck is accomplished by performing a verify cycle(VFY toggles on each address), sequencing through allmemory address locations, where all the data read will be"O"s.Programming AlgorithmProgramming is accomplished with an intelligent algorithm.The sequence of operations is to enter the programmingmode by placing Vpp on pin 22. This should be doneafter a minimum delay from power up, and be removedprior to power down by the same delay (see the timingdiagram and AC specifications for details). Once in thismode, programming is accomplished by addressing a location,placing the data to be programmed into a location onthe data pins, and clocking the PGM signal from VIHP toV ILP and back to V IHP with a pulse width of 200 fLs. Thedata is removed from the data pins and the content of thelocation is then verified by taking the VFY signal fromVIHP to VILP, comparing the output with the desired dataand then returning VFY to V IHp. If the contents are correct,a second overprogram pulse of 4 times the original.200 fLs is delivered with the data to be programmed agamon the data pins. If the data is not correct, a second 200 fLSpulse is applied to PGM with the data to be programm~don the data pins. The compare and overprogram operatIOnis repeated with an overprogram pulse width 4 times thesum of the initial program pulses. This operation is continueduntil the location is programmed or 10 initial programpulses have been attempted. If on the 10th attempt, t~elocation fails to verify, an overprogram pulse of 8 ms ISapplied, and the content of the location is once more verified.If the location still fails to verify, the device is rejected.Once a location verifies successfully, the address is advancedto the next location, and the process is repeateduntil all locations are programmed. After all locations areprogrammed, they should be verified at V ccp = 5.0V.IIA9A8A7A6ASA4 6A3 7A2 8Al 9AO 1000 1101 1202 13VSS 1428 vee27 Al026 All25 A1224 A1323 PGM22 VPP21 VFY20 NA07060504030086-8Figure 3. Programming Pinout (DIP Package)3-53

(inCY7C251. CY7C254~NDUcrOR =====================================================================Operating ModesReadRead is the normal operating mode for a programmed device.In this mode, all signals are normal TTL levels. ThePROM is addressed with a 14 bit field, 4 chip select bits,and the contents of the addressed location appear on thedata out pins.Program, Program Inhibit, Program VerifyThese modes are entered by placing a high voltage Vpp onpin 22. Pin 23 becomes an active LOW program (PGM)signal and pin 21 becomes an active LOW verify (VFY)signal. Pins 21 and 23 should never be active LOW at thesame time. The PROGRAM mode exists when PGM isLOW, and VFY is HIGH. The VERIFY mode exists whenthe reverse is true, PGM HIGH and VFY LOW and thePROGRAM INHIBIT mode is entered with both PGMand VFY HIGH. PROGRAM INHIBIT is specificallyprovided to allow data to be placed on and removed fromthe data pins without conflict.BlankcheckBlankcheck mode is identical to PROGRAM VERIFYand is entered in the same manner as described above.Programming SequenceThe flowchart in Figure 4 is a detailed description of theintelligent programming cycle used to program the devicescovered in this specification. Of particular importance arethe areas of power sequencing used to enter and exit theprogramming operation. This flowchart combined with thetiming diagrams AC and DC parameters accurately describethis complete operation.The timing diagram in Figure 5 contains all of the timinginformation necessary for describing the relations requiredfor programming the devices covered in this specification.Some of the information pertains to each cycle of programmingas specified in Figure 4, and some pertains only toentry and exit from the programming mode of operation.Tp, TpD and THP refer to the entry and exit from theprogramming mode of operation. Note that this is referencedto PGM and VFY operations.TDS, T AS, T AH and TDH refer to the required setup andhold times for the address and data for PGM and VFYoperations. These parameters must be adhered to, in alloperations, including VFY. This precludes the option thenof verifying the device by holding the VFY signal LOW,and sequencing the addresses.Table 1. Operating ModesPin FunctionModeRead or Output Disable CS4 CS3 CS2 CSt OutputsOther N/A VFY Vpp PGM (11-13,15-19)Pin Number (20) (21) (22) (23)Read VIL VIH VIL VIL Data OutOutput Disabldl] X X X VIH HighZOutput Disable[l] X X VIH X HighZOutput Disablel1] X VIL X X HighZOutput Disable[l] VIH X X X HighZProgram X VIHP Vpp VILP Data InProgram Verify X VILP Vpp VIHP Data OutProgram Inhibit X VIHP Vpp VIHP HighZBlank Check X VILP Vpp VIHP Data OutNote:1. X = Don't care but not to exceed Vee + 5%.3-54

WACY7C251CY7C254~~NDUcrOR ==================================================================~~ypical AC and DC CharacteristicsNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.6NORMALIZED SUPPLY CURRENT1.2 vs. AMBIENT TEMPERATURENORMALIZED ACCESS TIME1.2 vs. SUPPLY VOLTAGE1.41.2/V./1.0,.,.,./ VO.BTA = 25°Cf=MAX.0.64.0 4.5 5.0 5.5 6.0~QL..IN::::i0«~0::oZ1.11---~---+------l1.0 f-----,,\OO;:,----------j0.9 f-----t------'~--jO.B '---___--'-_____......1-55 25 125L..I~1=VI~S0«QL..IN::::i0«~0::oZ1.0 r-- -- ------.080.60.44.0 4.5 5.0TA =r 5OC5.5 6.0SUPPLY VOLTAGE(V)AMBIENT TEMPERATURE (OC)SUPPLY VOLTAGE (V)NORMALIZED ACCESS TIMEvs. TEMPERATURE1.6 ,...-------,-------,1.4 \------+-------11.2 \------+------11.0 \-----=:30"""'F''---------IO.B f-----t-------j0.6 L...-___ -'-_____ -'-55 25 125~5I-ZL..I0::0::::>0L..I00::::>0VIl-=>c...l-=>0OUTPUT SOURCE CURRENT,vs. VOLTAGE605040302010"" " "-'" ""o o 1.0 2.0 3.0 4.0'"' ..5-~~...JL..IQ30.025.020.015.010.05.0oTYPICAL ACCESS TIMECHANGE vs. OUTPUT LOADING1// // V...... ~.IV TA = 25°CV cc =4.5V -Io 200 400 600 800 1000AMBIENT TEMPERATURE(°C)OUTPUT VOLTAGE (V)CAPACITANCE (pF)~5I-zL..I0::0::::>0:.:::ziiiI- ::>c...I- ::>01751501251007550OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE/..,.".,----;II"VVcc =5.0VT A=250C -/l25Vo o 1.0 2.0 3.0 4.0OUTPUT VOLTAGE (V)0086-123-55

5ACY7C251CY7C254s~~O~UcrOR================================================================~• CYPRESSFigure 4. Programming Flowchart0086-133-56

5ACY7C251. CY7C254~~u~==================================================================TpVpP ____ ~~------------------------------------------------~Vpp PIN 22 VIHP -----+1------- TOp --------+1TOp ----+I /+---+- T HP ---+------..j/+---+- TAH --+---~ADDRESS V'HP-=~~::~C8~~~~~~~::::J:::::::!:::::l::::::::t:::::::)~-------V .- 1Lp_VIHP--+-------Jro--------------------+_~DATA VILP--+-------~------------------+_~.PGM PIN 23 VILP-_Vry PIN 21 V 1LP-V1HP---lf------------------------.V1HP--lI--------------------iIIFigure 5. Programming WaveformsNote: Power, V pp and Vee should not be cycled for each program verify cycle but remain static during programming.0086-143-57

QCY7C251. CY7C254~~UaoR================================================================Ordering InformationSpeed Ordering Package Operating(ns) Code Type Range45 CY7C251-45PC P21 CommercialCY7C251-45WCW22CY7C254-45WCW16CY7C254-45PCPISCY7C254-450C 01655 CY7C251-55PC P21CY7C251-55WCW22CY7C254-55WCW16CY7C254-55PCPISCY7C254-550C 016CY7C25l-55WMB W22 MilitaryCY7C25 I-550MB 022CY7C254-55WMBW16CY7C254-550MB 01665 CY7C25l-65PC P2l CommercialCY7C25l-65WCW22CY7C254-65WCW16CY7C254-65PCPISCY7C254-650C 016CY7C25 i -65WMB W22 MilitaryCY7C25 I-650MB 022CY7C25l-65LMBL55CY7C25l-65QMBQ55CY7C254-65WMBW16CY7C254-65LMBL55CY7C254-65QMBQ55CY7C254-650MB 0163-58

(;nCY7C251. CYPRFSS CY7C254SEMICONDUCIOR ============================~~~~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3IoZ 1,2,3Icc 1,2,3ISB[2] 1,2,3SubgroupsSwitching CharacteristicsParametersSubgroupstAA 7,8,9,10,11tACSl[l] 7,8,9,10,11tACS2[2] 7,8,9,10,11Notes:1. 7C254 only.2. 7C251 only.Document #: 38-00056-CII3-59

Features• CMOS for optimumspeed/power• Windowed for reprogrammability• High speed- 35 ns (commercial)- 45 ns (military)• Low power- 550 mW (commercial)- 660 mW (military)• Super low standby power(7C261)- Less than 185 mW whendeselected- Fast access: 35 ns• EPROM technology 100%programmable• Slim 300 mil or standard 600mil packaging available• 5V ± 10% V CC, commercial andmilitary• TTL compatible I/OLogic Block DiagramCYPRESSSEMICONDUCTOR• Direct replacement for bipolarPROMs• Capable of withstanding > 2000Vstatic dischargeProduct CharacteristicsThe CY7C261, CY7C263 andCY7C264 are high performance 8192word by 8 bit CMOS PROMs. Whendeselected, the 7C261 automaticallypowers down into a low power standbymode. It is packaged in the 300 milwide package. The 7C263 and 7C264are packaged in 300 mil and 600 milwide packages respectively and do notpower down when deselected. The reprogrammableCERDIP packages areequipped with an erasure window;when exposed to UV light, thesePROMs are erased and can then be reprogrammed.The memory cells utilizeproven EPROM floating gate technologyand byte-wide intelligent programmingalgorithms.CY7C261CY7C263/CY7C2648192 X 8 PROMPower Switched andReprogrammableThe CY7C261, CY7C263 andCY7C264 are plug-in replacements forbipolar devices and offer the advantagesof lower power, superior performanceand programming yield. TheEPROM cell requires only 12.5V forthe supervoltage and low current requirementsallow for gang programming.The EPROM cells allow for eachmemory location to be tested 100%, aseach location is written into, erased,and repeatedly exercised prior to encapsulation.Each PROM is also testedfor AC performance to guarantee thatafter customer programming the productwill meet DC and AC specificationlimits.Reading is accomplished by placing anactive LOW signal on CS. The contentsof the memory location addressed bythe address lines (Ao-A12) will becomeavailable on the output lines (00-07).Pin Configurations0052-20052-1

__.5ACY7C261CY7C263/CY7C264~ ~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2001VAmbient Temperature with(per MIL-STD-883, Method 3015)Power Applied .................... - 55°C to + 125°C Latchup Current .......................... > 200 rnASupply Voltage to Ground Potential UV Exposure ........................ 7258 Wsec/cm 2(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to OutputsOperating Rangein High Z State ...................... -0.5V to + 7.0VAmbientRangeVeeDC Input Voltage ................... - 3.0V to + 7.0VTemperatureDC Program VoltageCommercial O°Cto + 70°C 5V ±1O%(Pin 19 DIP, Pin 23 LCC) ...................... 14.0VMilitary!5] - 55°C to + 125°C 5V ±10%Electrical Characteristics Over the Operating Range[6]Parameters Description Test Conditions7C261-35,407C263-35, 407C264-35, 407C261-45,557C263-45,557C264-45,55Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,IOH = -4.0 rnA 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 16.0mA 0.4 0.4 VVIH Input HIGH Level!!] 2.0 2.0 VVIL Input LOW Level!!] 0.8 0.8 VIIX Input Current GND:O::: VIN:O::: Vee -10 +10 -10 +10 J.tAVeDInput Diode ClampVoltageNote 2 Note 2loz Output Leakage Current VOL :0::: V OUT :0::: V OH, Output Disabled -40 +40 -40 +40 J.tAlosIccISBOutput ShortCircuit Current!3]UnitsVee = Max., VOUT = GND -20 -90 -20 -90 rnAPower Supply Vee = Max., VIN = 2.0V Commercial 100 100 rnACurrent lOUT = OmA Military 120 rnAStandby Supply Vee = Max., CS ~ VIH Commercial 30 30 rnACurrent (7C261)lOUT = OmAMilitary 30 rnAIICapacitance [4]ParametersCINDescriptionInput CapacitanceCOUTOutput CapacitanceNotes:I. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment.2. The CMOS process does not provide a clamp diode. However, theCY7C261, CY7C263 & CY7C264 are insensitive to - 3V dc inputlevels and - 5V undershoot pulses of less than 10 ns (measured at50% point).Test Conditions Max. UnitsTA = 25°C, f = 1 MHz 5Vee = 5.0V 83. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.4. Tested initially and after any design or process changes that mayaffect these parameters.5. T A is the "instant on" case temperature.6. See the last page of this specification for Group A subgroup testinginformation.pF3-61

(;nCY7C261. CY7C263/CY7C264~NDUcrOR ~===================================================================Switching Characteristics Over the Operating Range[5, 617C261·35 7C261·40 7C261·45 7C261·557C263·35 7C263·40 7C263·45 7C263·55Parameters Description 7C264·35 7C264·40 7C264·45 7C264·55 UnitsMin. Max. Min. Max. Min. Max. Min. Max.tAA Address to Output Valid 35 40 45 55 nstHzcSl Chip Select Inactive to High Zls] 25 25 30 35 nstHZCS2 Chip Select Inactive to High Z (7C261)IS] 30 35 45 55 nstACSl Chip Select Active to Output Valid 25 25 30 35 nstACS2 Chip Select Active to Output Valid (7C261) 40 45 45 55 nstpu Chip Select Active to Power Up (7C261) 0 0 0 0 nstpD Chip Select Inactive to Power Down (7C261) 35 40 45 55 nsAC Test Loads and WaveformsR1250nR1250n5Vo---------~~~ 5 V 0--------""'1\,-.....3.0V----2~~--~_OUTPUT 0------.-------... OUTPUT 0-----....... ------..GND---""IR2R2s; 5ns s; 5nsINCLUDING I 30 pF 167!l INCLUDING I 5 pF 167nJIG AND0052-6JIG ANDSCOPE SCOPE Figure 2. Input PulsesFigure laFigure lb0052-4Equivalent to: THEVENIN EQUIVALENTloonOUTPUT O-----~ .."'A4.~--O 2.0 V- tpDVeeSUPPLYCURRENTAo-A12ADDRESS J(0052-5-~ 50%- tpu-"1 50%J1\-tAA-tHZCS-I- t ACS0052-7Notes:7. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, output loading of the specified IorlIOH andloads shown in Figure la, lb.Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the devices in the windowed package. For this reason,an opaque label should be placed over the window if thePROM is exposed to sunlight or fluorescent lighting forextended periods of time.The recommended dose of ultraviolet light for erasure is awavelength of 2537 Angstroms for a minimum dose (UVS. tHZCS is tested with load shown in Figure lb. Transition is measuredat steady state High level - 500 m V or steady state Low level + 500mV on the output from the 1.5V level on the input.intensity X exposure time) or 25 Wsee/cm 2 . For an ultra·violet lamp with a 12 mW /cm2 power rating the exposuretime would be approximately 45 minutes. The 7C261 or7C263 needs to be within 1 inch of the lamp during erasure.Permanent damage may result if the PROM is exposedto high intensity UV light for an extended period oftime. 7258WX sec/cm 2 is the recommended maximumdosage.3-62

CY7C261CY7C263/CY7C264~CfPRESS~~~OONDUcrOR=====================================================================Device ProgrammingThe CY7C261, CY7C263 & CY7C264 all program identically.They utilize an intelligent programming algorithm toassure consistent programming quality. These 64KPROMS use a single ended memory cell design. In an unprogrammedstate, the memory contains all "O"s. Duringprogramming, a "1" on a data-in pin causes the addressedlocation to be programmed, and a "0" causes the locationto remain unprogrammed.Programming PinoutThe Programming Pinout of all three devices are shown inFigure 3 below, and are identical. The programming modeis entered by raising the pin 19 to Vpp. In this mode, pin 21becomes a latch signal, allowing the upper 5 address bits tobe latched and held in an onboard register, while the lower8 address bits are presented on the same pins for selectingone of 256 memory bytes. The addressed location is programmedand verified with the application ofa PGM andVFY pulse applied to pins 22 and 23 respectively. Enteringand exiting the programming mode should be done withcare. Proper sequencing as described in the dialog on theprogramming algorithm and shown in the timing diagramand programming flow chart must be implemented.Programming And BlankcheckAddressing During Programming and BlankcheckAddressing to these devices in all modes of operation otherthan normal read operation is accomplished by multiplexingthe upper 5 address bits with the lower 8. The addressdesignations for the lower 8 addressing bits is AXO throughAX7 and the upper 5 address bits are designated A Y8through AYI2. This allows sufficient pins for an intelligentprogramming algorithm to be implemented without theneed to switch high voltage signals during the blankcheck,programming, and verification operation.Addressing while in these modes is accomplished by placingthe upper 5 bits of address on pins 8, 7, 6, 5, and 4 withthe least significant bit on pin 8. These address bits areloaded into an onboard register by clocking pin 21, thelatch signal, from VILP to VIHP and back to VILP. Thelower 8 address bits are then placed on pins 8 through 1,with the least significant bit on pin 8. The upper 5 bitsremain in the onboard latch until a new value is loaded orpower is removed from the device. All 256 bytes addressedby the lower 8 bits may be accessed by sequencing thelower 8 addresses without changing the upper 5 bits or relatchingthe value in the onboard register.BlankcheckBlankcheck is accomplished by performing a verify cycle,sequencing through all memory address locations, whereall the data read will be "O"s.Programming AlgorithmProgramming is accomplished with an intelligent algorithm.The sequence of operations is to enter the programmingmode by placing Vpp on pin 19. This should be doneafter a minimum delay from power up, and be removedprior to power down by the same delay (see the timingdiagram and AC specifications for details). Once in thismode, programming is accomplished by addressing a locationas described above, placing the data to be programmedinto a location on the data pins, and clocking the PGMsignal from V IHP to V ILP and back to V IHP with a pulsewidth of 200 JJ.s. The data is removed from the data pinsand the content of the location is then verified by takingthe VFY signal from VIHP to VILP, comparing the outputwith the desired data and then returning VFY to VIHP. Ifthe contents are correct, a second overprogram pulse of 4times the original 200 JJ.s is delivered with the data to beprogrammed again on the data pins. If the data is not correct,a second 200 JJ.s pulse is applied to PGM with thedata to be programmed on the data pins. The compare andoverprogram operation is repeated with an overprogrampulse width 4 times the sum of the initial program pulses.This operation is continued until the location is programmedor 10 initial program pulses have been attempted.If on the 10th attempt, the location fails to verify, an overprogrampulse of 8 ms is applied, and the content of theAX7 1AX6 2AX5 3AX4/ AY12 4AX3/ AY11 5AX2/ AY10 6AX1/ AY9 7AXO/ AY8 8010 9011 10012 1124 Vce23 V FY22 PGM21 LATCH20 NA19 Vpp18 NA17 01716 016015014Vss 1213 0130052-8Figure 3. Programming Pinout (DIP Package)3-63

5'nCY7C261. CY7C263/CY7C264~UaoR~~~~~~~~~~~~~~~~~~~~~~====~~============~Programming Sequencelocation is once more verified. If the location still fails toverify, the device is rejected. Once a location verifies successfully,the address is advanced to the next location, andthe process is repeated until all locations are programmed.After all locations are programmed, they should be verifiedat Vccp = 5.0V.Operating ModesReadRead is the normal operating mode for a programmed device.In this mode, all signals are normal TTL levels. ThePROM is addressed with a 13 bit field, a chip select, (activeLOW), is applied to the CS pin, and the contents of theaddressed location appear on the data out pins.Program, Program Inhibit, Program VerifyThese modes are entered by placing a high voltage Vpp onpin 19, with pins 18 and 20 set to VILP. In this state, pin 21becomes a latch signal, allowing the upper 5 address bits tobe latched into an onboard register, pin 22 becomes anactive LOW program (PGM) signal and pin 23 becomes anactive LOW verify (VFY) signal. Pins 22 and 23 shouldnever be active LOW at the same time. The PROGRAMmode exists when PGM is LOW, and VFY is HIGH. TheVERIFY mode exists when the reverse is true, PGMHIGH and VFY LOW and the PROGRAM INHIBITmode is entered with both PGM and VFY HIGH. PRO­GRAM INHIBIT is specifically provided to allow data tobe placed on and removed from the data pins without conflict.BlankcheckBlankcheck mode is identical to PROGRAM VERIFYand is entered in the same manner as described above.The flowchart in Figure 4 is a detailed description of theintelligent programming cycle used to program the devicescovered in this specification. Of particular importance arethe areas of power sequencing used to enter and exit theprogramming operation. This flowchart combined with thetiming diagrams AC and DC parameters accurately describethis complete operation. Note should be taken of theinner and outer addressing loops which allow 256 bytes tobe programmed each time the onboard register containingthe upper 5 address bits is loaded.The timing diagram in Figure 5 contains all of the timinginformation necessary for describing the relations requiredfor programming the devices covered in this specification.Some of the information pertains to each cycle of programmingas specified in the inner loops of Figure 5, some forthe outer loop where the upper address is advanced, andsome pertains only to entry and exit from the programmingmode of operation.In particular, the timing sequence associated with theLatch signal on pin 21 and addresses A Y8 through AY12pertain only to the outer loop where the upper 5 (N in theflow chart) address bits are incremented.Tp, Tpo and THP refer to the entry and exit from theprogramming mode of operation. Note that this is referencedto LATCH, PGM and VFY operations.ToS, T AS, TAH and TOH refer to the required setup andhold times for the address and data for PGM and VFYoperations. These parameters must be adhered to, in alloperations, including VFY. This precludes the option thenof verifying the device by holding the VFY signal LOW,and sequencing the addresses.Table 1. Operating ModesPins 4 thru 8Pins 1 thru 3Pins 9 thru 11 Pins 13 thru 17 Pin Pin Pin Pin Pin PinModeA7-AS, AX7-AXS A4-AO, AX4-AXO DOthruD2 D3thruD7 18 19 20 21 22 23AY12-AY8Read A7 thru A5 A4thruAO DOOthruD02 D03 thruD07 Al2 All CS AlO A9 A8Program AX7 thruAX5 AX4thruAXO D10thru DI2 DI3 thru DI7VILP Vpp VILP LATAYI2-AY8 Input InputVILP VIHPProgram Inhibit AX7thruAX5 AX4thruAXOHighZ HighZ VILP Vpp VILP LATAYI2-AY8VIHP VIHPProgram Verify AX7 thruAX5 AX4thruAXO DOOthruD02 D03 thruD07 VILP Vpp VILP LATAYI2-AY8 Output OutputVIHP VILPBlank Check AX7thruAX5 AX4thruAXO DIothruDh DI3 thruDhVILP Vpp VILP LATAYI2-AY8 Output OutputVIHP VILP3-64

5nCY7C261. CY7C263/CY7C264~NDUcrOR =====================================================================Typical AC and DC CharacteristicsNORMALizED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.6NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.2 .-----,.------'---,NORMALIZED ACCESS TIMEvs. SUPPLY VOLTAGE1.2u...YQUJN:::i«:20::0z1.41.2./ V./1.00.8 ./VV TA = 25°Cf=MAX.0.64.0 4.5 5.0 5.5 6.01.11--~---+-----~OB'-----~--------I-55 25125UJ:2~(f)VIUJUu«QUJN:::i«:20::0Z1.2 t---- r--...080.60.44.0 4.5 5.0---r---TA =~50C5.5 6.0SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE (OC)SUPPLY VOLTAGE (V)NORMALIZED ACCESS TIMEvs. TEMPERATURE1.6...-----,.-------,UJ~ 1.41-----+-------1VI~~ 1.21-----+-------1«Q~ lDr---~~----~:::i«:2~ OBI-----+-------Iz0.6'------'---------1-55 25 125

~ CY7C261.r~UCfOR ================~C~Y~7~C~2~63~/~C~Y;.7~C~26~4Figure 4. Programming Flowchart0052-93-66

~REBSCY7C261CY7C263/CY7C264'nrCoNDucrOR =======================================================================_TpV PIN24VCCP------w-~------------------------------------------------------~CC V - SS Tr __- _TRVpP ________ +-~------------------------------------------------~Vpp PIN 19 V1HP - ----------t-If )1... ._________ TOp _______________-+1 I-- T HP_I ~ ,VSS- ~T opi- I I-T )-+jT OP ~---+- T HP ---+---------~TOp!+- I LP IVIHP----i--------t~--~.~--------~TH~-r-----r-------+--------~LATCH PIN 21VILP __ +-__...... n~ ~I~ ____ I--__ -+-__ +-___ +-______ _T ALH ~ ~--+- TAH --+-------+1T A;)~-----+l r-- T AH-+V'HP---=:l:T:AL:S-I~~;:)I+--~m:~",",rl· ...... -T-A_S-~®:;:x7t--I--I--lADDRESS V 'k- AY8-AY121LPl AXO-AX7 D-----_TOS-_TOHPROGRAM "1" "1" - TOZDATA V 1HP --=~=====-:I--------rurn:iN------I~DATA IN J--~ DATA OUT1LP!D------------DON'T PROGRAM "0" "0"I - _TOVV1HP ----Ir------------------------i-i.1 I~PGM PIN 22 V1LP-JvVrv PIN 23 IHPV1LP-J~ ...... TOV­I-Tpp __ 1r--Tvp-lFigure 5. Programming WaveformsNote: Power, V pp and Vee should not be cycled for each program verify cycle but remain static during programming_0052-103-67

WnCY7C261. CY7C263/CY7C264~NDUcrOR =======================================================================Table 2. DC Programming Parameters TA = 25°CParameter Description Min. Max. UnitsVpp Programming Voltage 12.0 13.0 VVeep Power Supply VoltageDuring Programming4.75 5.25 VIpp Vpp Supply Current 50 rnAVIHP Input High VoltageDuring Programming3.0 Veep VVILP Input Low VoltageDuring Programming-3.0 0.4 VVOH Output High Voltage 2.4 VVOL Output Low Voltage 0.4 VTable 3. AC Programming Parameters TA = 25°CParameter Description Min. Max. UnitsTAS Address Setup Time to PGM/VFY 1.0 /LsTAH Address Hold Time from PGM/VFY 1.0 /LsTDS Data Setup Time to PGM 1.0 /LsTDH Data Hold Time PGM 1.0 /LsTpp Program Pulse Width 0.2 10 msTR,F Vpp Rise and Fall Time 100 nsTALS Address Setup Time to Latch 1.0 /LsTALH Address Hold Time from Latch 1.0 /LSTLP Latch Pulse Width 1.0 /LsTDY Delay to Verify 1.0 /LsTYD Verify to Data Out 1.0 /LsTYH Data Hold Time from Verify 1.0 /LsTyp Verify Pulse Width 2.0 /LsTDZ Verify to High Z 1.0 /LsTDP Delay to Function 1.0 /LsTHP Hold From Function 1.0 /LsTp Power Up/Down 20.0 ms3-68

__.5ACY7C261CY7C263/CY7C264~ ~~UcrOR==================================================================Ordering InformationSpeed Ordering Package Operating Speed Ordering Package Operating(ns) Code Type Range (ns) Code Type Range35 CY7C261-35PC P13 Commercial 55 CY7C261-55PC Pl3 CommercialCY7C261-35WC W14 CY7C261-55WC W14CY7C263-35PC P13 CY7C263-55PC P13CY7C263-35WC W14 CY7C263-55WC W14CY7C264-35PC P13 CY7C264-55PC PllCY7C264-35WC Wl4 CY7C264-55DC D12CY7C264-35DC D12 CY7C264-55WC W1240 CY7C261-40PC P13 Commercial CY7C261-55WMB Wl4 MilitaryCY7C261-40WC W14 CY7C261-55DMB Dl4CY7C263-40PC P13 CY7C261-55LMB L64CY7C263-40WC Wl4 CY7C261-55QMB Q64CY7C264-40PC Pl1 CY7C263-55WMB Wl4CY7C264-40DC D12 CY7C263-55DMB Dl4CY7C264-40WC W12 CY7C263-55LMB L6445 CY7C261-45PC P13CY7C263-55QMB Q64CY7C261-45WC Wl4CY7C264-55DMB Dl2CY7C263-45PC P13CY7C264-55WMB W12CY7C263-45WC Wl4CY7C264-45PC PllCY7C264-45DC D12CY7C264-45WC Wl2CY7C261-45WMB W14 MilitaryCY7C261-45DMB D14CY7C261-45LMB L64CY7C261-45QMB Q64CY7C263-45WMB Wl4CY7C263-45DMB Dl4CY7C263-45LMB L64CY7C263-45QMB Q64CY7C264-45DMB Dl2CY7C264-45WMB W12I3-69

5ACY7C261. CYPRFSS CY7C263/CY7C264~~UaoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3IcC 1,2,3ISB[2] 1,2,3SubgroupsSwitching CharacteristicsParametersSubgroupstAA 7,8,9,10,11tHZCSl[l] 7,8,9,10,11tHZCS2[2] 7,8,9,10,11tACSl[l] 7,8,9,10,11tACS2[2] 7,8,9,10,11Notes:1. 7C263 and 7C264 only.2. 7C261 only.Document #: 38-00005-C3-70

Features• CMOS for optimum speed/power• High speed- 40 ns max set-up- 20 ns clock to output• Low power- 550 mW (commercial)- 660 mW (military)• On-chip edge-triggered registers- Ideal for pipelinedmicroprogrammed systems• On-chip diagnostic shift register- For serial observability andcontrollability of the outputregister• EPROM technology- 100% programmable- Reprogrammable (7C269W)• 5V ± 10% Vee, commercial andmilitary• Capable of withstanding greaterthan 2001 V static discharge• Slim, 300 mil 28 pin plastic orhermetic DIP (7C269)CYPRESSSEMICONDUCTORFunctional DescriptionCY7C268CY7C26964 K RegisteredDiagnostic PROMThe CY7C268 and CY7C269 are 64KRegistered Diagnostic PROMs. Theyare both organized 8192 words by 8bits wide, and have both a PipelineOutput Register and an Onboard DiagnosticShift Register. In addition, bothdevices feature a Programmable InitializeByte which may be loaded into thePipeline Register with the Initialize signal.The Programmable Initialize Byteis the 8l93rd byte in the PROM and itsvalue is programmed at time of use.The 7C268 has 32 pins and features fulldiagnostic capabilities while the 7C269provides limited diagnostics and isavailable in a space efficient 28 pinpackage. This allows the designer tooptimize his design for either boardarea efficiency with the 7C269, or combinethe 7C268 with other diagnosticproducts with the standard interface.CY7C268: The 7C268 provides 13 addresssignals (Ao through A12), 8 dataout signals (00 through 07), ENA (enable),PCLK (pipeline clock) and INIT(initialize) for control. The full standardfeatured diagnostics of the 7C268utilizes the SI and SO (shift in and shiftout), MODE and DCLK signals. Thesesignals allow serial data to be shiftedinto and out of the Diagnostic ShiftRegister at the same time the PipelineRegister is used for normal operation.The MODE signal is used to controlthe transfer of the information in theDiagnostic Register to the PipelineRegister or the data on the Output Businto the Diagnostic Register. The dataon the Output Bus may be providedfrom the Pipeline Register or an externalsource.When the MODE signal is LOW, thePROM operates in a normal pipelinemode. The contents of the addressedmemory location is loaded into thePipeline Register on the rising edge ofPCLK. The outputs are enabled withthe ENA signal either synchronouslyor asynchronously, depending on howthe device is configured when programmed.If programmed for asynchronousenable, ENA LOW enablesIILogic Block DiagramPin ConfigurationsCY7C268CY7C269A7AsA.A3A2NODEVr:;cA8AtNCA'2501A,DA11AuE/Es.T501SDO0 70112-2DCLK(7e288)0112-30112-1'4"~.t~~~.t'4 3 2: 1 :32 31 30••• 29 A3 5 AIDA2 628 A11ENANODE 727NC 8DCLK 9 CY7C26826 iNif25 MCPCLK 10A, 112' A'223 501Ao 1222 SDO0 0 13 21 071415161718 19200'" C"

(;nCY7C268... CY7C269~~u~==================================================================Selection GuideMaximum Set-up Time (ns)Maximum Clock to Output (ns)Maximum Operating I CommercialCurrent (mA)MilitaryFunctional Description (Continued)the outputs. If configured for synchronous enable, ENALOW during the rising edge of PCLK will enable the outputssynchronously with PCLK. ENA HIGH during therising edge of PCLK will synchronously disable the outputs.The asynchronous Initialize signal INIT transfers theInitialize Byte into the Pipeline Register on a HIGH toLOW transition. INIT LOW disables PCLK and needs totransition back to a HIGH in order to enable PCLK.DCLK shifts data into SI and out of SO on each risingedge.When MODE is HIGH, the rising edge of the PCLK signalloadsthe Pipeline Register with the contents of theDiagnostic Register. Similarly, DCLK, in this mode, loadsthe Diagnostic Register with the information on the DataOutput Pins. The information loaded will be either the contentsof the Pipeline Register if the outputs are enabled, ordata on the bus, if the outputs are disabled (in a high impedancestate).CY7C269: This product is optimized for applications thatrequire diagnostics in a minimum amount of board area.Packaged in 28 pins, the PROM has 13Addtess Signals(Ao through A12), 8 Data Out Signals (00 through 07), Ell,(Enable or Initialize) and CLOCK (pipeline and diagnosticclock). Additional diagnostic signals consist of MODE, SI(shift in) and SO (shift out). Normal pipelined operationand Diagnostic operation are mutually exclusive.When the MODE signal is LOW, the 7C269 operates in anormal pipelined mode. CLOCK functions as a pipelineclock, loading the contents of the addressed memory locationinto the Pipeline Register on each rising edge. Thedata will appear on the Outputs if they are enabled. Onepin on the 7C269 is programmed to perform either theI7C268/9-40 7C268/9-50 7C268/9-6040 50 6020 25 25100 80 80120 100Enable or the Initialize function. If the Ell pin is used for aINIT (Asynchronous Initialize) function, the outputs arepermanently enabled and the Initialize Word is loaded intothe Pipeline Register on a High to LOW transition of theINIT signal. The INIT LOW disables CLOCK and mustreturn high to re-enable CLOCK. If the Ell pin is used foran enable signal, it may be programmed for either synchronousor asynchronous operation. This enable function thenoperates exactly the same as the 7C268.When the MODE signal is HIGH, the 7C269 operates inthe diagnostic mode. The Ell signal becomes a· secondarymode signal designating whether to shift the DiagnosticShift Register or to load either the Diagnostic Register orthe Pipeline Register. If Ell is HIGH, CLOCK performsthe function of DCLK, shifting SI into the least significantlocation of the Diagnostic Register and all bits one locationtoward the most significant location on each rising edge.The contents of the most significant location in the DiagnosticRegister are available on the SO pin.If the Ell signal is LOW, SI becomes a direction signal;transferring the contents of the Diagnostic Register intothe Pipeline Register when SI is LOW. When SI is HIGH,the contents of the Output pins are transferred into theDiagnostic Register. Both transfers occur on a LOW toHIGH transition of the CLOCK. If the Outputs are enabled,the contents of the Pipeline Register are transferredinto the Diagnostic Register. If the Outputs are disabled,an external source of data may be loaded into the DiagnosticRegister. In this condition, the SO signal is internallydriven to be the same as the Sl signal thus propagating the"direction of transfer information" to the next device in thestring.3-72

5nCY7C268. CY7C269~NDUCTOR =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential .... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to +7.0VDC Input Voltage ................... - 3.0V to + 7.0VDC Program Voltage .......................... 14.0VElectrical Characteristics Over the Operating Rangd2]Parameters Description Test ConditionsStatic Discharge Voltage ..................... >200IV(per MIL-STD-883, Method 3015)Latchup Current .......................... > 200 rnAUV Exposure ........................... 7258 Wsec/cOperating RangeRangeAmbientTemperatureVeeCommercial O°C to 70°C 5V ± 10%Military[l] - 55°C to + 125°C 5V ± 10%CommercialMilitaryMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = -2mA 2.4 2.4 VVOLOutput LOW VoltageVee = Min.,loL = 12 rnA(IOL = 8 rnA for Military)Units0.4 0.4 VVIH Input HIGH Voltage 2.0 2.0 VVIL Input LOW Voltage 0.8 0.8 VIIX Input Load Current GND::;: VIN::;: Vee 10 10 J-lAlozlosOutput LeakageCurrentOutput Short CircuitCurrentGND ::;: VOUT ::;: VeeOutput Disabled40 40 J-lAVee = Max., VOUT = GND 90 90 rnAVee Operating Supply Vee = Max.7C268/9-40 100lee Current lOUT = OmA 7C268/9-50 80 120 rnACapacitance [2]7C268/9-60 80 100Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 5COUTOutput CapacitanceVee = 5.0V8Switching Characteristics Over the Operating Range[3]7C268·40 7C268·50 7C268·60Parameters Description 7C269·40 7C269·50 7C269·60 UnitsMin. Max. Min. Max. Min. Max.tAS Address Set-Up to Clock 40 50 60 nstHA Address Hold from Clock 0 0 0 nsteo Clock to Output Valid 20 25 25 nstpw Clock Pulse Width 15 20 20 nstSES ES Set-Up to Clock (Sync Enable Only) 15 15 15 nstHES ES Hold from Clock 5 5 5 nstm Init to Out Valid 25 35 35 nstRI Init Recovery to Clock 20 25 25 nspF3-73

(inCY7C268. CY7C269~U~==================================================================Switching Characteristics Over the Operating Range[3] (Continued)7C268·40 7C268·50 7C268·60Parameters Description 7C269·40 7C269·50 7C269·60 UnitsMin. Max. Min. Max. Min. Max.tpwI Init Pulse Width 25 35 35 nstcos Output Valid from Clock (Sync. Mode) 20 25 25 nstHZC Output Inactive from Clock (Sync. Mode) 20 25 25 nstOOE Output Valid from E Low (Async. Mode) 20 25 25 nstHZE Output Inactive from E High (Async. Mode) 20 25 25 nsDiagnostic Mode Switching Characteristics Over the Operating Range!2]ParameterstSSDItHSDItosoOtOCLtOCHtSMtHMtMStsstsoDescriptionSet-Up SDI to ClockSDI Hold from ClockSDO Delay from ClockMinimum Clock LowMinimum Clock HighSet-Up to Mode ChangeHold from Mode Change (7C269)Mode to SDOSDIto SDOData Set-Up to DCLKtHOData Hold from DCLKNotes:1. T A is the "instant on" case temperature.2. See the last page of this specification for Group A subgroup testinginformation.AC Test Loads and WaveformsCommercialMilitaryMin. Max. Min. Max.Units30 35 ns0 0 ns30 40 ns25 25 ns25 25 ns25 30 ns0 0 ns25 30 ns40 45 ns25 30 ns10 15 ns3. Tested initially and after any design or process changes that mayaffect these parameters.5VOUTPUTR133811R133805V(5000 FOR MIL) (SOOI1 FOR MIL)OUTPUTR2R250pF 24811 5pF 2480(3330 FOR MIL)(3330 FOR MIL)IINCLUDING I INCLUDINGJIG AND_JIGAND _0112-6-= SCOPE -= - SCOPE -ALL INPUT PULSES3.0 v-----.i!"""""---"'"'!!LGND.. 5ns0112-71430(2000 FOR MIL) 2.11VOUTPUT ~ (2.0VFORMIL)0112-83-74

finCY7C268. CY7C269~NDUCTOR ==================================================================~Switching Waveforms 7C268, 7C269Pipeline Operation (Mode = 0)ADDRESS-------------------SYNCHRONOUS ENABLE(PROGRAMMABLE) _____ -'IPCLK / CLOCK (7C269)-----~I--'lOUTPUT~~~-----+---"ASYNCHRONOUS /ENABLE ______ -"Notes on Testing:Incoming test procedures on these devices should be carefully planned,taking into account the high performance and output drive capabilities ofthe parts. The following notes may be useful.1. Ensure that adequate decoupling capacitance is employed across thedevice Vee and ground terminals. Multiple capacitors are recommended,including a 0.1 p,F or larger capacitor and a 0.01 p,F orsmaller capacitor placed as close to the device terminals as possible.Inadequate decoupling may result in large variations of power supplyvoltage, creating erroneous function or transient performance failures.2. Do not leave any inputs disconnected (floating) during any tests.,'--------'0112-93. Do not attempt to perform threshold tests under AC conditions.Large amplitude, fast ground current transients normally occur as thedevice outputs discharge the load capacitances. These transients flowingthrough the parasitic inductance between the device ground pinand the test system ground can create significant reductions in observableinput noise immunity.4. Output levels are measured at 1.5V reference levels.5. Transition is measured at steady state HIGH level - 500 m V orsteady state LOW level + 500 mV on the output from the 1.5V levelon inputs with load shown in Figure lb.II7C268 Diagnostic WaveformsDCLK_~__________________ JSOlSOO-~-----MODEPCLK ____ IOUTPUT-------------------"0112-103-75

511CY7C268.. CY7C269~~NDUCTOR ~======================================~==~~~~~~~~~~~~~~==Switching Waveforms (Continued)7C269 Diagnostic Application (Shifting the Shadow Register)CLOCK---""'1MOOESOO-"""'--1"'"SOl __ ~ ____ ~ ____________ JIEIT0112-117C269 Diagnostic Application (Parallel Data Transfer)CLOCK-----+-"'1MOOESOlSOO __________-+~______ JIEITNotes:6. Asynchronous enable mode only.teo t0 0-°7 _________ E OUTDevice ProgrammingThe CY7C268 and CY7C269 program identically. Theyutilize an intelligent programming algorithm to assure consistentprogramming quality. These 64K PROMS use asingle ended memory cell design. In an unprogrammedstate, the memory contains all "O"s. During programming,a "I" on a data-in pin causes the addressed location to beprogrammed, and a "0" causes the location to remain unprogrammed.0112-127. The mode transition to HIGH latches the asynchronous enable state.If the enable state is changed and held before leaving the diagnosticmode (mode H --. L) then the output impedance change delay istMS·Programming PinoutThe Programming Pinout of both devices is shown in Figures3a and 3b. The programming mode is entered by putting12.5V on the Vpp pin. The addressed location is programmedand verified with the application of a PGM andVFY pulse. Entering and exiting the programming modeshould be done with care. Proper sequencing as describedin the dialog on the programming algorithm and shown inthe timing diagram and programming flow chart must beimplemented.3-76

CY7C268CY7C269A7AsAsA4A3A2PGMCLOCKAlAoAsA 10A11A12VppSDIVFY°7OsOsD4D30112-13Figure 3a. 7C268 Programming PinoutProgramming and Blankcheck (Memory Bits)BlankcheckBlankcheck is accomplished by performing a verify cycle(VFY toggles on each address), sequencing through allmemory address locations, where all the data read will be"O"s. (Refer to mode table for pin states)Programming AlgorithmProgramming is accomplished with an intelligent algorithm.The sequence of operations is to enter the programmingmode by placing 12.SV on Vpp. This should be doneafter a minimum delay from power up, and be removedprior to power down by the same delay (see the timingdiagram and AC specifications for details). Onc~ in thismode, programming is accomplished by addressmg a locationas described above, placing the data to be programmedinto a location on the data pins, and clocking the PGMsignal from V IHP to V ILP and back to V IHP with a p~lsewidth of 200 fJ-s. The data is removed from the data pmsand the content of the location is then verified by takingthe VFY signal from VIHP to VILP, comparing the outputwith the desired data and then returning VFY to V IHp. Ifthe contents are correct, a second overprogram pulse of 4times the original 200 fJ-s is delivered with the data to beprogrammed again on the data pins. If the data is not correct,a second 200 fJ-s pulse is applied to PGM with thedata to be programmed on the data pins. The compare andoverprogram operation is repeated with an overprogrampulse width 4 times the sum of the initial program pulses.This operation is continued until the location is programmedor 10 initial program pulses have been attempted.If on the 10th attempt, the location fails to verify, an overprogrampulse of 8 ms is applied, and the ~onte~t o~ thelocation is once more verified. If the 10catlOn still falls toverify, the device is rejected. Once a location verifies successfully,the address is advanced to the next location, andthe process is repeated until all locations are programmed.Figure 3b. 7C269 Programming Pinout0112-14After all locations are programmed, they should be verifiedat V ccp = S.OV.Programming Algorithm for the ArchitectureBoth the 7C268 and 7C269 offer a limited selection of programmedarchitecture. Programming these features shouldbe done with a single 10 ms wide pulse in place of theintelligent algorithm mainly because these features are verifiedoperationally, not with the VFY pin. Architecture programmingis implemented by applying the supervoltage totwo additional pins during programming. In programmingthe 7C269 architecture Vpp is applied to pins 3, 9 and 22while in programming the 7C268 architecture Vpp is appliedto pins 3, 11, 26. Specific choice of a particular modewill depend on the states of the other pins during programmingso it is important that the condition of the oth~r pinsbe met as set forth in the mode table. The same consIderationswith respect to power up and power down apply duringarchitecture programming as during intelligent ~rogramming.Once the supervoltages have been estabhshedand the correct logic states exist on the other device pins,programming may begin. Programming is accomplished bypulling PGM from HIGH to LOW and then back toHIGH with a pulse width equal to 10 ms.To check whether a 7C269 has been programmed as outputenable or initialize enable, pin 22 (Ell) should be pulledLOW followed by a LOW to HIGH transition on pin 8(CLOCK). The data read at the outputs is stored and complementdata is shifted into the shadow register. A shift.from shadow to pipeline is performed and the CLOCK ISagain pulled from LOW to HIGH. At this point, if the newdata read is data-complement, the device has been programmedas Output enable while if the new data read-truethen the device is programmed as Initialize enable and theconfiguration of the Initialize byte can be read directly bypulling Ell from HIGH to LOW.II3-77

~CY7C268CY7C269~~~UaoR==================================================================Mode Table 7C268Mode SelectP7P2 P3 P30 P6P9MOA6 AS A9 A2 OCLKPGMNormal Read[2] A6 A5 A9 A2 L XLoad SR to PR[2] A6 A5 A9 A2 H LLoad Output to SR A6 A5 A9 A2 H L/HShift Shadow[2] A6 A5 A9 A2 L L/HProgram (Memory) A6 A5 A9 A2 L LProgram Verify A6 A5 A9 A2 H LProgram Inhibit A6 A5 A9 A2 H LAsync. Enable Read A6 A5 A9 A2 L LSync. Enable Read A6 A5 A9 A2 L LAsync. Init. Read A6 A5 A9 A2 L LProgram Sync. Enable[l] H VHH X H L LProgram Initial Byte H VHH X L L LNotes:I. Default is Async. Enable.2. For the a~nchronous enable operation, the data out is enabled bybringing E LOW. For the synchronous enable operation, data out isenabled on the first LOW to HIGH clock transition after E is broughtMode Table 7C269Mode SelectNormal ReadLoad SR to PR[3]Load Output to SR[3]Shift Shadow[3]Program (Memory)Program VerifyProgram InhibitAsync. Enable ReadSync. Enable ReadAsync. Init. ReadProgram Sync. Enable[l]Program Initialize[2]Program Initial ByteNotes:I. Default is Async. Enable.2. Default is Enable.P2A6A6A6A6A6A6A6A6A6A6A6HHHP3ASA5A5A5A5A5A5A5A5A5A5VHHVHHVHHP26A9P6A2P7MOPGMA9 A2 LA9 A2 HA9 A2 HA9 A2 HA9 A2 LA9 A2 HA9 A2 HA9 A2 LA9 A2 LA9 A2 LA9 H LA9 L LA9 L LP22P26PtO PU Pt2 P23 P24 P27 P28SOOINTPCLK At AO SOl A12VFYVppE/Es AUL/H Al AD SDO X Al2 H H/L AllL/H Al AD SDI X Al2 H X AllL Al AD SDI L Al2 H H AllL Al AD SDO DIN Al2 H X AllL Al AD H L Al2 Vpp H AllL Al AD L L Al2 Vpp H AllL Al AD H L Al2 Vpp H AllX Al AD SDO L Al2 H H/L AllL/H Al AD SDO L Al2 H H/L AllX Al AD SDO L Al2 L L AllL VHH L H L H Vpp H HL VHH H H L X Vpp H LLOW. When E goes from LOW to HIGH (enable to disable) the outputswill go to the high impedance state (after a propagation delay) immediatelyif the asynchronous enable was programmed. If the synchronousenable was selected, a LOW to HIGH clock transition is required.P8 P9 PtO P2tCLK At AO SOlP20SOOVFYP24AUP22E/IVppP23A12L/H Al AD X HIZ All H/L Al2L/H Al AD L SDI All L Al2L/H Al AD H SDI All L Al2L/H Al AD DIN SDO All H Al2L Al AD X H All Vpp Al2L Al AD X L All Vpp Al2L Al AD X H All Vpp Al2L Al AD X HIZ All L Al2L/H Al AD X HIZ All L Al2L Al AD X HIZ All L Al2L VHH L X H H Vpp HL VHH L X H H Vpp LL VHH H X H L Vpp Al23. Iff selected, outputs always enabled. IfE selected, during diagnosticoperation the data outputs will remain in the state they were in whenthe mode was entered. When enabled, the data outputs will reflect theoutputs of the pipeline register. Any changes in the data in the pipelineregister will appear on the data output pins.3-78

5J1CY7C268. CY7C269~NDUcrOR ======================================================~====~====~DC Programming Parameters TA = 25°CParameter Description Min. Max. UnitsVpp Programming Voltage 12.0 13.0 VVccp Power Supply Voltage During Programming 4.75 5.25 VIpp Vpp Supply Current 50 rnAVIHP Input High Voltage During Programming 3.0 VVILPInput Low Voltage During Programming-3.0 0.4 VVOHOutput High Voltage2.4 VVOLOutput Low Voltage0.4 VAC Programming Parameters TA = 25°CParameterDescriptiontppProgram Pulse Width (Per Byte)tASAddress Set-up TimetAHAddress Hold TimetnHData Hold TimetnsData Set-up TimetR,FV pp Rise and Fall TimetnvDelay to VerifytvnVerify to Data OuttVHData Hold Time from VerifytvpVerify Pulse WidthtnzVerify to High ZMin. Max. Units10.0 ms1.0 /-LS1.0 /-Ls1.0 /-Ls1.0 /-Ls1.0 /-Ls1.0 /-LS1.0 /-Ls1.0 /-LS2.0 /-Ls1.0 /-LsIIErasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the 7C268 and 7C269 in the windowed package. Forthis reason, an opaque label should be placed over the windowif the PROM is exposed to sunlight or fluorescentlighting for extended periods of time.The recommended dose of ultraviolet light for erasure is awavelength of2537 Angstroms for a minimum dose (UVBitMap DataProgrammer AddressDecimalHex0 0• •8191 IFFF8192 20008193 2001Control Byteintensity X exposure time) or 25 Wsec/cm2. For an ultravioletlamp with a 12 mW Icm2 power rating the exposuretime would be approximately 45 minutes. The 7C268 or7C269 needs to be within 1 inch of the lamp during erasure.Permanent damage may result if the PROM is exposedto high intensity UV light for an extended period oftime. 7258 Wsec/cm 2 is the recommended maximum dosage.RAM DataContentsDATA•DATAINITBYTECONTROL BYTE00 Asynchronous output enable (default condition)01 Synchronous output enable02 Asynchronous initialize (CY7C269 only)3-79

fijiCY7C268CY7C269~IOO~UaoR==================================================================• CYPRESSFigure 4. Programming Flowchart0112-153-80

finCY7C268CY7C269~~NDUcrOR =====================================================================Vee7C268 PIN 327C269 PIN 28Vpp7C268 PIN 267C269 PIN 22~------------tDP------------~ADDRESSDATAVllP -tDS-------lV1HP _I______ I,..-___ P_R_O_G_R_AM_"_'_" __--\IPGM7C268 PIN 77C269 PIN 7V llPVrv7C268 PIN 227C269 PIN 20 V llPFigure 5. Programming Waveforms (Memory)0112-16Note:Power, Vpp and Vee should not be cycled for each program verify cycle but remain static during programming.VeePIN·Vpp~-------tDP--------~~--------tHP--------~PINS"(Ppp ALSO)ADDRESSDATA···PIN7PGMV ___1HPV 1lP ---V OHPVOlPV 1HPVllP0112-17"7C268-pin 267C269-pin 22**7C268-pins 3, 117C269-pins 3, 9"" "Data required on I/O's only during initial byte programmingFigure 6. Programming Waveforms for the Architecture CY7C268 and CY7C2693-81

(inCY7C268. CY7C269~UcrOR =====================================================================Typical DC and AC CharacteristicsNORMALIZED SUPPLYCURRENT vs. SUPPLYVOLTAGE1.6NORMALIZED SUPPLYCURRENT vs. AMBIENTTEMPERATURE1.2r------r--------,NORMALIZED ACCESS TIMEvs. TEMPERATURE1.6 r------r--------,0..YSN::::;""~0z1.41.21.00.8V.,V0.64.0 4.5 5.0 5.5 6.0/VTA = 25°Cf=t.4AX.~SN~oz0.8~-----L--------~-55 25 1251.41-----+-------11.21-----+---~~--11.0 I------::;;~"-----__l0.81-----+-------10.6 I--____ --I.. ________ ....J-55 25 125SUPPLY VOLTAGE (V)At.4BIENT TEt.4PERATURE (OC)At.4BIENT TEt.4PERATURE (OC)~~~~:::lU\oJ~:::l0en0-:::lQ..0-:::l0OUTPUT SOURCECURRENT vs. VOLTAGE605040302010o" " "- ~","0.0 1.0 2.0 3.0 4.0OUTPUT VOLTAGE(V)Ordering InformationSpeed Icc Ordering Package(ns) (rnA) Code Type40 100 CY7C268-40DC D20CY7C268-40WCCY7C269-40PCCY7C269-40DCCY7C269-40WCW20P21D22W2250 80 CY7C268-50DC D20CY7C268-50WCCY7C269-50PCCY7C269-50DCCY7C269-50WCW20P21D22W22120 CY7C268-50DMB D20CY7C268-50WMBCY7C268-50LMBCY7C268-50QMBCY7C269-50DMBCY7C269-50WMBCY7C269-50LMBCY7C269-50QMBW20L55Q55D22W22L64Q641J~~TYPICAL ACCESS TIMECHANGE vs. OUTPUTLOADING30.025.020.015.010.0V/V/'V5.00.0T A -25OCV ee =4.5V() 200 400 600 800 1000CAPACITANCE (pF)Operating Speed IccRange (ns) (rnA)Commercial 60 80Military100'it:'~IX:::lUlI

iACY7C268.. CYPRESS CY7C269~ s~~O~UcrOR~~~~~~~~~~~~~~~~~~~~~~~==================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3Vm 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3ICC 1,2,3ISH 1,2,3SubgroupsSwitching CharacteristicsParametersSubgroupstAS 7,8,9,10,11tHA 7,8,9,10,11tco 7,8,9,10,11tpw 7,8,9,10,11tSES 7,8,9,10,11tHES 7,8,9,10,11tcos 7,8,9,10,11Diagnostic Mode SwitchingCharacteristicsParametersSubgroupstSSDI 7,8,9,10,11tHSDI 7,8,9,10,11tDSDO 7,8,9,10,11tDCL 7,8,9,10,11tDCH 7,8,9,10,11tHM[I] 7,8,9,10,11tMS 7,8,9,10,11tss 7,8,9,10,11'lote:l. 7C269 only.Document #: 38-000693-83

PRELIMINARYCY7C271Features• CMOS for optimumspeed/power• Windowed for reprogrammability• High speed- 45 ns (commercial)- 55 ns (military)• Low power- 660 mW (commercial)- 715 mW (military)• Super low standby power- Less than 165 mW whendeselected• EPROM technology100% programmable• 5V ± 10% Vee, commercialand military• TTL compatible I/O• Slim 300 mil packageLogic Block Diagram• Direct replacement forbipolar PROMs• Capable of withstanding> 2001V static dischargeProduct CharacteristicsThe CY7C271 is a high performance32,768 word by 8 bit CMOS PROM.When deselected, the 7C271 automaticallypowers down into a low powerstandby mode. It is packaged in the 300mil slim package. The 7C271 reprogrammableCERDIP package isequipped with an erasure window;when exposed to UV light, the PROMis erased and can then be reprogrammed.The memory cells utilizeproven EPROM floating gate technologyand byte-wide intelligent programmingalgorithms.32,768 X 8 PROMPower Switched andReprogrammableThe CY7C271 is a plug-in replacementfor bipolar devices and offers the advantagesoflower power, superior performanceand programming yield. TheEPROM cell requires only 12.SV forthe supervoltage and low current requirementsallow for gang programming.The EPROM cells allow for eachmemory location to be tested 100%, aseach location is written into, erased,and repeatedly exercised prior to encapsulation.Each PROM is also testedfor AC performance to guarantee thatafter customer programming the productwill meet DC and AC specificationlimits.Reading is accomplished by placing activeLOW signals on CSt, and CE andan active HIGH on CS2. The contentsof the memory location addressed bythe address lines (Ao-At4) will becomeavailable on the output lines (00-07).Pin Configurations0102-2AS 5029 A12A4 6 28 A 13A3 7 27 Au.A2 8 26CS,A, 9 25 CS 2Ao 10 24 CENe 11 23 Ne0 0 12 22 070, 13 21 0 6141516171819200102-1NO U')"'o .... II')oz-%,ozoo0102-3Selection GuideMaximum Access Time (ns)Maximum OperatingCurrent (rnA)Standby Current (rnA)7C271-4545Commercial 120MilitaryCommercial 30Military7C271-55 7C271·6555 65120 120130 13030 3040 403-84

~ PRELIMINAR Y CY7C271~~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential .... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VDC Input Voltage ................... -3.0V to +7.0VDC Program Voltage .......................... 14.0VElectrical Characteristics Over the Operating Range[S]Parameters Description Test ConditionsStatic Discharge Voltage ..................... > 2001 V(per MIL-STD-883, Method 3015)Latchup Current .......................... > 200 rnAUV Exposure ........................ 7258 Wsec/cm2Operating RangeRangeAmbientTemperatureVeeCommercial O°C to + 70°C 5V ± 10%Military [4] - 55°C to + 125°C 5V ± 10%7C271-45 7C271-55 7C271-65Min. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = - 2.0 rnA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 12.0 rnA * 0.5 0.5 0.5 VVIH Input HIGH Level[I] 2.0 Vee 2.0 Vee 2.0 Vee VVIL Input LOW Level[l] 0.8 0.8 0.8 VIIX Input Current GND s VIN s Vee -10 +10 -10 + 10 -10 +10 /-LAVeDlozlOSleeISB8.0 rnA military:::!apacitance [6]Input Diode ClampVoltageOutput LeakageCurrentOutput ShortCircuit Currentl3]VOL s VOUT s VOH,Output DisabledVee = Max., VOUT = GNDNote 2 Note 2 Note 2Units-40 +40 -40 +40 -40 +40 /-LA-20 -90 -20 -90 -20 -90 rnAPower Supply Vee = Max., VIN = 2.0V Commercial 120 120 120 rnACurrentlOUT = OmAMilitary 130 130 rnAStandby Supply Vee = Max., CS ;;::: VIH Commercial 30 30 30 rnACurrentlOUT = OmAMilitary 40 40 rnAParameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C,f= 1 MHz 8COUTOutput CapacitanceVee = 5.0V8~otes:. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment.. The eMOS process does not provide a clamp diode. However, theeY7e271 is insensitive to - 3V dc input levels and - SV undershootpulses ofless than 10 ns (measured at 50% point).3. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.4. T A is the "instant on" case temperature .5. See the last page of this specification for Group A subgroup testinginformation.6. Tested initially and after any design or process changes that mayaffect these parameters.pF3-85

~ PRELIMINAR Y CY7C271~~~NDUcroR ==================================================~====~====~==~Switching Characteristics Ov~r the Operating Range[S, 71ParameterstAAtHZCStACStHZCEtACEtputpDDescriptionAddress to Output ValidChip Select Inactive to High Z[S](CSl and CS2 Only)Chip Select Active to Output Valid(CSl and CS2 Only)Chip Enable Inactive to High Z[S](CEOnly)Chip Enable Active toOutput Valid (CE Only)Chip Enable Active to Power UpChip Enable Inactive to Power DownMin.07C27l·45 7C27l·55 7C27l·65Max. Min. Max. Min. Max.Units45 55 65 ns30 35 40 ns30 35 40 ns50 60 70 ns50 60 70 ns0 0 ns50 60 70 nsAC Test Loads and WaveformsRl319.0.5Vj1(470.o.MIL)OUTPUT30pFINCLUDING IJIG AND~~6.o.(319.0. MIL)Rl319.0.5V;Fi(470.o. MIL)OUTPUT5pFINCLUDING IJIG ANDSCOPE -= -= SCOPE -= -=Equivalent to:Figure laTHEVENIN EQUIVALENTFigure lb~~6.o.(319.0. MIL)0102-43.0V~%GND 10% 10%~Sns- ~Figure 2. Input Pulses~ ~Sns0102-6136.0.OUTPUT ~ 2.13 COMMERCIAL190.0.OUTPUT ~ 2.02 MILITARYVecSUPPLYCURRENTAo- AUADDRESS )~-0102-5tpDl-SO%-tpu~ POWER DOWN CONTROLLED BY C1f-SO%-t AA ... tHzeS(E) --)'(I--tACS(E)Notes:7. Test conditions assume signal transition times of S ns or less, timingreference levels of I.SV, output loading of the specified IorJ10H andloads shown in Figure la, 1 h.Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the 7C271 in the windowed package. For this reason,an opaque label should be placed over the window if thePROM is exposed to sunlight or fluorescent lighting forextended periods of time.The recommended dose of ultraviolet light for erasure is awavelength of2537 Angstroms for a minimum dose (UV0102-7S. tHZCS(E) is tested with load shown in Figure 1 h. Transition is measuredat steady state High level - 500 m V or steady state Low level+ SOO m V on the output from the 1.5 level on the input.intensity X exposure time) or 25 Wsec/cm2. For an ultra·violet lamp with a 12 mW Icm 2 power rating the exposuretime would be approximately 45 minutes. The 7C271 needsto be within 1 inch of the lamp during erasure. Permanentdamage may result if the PROM is exposed to high intensityUV light for an extended period oftime. 7258W Xsec/cm2 is the recommended maximum dosage.3-86

~ PRELIMINAR Y CY7C271~~~UcrOR =====================================================================Table 2. DC Programming Parameters T A = 25°CParameters Description Min. Max. UnitsVpp Programming Voltage 12.0 13.0 VVeepPower Supply VoltageDuring Programming4.75 5.25 VIpp Vpp Supply Current 50 rnAVIHPVILPInput High VoltageDuring ProgrammingInput Low VoltageDuring Programming3.0 Veep V0.4 VVOH Output High Voltage 2.4 VVOL Output Low Voltage 0.4 V•Table 3. AC Programming Parameters TA = 25°CParameters Description Min. Max. UnitsTAS Address Setup Time to PGM/VFY 1.0 J-tsTAH Address Hold Time from PGM/VFY 1.0 J-tsTns Data Setup Time to PGM 1.0 J-tsTnH Data Hold Time PGM 1.0 J-tsTpp Program Pulse Width 0.1 10 msTR,F Vpp Rise and Fall Time 100 J-tsTnv Delay to Verify 1.0 J-tsTvn Verify to Data Out 1.0 J-tsTVH Data Hold Time from Verify 1.0 J-tsTvp Verify Pulse Width 2.0 J-tsTnz Verify to High Z 1.0 J-tsTp Power Up/Down 20.0 ms7C271 Programming Pin-OutAgVeeAs A 10A7 A"A6AsA4A3A12A'3A'4VppA2PGMA, VFYAo °7°0 °6°1 °5°2 °4Vss °30102-83-87

~ PRELIMINARY CY7C271~~~NDUcrOR =====================================================================PROGRAM1------ PROGRAM-------

~CYPRISS PRELIMINARY CY7C271~~~CO~UcrOR============================================================~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIR 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3ISB 1,2,3Subgroup&Switching CharacteristicsParameters SubgroupstAA 7,8,9,10,11tACS 7,8,9,10,11tACE 7,8,9,10,11Document #: 38-00068-BD3-89

Features• CMOS for optimum speed!power• High speed- 30 ns (commercial)- 45 ns (military)• Low power- 495 mW (commercial)- 660 mW (military)• EPROM technology 100%programmable• Slim 300 or standard 600 milDIP or 28 pin LCC• 5V ± 10% Vee, commercial andmilitary• TTL compatible I/O• Direct replacement for bipolarPROMsLogic Block DiagramCYPRESSSEMICONDUCTOR• Capable of withstanding> 1500V static dischargeProduct CharacteristicsThe CY7C281 and CY7C282 are highperformance 1024 word by 8 bit CMOSPROMs. They are functionally identical,but are packaged in 300 mil and600 mil wide packages respectively.The CY7C281 is also available in a 28pin leadless chip carrier. The memorycells utilize proven EPROM floatinggate technology and byte-wide intelligentprogramming algorithms.The CY7C281 and CY7C282 are pluginreplacements for bipolar devices andoffer the advantages of lower power,superior performance and programmingyield. The EPROM cell requiresonly 13.5V for the supervoltage andCY7C281CY7C2821024 x 8 PROMlow current requirements allow forgang programming. The EPROM cellsallow for each memory location to betested 100%, as each location is writteninto, erased, and repeatedly exercizedprior to encapsulation. Each PROM isalso tested for AC performance toguarantee that after customer programmingthe product will meet DC andAC specification limits.Reading is accomplished by placing anactive LOW signal on CSl and CS2,and active HIGH signals on CS3 andCS4. The contents of the memory locationaddressed by the address lines(Ao-A9) will become available on theoutput lines (00-07).Pin ConfigurationsROWDECODER10F6464 x 128PROGRAMMABLEARRAY06COLUMNDECODERcs; ---,.-------CS2CS3c~ -----~-10F16 ~------------------~ 01000009-1uII) CD ...... U 000 en

51CY7C281. CY7C282~NDUcrOR =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VStatic Discharge Voltage ............ " ....... > 1500V(per MIL-STD-883, Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto + 70°C SV ± 10%DC Program Voltage (Pins 18,20) ............... 14.0V Military!l] - SsoC to + 12SoC SV ± 10%Electrical Characteristics Over the Operating Range[2]7C281-30 7C281-45Parameters Description Test Conditions 7C282-30 7C282-45 UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 16.0 rnA 0.4 0.4 VVIH Input HIGH Level[3] 2.0 2.0 VVIL Input LOW Level[3] 0.8 0.8 VIIX Input Current GND ~ VIN ~ Vee -10 + 10 -10 +10 p,AVCDInput Diode ClampVoltageNote 4 Note 4loz Output Leakage Current VOL ~ VOUT ~ VOH, Output Disabled -40 +40 -40 +40 p,AlosleeCapacitance [6]Output ShortCircuit Current[S]Power SupplyCurrentVeeVce = Max., VOUT = GND -20 -90 -20 -90 rnAVce = Max.,lOUT = OmAI Commercial 100 90 rnAI Military 120 rnAParametersCINCOUTDescriptionInput CapacitanceOutput CapacitanceNotes:1. T A is the "instant on" case temperature.2. See the last page of this specification for Group A subgroup testinginformation.3. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment.Test Conditions Max. UnitsTA = 2SoC, f = 1 MHzSVce = S.OV 84. The CMOS process does not provide a clamp diode.However, the eY7C281 & CY7C282 are insensitive to - 3V dc inputlevels and - SV undershoot pulses of less than 10 ns (measured atSO% point).S. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.6. Tested initially and after any design or process changes that mayaffect these parameters.pF3-91

Switching Characteristics Over the Operating Rangel2, 7]CY7C281·30CY7C281·45Parameters Description CY7C282·30 CY7C282·45 UnitsMin. Max. Min. Max.tAAAddress to Output Valid3045nstHzCSChip Select Inactive to High Z(8)2025nstACSChip Select Active to Output Valid2025nsAC Test Loads and WaveformsRl250n5 V O-----"""\jY+.--,OUTPUT 0---...... ....---.......'NCLUD'NGI 30 pFJIG ANDSCOPER2l67nRl250n5V~----~~~OUTPUT 0----,.---......'NCLUD'NGI 5 pFJIG ANDSCOPER2l67n3.0V-----~-----....GND--.....;~s5nsFigure 2. Input PulsesS5ns0009-6Figure laFigure Ib0009-4Equivalent to: THEVENIN EQUIVALENTloonOUTPUT O----'\ .."'"'"r-----IO 2.0 V0009-5AO-AIOADDRESS________ J ~ ________________________________________________________________)~CS3.CS4 -----~~------------~( ~(CS1. CS 2 ------t------------J1\-------'I'---------------00- 0 7 ______-___ ~------:---lt-H-ZC-S-}-+::-:-:-:-:--I--------.t-AC_S~«?i-,,:!- ... +.a.~( _________Notes:7. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, output loading of the specified Iou'IOH andloads shown in Figure la, lb.0009-78. tHZCS is tested with load shown in Figure lb. Transition is measuredat steady state High level + 500 m V or steady state Low level + 500m V on the output from the 1.5V level on the input.3-92

~~CY7C281CY7C282WnEMICONDUcrOR =======================================================================Typical DC and AC Characteristics1.61.4u25l 1.2N:::iNORMALIZED SUPPLY CURRENTvs SUPPLY VOLTAGE/«:!: 1. 0a:ozo. VTABVO. 64.0 4.5 5.0 5.5~t=uwua:~00NORMALIZED SUPPLY CURRENT1.2,..;v..::.s.:..:A.=M=B..::.IE=N:....:..::.T....;T.=E::.;M.=P:..:E=R:.:A:.:T.::,U=R..::.E;......,O.BOL-____ ~ _____---I-55 251256050403020AMBIENT TEMPERATURE ('C)OUTPUT SOURCE CURRENTvs. VOLTAGE~"' "'" '"o~o 1.0 2.0 3.0 4.010OUTPUT VOLTAGE (V)~t= 1.0

(;nCY7C281. CY7C282~NDUcrOR =====================================================================Programming AlgorithmSTARTVccp = 5.0 V. Vpp = 13.5DEVICE BADThe CY7C281 and CY7C282 programming algorithm allows significantly faster programming than the "worst case" specification of 10 msec.Typical programming time for a byte is less than 2.5 msec. The use of EPROM cells allows factory testing of programmed cells, measurement of dataretention and erasure to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.The algorithm utilizes two different pulse types: initial and overprogram. The duration of the PGM pulse (tpp) is 0.1 msec which will then be followed by alonger overprogram pulse of 24 (0.1) (X) msec. X is an iteration counter and is equal to the NUMBER of the initial 0.1 msec pulses applied beforeverification occurs. Up to four 0.1 msec pulses are provided before the overprogram pulse is applied.The entire sequence of program pulses and byte verification is performed at Vee = 5.0. When all bytes have been programmed all bytes should becompared (Read mode) to original data with Vee = 5.0V.Figure 4. Programming Flowchart0009-103-94

fiACY7C281. CY7C282~UcrOR =====================================================================Programming InformationThe 7C281 and 7C282 lK x 8 CMOS PROMs are implementedwith a differential EPROM memory cell. ThePROMS are delivered in an erased state, containing neither"Is" nor "Os". This erased condition of the array may beassessed using the "BLANK CHECK ONES" and"BLANK CHECK ZEROS" function, see below.DC Programming Parameters TA = 25°CTable 1Blank CheckA virgin device contains neither ones nor zeros because ofthe differential cell used for high speed. To verify that aPROM is unprogrammed, use the two blank check modesprovided in Table 3. In both of these modes, address andread locations 0 thru 1023. A device is considered virgin ifall locations are respectively "Is" and "Os" when addressedin the "BLANK ONES AND ZEROS" modes.Because a virgin device contains neither ones nor zeros, itis neccessary to program both ones and zeros. It is recommendedthat all locations be programmed to ensure thatambiguous states do not exist.Parameter Description Min. Max. UnitsVpp Programming Voltage[l] 13.0 14.0 VVccp Supply Voltage 4.75 5.25 VVIHP Input HIGH Voltage 3.0 VVILP Input LOW Voltage 0.4 VVOH Output HIGH Voltage[2] 2.4 VVOL Output LOW Voltage[2] 0.4 VIpp Programming Supply Current 50 rnAIIAC Programming Parameters TA = 25°CTable 2Parameter Description Min. Max. Unitstpp Programming Pulse Width[3] 100 10,000 I-I-stAS Address Setup Time 1.0 I-I-stDS Data Setup Time 1.0 I-I-stAH Address Hold Time 1.0 I-I-stDH Data Hold Time 1.0 I-I-stR, tF Vpp Rise and Fall Time[3) 1.0 I-I-stVD Delay to Verify 1.0 I-I-stvp Verify Pulse Width 2.0 I-I-stDV Verify Data Valid 1.0 I-I-stDZ Verify to High Z 1.0 I-I-sNotes:1. V ccp must be applied prior to Vpp. 3. Measured 10% and 90% points.2. During verify operation.3-95

WnCY7C281. CY7C282Mode SelectionModeRead~U~================================================================Output Disable[4]Output Disable[4]Output Disable[4]Output Disable[4]ProgramProgram VerifyProgram InhibitRead or Output DisableOtherIntelligent ProgramBlank Check OnesCS4PGMPin Number (18)Blank Check ZerosNotes:4. X = Don't care but not to exceed Vee + 5%.Programming Sequence lK x 8VIHXXVILXVILPVIHPVIHPVILPVppVppPower the device for normal read mode operation with pin18,19,20, and 21 at VIH. Per Figure 5 take pin 20 to Vpp.The device is now in the program inhibit mode of operationwith the output lines in a high impedance state; see Tables3 and 4. Again per Figure 5 address program and verifyone byte of data. Repeat this for each location to be programmed.If the brute force programming method is used, the pulsewidth of the program pulse should be 10 ms, and eachTable 3Pin FunctionCS3 CS2 CSt OutputsVFY Vpp CSt (9-11, 13-17)(19) (20) (21)VIH VIL VIL Data OutX VIH X HighZVIL X X HighZX X X HighZX X VIH HighZVIHP Vpp VILP Data InVILP Vpp VILP Data OutVIHP Vpp VILP HighZVIHP Vpp VILP Data InVILP VILP VILP OnesVIHP VILP VILP Zeros5. During programming and verification, all unspecified pins to be atVILP·location is programmed with a single pulse. Any locationthat fails to verify causes the device to be rejected.If the intelligent programming technique is used, the programpulse width should be 100 /Ls. Each location is ultimatelyprogrammed and verified until it verifies correctlyup to and including 4 times. When the location verifies, oneadditional programming pulse should be applied of duration24 X the sum of the previous programming pulsesbefore advancing to the next address to repeat the process.1------PROGRAM-----I_---VERIFV ___ -* __PROGRAMO_TH-\ER ~BYTESVIHP -A:~RESS ---~ I,-------A-O-O-R-ES-S-ST-A-B-L-E -+---------~I __ ~ _____ _VILP - - - - •VIHP - --VILP - --OAT A ------0(~--+---~5~------------Vpp - ---PROGRAMMINGVOL TAGE (PIN 20)VIHP - - -VILP - --VIHP - --PGMVILP - --1~-----~--------~------------~5~-------------VIHP - --VILP - --Figure 5. Programming Waveforms0009-113-96

5'ACY7C281. CY7C282~~UcrOR==============================================================Ordering InformationSpeed Ordering Package Operating(ns) Code Type Range30 ns CY7C281-30PC P13 CommercialCY7C282-30PC PllCY7C281-300C 014CY7C281-30LC L64CY7C282-300C 01245 ns CY7C281-45PC P13 CommercialCY7C282-45PC PllCY7C281-450C 014CY7C281-45LC L64CY7C282-450C 012CY7C281-450MB 014 MilitaryCY7C281-45LMB L64CY7C282-450MB 012II3-97

finCY7C281. CY7C282.. ~U~============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3IcC 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstAA 7,8,9,10,11tACS 7,8,9,10,11Document #: 38-00006-B3-98

Features• Windowed for reprogrammability• CMOS for optimumspeed/power• High speed- 35 ns (commercial)- 35 ns (military)• Low power- 330 mW (commercial)- 413 mW (military)• EPROM technology 100%programmable• Slim 300 mil or standard 600mil packaging available• 5V ± 10% Vee, commercial andmilitary• TTL compatible I/O• Direct replacement for bipolarPROMsCY7C291CY7C292CYPRESSSEMICONDUCTOR Reprogrammable 2048 X 8PROM• Capable of withstanding > 2000Vstatic dischargeProduct CharacteristicsThe CY7C291 and CY7C292 are highperformance 2048 word by 8 bit CMOSPROMs. They are functionally identical,but are packaged in 300 mil and600 mil wide plastic and hermetic DIPpackages respectively. The, 300 mil ceramicDIP package is equipped with anerasure window; when exposed to UVlight the PROM is erased and can thenbe reprogrammed. The memory cellsutilize proven EPROM floating gatetechnology and byte-wide intelligentprogramming algorithms.The CY7C291 and CY7C292 are pluginreplacements for bipolar devices andoffer the advantages of lower power,reprogrammability, superior performanceand programming yield. TheEPROM cell requires only 13.SV forthe supervoltage and low current requirementsallow for gang programming.The EPROM cells allow for eachmemory location to be tested 100%, aseach location is written into, erased,and repeatedly exercised prior to encapsulation.Each PROM is also testedfor AC performance to guarantee thatafter customer programming the productwill meet DC and AC specificationlimits.Reading is accomplished by placing an 3active LOW signal on CSt. and activeHIGH signals on CS2 and CS3. Thecontents of the memory location addressedby the address lines (Ao-AlO)will become available on the outputlines (00-07).Logic Block DiagramPin Configurations128 x 128PROGRAMMABLEARRAY8 x 1 OF 16MUL TIPLEXERA l0Cs,CS 2CS 321 NC°700 0 6O "-

fillCY7C291. CY7C292~~UcrOR =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2001V(per MIL-STD-883, Method 3015)Ambient Temperature withUV Exposure ........................ 7258 Wsec/cm 2Power Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential .... - 0.5V to + 7.0V(Pin 24 to Pin 12)Latchup Current .......................... > 200 rnAOperating RangeDC Voltage Applied to OutputsAmbientRangein High Z State ...................... -0.5V to + 7.0VTemperatureVeeDC Input Voltage ................... -3.0V to + 7.0V Commercial O°Cto +700C 5V ±1O%DC Program Voltage (Pins 18,20) ............... 14.0V Military [6] - 55°C to + 125°C 5V ±1O%Electrical Characteristics Over the Operating Range[5]7C291L-35, SO 7C291-35, SOParameters Description Test Conditions 7C292L-35, SO 7C292-35, SO UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,loH = -4.0 mA 2.4 2.4 VVOL Output LOW Voltage Vee = Min.,loL = -16.0 mA 0.4 0.4 VVIH[1] Input HIGH Voltage 2.0 Vee Vee VVIL[I] Input LOW Voltage 0.8 0.8 VIIX Input Load Current GND s VIN s Vee -10 +10 -10 +10 p,AVeDInput Diode ClampVoltageloz Output Leakage GND s VOUT s Vee,CurrentOutput Disabledlos Output Short Vee = Max.,Circuit Currendl] VOUT = GNDIce Vee Operating Vee = Max.,Supply Current lOUT = OmA*-35: 7e291 onlyIINote 2 Note 2-40 +40 -40 +40 p,A-20 -90 -20 -90 mACommercial 60 90 mAMilitary * 120 mACapacitance [4]ParametersCINDescriptionInput CapacitanceCOUTOutput CapacitanceNotes:1. These are absolute voltages with respect to device ground pin andinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment.2. The CMOS process does not provide a clamp diode. However, theeY7C291 and CY7e292 are insensitive to - 3V dc input levels and- 5V undershoot pulses ofless than 10 ns (measured at 50% point).Test Conditions Max. UnitsT A = 25°C, f = 1 MHz 5Vee = 5.0V 83. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.4. Tested initially and after any design or process changes that mayaffect these parameters.5. See the last page of this specification for Group A subgroup testinginformation.6. TA is the "instant on" case temperature.pF3-100

5ACY7C291.. CY7C292. ~~NDUaOR ~================================================================~Switching Characteristics Over the Operating Range[5, 7]ParameterstAAtHzCStACSDescriptionAddress to Output ValidChip Select Inactive to High Z[s]AC Test Loads and WaveformsChip Select Active to Output Valid7C291·35 7C291·507C292·35 7C292·50Min. Max. Min. Max.35 5025 2525 25UnitsnsnsnsRl 250 n5V~----~~~R1250n5V~-----JV~~3.0 v-----~------.lOUTPUT~--~t------4'NCLUD'NGI 30 pFJIG ANDSCOPER2167nOUTPUT ~--_ ......----......INCLUDING I 5 pFJIG ANDSCOPER2167nGND---~,,5 nsFigure 2. Input Pulses,,5ns0008-6Figure laFigure Ib0008-4Equivalent to:THEVENIN EQUIVALENTloonOUTPUT 0 .... , o 2.0V0008-5Ao-AloADDRESSCS 2 - CS 3CS 1t,~~'---____-'1- NOTE 8 ~-~-----= NOTEt t 'HZCSi 'ACS =:t8 -@...°0-°7 XXNotes:7. Test conditions assume signal transition times of 5 ns or less, timingreference levels of 1.5V, output loading ofthe specified IorJ10H andloads shown in Figures la, lb.-... (-----0008-7S. tHZCS is tested with load shown in Figure lb. Transition is measuredat steady state High level - 500 m V or steady state Low level + 500mV on the output from the 1.5V level on the input.3·101

&IiCY7C291. CY7C292~NDUcroR =====================================================================Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTVS. SUPPLY VOLTAGE1.6,-----,.-----,---,.---,NORMALIZED SUPPLY CURRENTVS. AMBIENT TEMPERATURE1.2r------"T""'"-----.....NORMALIZED ACCESS TIMEVS. SUPPLY VOLTAGE1.2u::0wNJc(::Ea:0z1.4 ~--_4--_+--_+--,..1.21.04.5 5.0TA = 25'Cf=MAX.5.56.011cwN:J

5nCY7C291. CY7C292~UaoR==================================================================Programming AlgorithmIIDEVICE BADThe CY7C291 and CY7C292 programming algorithm allows significantly faster programming than the "worst case" specification of 10 msec.Typical programming time for a byte is less than 2.5 msec. The use of EPROM cells allows factory testing of programmed cells, measurement of dataretention and erasure to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.The algorithm utilizes two different pulse types: initial and overprogram. The duration of the PGM pulse (tpp) is 0.1 msec which will then be followed by alonger overprogram pulse of 24 (0.1) (X) msec. X is an iteration counter and is equal to the NUMBER of the initial O. 1 msec pulses applied beforeverification occurs. Up to four 0.1 msec pulses are provided before the overprogram pulse is applied.The entire sequence of program pulses and byte verification is performed at Veep = 5.0V. When all bytes have been programmed all bytes should becompared (Read mode) to original data with Vee = 5.0V.Figure 4. Programming Flowchart0008-103-103

finCY7C291CY7C292~oo~u~======================================================~==~~• CYPRESSProgramming InformationThe 7C291 and 7C292 2K x 8 CMOS PROMs are implementedwith a differential EPROM memory cell. ThePROMs are delivered in an erased state, containing neither"Is" nor "Os". This erased condition of the array may beassessed using the "BLANK CHECK ONES" and"BLANK CHECK ZEROS" function, see below.Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the 7C291. For this reason, an opaque label should beplaced over the window if the PROM is exposed to sunlightor fluorescent lighting for extended periods of time.The recommended dose of ultraviolet light for erasure is awavelength of2537 Angstroms for a minimum dose (UVintensity X exposure time) of25 Wsec/cm2. For an ultrav.ioletlamp with a 12 ~W/cm2 power rating the exposuretIme would be approxlmately 30-35 minutes.DC Programming Parameters TA = 25°CParameterVppVccpVIHPVILPVOHDescriptionProgramming Voltage[t]Supply VoltageInput HIGH VoltageInput LOW VoltageOutput HIGH Voltage[2]Table 1The 7C291 needs to be within 1 inch of the lamp duringerasure. Permanent damage may result if the PROM isexposed to high intensity UV light for an extended periodoftime. 7258W X sec/cm2 is the recommended maximumdosage.Blank CheckA virgin device contains neither ones nor zeros because ofthe differential cell used for high speed. To verify that aPROM is unprogrammed, use the two blank check modesprovided in Table 3. In each of these modes, the locations 0thru 2047 should be addressed and read. A device is consideredvirgin if all locations are respectively" 1 s" and "Os"when addressed in the "BLANK ONES AND ZEROS"modes.Because a virgin device contains neither ones nor zeros, itis necessary to program both ones and zeros. It is recommendedthat all locations be programmed to ensure thatambiguous states do not exist.Min. Max. Units13.0 14.0 V4.75 5.25 V3.0 V0.4 V2.4 VVOLOutput LOW Voltagel2]0.4 VIpp Programming Supply Current 50 rnAAC Programming Parameters TA = 25°CTable 2Parameter Description Min. Max. Unitstpp Programming Pulse Width[3] 100 10,000 p,stAS Address Setup Time 1.0 p,stos Data Setup Time 1.0 p,stAH Address Hold Time 1.0 p,stOH Data Hold Time 1.0 p,stR, tF Vpp Rise and Fall Time[3] 1.0 p,stvo Delay to Verify 1.0 p,stvp Verify Pulse Width 2.0 p,stov Verify Data Valid 1.0 p,stoz Verify to High Z 1.0 p,sNotes.1. V ccp must be applied prior to V pp. 3. Measured 10% and 90% points.2. Ouring verify operation.3-104

WnCY7C291. CY7C292Mode SelectionModeRead~~UcrOR ==========================================================~~~~Output Disable[4]Output Disable[4]Output Disable[4]ProgramProgram VerifyProgram InhibitIntelligent ProgramBlank Check OnesRead or Output DisableOtherBlank Check ZerosNotes:4. X = Don't care but not to exceed Vee + 5%.Programming Sequence 2K x 8Table 3CS3PGMPin Number (18)Power the device for normal read mode operation with pin18, 19 and 20 at VIR. Per Figure 5 take pin 20 to Vpp. Thedevice is now in the program inhibit mode of operationwith the output lines in a high impedance state; see Table 3.Again per Figure 5 address, program, and verify one byteof data. Repeat this for each location to be programmed.If the brute force programming method is used, the pulsewidth of the program pulse should be 10 ms, and eachVIHXXVILVILPVIHPVIHPVILPVppVppPin FunctionCS2 CSt OutputsVFY Vpp (9-11,13-17)(19) (20)VIH VIL Data OutX VIR HighZVIL X HighZX X HighZVIHP Vpp Data InVILP Vpp Data OutVIHP Vpp HighZVIHP Vpp Data InVILP VILP OnesVIHP VILP Zeros5. During programming and verification, all unspecified pins to be atVILP·location is programmed with a single pulse. Any locationthat fails to verify causes the device to be rejected.If the intelligent programming technique is used, the programpulse width should be 100 JJ-s. Each location is ultimatelyprogrammed and verified until it verifies correctlyup to and including 4 times. When the location verifies, oneadditional programming pulse should be applied of duration24 x the sum of the previous programming pulses beforeadvancing to the next address to repeat the process.IIVIHP - --PROGRAMOTHER BYTES1-0----PROGRAM-----l-_---VERIFY ---'*"..------\ ~ADDRESSADDRESS STABLEVILP--- _.II~~-___+-----.JI~ _VIHP ---VILP---Vpp---PROGRAMMINGVOLTAGE (PIN 20)VIHP - --VILP - --DATA -------(~~----~j~-----------~VIHP - --PlmVILP ---VIHP - -­VFYVILP ---Ir-----------~S~-----------Figure 5. Programming Waveforms0008-113-105

(;nCY7C291. CY7C292~U~~~~~~~~~================================================Ordering InformationSpeed Icc Ordering Package Operating Speed Icc Ordering Package Operating(os) (rnA) Code Type Range (ns) (rnA) Code Type Range35 60 CY7C291 L-35PC P13 Commercial 35 60 CY7C292L-35PC Pll CommercialCY7C291L-35WC W14 CY7C292L-35DC D1290 CY7C291-35PC P13 90 CY7C292-35PC PllCY7C291-358C 813 CY7C292-35DC D12CY7C291-35WC W14 50 60 CY7C292L-50PC Pll CommercialCY7C291-35LC L64 CY7C292L-50DC D12120 CY7C291-35WMB W14 Military 90 CY7C292-50PC Pll50 60 CY7C291 L-50PC P13 Commercial CY7C292-50DC D12CY7C291L-50WC W14 120 CY7C292-50DMB D12 Military90 CY7C291-50PC P13CY7C291-508C 813CY7C291-50WCCY7C291-50LCW14L64120 CY7C291-50WMB W14 MilitaryCY7C291-50DMBCY7C291-50LMBCY7C291-5OQMBD14L64Q643-106

5nCYPRESSCY7C291CY7C292S~lOO~UcrOR==~~~~~~~~~~~~~==~==~==~============~~~~~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Ioz 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstAA 7,8,9,10,11tACS 7,8,9,10,11Document #: 38-00007-BII3-107

Features• Windowed for reprogrammability• CMOS for optimumspeed/power• High speed- 25 os (commercial)- 30 ns (military)• Low power- 330 mW (commercial)- 660 mW (military)• Low standby power- 165 mW (commercial)- 220 mW (military)• EPROM technology 100%programmable• Slim 300 mil or standard 600mil packaging available• 5V ± 10% V cc, commercial andmilitary• TTL compatible I/O• Direct replacement for bipolarPROMsLogic Block DiagramCY7C291ACY7C292A/CY7C293ACYPRESSSEMICONDUCTOR Reprogrammable 2048 X 8PROM• Capable of withstanding > 2001 Vstatic dischargeProduct CharacteristicsThe CY7C291A, CY7C292A, andCY7C293A are high performance 2048word by 8 bit CMOS PROMs. Theyare functionally identical, but are packagedin 300 mil (7C291A, 7C293A)and 600 mil wide plastic and hermeticDIP packages (7C292A). TheCY7C293A has an automatic powerdown feature which reduces the powerconsumption by over 70% when deselected.The 300 mil ceramic DIP packageis equipped with an erasure window;when exposed to UV light thePROM is erased and can then be reprogrammed.The memory cells utilizeproven EPROM floating gate technologyand byte-wide intelligent programmingalgorithms.The CY7C291A, CY7C292A, andCY7C293A are plug-in replacementsfor bipolar devices and offer the advantagesof lower power, reprogrammability,superior performance and programmingyield. The EPROM cell requiresonly 12.5V for the supervoltage andlow current requirements allow forgang programming. The EPROM cellsallow for each memory location to betested 100%, as each location is writteninto, erased, and repeatedly exercisedprior to encapsulation. Each PROM isalso tested for AC performance toguarantee that after customer programmingthe product will meet DC andAC specification limits.Reading is accomplished by placing anactive LOW signal on CSI, and activeHIGH signals on CS2 and CS3. Thecontents of the memory location addressedby the address lines (Ao-AIO)will become available on the outputlines (00-07)'Pin Configurations01128 x 128PROGRAMMABLEARRAY0& As -

~RRSSCY7C291ACY7C292A/CY7C293A.nEMICONDUcrOR ;;;;;;;;;==================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential .... -O.SV to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -O.SV to +7.0VDC Input Voltage ................... - 3.0V to + 7.0VDC Program Voltage .......................... 13.0VUV Exposure ........................ 7258 Wsec/cm2Static Discharge Voltage ..................... > 2001 V(per MIL-STD-883, Method 3015)Latchup Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureVccCommercial O°C to + 70°C 5V ± 10%Military [5] - 55°C to + 125°e 5V ± 10%Electrical Characteristics Over the Operating Range[6]Parameters Description Test ConditionsVOHOutput HIGH Voltage Vce = Min.,IOH = -4.0mAVOL Output LOW Voltage Vee = Min.,IOL = -16.0 rnAVIRVILInput HIGH VoltageInput LOW VoltageIIX Input Load Current GND::;: VIN::;: VeeVeDInput Diode ClampVoltageIoz Output Leakage GND::;: VOUT::;: Vee,CurrentOutput Disabledlos Output Short Vee = Max.,Circuit Current[ll VOUT = GNDlee Vee Operating Vee = Max., CommercialSupply Current lOUT = OmA MilitaryISBStandby Supply Vee = Max., CommercialCurrent (7C293A Only) CSI :2: VIRMilitary7C291A-25 7C291A-30 7C291AL-35, 50 7C291A-35, 507C292A-25 7C292A-30 7C292AL-35, 50 7C292A-35, 507C293A-25 7C293A-30 7C293AL-35, 50 7C293A-35, 50Min. Max. Min. Max. Min. Max. Min. Max.Units2.4 2.4 2.4 2.4 V0.4 0.4 0.4 0.4 V2.0 Vee 2.0 Vee 2.0 Vee 2.0 Vee V0.8 0.8 0.8 0.8 V-10 +10 -10 +10 -10 +10 -10 +10 /-LANote 2 Note 2 Note 2 Note 2-40 +40 -40 +40 -40 +40 -40 +40 /-LA-20 -90 -20 -90 -20 -90 -20 -90 rnA120 60 90 rnA120 120 rnA30 30 30 rnA40 40 rnACapacitance [4]ParametersDescriptionTest Conditions Max. UnitsCIN Input Capacitance TA= 25°C,f= 1 MHz 5pFCOUTOutput CapacitanceVee = 5.0V 8Notes:1. These are absolute voltages with respect to device ground pin and3. For test purposes, not more than one output at a time should beinclude all overshoots due to system and/or tester noise. Do not attemptto test these values without suitable equipment.4. Tested initially and after any design or process changes that mayshorted. Short circuit test duration should not exceed 30 seconds.2. The eMOS process does not provide a clamp diode. However, theaffect these parameters.eY7C291A, eY7C292A and eY7C293A are insensitive to - 3V dc5. T A is the "instant on" case temperature.input levels and - 5V undershoot pulses of less than IOns (measured6. See the last page of this specification for Group A subgroup testingat 50% point).information.3-109

5ACY7C291A. CY7C292A/CY7C293A~UCTOR ==~~~~~~~~~~~~~~~~~~~~~~~~~=================Switching Characteristics Over the Operating Range[6, 71ParameterstAAtHZCSltACSltHZCS2tAcs2tputpDDescriptionAddress to Output ValidChip Select Inactive to High Z[S]Chip Select Active to Output ValidChip Select Inactive to High Z[9](7C293A CSI Only)Chip Select Active to Output Valid(7C293A CSI Only)[9]Chip Select Active to Power Up(7C293A CSI Only)Chip Select Inactive to Power Down(7C293A CSI Only)AC Test Loads and Waveforms7C291A-25 7C291A-30 7C291A-35 7C291A-507C292A-25 7C292A-30 7C292A-35 7C292A-507C293A-25 7C293A-30 7C293A-35 7C293A-50Min. Max. Min. Max. Min. Max. Min. Max.02520202727270Units30 35 50 ns20 25 25 ns20 25 25 ns32 35 45 ns32 35 45 ns0 0 ns32 35 45 nsR1250n5Vo---------~~~Rl250n5 V o-----""'ftv-.....,OUTPUT 0---...... ---..... OUTPUT 0---..... ----1R2R2INCLUDINGI 30 pF 167n INCLUDING I 6 pF 16HZJIG ANDJIG ANDSCOPESCOPE3.0 v-----=i:~...---~LGND---OlII:5:5 ns :5:5nsFigure 2. Input Pulses0120-5Figure laFigure Ib0120-4Equivalent to:THEVENIN EQUIVALENTloonOUTPUT O~----~ ...VeeSUPPLYCURRENT,,·.""'......----o 2.0 V0120-6-tpd ~~k-50%-tpuI---~50%A O -A l0ADDRESS ~(f4-tAA1+ t Hzes ' I--00-07 ___________ X~~~ __________ ~~NOTE8t Aes8Notes:7. Test conditions assume signal transition times of 5 ns or less, timingreference levels of l.5V, output loading of the specified lor/IoH andloads shown in Figures la, lb.~~~~0120-7S. tHZCS is tested with load shown in Figure lb. Transition is measuredat steady state High level - 500 m V or steady state Low level + 500mV on the output from the 1.5V level on the input.9. tHZCS2 and tACS2 refer to 7C293A CS, only.3-110

fillCY7C291ACY7C292A/CY7C293A~~UcrOR==================================================================~Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.6NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.2 r-------r-------,NORMALIZED ACCESS TIMEvs. SUPPLY VOLTAGE1.2tJ.::0wN::::i

WACY7C291A. CY7C292A/CY7C293A~NDUcroR =====================================================================Programming AlgorithmThe CY7C291A, CY7C292A and CY7C293A programming algorithm allows significantly faster programming than the "worst case" specification of 10ms.Typical programming time for a byte is less than 2.5 ms. The use of EPROM cells allows factory testing of programmed cells, measurement of dataretention and erasure to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.The algorithm utilizes two different pulse types: initial and overprogram. The duration of the PGM pulse (tpp) is 0.1 ms which will then be followed by alonger overprogram pulse of 24 (0.1) (X) ms. X is an iteration counter and is equal to the NUMBER of the initial 0.1 ms pulses applied before verificationoccurs. Up to four 0.1 ms pulses are provided before the overprogram pulse is applied.The entire sequence of program pulses and byte verification is performed at Veep = 5.0V. When all bytes have been programmed all bytes should becompared (Read mode) to original data with Vee = 5.0V.Figure 4. Programming Flowchart0120-83-112

5AProgramming InformationThe 7C291A, 7C292A and 7C293A 2K x 8 CMOSPROMs are implemented with a single ended EPROMmemory cell. The PROMs are delivered in an erasedstate, containing "Os". To verify that a PROM is unprogrammed,use the verify mode provided in Table 3. Thelocations 0 thru 2047 should be addressed and read.Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase these PROMs. For this reason, an opaque labelshould be placed over the window if the PROM is exposedCY7C291ACY7C292A/CY7C293ACYPRESSs~CO~UcrOR==================================================================to sunlight or fluorescent lighting for extended periods oftime.The recommended dose of ultraviolet light for erasure is awavelength of 2537 Angstroms for a minimum dose (UVintensity X exposure time) of 25 Wsec/cm2. For an ultravioletlamp with a 12 mW /cm2 power rating the exposuretime would be approximately 30-35 minutes.These PROMs need to be within 1 inch of the lamp duringerasure. Permanent damage may result if the PROM isexposed to high intensity UV light for an extended periodof time. 7258W X sec/cm2 is the recommended maximumdosage.DC Programming Parameters TA = 25°CTable 1ParameterDescriptionMin. Max. UnitsVpp Programming Voltage [ 1]12.0 13.0 VVccpSupply Voltage4.75 5.25 VVIHPInput HIGH Voltage3.0 VVILPInput LOW Voltage0.4 VVOHOutput HIGH Voltage[2]2.4 VVOLOutput LOW V oltagel2]0.4 VIpp Programming Supply Current 50 rnAIIAC Programming Parameters TA = 25°CTable 2Parameter Description Min. Max. Unitstpp Programming Pulse Width [3] 100 10,000 JJ-stAS Address Setup Time 1.0 JJ-stos Data Setup Time 1.0 JJ-stAH Address Hold Time 1.0 JJ-stOH Data Hold Time 1.0 JJ-stR, tF Vpp Rise and Fall Timel3] 1.0 JJ-stvo Delay to Verify 1.0 JJ-stvp Verify Pulse Width 2.0 JJ-stov Verify Data Valid 1.0 JJ-stoz Verify to High Z 1.0 JJ-sNotes.1. V ccp must be applied prior to Vpp. 3. Measured 10% and 90% points.2. During verify operation.3-113

fiACY7C291A. CY7C292A/CY7C293AMode SelectionModeRead~NDUcroR =====================================================================Output Disable[4]Output Disable[4]Output Disable[4]ProgramProgram VerifyProgram InhibitRead or Output DisableOtherIntelligent ProgramNotes:4. X = Don't care but not to exceed Vee + 5%.Programming Sequence 2K x 8Table 3CS3PGMPin Number (18)Power the device for normal read mode operation with pin18,19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. Thedevice is now in the program inhibit mode of operationwith the output lines in a high impedance state; see Table 3.Again per Figure 5 address, program, and verify one byteof data. Repeat this for each location to be programmed.If the brute force programming method is used, the pulsewidth of the program pulse should be 10 ms, and eachVIHXXVILVILPVIHPVIHPVILPPin FunctionCS2 CSt OutputsVFY Vpp (9-11,13-17)(19) (20)VIH VIL Data OutX VIH HighZVIL X HighZX X HighZVIHP Vpp Data InVILP Vpp Data OutVIHP Vpp HighZVIHP Vpp Data In5. During programming and verification, all unspecified pins to be atVILP·location is programmed with a single pulse. Any locationthat fails to verify causes the device to be rejected.If the intelligent programming technique is used, the programpulse width should be 200 ,""S. Each location is ultimatelyprogrammed and verified until it verifies correctlyup to and including 10 times. When the location verifies,one additional programming pulse should be applied of duration4 x the sum of the previous programming pulsesbefore advancing to the next address to repeat the process.VIHP -A:~RESSPROGRAM14-----PROGRAM-----t_---VERIFY ___ -*,>--_O_T_H-l,ER ~BYTES____..I11.....___ +-__ A_DD_R_E_SS_S_T_AB_L_E_+-_________ 1 ~ __....... ______VILP--- - -VIHP - --VILP - --DATA ------0(~--+---~ )~------------Vpp - --PROGRAMMINGVOL TAGE (PIN 20)VIHP - --~VILP - --VIHP - --VILP - --VIHP - --VILP - --Figure S. Programming Waveforms0120-113-114

(;ACY7C291ACY7C292A/CY7C293A~~UaoR================================================================Ordering InformationSpeed IcC Ordering Package Operating Speed ICC Ordering Package Operating(ns) (mA) Code Type Range (ns) (mA) Code Type Range25 120 CY7C291A-25PC P13 Commercial SO 60 CY7C291AL-sOPC P13 CommercialCY7C291A-25WC W14 CY7C291AL-sOWC W14CY7C292A-25PC Pll CY7C292AL-sOPC PllCY7C292A-25DC Dl2 CY7C293AL-sOPC P13CY7C293A-2sPC P13 CY7C293AL-sOWC W14CY7C293A-2sWC W14 90 CY7C291A-sOPC P13 Commercial30 120 CY7C291A-30DMB D14 Military CY7C291A-sODC D14CY7C291A-30WMB W14 CY7C291A-sOWC W14CY7C291A-30LMB L64 CY7C291A-sOLC L64CY7C291A-30QMB Q64 CY7C292A-sOPC PllCY7C292A-30DMB D12 CY7C292A-sODC D12CY7C293A-30DMB D14 CY7C293A-50PC P13CY7C293A-30WMB W14 CY7C293A-sODC D14CY7C293A-30LMB L64 CY7C293A-sOWC W14CY7C293A-30QMB Q64 CY7C293A-sOLC L6435 60 CY7C291AL-35PC P13 Commercial 120 CY7C291A-sODMB D14 MilitaryCY7C291AL-35WC W14 CY7C291A-sOWMB W14CY7C292AL-3sPC Pll CY7C291A-sOLMB L64CY7C293AL-35PC P13 CY7C291A-sOQMB Q64CY7C293AL-35WC W14 CY7C292A-sODMB D1290 CY7C291A-3sPC P13 Commercial CY7C293A-sODMB D14CY7C291A-3sDC D14 CY7C293A-sOWMB W14CY7C291A-3sWC W14 CY7C293A-sOLMB L64CY7C291A-3sLC L64 CY7C293A-50QMB Q64CY7C292A-3sPCCY7C292A-3sDCCY7C293A-3sPCCY7C293A-3sDCCY7C293A-3sWCCY7C293A-3sLCPllD12P13D14W14L64120 CY7C291A-3sDMB D14 MilitaryCY7C291A-3sWMBCY7C291A-3sLMBCY7C291A-3sQMBCY7C292A-3sDMBCY7C293A-3sDMBCY7C293A-3sWMBCY7C293A-3sLMBCY7C293A-3sQMBW14L64Q64D12D14W14L64Q643-115

CY7C291A~PR£SSCY7C292A/CY7C293A'nEMICONDUcrOR ================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3Icc 1,2,3ISB[2] 1,2,3SubgroupsSwitching CharacteristicsParametersSubgroupstAA 7,8,9,10,11tACSl[J] 7,8,9,10,11tACS2[2] 7,8,9,10,11Notes:1. 7C291A and 7C292A only.2. 7C293A only.Document #: 38-0007S-B3-116

~CYPRfSS..PROM Programming Information~ICONDUcrOR =:=;:=;:=;:=;:=;:=;:=;:=;=:=;:=;:=;:=;;;;;;~:=;:=;:=;:=;:=;=:=;:=;:=;:=;:=;====:=;====:=;========IntroductionPROMs or Programmable Read Only Memories have existedsince the early 1970's and continue to provide thehighest speed non-volatile form of semiconductor memoryavailable. Until the introduction of CMOS PROMs fromCypress, all PROMs were produced in bipolar technology,because bipolar technology provided the highest possibleperformance at an acceptable cost level. All bipolarPROMs use a fuse for the programming element. The fusesare in tact when the product is delivered to the user, andmay be programmed or written once with a pattern andused or read infinitely. The fuses are literally blown using ahigh current supplied by a Programming System. Since thefuses may only be blown or programmed once, they maynot be programmed during test. In addition, since theymay not be programmed until the user determines the pattern,they may not be completely tested prior to shipmentfrom the supplier. This inability to completely test, resultsin less than 100% yield during programming and use bythe customer for two reasons. First, some percentage of theproduct fails to program. These devices fall out during theprogramming operation, and although a nuisance are easilyidentified. Additional yield is lost because the device failsto perform even though it programs correctly. This failureis normally due to the device being too slow. This is a moresubtle failure, and can only be found by 100% post programAC testing, or even worse by trouble shooting anassembled board or system.Cypress CMOS PROMs use an EPROM programmingmechanism. This technology has been in use in MOS technologiessince the early 1970s. However, as with mostMOS technologies the emphasis has been on density, notperformance. CMOS at Cypress is as fast as or faster thanBipolar and coupled with EPROM, becomes a viable alternativeto bipolar PROMs from a performance point-ofview.In the arena of programming, EPROM has somesignificant advantages over fuse technology. EPROM cellsare programmed by injecting charge on an isolated gatewhich permanently turns off the transistor. This mechanismcan be reversed by irradiating the device with ultravioletlight. The fact that programming can be erased, totallychanges the testing and programming situation and philosophy.All cells can be programmed during the manufacturingprocess and then erased prior to packaging and subsequentshipment. While these cells are programmed, theperformance of each cell in the memory can be teste~ allowingthe shipment of devices that program every bme,and will perform as specified when programmed. In additionwhen these devices are supplied in a windowed packagethey can be programmed and erased indefinitely providingthe designer a RE-PROGRAMMABLE PROM fordevelopment.Programmable TechnologyEPROM Process TechnologyEPROM technology employs a floating or isolated gatebetween the normal control gate and the source/drain re­:rion of a transistor. This gate may be charged with electronsduring the programming operation and when;harged with electrons, the transistor is permanently:urned off. When uncharged (the transistor is unpro­~rammed) the device may be turned on and off normally3-117with the control gate. The state of the floating gate,charged or uncharged, is permanent because the gate isisolated in an extremely pure oxide. The charge may beremoved if the device is irradiated with ultraviolet energyin the form of light. This ultraviolet light allows the electronson the gate to recombine and discharge the gate. Thisprocess is repeatable and therefore can be used during theprocessing of the device repeatedly if necessary to assureprogramming function and performance.Two Transistor CellsIn order to provide an EPROM cell that is as fast as thefuse technology employed in bipolar processes, Cypressuses a two transistor EPROM cell. One transistor is optimizedfor reliable programming, and one transistor is optimizedfor high speed. The floating gates are connectedsuch that charge injected on the floating gate of the programmingtransistor is conducted to the read transistor,biasing it off.Differential Memory CellsIn the 4K (CY7C225); 8K (CY7C235, CY7C281, IICY7C282); and 16K (CY7C245, CY7C291, CY7C292)CMOS PROMs, Cypress employs a differential memory _cell and sense amplifier technique. Higher density devicessuch as the 7C261, 7C263, 7C264 or 7C269 64K PROMsemploy a single ended Cell and sense amplifier techniquesimilar to the approach used in more conventionalEPROMs.In a conventional high density EPROM a single EPROMtransistor is used to switch the input to one side of a differentialsense amplifier. The other side of the sense amplifieris biased at an intermediate level with a dummy cell. Anunprogrammed EPROM transistor will conduct and drivethe sense amplifier to a logic "0". A programmed EPROMtransistor will not conduct, and consequently drives thesense amplifier to a logic "I". A conventional EPROM celltherefore is delivered with a specific state "0" or "1" in itdepending on the number of inversions after the s~nse amplifierand can always be programmed to the OppOSIte state.Access time in this conventional approach is heavily dependenton the time the selected EPROM transistor takes tomove the input of the sense amplifier from a quiescent conditionto the threshold that the dummy cell is biasing thesecond input to the sense amplifier. This bias is severalvolts, and requires a significant delay before the sense amplifierbegins to react.Cypress PROMs employ a true differential cell approach,with EPROM cells attached to both inputs of the senseamplifier. As indicated above, the read transistor which isoptimized for speed is actually the transistor attached tothe sense amplifier. In the erased state, both EPROM transistorsconduct when selected eccentrically biasing the inputof the sense amplifier at the same level. If the in1?utswere at identical levels, the output of the sense amplifierwould be in a mestastable condition or, neither a "I" nor"0". In actual practice the natural bias and high gain of thesense amplifier combine to cause the output to favor one orthe other stable conditions. The difference between the twoconditions is however only a few millivolts and the memorycell should be considered to contain neither a "1" nor a"0". As a result of this design approach, the memory cellmust be programmed to either a "1" or a "0" depending onthe desired condition and the conventional BLANK

~ PROM Programming Information (Continued)~~~U~~~~~~~~~~~~~~~~~====~~~~~~~~~~~~~~==CHECK mechanism is invalid. The benefit of the approachhowever is that only a small differential signal from the cellbegins the sense amplifier switching and the access time ofthe memory is extremely fast.Single Ended Memory CellsAlthough a more conventional approach, single endedmemory cells and sensing techniques offer a superior tradeoffbetween die size and performance than the differentialcell for devices of 64K densities and above. The Singleended technique employed by Cypress uses a dummy cellfor the reference voltage thus providing a reference thattracks the programmed cell in process related parameters,power supply and temperature induced variations. TheMemory cell used is a second generation two transistor cellderived from earlier work at the 16K density level. It hasan optimized READ transistor that is matched to the senseamplifier, and a second transistor optimized for programming.The floating gates of the two transistors that makeup a memory cell are connected electrically so that thecharge programmed onto one device controls the thresholdof the second transistor.Unlike the differential memory approach, the erased singleended device contains all "O"s and on the the ones areprogrammed. Therefore a "1" on the data pins during programmingcauses a "1" to be programmed into the addressedlocation.Programming AlgorithmByte Addressing and ProgrammingAll Cypress CMOS PROMs are addressed and programmedon a byte basis unlike the bipolar products thatthey replace. The address lines used to access the memoryin a read mode are the same for programming, and theaddress map is identical. The information to be programmedinto each byte is presented on the data out pinsduring the programming operation and the data is readfrom these same pins for verification that the byte has beenprogrammed.Blank Check for Differential CellsSince a differential cell contains neither a "1" nor a "0"before it is programmed, the conventional BLANKCHECK is not valid. For this reason, all Cypress CMOSPROMs contain a special BLANK CHECK mode of operation.Blank check is performed by separately examiningthe "0" and "1" sides of the differential memory cell todetermine whether either side has been independently programmed.This is accomplished in two passes one comparingthe "0" side of the differential cell against a referencevoltage applied to the opposite side of the sense amplifierand then repeating this operation for the "1"s side of thecell. The modes are called BLANK CHECK ONES, andBLANK CHECK ZEROS. These modes are entered bythe application of a supervoltage to the device.Blank Check for Single Ended CellsSingle ended cells BLANK CHECK in a conventionalmanner. An erased device contains all "O"s and a programmedcall will contain a "I". Cypress PROMs that usethe single ended approach provide a specific mode to performthe BLANK CHECK which also provides the verifyfunction. This makes the need to switch high voltages unnecessaryduring the program verify operation. See specificdata sheets for details.Programming the Data ArrayProgramming is accomplished by applying a supervoltageto one pin of the device causing it to enter the programmingmode of operation. This also provides the programmingvoltage for the cells to be programmed. In this modeof operation, the address lines of the device are used toaddress each location to be programmed, and the data ispresented on the pins normally used for reading the contentsof the device. Each device has a READ and aWRITE pin in the programming mode. These are activelow signals and cause the data on the output pins to bewritten into the addressed memory location in the case ofthe WRITE signal or read out of the device in the case ofthe READ signal. When both the READ and WRITE signalsare high, the outputs are disabled and in a high impedancestate. Programming therefore is accomplished byplacing data on the output pins, and writing it into theaddressed location with the WRITE signal. Verification ofdata is accomplished by reading the information on theoutput pins while the READ signal is active.The timing for actual programming is supplied in theunique programming specification for each device.Special FeaturesDepending on the specific CMOS PROM in question, additionalfeatures that require programming may be availableto the designer. Two of these features are a ProgrammableINITIAL BYTE and Programmable SYNCHRO­NOUS/ ASYNCHRONOUS ENABLE available in someof the registered devices. Like programming the array,these features make use of EPROM cells and are programmedin a similar manner, using supervoltages. Thespecific timing and programming requirements are specifiedin the data sheet of the device employing the feature.Programming SupportProgramming support for Cypress CMOS PROMs is availablefrom a number of programmer manufacturers, someof which are listed below.Data I/O Corporation10525 Willows Rd. N.E.P.O. Box 97046Redmond, WA98073-9746(206) 881-6444Data I/O 29B Unipak IICypress Generic Family CodePart Number Part Number and PinoutRevisionCY7C225 27S25 FO B6 V12CY7C235 27S35 FO B5 V09CY7C245 27S45A FO BO V09CY7C261/3/4 27S49 EF 31 VllCY7C281/2 27S281/181 EE B4 V09CY7C291/2 27S291/191 EE AF V093-118

~ PROM Programming Information (Continued)~~~UcrOR==================================================================Stag Microsystems1600 Wyatt Dr.Santa Clara, CA 95054(408) 988-1118Stag PPZ Zm2000CypressPart NumberGenericPart NumberCY7C225 27S25CY7C235 27S35CY7C245 27S45ACY7C281/2 27S281/181CY7C291/2 27S291/191Family Codeand PinoutMenuDrivenRevisionRev 21Rev 21Rev 24Rev 21Rev 21Cypress Semiconductor, Inc.3901 North First St.San Jose, CA 95134(408) 943-2600Cypress CY3000 QuickPro Rev. PROM 2.10Cypress Generic Family CodePart Number Part Number and PinoutCY7C225CY7C235CY7C245CY7C261/3/4 Menu MenuCY7C268 Driven DrivenCY7C269CY7C281/2CY7C291/23-119

PRODUCTINFORMATIONSTATIC RAMS ,.PROMSEPLDSLOGICRISCBRIDGEMOSQUICKPRO,.QUALITY ANDRELIABILITYAPPLICATION BRIEFSPACKAGES".• fA.'.••

~ Section Contents~~~~UcrOR==================================================================EPLDs (Eraseable Programmable Logic Devices)Page NumberIntroduction to EPLDs .................................................................................. 4-1Device Number DescriptionPAL C 20 Series 16L8, 16R8, 16R6, 16R4 Reprogrammable CMOS PAL@ Device .................... 4-7PLD C 20G 10 CMOS Generic 24 Pin Reprogrammable PLD ................................... 4-25PLD C 20RA1O Reprogrammable Asynchronous CMOS Programmable Logic Device ............... .4-44PAL C 22V1O Reprogrammable CMOS PAL Device ......................................... .4-53CY7C330 Synchronous State Machine .................................................. 4-70CY7C331 Asynchronous Registered EPLD .............................................. 4-79CY7C332 Combinatorial Registered EPLD .............................................. 4-87PLD Programming Information .......................................................................... 4-92

~ Introduction to CMOS EPLDs~~~ffiOOcrOR =======================================================================Cypress EPLD Family FeaturesCypress Semiconductor's EPLD family offers the user thenext generation in Erasable Programmable Logic Devices(EPLD) based on our high performance 0.8,... CMOS process.These devices offer the user the power saving of aCMOS-based process, with delay times equivalent to thosepreviously found only in bipolar devices. No fuses are usedin Cypress' EPLD family, rather all devices are based onan EPROM cell to facilitate programming. By using anEPROM cell instead of fuses, programming yields of 100%can be expected since all devices are functionally tested anderased prior to packaging. Therefore, no programmingyield loss can be expected by the user.The EPROM cell used by Cypress serves the same purposeas the fuse used in most bipolar PLD devices. Before programming,the AND gates or Product Terms are connectedvia the EPROM cells to both the true and complementinputs. When the EPROM cell is programmed, the inputsfrom a gate or Product Term are disconnected. Programmingalters the transistor threshold of each cell so that noconduction can occur, which is equivalent to disconnectingthe input from the gate or Product Terms. This is similarto "blowing" the fuses of a bipolar device which disconnectsthe input gate from the Product Term. Selective programmingof each of these EPROM cells enables the specificlogic function to be implemented by the user.The programmability of Cypress' EPLDs allows the usersto customize every device in a number of ways to implementtheir unique logic requirements. Using EPLDs inplace of SSI or MSI components results in more effectiveutilization of boardspace, reduced cost and increased reli-ability. The flexibility afforded by these EPLDs allows thedesigner to quickly and effectively implement a number oflogic functions ranging from random logic gate replacementto complex combinatorial logic functions.The EPLD family implements the familiar "sum of products"logic by using a programmable AND array whoseoutput terms feed a fixed OR array. The sum of these canbe expressed in a Boolean transfer function and is limitedonly by the number of product terms available in theAND-OR array. A variety of different sizes and architecturesare available. This allows for more efficient logic optimizationby matching input, output and product terms tothe desired application.EPLD NotationTo reduce confusion and to have an orderly way of representingthe complex logic networks, logic diagrams areprovided for the various part types. In order to be useful,Cypress logic diagrams employ a common logic conventionthat is easy to use. Figure 1 shows the adopted convention.In Figure 1, an "x" represents an unprogrammed EPROMcell that is used to perform the logical AND operationupon the input terms. The convention adopted does notimply that the input terms are connected on the commonline that is indicated. A further extension of this conventionis shown in Figure 2 which shows the implementationof a simple transfer function. The normal logic representationof the transfer function logic convention is shown inFigure 3.~::[)--- AoBoC = -+#-0-AoBoCFigure 10024-1Figure 20024-2Figure 30024-34-1

~ Introduction to CMOS EPLDs(Continued)~~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===PLD Circuit Configurationsputs without feedback, maximum use of the buried macrocellI/O pins for inputs can be achieved. The CY7C330Cypress EPLDs have several different output configurationsthat cover a wide spectrum of applications. The avail­no external output, illustrated in Figure 8, which are usedalso contains four dedicated buried or hidden registers withable output configurations offer the user the benefits of as additional state register resources for creation of highboth lower package counts and reduced costs when used. performance state machines.This approach allows the designer to select a PLD that bestfits the needs of his application. An example of some of theconfigurations that are available are listed below.Programmable I/OFigure 4 illustrates the programmable I/O offered in theCypress EPLD family which allows product terms to directlycontrol the outputs of the device. One product termis used to directly control the three-state output buffer,which then gates the summation of the remaining terms tothe output pin. The output of this summation can be fedback into the PLD as an input to the array. This programmableI/O feature allows the PLD to drive the output pinwhen the three-state output is enabled or, the I/O pin canbe used as an input to the array when the three-state outputis disabled.Registered Outputs with FeedbackFigure 5 illustrates the registered output offered on a numberof the Cypress EPLDs allows this circuit to function asa state sequencer. The summation of the product terms isstored in the D-type output flip-flop on the rising edge ofthe system clock. The Q output of the flip-flop can then begated to the output pin by enabling the three-state outputbuffer. The output of the flip-flop can also be fed back intothe array as an input term. The output feedback featureallows the PLD to remember and then alter its functionbased upon that state. This circuit can be used to executesuch functions as counting, skip, shift and branch.Buried Register FeedbackA number of Cypress EPLDs provide registers which maybe "buried" or "hidden" to create registers for state machineimplementation without sacrificing the use of the associateddevice pin. The device pin normally associatedwith the register may still be used as a device input. Theproprietary CY7C330 Reprogrammable Synchronous StateMachine macrocell illustrates, in Figure 6, the use of buriedregisters with provision for saving the I/O pin for useas an input. If the feedback path is selected by the feedbackmultiplexer, the Q of the register is fed back to the array asan input. The I/O pin can still be routed to the array as anexternal input by use of a special multiplexer shown inFigure 7 provided for that purpose for each of the six macroce11pairs. A special configuration bit, C3, selects the inputregister output from one of the I/O pins of the pair ofmacrocell I/O pins which is to be fed to the array as anexternal input. By proper placement of the buried registersadjacent to I/O macrocells used as normal registered out-Asynchronous Register ControlCypress also offers EPLDs which may be used in asynchronoussystems in which register clock, set and reset are controlledby the outputs of the product term array. The clockis created by the processing of external inputs and/or internalfeedback by the logic of the product term array and isthen routed to the register clock. The register set and resetare similarly controlled by product term outputs and canbe triggered at any time independent of the clock in responseto external and/or feedback inputs processed by thelogic array. The proprietary CY7C331 Asynchronous RegisteredEPLD, for which the I/O macrocell is illustrated inFigure 9, is an example of such a device. The register clock,set and reset functions of the CY7C331 are all controlledby product terms and enable their respective functions dependentonly on input signal timing and combinatorial delaythrough the device logic array.Programmable Macro CellThe Programmable Macro Cell, illustrated in Figure 10,provides the capability of defining the architecture of eachoutput individually. Each of the potential outputs may bespecified to be "REGISTERED" or "COMBINATORI­AL". Polarity of each output may also be individually selectedallowing complete flexibility of output configuration.Further configurability is provided through "ARRAY"configurable "OUTPUT ENABLE" for each potential output.This feature allows the outputs to be reconfigured asinputs on an individual basis or alternately used as a bidirectionalI/O controlled by the programmable array.Input Register CellOther Cypress EPLDs provide input register cells whichallow capture for processing of short duration inputs whichwould not otherwise be present at the inputs for sufficienttime to allow the device to respond. Both the proprietaryCY7C330 Reprogrammable Synchronous State Machineand the proprietary CY7C332 Combinatorial EPLD providethese input register cells which are shown in Figure11. The clock for the input register may be provided fromone of two external clock input pins selectable by a configurationbit, C4, dedicated for this purpose for each inputregister. This choice of input register clock allows signalsto be captured and processed from two independent systemsources each controlled by its own independent clock.These input register cells are provided within I/O macrocells,as well as, for dedicated input pins.4-2

~ Introduction to CMOS EPLDs(Continued)~~~~====================================================~========NPUTS, FEEDBACK, AND I/OI~'1111111111111111111111111111111 ~I/OFigure 4. Programmable I/O0024-4INPUTS FEEDBACK AND I/O CLOCK OC:>- ..-- I- D Q~~...r:::r_-~~e.....21Figure S. Registered Outputs with Feedback0024-5IIGLOBALSYNCHRONOUS SETINPUT OR FEEDBACK TO LOGIC ARRAYTO SHAREDMACRO CELLINPUT MUXGLOBAL STATEREGISTER CLOCKCLK(PIN 1)Figure 6. CY7C330 I/O Macro CellINPUTCLOCKS CK2 CK1(PIN 3)(PIN 2)0024-74-3

~ Introduction to CMOS EPLDs (Continued)~~~NDUcrOR~===================================================================FROMLOGICARRAYFEEDBACKTO LOGICARRAYINPUT TOLOGICARRAYFEEDBACKTO LOGICARRAYFROMLOGICARRAY0024-8Figure 7. CY7C330 I/O Macro Cell Pair Shared Input MUXGLOBAL SYNCHRONOUS SETFEEDBACK TO LOGIC ARRAYGLOBAL STATEREGISTER CLOCKCLK(PIN 1)Figure 8. CY7C330 Hidden State Register Macro Cell0024-94-4

~ Introduction to CMOS EPLDs (Continued)~~~~uaOR =======================================================================PIN 14 ----I OEMUXSET PRODUCT TERMSOUTPUTREGISTERQ ~~----------~CLOCK PRODUCT TERMRESET PRODUCT TERMR__ ....!i;....I--------1FE~~~CKSQDINPUTREGISTERTO SHAREDINPUT MUXFigure 9. CY7C331 Registered Asynchronous Macrocell0024-10OECLOCK ARI0.-LL· r-I- MACRO-CELL· ... t>3 -b 11 I-.. -Figure 10. Programmable Macro Cell#I~I/OSP0024-64-5

fir~ ===ID;;;;;:t;;;;;:r;;;;;:o;;;;;:d;;;;;:uc;;;;;:t;;;;;:io;;;;;:D=to=C=M=O=S=E;;;;;:P=L;;;;;:D=s;;;;;:

Features-.:zPAL® C 20 Seriesif CYPRESS, SEMICONDUCTOR Reprogrammable CMOSPAL® C 16L8, 16R8, 16R6, 16R4• CMOS EPROM technology forreprogrammability• High performance at quarterpower-tpD = 25ns-ts = 20ns- teo = 15 ns-Icc = 45mA• High performance at militarytemperature-tpD = 20ns-ts = 20ns- teo = 15 ns- Icc = 70 mA• Commercial and militarytemperature range• High reliability- Proven EPROM technology- > 1500V input protectionfrom electrostatic discharge- 100% AC/DC tested- 10% power supply tolerances- High noise immunity- Security feature preventspattern duplication- 100% programming andfunctional testingFunctional DescriptionCypress PAL C Series 20 devices arehigh speed electrically programmableand UV erasable logic devices producedin a proprietary "N" well CMOSEPROM process. These devices utilizethe sum of products (AND-OR) structureproviding users the ability to pro-gram custom logic functions servingunique requirements.PALs are offered in 20-pin plastic andceramic DIP, Plastic SOJ, and ceramicLCC packages. The ceramic packagecan be equipped with an erasure window;when exposed to UV light, thePAL is erased and can then be reprogrammed.Before programming, AND gates orPRODUCT TERMS are connected viaEPROM cells to both TRUE andCOMPLEMENT inputs. Programmingan EPROM cell disconnects anINPUT TERM from a PRODUCTTERM. Selective programming ofthese cells allows a specific logic functionto be implemented in a PAL C device.PAL C devices are supplied in ...four functional configurations, desig- ...Logic Symbols and DIP and SOJ Pinouts16R8 16R6 16R416L8LCCPinouts0038-1 0038-2uD. UD.D.~ ~o_ u>o _u> _ u> ::::.0038-3 0038-4U_>00 00 00 00 00 0- ~I~ 0 0 - ~I~ ~ 0 - ~I~ ~ ~> 0038-5 > - 0038-6 > --I/OI/O0 I/O0 I/O0 I/O0 I/O- en- 0 0en ::::.0038-7 > 0038-8PAL® is a registered trademark of Monolithic Memories Inc.CYPRESS SEMICONDUCTOR is a trademark of Cypress Semiconductor Corporation.4-7

~ PAL®C20Series~~~ucr~================================================================~Functional Description (Continued)nated 16R8, 16R6, 16R4 and 16L8. These eight deviceshave potentially 16 inputs and 8 outputs configurable bythe user. Output configurations of 8 registers, 8 combinatorial,6 registers and 2 combinatorial as well as 4 registersand 4 combinatorial are provided by the four functionalvariations of the product family. All combinatorial outputson the 16R6 and 16R4 as well as 6 of the combinatorialoutputs on the 16L8 may be used as optional inputs. Allregistered outputs have the Q bar side of the register fedback into the main array. The registers are automaticallyinitialized on power up to Q output LOW and Q outputHIGH. All unused inputs should be tied to ground.All PAL C devices feature a SECURITY function whichprovides the user protection for the implementation of proprietarylogic. When invoked, the contents of the normalarray may no longer be accessed in the verify mode. BecauseEPROM technology is used as a storage mechanism,the content of the array is not visible under a microscope.The PAL C device also contains a PHANTOM ARRAYused for functional and performance testing. The contentof this array is always accessible, even when security isinvoked.Cypress PAL C products are produced in an advanced 1.2micron "N" well CMOS EPROM technology. The use ofthis proven EPROM technology is the basis for a superiorproduct with inherent advantages in reliability, testability,programming and functional yield. EPROM technologyhas the inherent advantage that all programmable elementsmay be programmed, tested and erased during the manufacturingprocess. This also allows the device to be 100%Commercial Selection Guidefunctionally tested during manufacturing. An ability topreload the registers of registered devices during the testingoperation makes the testing easier and more efficient. ThePHANTOM ARRAY and PHANTOM operating modeallow the device to be tested for functionality and performanceafter it has been packaged. Combining these inherentand designed-in features, an extremely high degree of functionality,programmability and assured AC performanceare provided and testing becomes an easy task.The REGISTER PRELOAD allows the user to initializethe registered devices to a known state prior to testing thedevice, significantly simplifying and shortening the testingprocedure.The PHANTOM MODE of operation provides a completelyseparate operating mode where the functionality ofthe device along with its AC performance may be ascertained.The user need not be encumbered by programmedcells in the normal operating mode. This PHANTOMMODE of operation allows additional input lines to be programmedto operate the PAL C device, exercising the devicefunctionally and allowing AC performance measurementsto be made. The PHANTOM MODE of operationacknowledges only the INPUT TERMS shown shaded inthe functional block diagrams. Likewise, the normalPHANTOM INPUT TERMS do not exist in the normalmode of operation. During the final stages of manufacturing,some cells in the PHANTOM ARRAY are programmedfor final AC and functional testing. These cellsremain programmed, and may be used at incoming inspectionto verify both functional and AC performance.GenericOutput lee (mA) tpD (ns) ts (ns) teo (ns)Part Logic OutputsNumber EnableL STD -25 -35 -25 ·35 ·25 ·3516L8(8) 7-wide(6) BidirectionalAND-OR-InvertProgrammable(2) Dedicated45 70 25 35 - - - -16R8 (8) 8-wide AND-OR Dedicated Registered Inverting 45 70 - - 20 30 15 25(6) 8-wide AND-OR Dedicated Registered Inverting16R6 (2) 7-wide 45 70 25 35 20 30 15 25ProgrammableAND-OR-InvertBidirectional(4) 8-wide AND-OR Dedicated Registered Inverting16R4 (4) 7-wide 45 70 25 35 20 30 15 25Programmable BidirectionalAND-OR-InvertMilitary Selection GuideGenericOutputleetpD (ns) ts (ns) teo (ns)Part Logic OutputsNumber Enable (mA)-20 ·30 ·40 -20 -30 ·40 -20 -30 ·4016L8(8) 7-wide(6) BidirectionalProgrammableAND-OR-Invert(2) Dedicated70 20 30 40 - - - - - -16R8 (8) 8-wide AND-OR Dedicated Registered Inverting 70 - - - 20 25 35 15 20 25(6) 8-wide AND-OR Dedicated Registered Inverting16R6 (2) 7-wide 70 20 30 40 20 25 35 15 20 25Programmable BidirectionalAND-OR-Invert(4) 8-wide AND-OR Dedicated Registered Inverting16R4 (4) 7-wide 70 20 30 40 20 25 35 15 20 25Programmable BidirectionalAND-OR-Invert4-8

~ PAL®C20Series~~~U~ =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CUV Exposure ........................ 7258 Wsec/cm2Ambient Temperature withStatic Discharge Voltage ..................... > 1500VPower Applied .................... - 55°C to + 125°C (per MIL-STD-883 Method 3015)Supply Voltage to Ground Potential(Pin 20 to Pin 10) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to +7.0VDC Input Voltage ................... - 3.0V to + 7.0VLatchup Current .......................... > 200 mAOperating RangeRangeAmbientTemperatureOutput Current into Outputs (Low) ............. 24 mA Commercial O°Cto +70°C 5V ±10%DC Programming Voltage ...................... 14.0V Military [8] - 55°C to + 125°C 5V ±10%VeeElectrical Characteristics Over Operating Range (Unless Otherwise Noted)[7]Parameters Description Test Conditions Min. Max. UnitsVee = Min. IOH = -3.2mA CommercialVOH Output HIGH Voltage 2.4 VVIN = VIH or VIL IOH = -2mA MilitaryVee = Min. IOL = 24mA CommercialVOL Output LOW Voltage 0.4 VVIN = VIH or VIL IOL = 12mA MilitaryVIH Input HIGH Level Guaranteed Input Logic HIGH[2] Voltage for all Inputs 2.0 VVIL Input LOW Level Guaranteed Input Logical LOW[2] Voltage for all Inputs 0.8 VIIX Input Leakage Current VSS s VIN s Vee[1] -10 10 p.AVpp Programming Voltage Ipp = 50 mA Max. 13.0 14.0 VIse Output Short Circuit Current Vee = Max., VOUT = 0.5V[3] -300 mAAll Inputs = GND, "L" 45 mAIcc Power Supply Current Vee = Max., STD 70 mAlOUT = 0 mA[6]MIL 70 rnAIoz Output Leakage Current Vee = Max., Vss s VIN s Vee -100 100 p.ACapacitance [41Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 7COUT Output Capacitance VIN = 0, Vee = 5.0V 7pFII4-9

~ PAL® C20Series~~~~UcrOR==================================================================Switching Characteristics PAL C 20 Series Over Operating Range [5, 7]CommercialMilitaryParameters Description ·25 ·35 ·20 ·30 ·40 UnitstpDInput or Feedback to Non·RegisteredOutput 16L8, 16R6, 16R4Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.25 35 20 30 40 nstEA Input to Output Enable 16L8, 16R6, 16R4 25 35 20 30 40 nstER Input to Output Disable 16L8, 16R6, 16R4 25 35 20 30 40 nstpzx Pin 11 to Output Enable 16R8, 16R6, 16R4 20 25 20 25 25 nstpxz Pin 11 to Output Disable 16R8, 16R6, 16R4 20 25 20 25 25 nstco Clock to Output 16R8, 16R6, 16R4 15 25 15 20 25 nsts Input or Feedback Setup Time 16R8,16R6,16R420 30 20 25 35tH Hold Time 16R8, 16R6, 16R4 0 0 0 0 0 nstp Clock Period 35 55 35 45 60 nstw Clock Width 15 20 12 20 25 nsfMAX Maximum Frequency 28.5 18 28.5 22 16.5 MHzNotes:1. IIX (Pin 1) = 25 p.A Max., Vss ~ VIN ~ 2.7V. IIX (Pin 1) = 1 rnAMax., 2.7V ~ VIN S; Vcc.5. Figure la test load used for all parameters except tEA. tER tpzx andtpxz. Figure 1 b test load used for tEA, tER, tpzx and tpxz.2. These are absolute values with respect to device ground and all overshootsdue to system or tester noise are included.6. ICC(AC) = (0.6 mAIMHz) X (Operating Frequency in MHz) +IcC(oC). IcC(oC) is measured with an unprogrammed device.3. Not more than one output should be tested at a time. Duration of theshort circuit should not be more than one second. VOUT = 0.5V hasbeen chosen to avoid test problems caused by tester ground degradation.7. See the last page of this specification for Group A subgroup testinginformation.8. T A is the "instant on" case temperature.4. Tested initially and after any design or process changes that mayaffect these parameters.AC Test Loads and WaveformsR1 175 rI5VO---------~~~OUTPUT o-------4~------.6I~PFFigure la. CommercialR2133HR1175r15Vo---------JV~~OUTPUT (r-----.-----.R2133r1Figure lb. Commercial0038-11Equivalent to:THEVENIN EQUIVALENT COMMERICALns75r1OUTPUT O----..JI"M 02.16V0038-10R1 337 rIR1 337 rI5 V 5 V O-------JV~---,OUTPUTFigure lc. MilitaryR2247r1OUTPUT 0-----_0--------.Figure Id. MilitaryR2247r10038-9Equivalent to:THEVENIN EQUIVALENT MILITARY143r1OUTPUT O---..... \NI..,..---~O 2.11 V0038-123.0 V-----..J~ __ ---~GND---~s5nsFigure 2:;;5 ns0038-134-10

~ PAL® C 20 Series~~~~~==================================================================~witching WaveformsINPUTS, I/O,REGISTEREDFEEDBACK~~ ________ ~~~UC~~ __________________________________ ~~ ______ ~ ________CPREGISTERED ----,n;x']tNr-------1------,~~~~t__4l+to(OUTPUTS: ____ -L~~~L-------~-------J~~~ ~~~ ______________ ~ ________ ~--------COMBINATORIALOUTPUTS:PD_ ___________________ t~:~~~~~~"'~~~_tE_A________________________________ rErasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the PAL C device. For this reason, an opaque labelshould be placed over the window if the device is exposedto sunlight or fluorescent lighting for extended periods oftime. In addition, high ambient light levels can create holeelectronpairs which may cause "blank" check failures or"verify errors" when programming "windowed" parts.This phenomenon can be avoided by use of an opaque labelover the window during programming in high ambientlight environments.The recommended dose for erasure is ultraviolet light witha wavelength of 2537 Angstroms for a minimum dose (UVintensity x exposure time) of25 Wsec/cm2. For an ultravioletlamp with a 12 m W /cm2 power rating, the exposurewould be approximately 35 minutes. The PAL C deviceneeds to be placed within 1 inch of the lamp during erasure.Permanent damage may result if the device is exposedto high intensity UV light for an extended period of time.7258 Wsec/cm 2 is the recommended maximum dosage.ProgrammingPAL C devices are programmed a BYTE at a time using avoltage to transfer electrons to a floating gate. The arrayprogrammed is addressed as memory of 256 bytes, usingaddress Tables 4 and 5. These addresses are supplied to thedevice over Pins 2 through 9. The data to be programmedis supplied on data inputs DO through D7 (Pins 19 throughFigure 3DC Programming Parameters Ambient Temperature = 25°CTable 10038-1412 inclusive). In the unprogrammed state, all inputs areconnected to product terms. A "1" on a data line causes acell to be programmed, disconnecting an INPUT TERMfrom a PRODUCT TERM. During verify, an unprogrammedcell causes a "1" to appear on the output, while aprogrammed cell will appear as a "0". Table 3 describesthe operating modes of the device and the programmingwaveforms are described in Figures 6 through 9. The actualsequence required to program a cell is described in Figure 5and applies for programming either standard or phantomportions of the array. The security bit should be programmedusing a single 10 ms pulse, and verified per Figure9.VppAoVeepDoA1 01A2 02A3 03A4 04AsD!;As 06A7 0.,VssPGM/~0038-15Figure 4. Programming Pin ConfigurationParameter Description Min. Max. Units NotesVpp Programming Voltage 13.0 14.0 VVccp Supply Voltage During Programming 4.75 5.25 VVIHP Programming Input High Voltage 3.0 VVILP Programming Input Low Voltage 0.4 VVOH Output High Voltage 2.4 V 1VOL Output Low Voltage 0.4 V 1Ipp Programming Supply Current 50 rnAII4-11

~ PAL® C20Series~~~~UaoR==================================================================AC Programming Parameters Ambient Temperature = 25°CTable 2Parameter Description Min. Max. Units Notestpp Programming Pulse Width 100 10,000 IJ-s 2ts Setup Time 1.0 IJ-stH Hold Time 1.0 IJ-str, tf Vpp Rise and Fall Time 1.0 IJ-s 2tvo Delay to Verify 1.0 IJ-stvp Verify Pulse Width 2.0 IJ-stov Verify to Data Vaiid 20.0 IJ-stoz Verify to High Z 1.0 IJ-sTable 3Pin Name Vpp PGM/OE AlPin Number (1) (11) (3)Operating ModesPAL X X XProgram PAL Vpp Vpp XProgram Inhibit Vpp VIHP XProgram Verify/Blank Check Vpp VILP XPhantom PAL X X XProgram Phantom PAL Vpp Vpp XPhantom Program Inhibit Vpp VIHP XPhantom Program Verify Vpp VILP XProgram Security Bit Vpp Vpp VppVerify Security Bit X X Note 9Register Preload X X XNotes:1. Ouring verify operation2. Measured at 10% and 90% points3. VSS < X < Vccp4. All "X" inputs operational per normal PAL function.5. Address inputs occupy Pins 2 thru 9 inclusive, for both programmingand verification see programming address Tables 4 and 5.6. All "X" inputs operational per normal PAL function except that theyoperate on the function that occupies the phantom array.7. Address inputs occupy Pins 2 thru 9 inclusive, for both programmingand verification see programming address Tables 4 and 5. Pin 7The programmable array is addressed as a basic 256 by 8memory structure with a duplication of the phantom arraylocated at the same addresses as columns 0, 1,2 and 3. Theability to address the phantom array as differentiated fromthe first 4 columns of the normal array is accomplished bytaking Pin 7 to Vpp and entering the phantom mode ofoperation as shown in Tables 3 and 5. In either case, phantomor normal, product terms are addressed in groups of 8per Table 4. Notice that this is accomplished by modulo 8A2 A3 A4 AS D7-DO(4) (5) (6) (7) (12-19) NotesX X X X Programmed Function 3,4X X X X Data In 3,5X X X X HighZ 3,5X X X X Data Out 3,5,11X X Vpp X Programmed Function 3,6X X X Vpp Data In 3,7X X X Vpp HighZ 3,7X X X Vpp Data Out 3,7X X X X HighZ 3,8Vpp X X X HighZ 3XVpp X X Data In 3,10is used to select the phantom mode of operation and must be taken toVpp before selecting phantom program operation with Vpp on Pin I.8. See Figure 8 for security programming sequence.9. The state of Pin 3 indicates if the security function has been invokedor not. If Pin 3 = VOL security is in effect, if Pin 3 = V OH, the datais unsecured and may be directly accessed.10. For testing purposes, the output latch on the I6R8, I6R6 and I6R4may be preloaded with data from the appropriate associated outputline.11. It is necessary to toggle Pin 11 (OE) HIGH during all address transitionswhile in the Program Verify or Blank Check mode.selecting every eighth product term starting with 0, 8, 16,24, 32, 40, 48 and 56 corresponding to PROGRAMMEDDATA INPUT on DO through D7 respectively and incrementingeach product term by one until all 64 PRODUCTTERMS are addressed. Each of the INPUT TERMS isaddressed 8 times corresponding to the 8 groups of individualproduct terms addressed before being incremented.4-12

~ PAL® C 20 Series~~~NDUcrOR =====================================================================Table 4Binary AddressesPin Numbers(4) (3) (2)Product Term AddressesLine NumberVILP VILP VILP 0 8 16 24 32 40 48 56VILP VILP VIHP 1 9 17 25 33 41 49 57VILP VIHP VILP 2 10 18 26 34 42 50 58VILP VIHP VIHP 3 11 19 27 35 43 51 59VIHP VILP VILP 4 12 20 28 36 44 52 60VIHP VILP VIHP 5 13 21 29 37 45 53 61VIHP VIHP VILP 6 14 22 30 38 46 54 62VIHP VIHP VIHP 7 15 23 31 39 47 55 63DO Dl D2 03 04 05 06 D7Programmed Data InputInput Term AddressesTable 5Input Term AddressesInputBinary AddressesInputBinary AddressesTerm Pin Numbers Term Pin NumbersNumbers(9) (8) (7) (6) (5) Numbers (9) (8) (7) (6) (5)0 VILP VILP VILP VILP VILP 18 VIHP VILP VILP VIHP VILP1 VILP VILP VILP VILP VIHP 19 VIHP VILP VILP VIHP VIHP2 VILP VILP VILP VIHP VILP 20 VIHP VILP VIHP VILP VILP3 VILP VILP VILP VIHP VIHP 21 VIHP VILP VIHP VILP VIHP4 VILP VILP VIHP VILP VILP 22 VIHP VILP VIHP VIHP VILP5 VILP VILP VIHP VILP VIHP 23 VIHP VILP VIHP VIHP VIHP6 VILP VILP VIHP VIHP VILP 24 VIHP VIHP VILP VILP VILP7 VILP VILP VIHP VIHP VIHP 25 VIHP VIHP VILP VILP VIHP8 VILP VIHP VILP VILP VILP 26 VIHP VIHP VILP VIHP VILP9 VILP VIHP VILP VILP VIHP 27 VIHP VIHP VILP VIHP VIHP10 VILP VIHP VILP VIHP VILP 28 VIHP VIHP VIHP VILP VILP11 VILP VIHP VILP VIHP VIHP 29 VIHP VIHP VIHP VILP VIHP12 VILP VIHP VIHP VILP VILP 30 VIHP VIHP VIHP VIHP VILP13 VILP VIHP VIHP VILP VIHP 31 VIHP VIHP VIHP VIHP VIHP14 VILP VIHP VIHP VIHP VILP PO VILP VILP Vpp X X15 VILP VIHP VIHP VIHP VIHP PI VILP VIHP Vpp X X16 VIHP VILP VILP VILP VILP P2 VIHP VILP Vpp X X17 VIHP VILP VILP VILP VIHP P3 VIHP VIHP Vpp X X4-l3

STARTVCCp=5.0VVpp=13.5VIADDR 1STLOCATION1M =0IPROGRAMONE PULSEOF 0.1 msec1M=M+lIM=20?YES.. ~ NOFAILVERIFYONE BYTE?I PASSPROGRAMONE PULSEOF 4 (0.11(MI msec1M = 20?I VERIFY IYES1BYTEI FAIL1 NOPASSI INCREMENT 1 LASTADDR NO ADDRESS?1 I1 YESREADI REJECT 1Vccp=5.0V FAILDEVICE1 I1 PASSALL BYTES?PROGRAMCOMPLETEGOODDEVICEFigure 5. Programming Flowchart0038-164-14

~ PAL® C 20 Series~~~NDucroR =====================================================================PROGRAM PROGRAM VERIFYINHIBITtAHVIHP - -­ADDRESS-ADDRESS Ao THRU A91~VILP - - --~LI---tAStov--tozI-"tos .....VIHP - - -­- -~DATAT -DATA IN Do THRU 07 DATA OUT Do THRU 07~.... F- ..; ... -VILP - - ---=tr .1. 'tAS_ fo-tOHIvpP-----~tAH tfIIVIHP - - -­VPPVILP - - --Vpp ___ _VIHP - - -­PGM/OEVILP - - --"t\~tr_-~tf-,....,F- .... r-I PROGRAM _F-I-~.....-tpp- ...f.--tvo-VERIFY 7~Figure 6. Programming Waveforms Normal Arraytvp0038-1714-----PROGRAM----_~pr~~:~M_ ..... -------VERIFY-------~1+----tAH----+IVIHP- - ------""'\p-----------------------+-------+------------+----------...,.l,.--VILP- ADDRESS -- ___ ..1-1'-____________ -+-_____ +-_________ + ________...11Vpp - --VILP- --VIHP--­DATA ------~-----4VILP---VPP- --tOHVPPVIHP- --VILP - - - ___ ~,Vpp---VIHP------------~PGM/OEVILP---VERIFYtvo--tII+----tvP----tFigure 7. Program Waveforms Phantom Array0038-184-15

~~====================================~P~A~L~®;R~C~2~o~s~e~r~ie~svpP----trVIHP- - -­AlVllP - - --vPP ___ _VIHP---­vppVllP - - --vpp----tAHVIHP---­PGM/(llVllP - - - - -------.....;;;=lFigure 8. Activating Program Security0038-19VIHP - - --VllP _ ~~~ ----------------------.JVpp----DATA OUT Al (NOTE 1)VllP - - - - -------------------...;;;IftovtozVIHP - - -­A2~-----tvp----~~Figure 9. Verify Program Security0038-204-16

~CYPRESSPAL® C 20 Series~~~CO~UaDR==============================================~~~==~~~~~Functional Logic Diagram PAL C 16L8INPUTS (0 - 311.... ~1~191..;:1 ......... ----181~ .......... ----17;;; 16CDI2~II:III 5~t3jQQII:A. 15II____ ~1~14I ~IO-....... ---- 13t ~1IO_-----12~++~~~~~-++++-++++~HH~~+-~tt=======~~----------114 5 6 7 8 91011 28293031 0038-214-17

~RESSPAL® C 20 Series'nICoNDucroR =====================================================Functional Logic Diagram PAL C 16R4INPUTS (0 - 31)>--f~>1~------------19~~~-----------1817M 16--i~~~------i------13~~~------+-----12114567 891011 12131415 16171819 20212223 282930310038-224-18

~CYPRfSSPAL® C 20 Series~~~~~~==========================================================~~Functional Logic Diagram PAL C 16R6INPUTS (0 - 3111817M 16'" I~en::Ea:5w~~U::I0~ 15II13>-~=)o~------~----121145 67 891011 12131415 18171819 202122 24252627 282930310038-234-19

~RJSSPAL® C 20 Series~~IOO~UaoR==================================================================Functional Logic Diagram PAL C 16R8INPUTS (0 - 31)1918M 16'" I~(I):Effi 5t-t-o::>c0g:151413121145 67 891011 12131415 161718 202122 282930314-20

~ PAL®C20Series~~~NDUcrOR =====================================================================Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.4.-----r--....... --,.--."NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.6 r:;..;..:..::..:::..::::-=....;:-----...NORMALIZED PROPAGATIONDELAY vs. SUPPLY VOLTAGE1.21.2 I----+---+----.F--~uu 1.21--~~-_+_----~faN:i~ 1.0rri0.8 I------+-----==~ _ _IEfaN::;c(:::Err0z1.11.00.9~"" ""'" .....4.5 5.0 6.00.6L---__ -1..____.....J-55 25 1250.84.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE ('C)SUPPLY VOLTAGE (V)NORMALIZED PROPAGATION DELAYvs. TEMPERATURE1.3,..-----~-----...,DELTA PROPAGATION TIMEvs. OUTPUT LOADING20.0NORMALIZED SETUP TIMEvs. SUPPLY VOLTAGE1.2~...fa~ 1.11--------+--~L--_Ic(:::Err~125cQc(8Q15.010.05.0V p/'"~y.."".V200 400 600 800 1 DODEfaN::;c(:::Err0z1.11.00.9~"" "" '" "0.84.0 4.5 5.0 5.5 6.0IIAMBIENT TEMPERATURE ('C)CAPACITANCE (pF)SUPPLY VOLTAGE (V)NORMALIZED SETUP TIMEvs. TEMPERATURE1.3 ....... ----,..------......,NORMALIZED CLOCK TO OUTPUTTIME vs. SUPPLY VOLTAGE1.1 r----..,..---r--~--...NORMALIZED CLOCKTO OUTPUTTIME vs. TEMPERATURE~faN::;c(:::Erroz~faN::;c(:::Erroz~SN::;c(:::ErroZ0.9L---L __....l..-__ L-_.....J4.0 4.5 5.0 5.5 6.0AMBIENT TEMPERATURE ('C)SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE ('C)cE10.0 c(8Q20.015.05.0DELTA CLOCK TO OUTPUT TIMEvs. OUTPUT LOADING/yV v/'"./0.0 0 200 400 6DO 600 1000~!...~rrrr:::lu~ziii...~...:::l0200175150OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE/VJ...--1257100J75-,50~~c=~~;~v _/ I257~.o 1.0 2.0 3.0 4.0~!...~a::rr:::luwua:::::l51... ~:::l0OUTPUT SOURCE CURRENTvs. VOLTAGE14012010080604020r\.~"-'" ~ "~.........1.0 2.0 3.0 4.0CAPACITANCE (pF)OUTPUT VOLTAGE (V)4-21OUTPUT VOLTAGE (V)0038-25

~ PAL®C20Series~~~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==Ordering InformationtpD(ns)ts(ns)teo Icc Ordering CodeOperating(ns)Package(mA) Range20 - - 70 PAL C 16LS-200MB 06 MilitaryPAL C 16LS-20LMBL61PAL C 16L8-20WMBW625 - - 45 PAL C 16L8L-25PC P5 CommercialPAL C 16LSL-25VCV5PAL C 16LSL-25LCL61PAL C 16L8L-25WCW670 PAL C 16L8-25PC P5PAL C 16L8-25VCV5PAL C 16L8-25LCL61PAL C 16L8-25WCW630 - - 70 PAL C 16L8-300MB 06 MilitaryPAL C 16LS-30LMBL61PAL C 16L8-30WMBW635 - - 45 PAL C 16L8L-35PC P5 CommercialPAL C 16L8L-35VCV5PAL C 16L8L-35LCL61PAL C 16L8L-35WCW670 PAL C 16L8-35PC P5PAL C 16LS-35VCV5PAL C 16L8-35LCL61PAL C 16L8-35WCW640 - - 70 PAL C 16L8-400MB 06 MilitaryPAL C 16LS-4OLMBL61PAL C 16L8-4OWMBW620 20 15 70 PAL C 16R4-200MB 06 MilitaryPAL C 16R4-20LMBL61PALC 16R4-20WMBW625 20 15 45 PAL C 16R4L-25PC P5 CommercialPAL C 16R4L-25VCV5PAL C 16R4L-25LCL61PAL C 16R4L-25WCW670 PAL C 16R4-25PC P5PAL C 16R4-25VCV5PAL C 16R4-25LCL61PAL C 16R4-25WCW630 25 20 70 PAL C 16R4-300MB 06 MilitaryPAL C 16R4-30LMBL61PAL C 16R4-30WMBW635 30 25 45 PAL C 16R4L-35PC P5 CommercialPAL C 16R4L-35VCV5PAL C 16R4L-35LCL61PAL C 16R4L-35WCW670 PAL C 16R4-35PC P5PAL C 16R4-35VCV5PAL C 16R4-35LCL61PAL C 16R4-35WCW640 35 25 70 PAL C 16R4-400MB 06 MilitaryPAL C 16R4-4OLMBL61PAL C 16R4-4OWMBW64-22

~ PAL® C20Series~~~~UcrOR=====================================================================Ordering Information (Continued)tpD ts teo Icc Operating(ns) (ns) (ns)Ordering Code Package(rnA) Range20 20 15 70 PAL C 16R6-20DMB D6 MilitaryPAL C 16R6-20LMBL61PAL C 16R6-20WMBW625 20 15 45 PAL C 16R6L-25PC P5 CommercialPAL C 16R6L-25VCPAL C 16R6L-25LCL61PAL C 16R6L-25WCW670 PAL C 16R6-25PC P5PAL C 16R6-25VCVSPAL C 16R6-25LCL61PAL C 16R6-25WCW630 25 20 70 PAL C 16R6-30DMB D6 MilitaryPAL C 16R6-30LMBL61PAL C 16R6-30WMBW635 30 25 45 PAL C 16R6L-35PC 1 P5 CommercialPAL C 16R6L-35VCPAL C 16R6L-35LCPAL C 16R6L-35WCV5V5L61W6II70 PAL C 16R6-35PC P5PAL C 16R6-35VC V5PAL C 16R6-35LCL61PAL C 16R6-35WCW640 35 25 70 PALC 16R6-40DMB D6 MilitaryPAL C 16R6-40LMBL61PAL C 16R6-40WMBW6- 20 15 70 PAL C 16RS-20DMB D6 MilitaryPAL C 16RS-20LMBL61PAL C 16RS-20WMBW6- 20 15 45 PAL C 16RSL-25PC P5 CommercialPAL C 16RSL-25VCPAL C 16RSL-25LCPAL C 16RSL-25WCV5L61W670 PAL C 16RS-25PC P5PAL C 16RS-25VCV5PAL C 16RS-25LCPAL C 16RS-25WCW6- 25 20 70 PAL C 16RS-30DMB D6 MilitaryPAL C 16RS-30LMBL61PAL C 16RS-30WMBW6- 30 25 45 PAL C 16RSL-35PC P5 CommercialPAL C 16RSL-35VCPAL C 16RSL-35LCPAL C 16RSL-35WCL61V5L61W670 PAL C 16RS-35PC P5PAL C 16RS-35VCV5PAL C 16RS-35LCL61PAL C 16RS-35WCW6- 35 25 70 PAL C 16RS-40DMB D6 MilitaryPAL C 16RS-40LMBPAL C 16RS-40WMB4-23L61W6

~ PAL®C20Series~~~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Vpp 1,2,3Icc 1,2,3Ioz 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstpD 9,10,11tpzx 9,10,11teo 9,10,11ts 9,10,11tH 9,10,11Document #: 38-00001-A4-24

CYPRESSSEMICONDUCTORPLDC20GIOCMOS Generic 24 PinLogic DeviceFeatures• Fast- Commercial: tpD = 15 ns,teo = 10 ns, ts = 12 ns- Military: tpD = 20 ns,teo = 15 ns, ts = 17 ns• Low power- ICC max.: 70 mA,Commercial- ICC max.: 100 mA, Military• Commercial and militarytemperature range• User-programmable output cells- Selectable for registered orcombinatorial operation- Output polarity control- Output enable sourceselectable from pin 13 orproduct termLogic Symbol• Generic architecture to replacestandard logic functionsincluding: 20LI0, 20LS, 20R8,20R6, 20R4, 12LI0, 14LS, 16L6,18L4, 20L2 and 20V8• Eight product terms and one OEproduct term per output• CMOS EPROM technology forreprogrammability• Highly reliable- Uses proven EPROMtechnology- Fully AC and DC tested- Security feature preventslogic pattern duplication- > 2000V input protection forelectrostatic discharge- ± 10% power supply voltageand higher noise immunity20GI0Functional DescriptionCypress PLD devices are high speedelectrically programmable Logic Devices.These devices utilize the sum ofproducts (AND-OR) structure providingusers the ability to program customlogic functions for unique requirements.In an unprogrammed state the ANDgates are connected via EPROM cellsto both the true and complement of everyinput. By selectively programmingthe EPROM cells, AND gates may beconnected to either the true or complementor disconnected from both trueand complement inputs.Cypress PLD C 20G 10 uses an advanced0.8 micron CMOS technologyand a proven EPROM cell as the pro-LCC Pinout~ !:l~~u z __ u>~~PLCCPinout0053-154 3 2 11128272615 '-' 25I 6I 7I 8 20G10I 9I 10NC 11 1912131415161718NCI/OI/OI/OI/oI/oI/oNCNeINeI/OI/OI/OI/OI/OI/ONe0053-170053-264-25

~CYPRESSPLD C 20GIO~~~~O~UcrOR============================================================~==~Selection GuideGenericPartNumberIcCL Com Mil Com20G10-15[5] - 70 - 1520G 10-20[5] - - 100 -20GlO-25 - 55 - 2520GlO-30 - - 80 -20GlO-35 - 55 - 3520G10-40 - - 80 -tpD ts teoMil Com Mil Com Mil- 12 1020 - 17 15- 15 - 1530 - 20 20- 30 - 2540 - 35 - 25Functional Description (Continued)grammable element. This technology and the inherent advantageof being able to program and erase each cell enhancesthe reliability and testability of the circuit. This reducesthe burden on the customer to test and to handlerejects.A preload function allows the registered outputs to be presetto any pattern during testing. Preload is important fortesting the functionality of the Cypress PLD device.20G 10 Functional DescriptionTh~ PLD C 20G lOis a generic 24 pin device that can beprogrammed to logic functions which include but are notlimited to: 20LlO, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8,16L6, 18L4, 20L2 and 20V8. Thus, the PLD C 20GlOprovides significant design, inventory and programmingflexibility over dedicated 24 pin devices. It is executed in a24 pin 300 mil molded DIP and a 300 mil windowed Cerdip.It provides up to 22 inputs and 10 outputs. When thewindowed CERDIP is exposed to UV light, the 20G 10 iserased and then can be reprogrammed.The Programmable Output Cell provides the capability ofdefining the architecture of each output individually. Eachof the 10 output cells may be configured with "REGIS­TERED" or "COMBINATORIAL" outputs, "ACTIVEHIGH" or "ACTIVE LOW" outputs, and "PRODUCTTERM" or "PIN 13" generated output enables. Three ArchitectureBits determine the configurations as shown inTable 1 and in Figures 2 through 9. A total of eight differentconfigurations are possible, with the two most commonshown in Figure 4 and Figure 6. The default or unprogrammedstate is REGISTEREDI ACTIVE LOW 1PRODUCT TERM OE as shown in Figure 2. The entireProgrammable Output Cell is shown in Figure 1.The architecture bit 'Cl' controls the REGISTEREDICOMBINATORIAL option. In the "COMBINATORI­AL" configuration, the output can serve as an 1/0 pin, orif the output is disabled, as an input only. Any unusedinputs should be tied to ground. In the "REGISTERED"configuration, the output of the register is fed back to thearray. This allows the creation of control-state machines byproviding the next state. The register is clocked by thesignal from Pin 1. T~ register is initialized on power up toQ output LOW and Q output HIGH.In both the Combinatorial and Registered configurations,the source of the "OUTPUT ENABLE" signal can be individuallychosen with architecture bit 'C2'. The OE signalmay be generated within the array, or from the externalOE pin (Pin 13). The Pin 13 allows direct control of theoutputs, hence having faster enable/disable times.Each output cell can be configured for "OUTPUT PO­LARITY". The output can be either Active HIGH or ActiveLOW. This option is controlled by architecture bit'CO'.Along with this increase in functional density, the CypressPLD C 20G 10 provides lower power operation through theuse of CMOS technology, increased testability with a registerpreload feature and guaranteed AC performancethrough the use of a phantom array. The phantom arrayallows the 20GI0 to be programmed with a test patternand tested prior to shipment for full AC specificationswithout using any of the functionality of the device specifiedfor the product application. In addition, this samephantom array may be used to test the PLD C 20G 10 atincoming inspection before committing the device to a specificfunction through programming.Programmable Output CellC2---!---t--------++-+---.JCo __-!-..__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_---l___C,---7-........ -----------IFigure 1PIN 13 0053-324-26

~ PLDC20GIO~~~~================================================================Configuration TableFigure C2 Cl2 0 03 0 06 0 17 0 14 1 05 1 08 1 19 1 1Registered Output ConfigurationsTable 1Co01010101ConfigurationProduct Term OE/Registeredl Active LOWProduct Term OElRegisteredl Active HIGHProduct Term OE/Combinatorial/ Active LOWProduct Term OE/Combinatorial/ Active HIGHPin 13 OElRegisteredl Active LOWPin 13 OElRegisteredl Active HIGHPin 13 OE/Combinatorial/ Active LOWPin 13 OE/Combinatorial/ Active HIGHFigure 2. Product Term OEI Active LOW0053-370053-38Figure 3. Product Term OEI Active HIGHFigure 4. Pin 13 OEI Active LOW0053-39Figure 5. Pin 13 OEI Active HIGH0053-40Combinatorial Output Configurations[6]0053-33Figure 6. Product Term OEI Active LOW0053-34Figure 7. Product Term OEI Active HIGH~PIN130053-35Figure 8. Pin 13 OEI Active LOW~PIN130053-36Figure 9. Pin 13 OEI Active HIGH4-27

~ . PLD C 20G10~~~NDUcrOR=====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -6SoC to + IS0°C Static Discharge Voltage ..................... >2001VAmbient Temperature with(per MIL-STD-883 Method 30 IS)Power Applied .................... - 55°C to + 125°C Latchup Current .......................... > 200 rnASupply Voltage to Ground Potential .... - O. SV to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - O.SV to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current into Outputs (Low) ........ ; .... 16 rnADC Programming Voltage ...................... 14.0VOperating RangeRangeElectrical Characteristics Over Operating Range (Unless Otherwise Noted)[7]AmbientTemperatureVeeCommercial O°Cto + 70°C 5V ± 10%Military [8] - 55°C to + 125°C 5V ± 10%Parameters Description Test Conditions Min. Max. UnitsVOHOutput HIGH VoltageVee = Min. IOH = -3.2mA CommercialVIN = VIR or VILIOH = -2mA Military2.4 VVee = Min. IOL = 16mA CommercialVOL Output LOW Voltage 0.5 VVIN = VIH or VIL IOL = 12mA MilitaryVIR Input HIGH Level Guaranteed Input Logical HIGH[l] Voltage for all Inputs 2.0 VVIL Input LOW Level Guaranteed Input Logical LOW[l] Voltage for all Inputs 0.8 VIIX Input Leakage Current Vss :s; VIN:S; Vee -10 10 p,AVpp Programming Voltage @ Ipp = 50 rnA Max. 13.0 14.0 VIseOutput Short CircuitCurrentVee = Max., VOUT = 0.5V[2] -90 rnACommercial -15 [5] 70O:S; VIN:S; Vee Commercial -25, -35 55lee Power Supply Current rnAVee = Max., lOUT = 0 rnA Military -20[5] 100Military -30, -40 80Ioz Output Leakage Current Vee = Max., VSS :s; VOUT :s; Vee -100 100 p,A4-28

~ PLDC20GI0~~~NDUcroR =====================================================================Capacitance [3]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance T A = 25°C, f = 1 MHz 4COUT Output Capacitance VIN = 0, Vee = 5.0V 7pFSwitching Characteristics PLD C 20GIO Over Operating Range[4, 71CommercialMilitaryParameters Description ·15[5] ·25 ·35 ·20[5] ·30 ·40 UnitstpDInput or Feedback toNon-Registered OutputtEA Input to Output Enable 15tER Input to Output Disable 15tpzx Pin 13 to Output Enable 12tpxz Pin 13 to Output Disable 12teo Clock to Output 10ts Input or Feedback Setup Time 12 15tH Hold Time 0 0tp Clock Period 22 35tw Clock Width 11 15fMAX Maximum Frequency 45.5 33.3Notes:1. These are absolute values with respect to device ground and all overshootsdue to system or tester noise are included.2. Not more than one output should be tested at a time. Duration of theshort circuit should not be more than one second. VOUT = O.5V hasbeen chosen to avoid test problems caused by tester ground degradation.3. Tested initially and after any design or process changes that mayaffect these parameters.Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max1525252520201535 20 30 40 ns35 20 30 40 ns35 20 30 40 ns25 17 25 25 ns25 17 25 25 ns25 15 20 25 ns30 17 20 35 ns0 0 0 0 ns55 32 45 60 ns20 16 20 25 ns18 31.3 25 16.5 MHz4. Figure lOa test load used for all parameters except tER, tpzx andtpxz. Figure JOb test load used for tER, tpzx and tpxz.5. Preliminary specifications.6. Bidirectionall!O configurations are possible only when the combinatorialoutput option is selected.7. See the last page of this specification for Group A subgroup testinginformation.8. TA is the "instant on" case temperature.II4-29

~ PLDC20GIO~~~~================================================================AC Test Loadsnand Waveforms (Commercial)nINPUT PULSESR1 238.0. R1 238.0.(319.0. MIL) (319.0. MIL)3.0 V-----.----....IOUTP~~R2OUTP~~. R2GND---~INCLUDING50 PF'I 170.0. 5pF' 170.0.(236.0. MIL) I (236.0. MIL)JIG AND -= -= -=-- Figure 11SCOPEFigure lOaFigure lObEquivalent to: THEVENIN EQUIVALENT (Commercial) Equivalent to: THEVENIN EQUIVALENT (Military)0053-6~ 5ns0053-8OUTPUT no--~Switching WaveformsOUTPUT on---0053-7 0053-24INPUTS, I/O,;~~~~~~:D ~~~~ ____ ~CC(W~Q£~ _____________________________ ~~ ______ ~ ______ __CPREGISTERED ----,~m70V---------t----\).t+"(~'r"oH.....__ +41+C_________________ ~_tPD ________________________________ -'~~~~~+-~~""~~~_tE_A_OUTPUTS: ____ -l~~~~------~------jUUU~ ~~ ________________ ~ ______ ~--------COMBINATORIAL ...OUTPUTS:Note:For more information regarding PLD devices, refer to the Application Brief in the Appendix.0053-94-30

~~~========================================~P~L~D~C~2~O~G~1~OFunctional Logic Diagram PLD C 20G 10Vl::p;a::I.IJl-I­U::>oa::a.1-rD PI P 3Po P2OE0: -~OE02~OE0:-3~,OE0_:-4~'OE05~O~ -6 I~'OE07 .~OE0:-8 ,~91011OE0.-~OE0~~0 4 8 12 16 20 24 2832 36 40.r'I.it>,.,tFi=0c1- I>CELL ~ 23...::=~ OUTPUT- ~'-l""I..,">-- OUTPUTCELL1I> CELL~ 22:::::=rlc1- I> ~ 21.:=IP-r OUTPUT r1.....,. ..... ~11:>- OUTPUT:a::J~--I>CELL~.==~1CELLI>"'--..--i>:- ~1l"""l"V ....OUTPUTCELLI>!==C::t r-- OUTPUT~d-~120d-.:=lb16CELLI>7:ct J- OUTPUT I-~.:=Hr-- OUTPUT I-lb1:c:J-.CELL~ ~ 5I>-- ....r--~lbA I>CELL 1--;~~"' .....9841 3INPUT LINES0053-234-31

~ PLDC20GIO~~~UCTOR ==~~~~~~~~~~===============================================Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the PLO C 20G 10. For this reason, an opaque labelshould be placed over the window if the device is exposedto sunlight or fluorescent lighting for extended periods oftime. In addition, high ambient light levels can create holeelectronpairs which may cause "blank" check failures or"verify errors" when programming "windowed" parts.This phenomenon can be avoided by use of an opaque labelover the window during programming in high ambientlight environments.The recommended dose for erasure is ultraviolet light witha wavelength of2537 Angstroms for a minimum dose (UVintensity X exposure time) of25 Wsec/cm2. For an ultravioletlamp with a 12 m W / cm2 power rating, the exposurewould be approximately 35 minutes. The PLO C 20G 10needs to be placed within 1 inch of the lamp during erasure.Permanent damage may result if the device is exposedto high intensity UV light for an extended period of time.7258 Wsec/cm2 is the recommended maximum dosage.Device ProgrammingThe PLO C 20G 10 can be programmed on inexpensiveconventional PROM/EPROM programmers with appropriatepersonality or socket adapters and the CY3000QuickPro programmer. Once the PLO device is programmed,one additional location can be programmed toprohibit logic pattern verification. This security featuregives the user additional protection to safeguard his proprietarylogic. This feature is highly reliable and due tbEPROM technology it is impossible to visually read theprogrammed cell locations.The PLO C 20G 10 has multiple programmable functions.In addition to the normal array, a "PHANTOM" array,"TOP and BOTTOM TEST" and a "SECURITY" featureare programmable. The PLO C 20G 10 security mechanism,when invoked, prevents access to the "NORMAL"and "TOP/BOTTOM TEST" array. The "PHANTOM"array feature is still accessible, allowing programming andverification ofthe pattern in the "PHANTOM" array.Functional operation of all other features is allowed regardlessof the state of the "SECURITY BIT". In addition,the device contains 10 programmable output cells whichare programmed to configure the device functionality foreach specific application.The logic array is divided into a "NORMAL" array and a"PHANTOM" array. The normal array is used to configurethe device to perform a specific function as required bythe user, and the phantom array is provided as a test arrayfor Cypress' testing the device prior to user programmingthus assuring a reliable, thoroughly tested product. The"PHANTOM" array contains four additional columnsconnected to input pins 2 (TRUE), 7 (INVERTING), 10(TRUE) and 11 (TRUE). These inputs may be programmedto be connected to all normal product terms.This allows all sense amplifiers and programmable outputcells to be exercised for both functionality and performanceafter assembly and prior to shipment. These features are inaddition to the normal array. They do not affect normaloperation, allowing the user full programming of the normalarray, while allowing the device to be fully tested.The "TOP TEST" and "BOTTOM TEST" feature, allowconnection of all input terms to either pin 23 or 13. Theselocations may be programmed and subsequently exercisedin the "TOP TEST" and "BOTTOM TEST" mode. Likethe Phantom array above, this feature has no effect in thenormal mode of operation. Cells in the PHANTOM AR­RAY, TOP TEST, and BOTTOM TEST areas are programmedat Cypress during the manufacturing operation,and they therefore will be programmed when received in anon-windowed package by the user. Consequently, the userwill normally have no need to program these cells.The architecture bits Co, Cl and C2 are used to configureeach programmable output cell individually. Co selects outputpolarity, Cl selects the combinatorial or registeredmode of operation and C2 selects the source of output enable.If the registered mode of operation is selected, thefeedback path is automatically selected to be from the register.In the combinatorial mode the feedback path is automaticallyselected to be from the I/O pin. In this combinatorialmode, the output from the array may be fed into thearray or if the output is deselected using the output enableproduct term the pin may be used as an external input.There is not a mode where the I/O pin may be used as acombinatorial output or an input pin, while the register isused as a state register. The architecture bits are programmedas a separate item during normal programming.An I/O pin is configured to be an input by programmingthe output cell into a combinatorial mode and disabling theouput with the output enable product term.PinoutThe PLO C 20G 10 PROGRAMMING pinout is shown inFigure 12. In the Programming pinout configuration, thedevice may be programmed and verified for the NORMALmode of operation and also programmed, verified and operatedin PHANTOM and TEST modes. These specialmodes of operation are achieved through the use of supervoltagesapplied to certain pins. Care should be exercisedwhen entering and exiting these modes, paying specific attentionto both the operating modes as specified in Table 1and the sequencing of the supervoltages as shown in thetiming diagrams.Programming PinoutveeVppAODOA1 01A2 02A3 03A4 04A5 05A6 06A7 07A8 08A9 09VssFigure 12PGM/Vr0053-274-32

~ PLDC20GIO~~~UaoR==================================================================Programming AlgorithmWith the exception of the Security bit, all arrays are programmedin a similar manner. The data to be programmedis represented by a "1" or "0" on the I/O pins. A "1"indicates that an unprogrammed location is to be program~edand a "0" indicates that an unprogrammed locationis to remain unprogrammed. All locations to be programmedare addressed as row and column locations. Table2 "Operating Modes" along with Tables 3 through 6provide the specific address for each addressed location tobe programmed along with mode selection information forboth programming and operation in the "PHANTOM"and "TEST" modes.When programming the security bit, a supervoltage on pin3 is used as data with a programming pulse on pin 13.Verification is controlled with a supervoltage on pins 4 andthe data out on pin 3.20GIO JEDEC MapThe 20GlO JEDEC Map is organized as follows: theEPROM fuses for the product terms and input lines arelocated between ()()()() and 3959 (decimal). The architecturebits are located between locations 3960 and 3989. Location3960 is the Polarity Bit (CO), location 3961 is the Registered/CombinatorialBit (Cl), and location 3962 is theOutput Enable Bit (C2) for output pin 23. Locations 3963,3964, and 3965 are the architecture bit locations for outputpin 22. This pattern repeats for output pins 21, 20, 19, 18,17, 16, 15, and 14.Operating ModesTable 2 describes the operating and programming modes ofthe PLD C 20GI0. The majority of the programmingmodes function with a PROGRAM, PROGRAM INHIB­IT and PROGRAM VERIFY sequence. The exception isthe Security Program operation, which shows no programinhibit function. Two timing diagrams are provided forthese two different methodologies of programming in Figures14 & 15. Tables 3 through 6 are used as indicated toprovide the individual addresses of the various arrays andcells to be programmed. There are 5 operating modes inaddition to the programming modes for the PAL C 22VlO.These provide NORMAL operation, PHANTOM operation,TOP TEST, BOTTOM TEST and a register preloadfeature for testing.In the normal operating mode, all signals are TTL levelsand the device functions as it is internally programmed inthe NORMAL array. In the PHANTOM mode of operation,the device operates logically as a function of the contentsof the PHANTOM array. In this mode pins 2, lO &11 are non-inverting inputs and pin 7 is an inverting input.The programmable output cells function as they are programmedfor normal operation. If the programmable outputcells have not yet been programmed, they are in a registeredinverting configuration. The PHANTOM mode isinvoked by placing a supervoltage Vpp on pin 6. Careshould be exercised when entering and leaving this modethat the supervoltage is applied no sooner than 20 ms afterthe Vee is stable, and removed a minimum of 20 ms beforeVee is removed.TOP and BOTTOM TESTThe TOP TEST and BOTTOM TEST modes are enteredand exited in the same manner, with the same concern forpower sequencing, but the supervoltage is applied to pins 9& lO respectively. In these modes an extra product termcontrols an output pin. TOP TEST controls pin 23, andBOTTOM TEST controls pin 14. These product terms arecontrolled by the normal device inputs, and allow testing of •all input structures. ~PreloadFinally for testing of programmed functions, a preload featureallows any or all of the registers to be loaded with aninitial value for testing. This is accomplished by raising pin8 to a supervoltage Vpp, which puts the output drivers in ahigh impedance state. The data to be loaded is then placedon the I/O pins of the device and is loaded into the registerson the positive edge of the clock on pin 1. A "0" on theI/O pin preloads the register with a "0" and a "1" preloadsthe register with a "1". The actual signal on the output pinwill be the inversion of the input data. The data on the I/Opins is then removed, and pin 8 returned to a normal TTLvoltage. Again care should be exercised to power sequencethe device properly.4-33

~ PLDC20Gl0~~~UcrOR =====================================================================Operating ModesOperating Modes Pin Pin Pin Pin Pin Pin1 2 3 4 5 6Feature FunctionMainProgram VppArray Program Inhibit Vpp Table 3ProductProgram Verify[3] VppOutput Program VppEnableProductProgram Inhibit Vpp Table 3Terms Program Verify VppProgram VppTop Test,Bottom Test Program Inhibit Vpp Table 3NotesProgram Verify VppArchitectureBitsSecurityBitProgramProgram InhibitProgram VerifyProgramVerifyVpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp Vpp Data InVpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Table 5 Vpp VIHP HighZVpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp VILP Data OutVpp VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Vpp VILP VILP VILP VILPVILP VILP Data Vpp VILP VILPOutNormal CP/I I I I I IPAL Phantom CP/I I NA NA NA VppMode Top Test I I I I I IOperationBottom Test I I I I I IReg Preload Notes NA NA NA NA NATable 2Pin7VILP VILP VILP VILP VILP VILPIIIINAPin Pin Pin Pin Pin Pin Pin Pin8 9 10 11 13 14 17 20Pins15,16,18,19,21 & 22Phantom Program Vpp VILP VILP VILP VppVppData InArrayProductProgram Inhibit Vpp VILP VILP Table 6 VILP Vpp Table 4 VIHP HighZTerms Program Verify Vpp VILP VILP VILP VppVILPData OutPhantomOutputProgram Vpp VILP VILP VILP Vpp VIHP VIHP VIHP Vpp VppData InEnable Program Inhibit Vpp VILP VILP Table 6 VILP Vpp VIHP VIHP VIHP Vpp VIHPHighZProductTermsProgram Verify Vpp VILP VIL VILP Vpp VIHP VIHP VIHP Vpp VILPData OutNotes:1. DATA IN and DATA OUT for programming Synchronous Set,Asynchronous Reset, TOP TEST and BOTTOM TEST is programmedand verified on the following pins.2. The preload clock on pin 1 loads the Registers on a LOW goingHIGH transition.3. It is necessary to toggle OE (Pin 13) HIGH during all address transitionswhile in the program verify/blank check mode.Pin 14 BOTTOM TESTPin 17 = Synchronous SetPin 20 = Asynchronous ResetPin 23 = TOP TESTPin23VppData InTable 4 VIHP HighZVILPData OutVIHP VIHP VIHP Vpp VppData InVIHP VIHP VIHP Vpp VIHPHighZVIHP VIHP VIHP Vpp VILPData OutVIHP VIHP VIHP VIHP VppData Data DataDataVILPIn In In InVIHP VIHP VIHP VIHP VIHP HighZ HighZ HighZ HighZ HighZVIHP VIHP VIHP VIHP VILPData Data DataDataDrivenOut Out OutOutDriven OutputsI I I I I I/ONA NA I I NA OutputI Vpp I I I NAI I Vpp I I Out NAVpp NA NA NA VILP Data InVILPOut4-34

~ PLDC20GI0~~~NDU~ =====================================================================Input Term AddressesTable 3 is used during the programming and verification ofthe main array, output enable, asynchronous reset, synchronouspreset, TOP and BOTTOM TEST as shown inTable 2.Input Term AddressesInput Pin PinTerm 2 30 VILP VILP1 VIHP VILP2 VILP VIHP3 VIHP VIHP4 VILP VILP5 VIHP VILP6 VILP VIHP7 VIHP VIHP8 VILP VILP9 VIHP VILP10 VILP VIHP11 VIHP VIHP12 VILP VILP13 VIHP VILP14 VILP VIHP15 VIHP VIHP16 VILP VILP17 VIHP VILP18 VILP VIHP19 VIHP VIHP20 VILP VILP21 VIHP VILP22 VILP VIHP23 VIHP VIHP24 VILP VILP25 VIHP VILP26 VILP VIHP27 VIHP VIHP28 VILP VILP29 VIHP VILP30 VILP VIHP31 VIHP VIHP32 VILP VILP33 VIHP VILP34 VILP VIHP35 VIHP VIHP36 VILP VILP37 VIHP VILP38 VILP VIHP39 VIHP VIHP40 VILP VILP41 VIHP VILP42 VILP VIHP43 VIHP VIHPTable 3It provides the addressing for the 44 normal input termcolumns which are connected with an EPROM transistorto the product terms.Pin Pin Pin Pin4 5 6 7VILP VILP VILP VILPVILP VILP VILP VILPVILP VILP VILP VILPVILP VILP VILP VILPVIHP VILP VILP VILPVIHP VILP VILP VILPVIHP VILP VILP VILPVIHP VILP VILP VILPVILP VIHP VILP VILPVILP VIHP VILP VILPVILP VIHP VILP VILPVILP VIHP VILP VILPVIHP VIHP VILP VILPVIHP VIHP VILP VILPVIHP VIHP VILP VILPVIHP VIHP VILP VILPVILP VILP VIHP VILPVILP VILP VIHP VILPVILP VILP VIHP VILPVILP VILP VIHP VILPVIHP VILP VIHP VILPVIHP VILP VIHP VILPVIHP VILP VIHP VILPVIHP VILP VIHP VILPVILP VIHP VIHP VILPVILP VIHP VIHP VILPVILP VIHP VIHP VILPVILP VIHP VIHP VILPVIHP VIHP VIHP VILPVIHP VIHP VIHP VILPVIHP VIHP VIHP VILPVIHP VIHP VIHP VILPVILP VILP VILP VIHPVILP VILP VILP VIHPVILP VILP VILP VIHPVILP VILP VILP VIHPVIHP VILP VILP VIHPVIHP VILP VILP VIHPVIHP VILP VILP VIHPVIHP VILP VILP VIHPVILP VIHP VILP VIHPVILP VIHP VILP VIHPVILP VIHP VILP VIHPVILP VIHP VILP VIHPII4-35

~ PLDC20GIO~~~NDUcroR =====================================================================Product Term AddressesTable 4 is used for the programming of the "PHANTOM"and normal array. It provides the addressing for the 8product terms associated with each input.Product Term AddressesTable 4Product Pin PinTerm 8 90 VILP VILP1 VIHP VILP2 VILP VIHP3 VIHP VIHP4 VILP VILP5 VIHP VILP6 VILP VIHP7 VIHP VIHPArchitecture Bit AddressingPin Pin10 11VILPVILPVILPVILPVIHPVIHPVIHPVIHPVILPVILPVILPVILPVILPVILPVILPVILPTable 5 provides the addressing for the architecture bitsused to control the configuration of the individual ProgrammableOutput Cells. In the unprogrammed state, theProgrammable Output Cells are in a registered, active lowor inverting configuration with output enable controlledfrom the product term. They are programmed with a "1"on the pin associated with the Programmable Output Cellsand the appropriate address as shown in Table 5. Eacharchitecture bit that is not to be programmed, requires a"0" on the I/O pin associated with the Programmable OutputCells.Architecture Bit AddressingTable 5ArchitecturePinBit 9OutputPolarityCORegister/CombinatorialOutput ClProduct Term/Pin 13Output EnableC2VILPVIHPVILPPhantom Input Term AddressingPin10VILPVILPVIHPPhantom input terms are addressed as columns PO thru P3and represent inputs from pins 2,7, 10 and 11 respectively.Pin 7 is inverted, and the remaining 3 are normal non-inverting.This PHANTOM array allows the output structuresto be tested. They are only present in PHANTOMmodes of operation.Phantom Input Term AddressesTable 6PhantomInputTermPOPIP2P3Pin4VILPVIHPVILPVIHPProgramming Flow ChartPin5VILPVILPVIHPVIHPThe programming flow chart describes the sequence of operationsfor programming the NORMAL and PHANTOMarrays, the NORMAL and PHANTOM output enableproduct terms, the set and preset product terms, the TopTest product term, the Bottom Test product term, and thearchitecture bits. The exact sequencing and timing of thesignals is shown in the "Array Programming Timing Diagram".The logical sequence to program the device is described indetail in the flow chart below, and should be followed exactlyfor optimum intelligent programming that both minimizesprogramming time and realizes reliable programming.Particular attention should be paid to the applicationof Vee prior to Vpp, and removal ofVpp prior to Vee. SeeFigure 14 and Table 8 for specific timing and AC requirements.Notice that all programming is accomplished withoutswitching Vpp on pin 1 and that after programmingand verifying all locations individually, the programmedlocations should be verified one final time.The normal word programming cycle, programs and verifiesa word at a time as shown in the programming flowchart,Figure 13 and timing diagram Figure 14. After alllocations are programmed, the flowchart requires a verifyof all words. There is no independent timing diagram forthis operation, rather Figure 14 also provides the correcttiming information for this operation. When performingthis verify only operation, eliminate the program portion ofthe cycle but maintain the setup and hold timing relative tothe verify pulse. Under no circumstances should the verifysignal be held low and the addresses toggled.Note that the overprogram pulse in step 10 of the programmingflowchart is a variable, "4" times the initial valuewhen programming the NORMAL, PHANTOM, TOPTEST, BOTTOM TEST and OUTPUT ENABLE productterms and "8" times the initial value when programmingthe ARCHITECTURE BITS.4-36

Programming FlowchartSTARTVee = 5.0VVpp = 13.5VADDRESS FIRST LOCATION,PLACE DATA TO BE PROGRAMMEDON THE I/O PINSx=ONote:1. This value is "4" for programmingthe NORMAL array,PHANTOM array TOP TEST,BOTTOM TEST and OUTPUTENABLE PRODUCT TERMS.The value is "8" when programmingARCHITECTURE BITS.PROGRAM ONE PULSEOF 0.2mSx = x + 1x = 10?NOIIVERIFY ONE WORDPASSPROGRAM ONE PULSE OF«NOTE 1) • 0.2 • X) mSX = 10NO~--------~----L---~'-------.,;.~YESVERIFY ALL WORDS ATVeep = 5.0 VOLTSDEVICE FAILPASSGOOD DEVICEVpp = O.OVVee = O.OVSTOPFigure 130053-284-37

Timing DiagramsProgramming timing diagrams are provided for two cases,programming of all cells except the SECURITY BIT andprogramming the SECURITY BIT.ArrayProgramming the NORMAL and PHANTOM arrays andoutput enables, reset, preset, architecture bits and the top/bottom test features uses the timing diagram in Figure 14.ADDRESS refers to all applicable information in Tables 2through 6 that is not specifically referenced in the timingdiagram. DATA IN is provided on the I/O pins andProgramming WaveformsDATA OUT is verified on the same pins. A "1" (V IHP) onan I/O pin causes the addressed location to be programmed.A "0" on the I/O pin leaves the addressed locationto be unprogrammed. All setup hold and delay timesmust be met, and in particular the sequence of operationsshould be strictly followed. During verify only operation itis not acceptable to hold PGM/VFY low and sequenceaddresses, as it violates address setup and hold times. Propersequencing of all power and supervoltages is essential, toreliable programming of the device as improper sequencingcould result in device damage.VeepVee PIN 24 -NOTE 1 V SS-Vpp_Vpp PIN 1Vss~--------------TDP-----------~ADDRESSNOTE 2V 1HPDATAV 1HPPG ... /wyPIN 13V1HP-V1LP-V1LP-V1LP----------..;i(Notes:1. Power, Vpp & Vee should not be cycled for each program/verifycycle, but may remain static during programming.Figure 142. For programming OE Product Terms & Architecture bits, Pin 11(A9) must go to Vpp and satisfy TAS and TAN.0053-294-38

~ PLDC20GIO~~~~UcrOR==================================================================~Security CellThe security cell is programmed independently per the timingdiagram in Figure 15, and the information in Table 2.Note again that proper sequencing of power and programmingsignals is required. Data in is represented as a supervoltageon pin 3 and verified as a TTL signal output on theProgramming Waveforms Security CellVee PIN 24 VeeP - -JVSS-vpp_TpV1LPsamepin. A "0" on pin 3 indicates that the security bit hasbeen programmed, and a "I" indicates that security bit hasnot been programmed. Security is programmed with a single50 ms pulse on pin 13. A supervoltage on pin 4 is usedto verify security after Vpp has been removed from pin 1.~!. _____________ TP _____________ '~~Vpp PIN 1Vss-TopVpp_PGMPIN 13Vpp_V 1LP_IISECURITYVFYPIN4Vpp_DATA PIN3 V 1HP-V1LP-I+------T ovFigure 150053-304-39

~ PLDC20GIO~~~NDU~ ~~~~~==========================================~========~==~DC Programming Parameters TA = 25°CTable 7Parameter Description Min. Max. UnitsVpp Programming Voltage 13.0 14.0 VoltsVeepVIHPVILPSupply VoltageDuring ProgrammingInput HIGH VoltageDuring ProgrammingInput LOW VoltageDuring Programming4.75 5.25 Volts3.0 Veep Volts-3.0 0.4 VoltsVOH Output HIGH Voltage 2.4 VoltsVOL Output LOW Voltage 0.4 VoltsIppAC Programming ParametersProgrammingSupply CurrentTable 840 mAParameter Description Min. Max. UnitsTpDelay to ProgrammingVoltage20 msTOp Delay to Program 1 ILsTHPHold from Programor Verify1 ILsTR,F Vpp Rise & Fall Time 50 nsTAS Address Setup Time 1 ILsTAH Address Hold Time 1 ILsToS Data Setup Time 1 ILsTOH Data Hold Time 1 ILsTpp Programming Pulsewidth 0.2 10 msTsppTovProgramming Pulsewidthfor SecurityDelay from Programto Verify50 ms2 ILsTvo Delay to Data Out 1 ILsTvp Verify Pulse Width 2 ILsToZ Verify to High Z 1 ILs4-40

~CfPRfSSPLDC20GIO~~~UcroR ~~~~~~~~~~~~~~~~~~~~~~~~~==~==~========~Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.4 "'---"'--"'T"---r--"711NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.2NORMALIZED PROPAGATIONDELAYvs. SUPPLY VOLTAGE11~::;C~a:0z1.21.00.'4.5TA • 25'C,oMAX.5.0 5.5 1.00·~~----~251:----~125~::; 1.0C"-~a:~1.1~0.90.'4.0"-4.5 5.0 5.5I'-..........6.0SUPPL V VOLTAGE (VIAMBIENT TEMI'ERATURE C'CISUPPLY VOLTAGE (VINORMALIZED PROPAGATION DELAYvs. TEMPERATURE1.3..-----..------........,DELTA PROPAGATION TIMEvs. OUTPUT LOADING20.0NORMALIZED SETUP TIMEvs. SUPPLY VOLTAGE1.2AMBIENT TEMI'ERATURE ('CINORMALIZED SETUP TIMEvs. TEMPERATURE1.3..----__,..--------,!jC~Q15.010.05.0.JII'V ~./~VV200 400 &00 100 1000CAI'ACITANCE CpFINORMALIZED CLOCK TO OUTPUTTIME vs. SUPPLY VOLTAGE1.1..---.,.--"'T"---r---,i ,.1.'~"- "-~0.' ......O.• 4.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (VINORMALIZED CLOCKTO OUTPUTTIME vs. TEMPERATUREo~~::;cI ozAMBIENT TEMI'ERATURE ('CI0·~':'.0--4:":.5:----:'5.':"0 -~5~.5-~I.OSUPPLY VOLTAGE (VIAMBIENT TEMPERATURE ('CIc:j~Q20.015.010.05.0DELTA CLOCK TO OUTPUT TIMEvs. OUTPUT LOADINGV//V~0.00 200 400 100 100 1000"1~a:a::I~~Ziii~0120OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE105 ~1075804530L15I1/o0.0j/lLV~~c==J;~V -I1.0 2.0 3.0 4.0C!I-~cz:cz::I~...~cz::Iiiil-i I-;,07080so40302010OUTPUT SOURCE CURRENTvs. VOLTAGEI\..~~" '"....... ~........1.0 2.0 3.0 4.0CAI'ACITANCE CpFlOUTPUT VOLT AGE (VIOUTPUT VOLT AGE (VI0053-314-41

~ PLDC20GIO~~~~U~R==================================================================Ordering InformationtpD ts teo Icc OperatingOrdering Code Package(os) (ns) (ns) (rnA) Range15 12 10 70 PLD C 20010-15PC P13 CommercialPLD C 20010-15WCPLD C 2001O-15JCW1420 17 15 100 PLD C 2001O-20DMB D14 MilitaryPLD C 20010-20WMBPLD C 2001O-20LMBJ64W1425 15 15 55 PLD C 2001O-25PC P13 CommercialPLD C 2001O-25WCPLD C 2001O-25JCL64W1430 20 20 80 PLD C 2001O-30DMB D14 MilitaryPLD C 20010-30WMBPLD C 20010-30LMBJ64W1435 30 25 55 PLD C 2001O-35PC P13 CommercialPLD C 2001O-35WCPLD C 2001O-35JCL64W1440 35 25 80 PLD C 2001O-40DMB D14 MilitaryPLD C 20010-40WMBPLD C 2001 0-40LMBJ64W14L644-42

~ PLDC20GI0~~~~~==================================================~~~~~==MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Vpp 1,2,3Icc 1,2,3Ioz 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstPD 7,8,9,10,11tpzx 7,8,9,10,11teo 7,8,9,10,11ts 7,8,9,10,11tH 7,8,9,10,11Document #: 38-00019-C4-43

CYPRESSSEMICONDUCTORPRELIMINAR YPLDC20RAIOReprogrammableAsynchronous CMOSProgrammable Logic DeviceFeatures• Advanced user programmablemacro cell• CMOS EPROM technology forreprogrammability• Up to 20 input terms• 10 programmable I/O macrocells• Output macro cell programmableas combinatorial orasynchronous D-type registeredoutput• Product term control of registerclock, reset and set and outputenable• Register preload and power upreset• Four uncommitted product termsper output macro cellBlock Diagram and DIP Pinout• Fast- CommercialtpD = 20 nsteo = 20 nstsu = 10 ns- MilitarytpD = 25 nsteo = 25 nstsu = 15 ns• Low power- ICC max = 80 mACommercial- ICC max = 100 mAMilitary• High reliability- Proven EPROM technology- > 2001 V input protection- 100% programming andfunctional testing• Windowed DIP, windowed LCC,DIP, LCC, PLCC availableFunctional DescriptionThe Cypress PLD C 20RAlO is a highperformance, second generation programmablelogic device employing aflexible macro cell structure which allowsany individual output to be configuredindependently as a combinatorialoutput or as a fully asynchronousD-type registered output.The Cypress PLD C 20RA 10 provideslower power operation with superiorspeed performance than functionallyequivalent bipolar devices through theuse of high performance 0.8 micronCMOS manufacturing technology.The PLD C 20RA lO is packaged in a24 pin 300 mil molded DIP, a 300 milwindowed cerdip, and a 28 lead squareleadless chip carrier and provides up to20 inputs and 10 outputs. When thewindowed cerdip is exposed UV light,the 20RA lOis erased and then can bereprogrammed.Vss 19 IB 17EI16 15 141312 10PROGRA ...... ABLEAND ARRAY(BOX 40)BVee0118-14-44

~ PRELIMINARY PLD C 20RAIO~~~NDUcrOR=====================================================================Macro Cell ArchitectureFigure 1 illustrates the architecture of the 20RAI0 macrocell. The cell dedicates three product terms for fully asynchronouscontrol of the register set, reset and clock functions,as well as, one term for control of the output enablefunction.The output enable product term output is "and'ed" withthe input from pin 13 to allow either product term or hardwired external control of the output or a combination ofcontrol from both sources. If product term only control isselected, it is automatically chosen for all outputs since, forthis case, the external output enable pin must be tied low.The active polarity of each output may be programmedindependently for each output cell and is subsequentlyfixed. Figure 2 illustrates the output enable options available.When an I/O cell is configured as an output, combinatorialonly capability may be selected by forcing the set and resetproduct term outputs to be high under all input conditions.This is achieved by programming all input term programmingcells for these two product terms. Note that the outputcell may be changed "on the fly" from a combinatorialto a D type registered output, or the reverse, under thecontrol of the set and reset product terms. Figure 3 illustratesthe available output configuration options.An additional four uncommitted product terms are providedin each output macro cell as resources for creation ofuser defined logic functions.Programmable I/OBecause any of the 10 I/O pins may be selected as a input,the device input configuration programmed by the usermay vary from a total of nine programmable plus ten dedicatedinputs (a total of nineteen inputs) and one outputdown to a ten input, ten output configuration with all tenprogrammable I/O cells configured as outputs. Each inputpin available in a given configuration is available as aninput to the four control product terms and four uncommittedproduct terms of each programmable I/O macrocell that has been configured as an output.An I/O cell is programmed as an input by tying the outputenable pin, pin 13, low and by programming the outputenable product to provide a high output, thereby "threestate"the output, for all possible input combinations. Thisis achieved by programming all input term programmablecells for this output enable product term.When utilizing the I/O macro cell as an output, the inputpath functions as a feedback path allowing the output signalto be fed back as an input to the product term inputarray. When the output cell is configured as a registeredoutput, this feed back path may be used to feed back thecurrent output state to the device inputs to provide currentstate control of the next output state as required for statemachine implementation.Preload and Power-up ResetFunctional testability of programmed devices is enhancedby inclusion of register preload capability which allows thestate of each register to be set by loading each register froman external source prior to exercising the device. Testing ofcomplex state machine designs is simplified by the ability 4to load an arbitrary state without cycling through long testvector sequences to reach the desired state. Recovery fromillegal states can be verified by loading illegal states andobserving recovery. Preload of a particular register is accomplishedby impressing the desired state on the registeroutput pin and lowering the signal level on the preloadcontrol pin (pin 1) to a logic low level. If the specifiedpreload set up, hold and pulse width minimums have beenobserved, the desired state is loaded into the register. Toinsure predictable system initialization, all registers arepreset to a logic low state upon power up, thereby settingthe active low outputs to a logic high.DPLSQPRPLFigure 1. PLD C 20RA10 Macro CellOE0118-44-45

~ PRELIMINARY PLDC20RAIO~~~UaoR==~~~~~~~~~~~~~~~~==~~~~~~~~~~~~====Output Always EnabledProgrammable0118-130118-14Hard-WiredCombination ofProgrammable and Hard-Wired0118-150118-16Figure 2. Four Possible Output Enable Alternatives for the PLD C 20RAIORegistered/Active LowCombinatorial/ Active Low0118-180118-17Registered/Active HighCombinatorial/Active High0118-200118-19Figure 3. Four Possible Macro Cell Configurations for the PLD C 20RAIO4-46

~ PRELIMINARY PLD C 20RAIO~~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~========~=Selection GuideGeneric tpDns tsuns teons IeemAPart NumberCom Mil Com Mil Com Mil Com Mil20RA10-20 20 - lO - 20 - 80 -20RA10-25 - 25 - 15 - 25 - 10020RAlO-30 30 - 15 - 30 - SO -20RAlO-35 - 35 - 20 - 35 - 100Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -O.SV to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -O.SV to + 7.0VStatic Discharge Voltage ..................... >2OO1V(per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 mAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°C to +70°C 5V ± lO%Output Current into Outputs (Low) ............. 16 mA Military [5] - 55°C to + 125°C 5V ± lO%Electrical Characteristics Over Operating Rangd6]Parameters Description Test Conditions Min. Max. UnitsVOH Output HIGH Voltage Vee = Min., IOH = -3.2mA COM'LVIN = VIH or VIL IOH = -2mA MILVee2.4 VVOL Output LOW Voltage Vee = Min., IOL = SmA 0.5 VVIN = VIH or VILVIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[ll 2.0 VVIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[1] O.S VIIX Input Leakage Current Vss ::;: VIN ::;: Vee, Vee = Max. -lO 10 JJ-AIoz Output Leakage Current Vee = Max., Vss::;: VOUT::;: Vee -40 40 JJ-AIse Output Short Circuit Current Vee = Max., VOUT = 0.5V[2] -30 -90 rnAIce Power Supply Current Vee = Max., VIN = GND Outputs OpenCapacitance [3]COM'L SO rnAMIL 100 rnAParameters Description Test Conditions Min. Max. UnitsCIN Input Capacitance VIN = 2.0V @ f = 1 MHz 5COUT Output Capacitance VOUT = 2.0V@f= 1 MHz SNotes:1. These are absolute values with respect to device ground and all overshootsdue to system or tester noise are included.2. Not more than one output should be tested at a time. Duration of theshort circuit should not be more than one second. V OUT = O.5V hasbeen chosen to avoid test problems caused by tester ground degradation.3. Te~ted initially and after any design or process changes that mayaffect these parameters.4. Figure latest load used for all parameters except tEA, tER. tpzx andtpxz. Figure 1 b test load used for tEA. tER. tpzx and tpxz.5. TA is the "instant on" case temperature.6. See the last page of this specification for Group A subgroup testinginformation.pF4-47

~ PRELIMINARY PLDC20RAIO~~~NDucrOR ================================================~~======~======~Switching Characteristics PLD C 20RAIO Over Operating Range[4, 6]Parameters Description -20tpDInput or Feedback toNon-Registered OutputCommercialMin. Max. Min.tEA Input to Output Enable 25tER Input to Output Disable 25tpzx Pin 13 to Output Enable 15tpxz Pin 13 to Output Disable 15tco Clock to Output 20tsu Input or Feedback Setup Time 10 15tH Hold Time 0 5tp Clock Period 30 45tw Clock Width 15 20fMAX Maximum Frequency 33.3 22.2ts Input to Asynchronous Set 20tR Input to Asynchronous Reset 25twp Preload Pulse Width 30 35tsup Preload Setup Time 20 25tHP Preload Hold Time 20 25AC Test Loads and Waveforms (Commercial)Equivalent to:Rl,457.o.(470.0. mil)5V o---~Iv-...,OUTPUT 0---+--"'"Including Jig Iand Scope _50pF20Rl,457.o.OUTP::=n(470.o. mil)R2R2270.0. 15 pF 270.0.(319.0. mil) (319.0. mil)~ -=--=-Figure 1aFigure 1bTHEVENIN EQUIVALENT (Commercial)-30Max.3030302020303540Equivalent to:0118-6Military-25 -35 UnitsMin. Max. Min. Max.25 35 ns30 35 ns30 35 ns20 25 ns20 25 ns25 35 ns15 20 ns0 5 ns40 55 ns20 25 ns25.0 18.1 MHz25 40 ns30 45 ns35 40 ns25 30 ns25 30 ns,.v=;tt-INPUT PULSES~GND 10% 10%f..--s:.5nsFigure 2THEVENIN EQUIVALENT (Military)S5ns0118-7170.nOUTPUT~1.86V0118-8190.nOUTPUT~2.02V0118-94-48

~ PRELIMINARY PLD C 20RAIO~~~~u~ ================================================================LCC and PLCC Pinoutso -~ ~.s> I~ ~ ~ ~4 3 2 :1:282726•••• 25 1/0212 13 14 15 16 17 181/031/041/051/061/07NCo -_N ~ .s> I~ ~ ~ ~12 13 14 15 16 17 181/021/031/041/051/061/07NCSwitching Waveforms0118-210118-22INPUTS. REGISTEREDFEEDBACK _--'j~'-__'I"~~~I'\'-_________..I'I~~.....I'I'-___CP----"1IIASYNCHRONOUSSET ____ -+ _____ -+-""'1ASYNCHRONOUSRESET ____ -+ _____ -+-----1-______ 1REGISTERED ----~~~------~~r----~-~-~~OUTPUTSI~""' __COMBINATORIAL OUTPUTS __________ ~~ ~ _______....,PIN 13 OUTPUT ~ qENABLE(6E)REGISTERED AND -----------------~;"")t -(""«'I""ICr-:....-----COMBINATORIAL OUTPUTS _________________"""_~__• •__ _0118-10Preload Switching Waveforms~~~:~ _____ X_X_f ___ ts_U_pttHP~: _------------PRELOAD CLOCK (Pi:) _ _twp0118-124·49

~CfPFFSS PRELIMINARY PLDC20RAIOWnEMICONDucroR =======;;;;;:;;;;;;;;;:;;;;;;;;;:==============Functional Logic Diagram PLD C 20RAIO....v1107~~ i [tPL3 ..... ..... L-8:J.< -15R P~cnrt [tPLR P3 .... ..... L-[tPL16......23~23~22~rt~4 .... ..... L-24......31~~~[) ~PLR P[J5 .....L..-32 h39R P~1~6 ..... ..... L-7 "401..j~t [t47PLR P.A L-R48 ~-:J.

~ PRELIMINARY PLD C 20RA10~~~aIDUCKR ============================================================~Ordering InformationICC tpD tsu teo Ordering Code Package Operating Range(mA) (ns) (ns) (ns)80 20 10 20 PLO C 20RAlO-20PC P13 CommercialPLO C 20RAlO-20WCPLO C 20RAlO-20JC100 25 15 25 PLO C 20RAlO-250MB 014 MilitaryPLO C 20RA10-25WMBPLO C 20RAlO-25LMBPLO C 20RAlO-25QMB80 30 15 30 PLO C 20RAlO-30PC P13 CommercialPLO C 20RA10-30WCPLO C 20RA10-30JC100 35 20 35 PLO C 20RAlO-350MB 014 MilitaryPLO C 20RAlO-35WMBPLO C 20RAlO-35LMBPLO C 20RAlO-35QMBW14J64W14L64Q64W14J64W14L64Q64II4-51

~ PRELIMINARY PLDC20RAIO~jr;~~UcrOR~========================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3SubgroupsVIL 1,2,3hx 1,2,3Ioz 1,2,3Icc 1,2,3Switching CharacteristicsParameters SubgroupstpD 9,10,11tpzx 9,10,11teo 9,10,11tsu 9,10,11tH 9,10,11Document #: 38-000734-52

CYPRESSSEMICONDUCTORPAL C 22VIOReprogrammable CMOSPAL® DeviceFeatures• Advanced second generationPAL architecture• Low power- 55 rnA max "L"- 90 rnA max standard- 120 rnA max military• CMOS EPROM technology forreprogrammability• Variable product terms- 2 X (8 thru 16) productterms• User programmable macro cell- Output polarity control- Individually selectable forregistered or combinatorialoperation- "IS" commercial10 ns teo12 ns ts15 ns tpD45 MHzLogic Symbol and PinoutVss- "20" military15 ns teo17 ns ts20 ns tpD31 MHz• Up to 22 input terms and 10outputs• Enhanced test features- Phantom array- Top Test- Bottom Test- Preload• High reliability- Proven EPROM technology- > 2000V input protection- 100% programming andfunctional testing• Windowed DIP, windowed LCC,DIP, LCC, PLCC availablePAL@ is a registered trademark of Monolithic Memories Inc.Functional DescriptionThe Cypress PAL C 22VlO is a CMOSsecond generation Programmable LogicArray device. It is implemented withthe familiar sum-of-products (AND­OR) logic structure and a new concept,the "Programmable Macro Cell".The PAL C 22VIO is executed in a 24pin 300 mil molded DIP, a 300 milwindowed Cerdip, a 28 lead squareleadless chip carrier, a 28 lead squareplastic leadless chip carrier and providesup to 22 inputs and 10 outputs.When the windowed CERDIP is exposedto UV light, the 22VlO is erasedand then can be reprogrammed. TheProgrammable Macro Cell providesthe capability of defining the architectureof each output individually. Eachof the 10 potential outputs may bespecified to be "REGISTERED" or"COMBINATORIAL". Polarity ofIILCC and PLCC Pinout4 3I 5 I/oI/oI/oHC 8 HCI 9 I/OI 10 I/OI 11 19 I/O121314151617180023-10023-104-53

~ PAL C 22VIO~~~U~==================================================================Functional Description (Continued)each output may also be individually selected allowingcomplete flexibility of output configuration. Further configurabilityis provided through "ARRAY" configurable"OUTPUT ENABLE" for each potential output. This featureallows the 10 outputs to be reconfigured as inputs onan individual basis or alternately used as a combinationI/O controlled by the programmable array.The PAL C 22V1O features a "VARIABLE PRODUCTTERM" architecture. There are 5 pairs of product termsbeginning at 8 product terms per output and incrementingby 2 to 16 product terms per output. By providing thisvariable structure the PAL C 22V1O is optimized to theconfigurations found in a majority of applications withoutcreating devices that burden the product term structureswith unuseable product terms and lower performance.Additional features of the Cypress PAL C 22V1O include asynchronous PRESET and an asynchronous RESET productterm. These product terms are common to all MACROCELLS eliminating the need to dedicate standard productterms for initialization functions. The device automaticallyresets on power-up.The PAL C 22VI0 featuring programmable macro cellsand variable product terms provides a device with the flexibilityto implement logic functions in the 500 to 800 gatearray complexity. Since each of the 10 output pins may beindividually configured as inputs on a temporary or permanentbasis, functions requiring up to 21 inputs and only asingle output down to 12 inputs and 10 outputs are possible.The 10 potential outputs are enabled through the useof product terms. Any output pin may be permanently selectedas an output or arbitrarily enabled as an output andan input through the selective use of individual productterms associated with each output. Each of these outputs isachieved through an individual programmable macro cell.These macro cells are programmable to provide a combinatorialor registered inverting or non-inverting output. In aMacrocellregistered mode of operation, the output of the register isfed back into the array providing current status informationto the array. This information is available for establishingthe next result in applications such as control-statemachines.In a combinatorial configuration, the combinatorialoutput or, ifthe output is disabled, the signal presenton the I/O pin is made available to the array. The flexibilityprovided by both programmable macro cell productterm control of the outputs and variable product termsallows a significant gain in functional density through theuse of programmable logic.Along with this increase in functional density, the CypressPAL C 22VI0 provides lower power operation thru the useof CMOS technology, increased testability with a registerpreload feature and guaranteed AC performance throughthe use of a phantom array. This phantom array (Po-P3)and the "TOP TEST" and "BOTTOM TEST" features allowthe 22VIO to be programmed with a test pattern andtested prior to shipment for full AC specifications withoutusing any of the functionality of the device specified for theproduct application. In addition, this same phantom arraymay be used to test the PAL C 22V1O at incoming inspectionbefore committing the device to a specific functionthrough programming. PRELOAD facilitates testing programmeddevices by loading initial values into the registers.Configuration Table 1Registered/CombinatorialCl Co Configurationr---------------------,>+------------.-~DAR0 0 Registered/ Active Low0 1 Registered/Active HighQ ...... ----I1 0 Combinatorial/Active Low1 1 Combinatorial! Active HighOUTPUTSELECTMUXIIICPSPINPUT/FEEDBACKMUXC1------~----~------------------------~Co-------+----------------------------------~L ____________________ ~MACROCELL0023-24-54

~ PALC22VIO~~~NDUcroR =====================================================================Selection GuideGeneric ICC rnA tpDns ts ns teonsPart Number"L" Com Mil Com Mil Com Mil Com Mil22VlO-15 [S) 90 - 15 - 12 - 10 -22VlO-20[S) 90 120 20 20 12 17 15 1522VlO-25 55 90 100 25 25 15 20 15 2022VIO-30 - 100 - 30 - 25 - 2022V10-35 55 90 - 35 - 30 - 25 -22VlO-40 - 100 - 40 - 35 - 25Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CDC Programming Voltage ...................... I4.0VAmbient Temperature withStatic Discharge Voltage ..................... > 2001 VPower Applied .................... - 55°C to + 125°C (per MIL-STD-883 Method 3015)Supply Voltage to Ground PotentialLatchup Current .......................... > 200 rnA(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to OutputsOperating Rangein High Z State ...................... -0.5V to + 7.0VAmbientRangeVeeDC Input Voltage ................... - 3.0V to + 7.0VTemperatureOutput Current into Outputs (Low) ............. 16 rnA Commercial O°C to + 70°C 5V ± 10%UV Exposure ........................ 7258 Wsec/cm2 Military [7) - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over Operating Range[6]Parameters Description Test Conditions Min. Max. UnitsVOH Output HIGH Voltage Vee = Min., IOH = -3.2mA COM'LVIN = VIH or VIL IOH = -2mA MILVOL Output LOW Voltage Vee = Min., IOL=16mA COM'LVIN = VIH or VIL IOL = 12mA MIL2.4 V0.5 VVIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[t) 2.0 VVIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs(1) 0.8 VIIX Input Leakage Current Vss ::;: VIN ::;: Vee, Vee = Max. -10 10 ,...,AIoz Output Leakage Current Vee = Max., Vss ::;: VOUT ::;: Vee -40 40 ,...,AIse Output Short Circuit Current Vee = Max., VOUT = 0.5V[2) -30 -90 mAIcc Power Supply Current Vee = Max., VIN = GND Outputs OpenCapacitance [3]"L" 55 mACOM'L 90 mAMIL 100 mAMIL-20[S) 120 mAParameters Description Test Conditions Min. Max. UnitsCIN Input Capacitance VIN = 2.0V @ f = 1 MHz 5COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 8pFNotes:1. These are absolute values with respect to device ground and all overshootsdue to system or tester noise are included.4. Figure latest load used for all parameters except tEA, tER, tpzx andtpxz. Figure 1 b test load used for tEA, tER, tpzx and tpxz·2. Not more than one output should be tested at a time. Duration of the S. Preliminary specifications.short circuit should not be more than one second. VOUT = O.SV has 6. See the last page of this specification for Group A subgroup testingbeen chosen to avoid test problems caused by tester ground degradation.information.7. TA is the "instant on" case temperature.3. Tested initially and after any design or process changes that mayaffect these parameters.4-55

~ PAL C 22VIO~~~U~ =====================================================================Switching Characteristics PAL C 22VIO[4, 6]CommercialMilitaryParameters Description .15[5] .20[5] ·25 ·35 .20[5] ·25 ·30 ·40tpDInput or Feedback toNon·Registered OutputMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.15 20tEA Input to Output Enable 15 20tER Input to Output Disable 15 20teo Clock to Output 10 15tsInput or FeedbackSetup Time12 12 15tH Hold Time 0 0 0tp Clock Period (ts + t co ) 22 27 30tw Clock Width 11 13 15fMAX Maximum Frequency 45.4 37.0 33.3tAWtARtAPAsynchronous ResetWidthAsynchronous ResetRecovery TimeAsynchronous Reset toRegistered Output Reset15 20 2515 20 2520 25252525152535 20 25 30 4035 20 25 25 4035 20 25 25 4025 15 20 20 2530 17 20 25 350 0 0 0 055 32 40 45 6025 16 15 20 3018.1 31.2 25.0 22.2 16.635 20 25 30 4035 20 25 30 4035 25 25 30 40UnitsnsnsnsnsnsnsnsnsMHznsnsnsAC TestnLoads and Waveformsn(Commercial)Rl 238.0. Rl 238.0.(319.0. ~IL) (319.0. ~IL)OUTP~~ OUTP~~R2R250 pF 170.0. 5 pF 170.0.I(236.0. ~IL) I (236.0. ~IL)INCLUDINGJIG AND ':' ':' ':' ':'SCOPEFigure laFigure lbEquivalent to: THEVENIN EQUIVALENT (Commercial)0023-11INPUT PULSES3.0 v----~~ ___ --.....,._GNO ---iii],,; 5 osFigure 2Equivalent to: THEVENIN EQUIVALENT (Military)0023-1299.0.OUTPUT~2.08VSwitching WaveformsINPUTS I/O.0023-13136.0.OUTPUT~2.13VREGISTERED ---"',lr-~~~M\IIr"-----------""\.L""-W'-----SYN~~g~~~~----~~---~~~~-----------------~~--~----------PRESETCP0023-14ASYNCHRONOUSRESET _______ ...... ________ + __ '"_______ ~~,,_--~--~~~,,--__ --------__ -.~tE~RI~·,tJ~~~-------REGISTEREDOUTPUTS: ______ ~~'I'-_~ __ ~~I~ _______ ~~CO~BINATORIAL --------------------OUTPUTS: ___________________ _· tER I·. t~ 1+----------~)~)>> (~((~---0023-34·56

~~==========================================~P~A~L~C~2~2V~10Functional Logic Diagram PAL C 22VIO1-{> '1 Ps~..~'0 '2 . . . 12-All0~2~6..2. 2' 2' 52 3. ..,.."lEt>-~~7 1:8" ""coo-.. ~=0~==~:6b~.A,. ....~CElL~">-- ~6bMACIIO-" ;">--CElL3~ 1# >0A~CElL.,....OE;>-- ~14* ""CRO-~..~-;: ;~b= p- ""ClIO-0; ;::==5* F n~'*..789,~13#0;" ;":..02322>CELL 1>--~th""COOf>CELL1F n')....- ~th""CRO-~_'t::::== ~ ~6b~== == ==~. .A~10 ~7......)-- ""ClIO-~CELL 1~.... 11~"'T-T-2120I>CELL 1">-- ~~MACRO-"'T-T-">--;1, 4~SP~11 13.Ao........r987650023-44-57

~ PAL C 22VIO~~~~UcrOR==================================================================Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.4 r---r---r--.....,--,.NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.8 r-----..,-----....,1.2NORMALIZED PROPAGATIOl"DELAYvs. SUPPLY VOLTAGEIIeN~«::Ea:0z1.21---+--+----,lL-.-......j1.00.84.5 5.0 6.0SUPPLY VOLTAGE (VIII 1.21-----"~-+_------I~::;~ 1.01-------''''k-------Ia:oz0.8t-----+---.-.:~1;;:::""-I0·~55~----:.I:25~---~125AMBIENT TEMPERATURE ('CIE51N::;«~a:0Z1.11.00.9"'" ~ ~......'"0.84.0 4.5 6.0 5.5 6.0SUPPLY VOLTAGE (VINORMALIZED PROPAGATION DELAYn. TEMPERATURE1.3r----....,.------,DELTA PROPAGATION TIMEvs. OUTPUT LOADING20.01.2NORMALIZED SETUP TIMEvs. SUPPLY VOLTAGE~ 1.2eN~ 1.11-----+--_L-.--I«:IEa:~125!E«8c15.010.05.0/1.V~:/ ~/'200 400 800 800 1000Q~51N::;«~a:cZ1.11.00.9"'" , '"~ ......0.84.0 4.5 5.0 5.5 6.0AMBIENT TEMPERATURE ('CINORMALIZED SETUP TIMEvs. TEMPERATURE1.3 r----.....,-----....,CAPACITANCE (pFINORMALIZED CLOCK TO OUTPUTTIME vs. SUPPLY VOLTAGE1.1 r---r---r--.....,--...,SUPPLY VOLTAGE (VINORMALIZED CLOCKTO OUTPUTTIME vs. TEMPERATURE:§51N::;«~a:oz0·~1.-.0--4.L..5--5....1..0--..J5.5--..I8.0AMBIENT TEMPERATURE ('CISUPPLY VOLTAGE (VIAMBIENT TEMPERATURE ('CIDELTA CLOCK TO OUTPUT TIMEvs. OUTPUT LOADING20.015.010.05.0/./V , ~V200 400 800 800 1000!~~a:a:::Iu~Ziii~0OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE--12010590V758045 J30//15o I0.0/1/~~c=;:;~V _L1.0 2.0 3.0 4.04(!~aia:a:::I...uua:::Ili1~i~::I0OUTPUT SOURCE CURRENTvs. VOLTAGE70805040302010t\." '" " -' '~""""'"1.0 2.0 3.0 4.0CAPACITANCE (pFIOUTPUT VOLTAGE (VIOUTPUT VOLTAGE (VI0023-154-58

~ PALC22VIO~~~UaoR==================================================================Erasure CharacteristicsWavelengths of light less than 4000 Angstroms begin toerase the PAL C 22V 10. For this reason, an opaque labelshould be placed over the window if the device is exposedto sunlight or fluorescent lighting for extended periods oftime. In addition, high ambient light levels can create holeelectronpairs which may cause "blank" check failures or"verify errors" when programming "windowed" parts.This phenomenon can be avoided by use of an opaque labelover the window during programming in high ambientlight environments.The recommended dose for erasure is ultraviolet light witha wavelength of 2537 Angstroms for a minimum dose (UVintensity X exposure time) of25 Wsec/cm2. For an ultravioletlamp with a 12 mW /cm 2 power rating, the exposurewould be approximately 35 minutes. The PAL C 22VIOneeds to be placed within 1 inch of the lamp during erasure.Permanent damage may result if the device is exposedto high intensity UV light for an extended period of time.7258 Wsec/cm2 is the recommended maximum dosage.Device ProgrammingThe PAL C 22VI0 has multiple programmable functions.In addition to the normal array, a "PHANTOM" array,"TOP and BOTTOM TEST" and a "SECURITY" featureare programmable. The PAL C 22VIO security mechanism,when invoked, prevents access to the "NORMAL"and "TOP/BOTTOM TEST" array. The "PHANTOM"array feature is still accessible, allowing programming andverification of the pattern in the "PHANTOM" array.Functional operation of all other features is allowed regardlessof the state of the "SECURITY BIT". In addition,the device contains 10 MACROCELLS which are programmedto configure the device functionality for eachspecific application.The logic array is divided into a "NORMAL" array and a"PHANTOM" array. The normal array is used to configurethe device to perform a specific function as required bythe user, and the phantom array is provided as a test arrayfor Cypress' testing the device prior to user programmingthus assuring a reliable, thoroughly tested product. The"PHANTOM" array contains four additional columnsconnected to input pins 2 (TRUE), 7 (INVERTING), 10(TRUE) and 11 (TRUE). These inputs may be programmedto be connected to all normal product terms.This allows all sense amplifiers and macrocells to be exercisedfor both functionality and performance after assemblyand prior to shipment. These features are in addition tothe normal array. They do not affect normal operation,allowing the user full programming of the normal array,while allowing the device to be fully tested.The "TOP TEST" and "BOTTOM TEST" feature, allowconnection of all input terms to either pin 23 or 13. Theselocations may be programmed and subsequently exercisedin the "TOP TEST" and "BOTTOM TEST" mode. Likethe Phantom array above, this feature has no effect in thenormal mode of operation. Cells in the PHANTOM AR­RAY, TOP TEST, and BOTTOM TEST areas are programmedat Cypress during the manufacturing operation,and they therefore will be programmed when received in anon-windowed package by the user. Consequently, the userwill normally have no need to program these cells.The Cypress PAL C 22VIO contains 10 identical MACRO­CELLS which may be individually configured. EachMACROCELL is associated with a single I/O pin andthrough the architecture bits, each associated pin may bepermanently configured as an input, an output or be usedas both input and output as a function of the logical functionin the array. Each MACROCELL consists of a type"D" latch, an output multiplexer, a feedback multiplexerand a tristatable output driver that is controlled by aunique product term. The clock is common to all MAC­ROCELLS, and comes from pin 1 of the device. Each registeralso has an asynchronous reset and a synchronouspreset. These are each driven by product terms. Theseproduct terms are common to all MACROCELLS allowingall registers to either be asynchronously reset or synchronouslypreset by a logical function in the array. Thedevice is automatically reset at power up. A preload featureallows the registers to be preloaded with any state for testing.The architecture bits CO and Cl are used to configure eachMACROCELL individually. CO selects the polarity of theoutput and C 1 selects the combinatorial or registered modeof operation. If the registered mode of operation is selected,the feedback path is automatically selected to be from theregister. In the combinatorial mode the feedback path isautomatically selected to be from the I/O pin. In this combinatorialmode, the output from the array may be fed intothe array or if the output is deselected using the outputenable product term the pin may be used as an externalinput. There is not a mode where the I/O pin may be usedas a combinatorial output or an input pin, while the registeris used as a state register. The architecture bits areprogrammed as a separate item during normal programming.An I/O pin is configured to be an input by programmingthe MACROCELL into a combinatorial mode anddisabling the ouput with the output enable product term.PinoutThe PAL C 22VIO PROGRAMMING pinout is shown inFigure 3. In the Programming pinout configuration, thedevice may be programmed and verified for the NORMALmode of operation and also programmed, verified and operatedin PHANTOM and TEST modes. These specialmodes of operation are achieved through the use of supervoltagesapplied to certain pins. Care should be exercisedwhen entering and exiting these modes, paying specific attentionto both the operating modes as specified in Table 1and the sequencing of the supervoltages as shown in thetiming diagrams.4-59

5r~=Programming PinoutvppAOA1A2A3A4A5A6A7A8A9VssFigure 3Programming AlgorithmveeDO010203040506070809PGM/VF0023-6With the exception of the Security bit, all arrays are programmedin a similar manner. The data to be programmedis represented by a "1" or "0" on the I/O pins. A "1"indicates that an unprogrammed location is to be programmedand a "0" indicates that an unprogrammed locationis to remain unprogrammed. All locations to be programmedare addressed as row and column locations. Table1 "Operating Modes" along with Tables 2 through 5provide the specific address for each addressed location tobe programmed along with mode selection information forboth programming and operation in the "PHANTOM"and "TEST" modes.When programming the security bit, a supervoltage on pin3 is used as data with a programming pulse on pin 13.Verification is controlled with a supervoltage on pins 4 andthe data out on pin 3.Operating ModesTable 1 describes the operating and programming modes ofthe PAL C 22VI0. The majority of the programmingmodes function with a PROGRAM, PROGRAM INHIB­IT and PROGRAM VERIFY sequence. The exception isthe Security Program operation, which shows no programinhibit function. Two timing diagrams are provided forthese two different methodologies of programming in Figures5 & 6. Tables 2 through 5 are used as indicated toPAL C 22Vl0provide the individual addresses of the various arrays andcells to be programmed. There are 5 operating modes inaddition to the programming modes for the PAL C 22VI0.These provide NORMAL operation, PHANTOM operation,TOP TEST, BOTTOM TEST and a register preloadfeature for testing.In the normal operating mode, all signals are TTL levelsand the device functions as it is internally programmed inthe NORMAL array. In the PHANTOM mode of operation,the device operates logically as a function of the contentsof the PHANTOM array. In this mode pins 2, 10 &11 are non-inverting inputs and pin 7 is an inverting input.The MACROCELLS function as they are programmed fornormal operation. If the MACROCELLS have not yetbeen programmed, they are in a registered inverting configuration.The PHANTOM mode is invoked by placing asupervoltage Vpp on pin 6. Care should be exercised whenentering and leaving this mode that the supervoltage is appliedno sooner than 20 ms after the Vee is stable, andremoved a minimum of 20 ms before Vee is removed.TOP and BOTTOM TESTThe TOP TEST and BOTTOM TEST modes are enteredand exited in the same manner, with the same concern forpower sequencing, but the supervoltage is applied to pins 9& 10 respectively. In these modes an extra product termcontrols an output pin. TOP TEST controls pin 23, andBOTTOM TEST controls pin 14. These product terms arecontrolled by the normal device inputs, and allow testing ofall input structures.PreloadFinally for testing of programmed functions, a preload featureallows any or all of the registers to be loaded with aninitial value for testing. This is accomplished by raising pin8 to a supervoltage Vpp, which puts the output drivers in ahigh impedance state. The data to be loaded is then placedon the I/O pins of the device and is loaded into the registerson the positive edge of the clock on pin 1. A "0" on theI/O pin preloads the register with a "0" and a "1" preloadsthe register with a "1". The actual signal on the output pinwill depend on the output polarity selected when theMACROCELL is programmed. The data on the I/O pinsis then removed, and pin 8 returned to a normal TTL voltage.Again care should be exercised to power sequence thedevice properly.4-60

~ PALC22VIO~~~U~================================================================)perating ModesOperating Modes Pin Pin Pin Pin Pin Pin1 2 3 4 5 6Feature FunctiondainProgramVpp~rray Program Inhibit Vpp Table 2>roductProgram Verify[3] Vpp)utput Program Vpp~nable>roductProgram Inhibit Vpp Table 2rerms Program Verify VppIync Set,~syncteset,ropTest,ProgramVppProgram Inhibit Vpp Table 2~ottom Test Program Verify~otesVppTable 1Pin7Pin Pin Pin Pin Pin Pin Pin Pin8 9 10 11 13 14 17 20Pins15,16,18,19,21 &22Pin23VppData InTable 3 VIHP HighZVILPData OutVIHP VIHP VIHP Vpp VppData InVIHP VIHP VIHP Vpp VIHPHighZVIHP VIHP VIHP Vpp VILPData OutVIHP VIHP VIHP VIHP VppData Data DataDataVILPIn In In InVIHP VIHP VIHP VIHP VIHP HighZ HighZ HighZ HighZ HighZVIHP VIHP VIHP VIHP VILPData Data DataDataDrivenOut Out OutOutProgram~rchitec-Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp Vpp Data Inure Bits Program Inhibit Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Table 4 Vpp VIHP HighZProgram Verify Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP Vpp VILP Data OutlecurityProgram Vpp VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Vpp VILP VILP VILP VILP~itVerifyVILP VILP Data Vpp VILP VILP VILP VILP VILP VILP VILP VILPOutDriven OutputsNormal CP/I I I I I I I I I I I I I/O>AL Phantom NA I NA NA NA Vpp I NA NA I I NA Outputdode Top Test I I I I I I I I Vpp I I I NA)perationBottom Test I I I I I I I I I Vpp I I Out NAReg Preload Notes NA NA NA NA NA NA Vpp NA NA NA VILP Data In>hantom Program Vpp VILP VILP VILP VppVppData In~rray>roductProgram Inhibit Vpp VILP VILP Table 5 VILP Vpp Table 3 VIHP HighZrerms Program Verify Vpp VILP VILP VILP VppVILPData Out>hantom)utputProgram Vpp VILP VILP VILP Vpp VIHP VIHP VIHP Vpp VppData In~nable Program Inhibit Vpp VILP VILP Table 5 VILP Vpp VIHP VIHP VIHP Vpp VIHPHighZ>roductrermsProgram Verify Vpp VILP VIL VILP Vpp VIHP VIHP VIHP Vpp VILPData Out~otes:. DATA IN and DATA OUT for programming Synchronous Set,Asynchronous Reset, TOP TEST and BOTTOM TEST is programmedand verified on the following pins.Pin 14 = BOTTOM TESTPin 17 = Synchronous SetPin 20 = Asynchronous ResetPin 23 = TOP TESTVILP2. The preload clock on pin 1 loads the Registers on a LOW goingHIGH transition.3. It is necessary to toggle OE (Pin 13) HIGH during all address transitionswhile in the program verify !blank check mode.Out•4-61

~ PALC22VIO~,-~==============================~~==~====Input Term AddressesTable 2 is used during the programming and verification ofthe main array, output enable, asynchronous reset, synchronouspreset, TOP and BOTTOM TEST as shown inTable 1.Input Term AddressesInput Pin PinTerm 2 30 VILP VILP1 VIHP VILP2 VILP VIHP3 VIHP VIHP4 VILP VILP5 VIHP VILP6 VILP VIHP7 VIHP VIHP8 VILP VILP9 VIHP VILP10 VILP VIHP11 VIHP VIHP12 VILP VILP13 VIHP VILP14 VILP VIHP15 VIHP VIHP16 VILP VILP17 VIHP VILP18 VILP VIHP19 VIHP VIHP20 VILP VILP21 VIHP VILP22 VILP VIHP23 VIHP VIHP24 VILP VILP25 VIHP VILP26 VILP VIHP27 VIHP VIHP28 VILP VILP29 VIHP VILP30 VILP VIHP31 VIHP VIHP32 VILP VILP33 VIHP VILP34 VILP VIHP35 VIHP VIHP36 VILP VILP37 VIHP VILP38 VILP VIHP39 VIHP VIHP40 VILP VILP41 VIHP VILP42 VILP VIHP43 VIHP VIHPTable 2It provides the addressing for the 44 normal input termcolumns which are connected with an EPROM transistorto the product terms.Pin Pin Pin Pin4 5 6 7VILP VILP VILP VILPVILP VILP VILP VILPVILP VILP VILP VILPVILP VILP VILP VILPVIHP VILP VILP VILPVIHP VILP VILP VILPVIHP VILP VILP VILPVIHP VILP VILP VILPVILP VIHP VILP VILPVILP VIHP Vn,p VILPVILP VIHP VILP VILPVILP VIHP VILP VILPVIHP VIHP VILP VILPVIHP VIHP VILP VILPVIHP VIHP VILP VILPVIHP VIHP VILP VILPVILP VILP VIHP VILPVILP VILP VIHP VILPVILP VILP VIHP VILPVILP VILP VIHP VILPVIHP VILP VIHP VILPVIHP VILP VIHP VILPVIHP VILP VIHP VILPVIHP VILP VIHP VILPVILP VIHP VIHP VILPVILP VIHP VIHP VILPVILP VIHP VIHP VILPVILP VIHP VIHP VILPVIHP VIHP VIHP VILPVIHP VIHP VIHP VILPVIHP VIHP VIHP VILPVIHP VIHP VIHP VILPVILP VILP VILP VIHPVILP VILP VILP VIHPVILP VILP VILP VIHPVILP VILP VILP VIHPVIHP VILP VILP VIHPVIHP VILP VILP VIHPVIHP VILP VILP VIHPVIHP VILP VILP VIHPVILP VIHP VILP VIHPVILP VIHP VILP VIHPVILP VIHP VILP VIHPVILP VIHP VILP VIHP4-62

~ PALC22VIO~~~U~================================================================Product Term AddressesTable 3 is used for the programming ofthe "PHANTOM"and normal array. It provides the addressing for the up to16 product terms associated with each input. Notice thatthe number of product terms varies from 8 to 16 and backto 8 from the top to the bottom output. In Table 3, productterm "0" refers to the top product term associated with theMACROCELLS on pins 18 and 19, while address 15 refersto the bottom or last product term associated with thesame pins. In the same manner, the 8 product terms associatedwith pins 14 and 23 are addressed as "0" through "7".The balance of the product terms associated with the remainingI/O pins are addressed as "0" through "10", "12"and "14".Product Term AddressesTable 3Product Pin PinTerm 8 90 VILP VILP1 VIHP VILP2 VILP VIHP3 VIHP VIHP4 VILP VILP5 VIHP VILP6 VILP VIHP7 VIHP VIHP8 VILP VILP9 VIHP VILP10 VILP VIHP11 VIHP VIHP12 VILP VILP13 VIHP VILP14 VILP VIHP15 VIHP VIHPArchitecture Bit AddresssingPin Pin10 11VILPVILPVILPVILPVIHPVIHPVIHPVIHPVILPVILPVILPVILPVIHPVIHPVIHPVIHPVILPVILPVILPVILPVILPVILPVILPVILPVIHPVIHPVIHPVIHPVIHPVIHPVIHPVIHPTable 4 provides the addressing for the architecture bitsused to control the configuration of the individual MAC­ROCELLS. In the unprogrammed state, the MACRO­CELLS are in a registered, active low or inverting configuration.They are programmed with a "1" on the pin associatedwith the MACROCELL and the appropriate addressas shown in Table 4. Each architecture bit that is not to beprogrammed, requires a "0" on the I/O pin associated withthe MACROCELL.Architecture Bit AddresssingTable 4Architecture Pin PinBit 9 10OutputPolarity VILP VILPCORegister/Non-Register VIHP VILPOutput C1Phantom Input Term AddressingPhantom input terms are addressed as columns PO thru P3and represent inputs from pins 2, 7, 10 and 11 respectively.Pin 7 is inverted, and the remaining 3 are normal non-inverting.This PHANTOM array allows the output structuresto be tested. They are only present in PHANTOMmodes of operation.Phantom Input Term AddressesTable 5PhantomInputTermPOPIP2P3Pin4VILPVIHPVILPVIHPProgramming Flow ChartThe programming flow chart describes the sequence of operationsfor programming the NORMAL and PHANTOMarrays, the NORMAL and PHANTOM output enableproduct terms, the set and preset product terms, the TopTest product term, the Bottom Test product term, and the 4architecture bits. The exact sequencing and timing of thesignals is shown in the "Array Programming Timing Diagram".The logical sequence to program the device is described indetail in the flow chart below, and should be followed exactlyfor optimum intelligent programming that both minimizesprogramming time and realizes reliable programming.Particular attention should be paid to the applicationof Vee prior to V pp, and removal of V pp prior to Vee. SeeFigure 5 and Table 7 for specific timing and AC requirements.Notice that all programming is accomplished withoutswitching Vpp on pin 1 and that after programmingand verifying all locations individually, the programmedlocations should be verified one final time.The normal word programming cycle, programs and verifiesa word at a time as shown in the programming flowchart,Figure 4 and timing diagram Figure 5. After alliocationsare programmed, the flowchart requires a verify of allwords. There is no independent timing diagram for thisoperation, rather Figure 5 also provides the correct timinginformation for this operation. When performing this verifyonly operation, eliminate the program portion of thecycle but maintain the setup and hold timing relative to theverify pulse. Under no circumstances should the verify signalbe held low and the addresses toggled.Pin5VILPVILPVIHPVIHPNote that the overprogram pulse in step 10 of the programmingflowchart is a variable, "4" times the initial valuewhen programming the NORMAL, PHANTOM, TOPTEST, BOTTOM TEST and OUTPUT ENABLE productterms and "8" times the initial value when programmingthe ARCHITECTURE BITS.4-63

~~====================================~P~A~L~C~2~2V;1~OProgramming FlowchartSTARTVee = 5.0VVpp = 13.5VADDRESS FIRST LOCATION,PLACE DATA TO BE PROGRA ...... EDON THE I/O PINSX=ONote:1. T~is value is "4" for programmmgthe NORMAL array,PHANTOM array TOP TEST,BOTTOM TEST and OUTPUTENABLE PRODUCT TERMS.T~e value is "s" when programmmgARCHITECTURE BITS.PROGRA ... ONE PULSEOF 0.2mSx = X + 1X = 10?NOVERIFY ONE WORDPASSPROGRA ... ONE PULSE OF«NOTE 1) • 0.2 • X) j.£SX = 10NOr---------~----~~---.------1YESVERIFY ALL WORDS ATVeep = 5.0 VOLTSPASSGOOD DEVICEVpp = O.OVVee = O.OVSTOPFigure 30023-74-64

~ PAL C 22VI0_r~~================~~Timing DiagramsProgramming timing diagrams are provided for two cases,programming of all cells except the SECURITY BIT andprogramming the SECURITY BIT.ArrayProgramming the NORMAL and PHANTOM arrays andoutput enables, reset, preset, architecture bits and the top/bottom test features uses the timing diagram in Figure 4.ADDRESS refers to all applicable information in Tables 1through 5 that is not specifically referenced in the timingdiagram. DATA IN is provided on the I/O pins andProgramming WaveformsDATA OUT is verified on the same pins. A "1" (VIHP) onan I/O pin causes the addressed location to be programmed.A "0" on the I/O pin leaves the addressed locationto be unprogrammed. All setup hold and delay timesmust be met, and in particular the sequence of operationsshould be strictly followed. During verify only operation itis not acceptable to hold PGMIVFY low and sequenceaddresses, as it violates address setup and hold times. Propersequencing of all power and supervoltages is essential, toreliable programming of the device as improper sequencingcould result in device damage.VccpVee PIN 24NOTE 1 V SS-VppVpp PIN 1Vss 14-------TOP ------+1ADDRESSNOTE 2V 1HPV1LP -DATAV 1HPV1LP -PG~/VFYPIN 13Vpp_V 1HP - ---------~V1LP -Notes:1. Power, Vpp & Vee should not be cycled for each program/verifycycle, but may remain static during programming.Figure 42. For programming OE Product Terms & Architecture bits, Pin 11(A9) must go to Vpp and satisfy TAS and TAN.0023-84-65

Security CellThe security cell is programmed independently per the timingdiagram in Figure 5, and the information in Table 1.Note again that proper sequencing of power and programmingsignals is required. Data in is represented as a supervoltageon pin 3 and verified as a TTL signal output on theProgramming Waveforms Security Cellvee PIN 24Veep--JVSS -Tpsame pin. A "0" on pin 3 indicates that the security bit hasbeen programmed, and a "1" indicates that security bit hasnot been programmed. Security is programmed with a single50 ms pulse on pin 13. A supervoltage on pin 4 is usedto verify security after V pp has been removed from pin 1.~" _____________ TP ____________ ~~vpp_Vpp PIN 1VSS-V pp_TopDATA PIN3 V1HP -TOZV1LP -PGMPIN 13Vpp_V IL • P _SECURITYVFYPIN4Vpp_V 1LP -I+---TOVFigure 50023-94-66

~ PAL C 22VIO~~~~================================================================DC Programming Parameters TA = 25°CTable 6Parameter Description Min. Max. UnitsVpp Programming Voltage 13.0 14.0 VoltsVeepVIHPVILPSupply VoltageDuring ProgrammingInput HIGH VoltageDuring ProgrammingInput LOW VoltageDuring Programming4.75 5.25 Volts3.0 Veep Volts-3.0 0.4 VoltsVOH Output HIGH Voltage 2.4 VoltsVOL Output LOW Voltage 0.4 VoltsIppAC Programming ParametersProgrammingSupply CurrentTable 740 rnAParameter Description Min. Max. UnitsTpDelay to ProgrammingVoltage20 msTop Delay to Program 1 p.sTHPHold from Programor Verify1 p.sTR,F Vpp Rise & Fall Time 50 nsTAS Address Setup Time 1 p.sTAH Address Hold Time 1 p.sToS Data Setup Time 1 p.sTOH Data Hold Time 1 p.sTpp Programming Pulsewidth 0.2 10 msTSppTovProgramming Pulsewidthfor SecurityDelay from Programto Verify50 ms2 p.sTvo Delay to Data Out 1 p.sTvp Verify Pulse Width 2 p.sToz Verify to High Z 1 p.s4-67

~ PAL C 22VIO~~~U~~~~~~~==~======~==~==~~==~==========================Ordering InformationICC tpD ts teo Ordering Code Package Operating Range(mA) (ns) (ns) (ns)90 15 12 10 PAL C 22V10-15PC P13 CommercialPAL C 22VlO-15WCPAL C 22VlO-15JC90 20 12 15 PAL C 22VlO-20PC P13 CommercialPAL C 22VlO-20WCPAL C 22VlO-20JC120 20 17 15 PAL C 22VlO-200MB 014 MilitaryPAL C 22VlO-20WMBPAL C 22VlO-20LMBPAL C 22VlO-2OQMB55 25 15 15 PAL C 22VlOL-25PC P13 CommercialPAL C 22VlOL-25WCPAL C 22VlOL-25JC90 25 15 15 PAL C 22VlO-25PC P13 CommercialPAL C 22VlO-25WCPAL C 22VlO-25JC100 25 20 20 PAL C 22V10-250MB 014 MilitaryPAL C 22VlO-25WMBPAL C 22VlO-25LMBPAL C 22VlO-25QMB100 30 25 20 PAL C 22VlO-300MB 014 MilitaryPAL C 22VlO-30WMBPAL C 22VlO-30LMBPAL C 22VlO-30QMB55 35 30 25 PAL C 22VlOL-35PC P13 CommercialPAL C 22VlOL-35WCW14J64W14J64W14L64Q64W14J64W14J64W14L64Q64W14L64Q64W14PAL C 22VlOL-35JC '16490 35 30 25 PAL C 22VlO-35PC P13 CommercialPAL C 22VlO-35WCPAL C 22VlO-35JC100 40 35 25 PAL C 22VlO-400MB 014 MilitaryPAL C 22VlO-40WMBPAL C 22VlO-40LMBPAL C 22VlO-40QMBW14J64W14L64Q644-68

~ PALC22Vl0~~~~UcrOR======================================~==~======~====~~==MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstpD 7,8,9,10,11teo 7,8,9,10,11ts 7,8,9,10,11tH 7,8,9,10,11tw 7,8,9,10,11IIDocument #: 38-00020-B4-69

Features• 12 I/O macro cells each having:- registered, three-state I/Opins- input register clock selectmultiplexer- feed back multiplexer- output enable (OE)multiplexer• All twelve macro cell stateregisters can be hidden• User configurable stateregisters-JK, RS, T, or D• Input multiplexer per pair ofI/O macro cells allows I/O pinassociated with a hidden macrocell state register to be saved foruse as an input• 4 dedicated hidden registers• 11 dedicated, registered inputs• 3 separate clocks-2 inputs,1 output• Common (PIN 14 controlled) orproduct term controlled outputenable for each I/O pinCYPRESSSEMICONDUCTOR• 256 product terms-32 per pairof macro cells, variabledistribution• Global, synchronous, productterm controlled, state registerset and reset-inputs to productterm are clocked by input clock• 50 MHz operation- 5 ns input setup and 15 nsclock to output- 20 ns input register to stateregister• Low power- 120 mA maximum Icc• 28 pin 300 mil DIP, LCC• Erasable and reprogrammableProduct CharacteristicsThe CY7C330 is a high-performance,eraseable, programmable, logic device(EPLD) whose architecture has beenoptimized to enable the user to easilyand efficiently construct very high performancesynchronous state machines.CY7C330CMOS ProgrammableSynchronous State MachineThe unique architecture of theCY7C330, consisting of the user-configurableoutput macrocell, bi-directionalI/O capability, input registers,and three separate clocks, enables theuser to design high performance statemachines that can communicate eitherwith each other or with microprocessorsover bi-directional parallel bussesof user-definable widths.The three separate clocks permit independent,synchronous state machinesto be synchronized to each other. Thetwo input clocks, Ct, C2, enable thestate machine to sample input signalsthat may be generated by another systemand that may be available on itsbus for a short period of time.The user-configurable state registerflip-flops enable the designer to designateJK, RS, T, or D type devices, sothat the number of product terms requiredto implement the logic is minimized.Block Diagram and DIP Pinout0E/1 0 19 Is 17 16 15 Vss'14 13 12 1, 10/CK2 CKI ClKLCCPinout:~Ed~~~• 3 2 :1:28272612 5...2513 6 24 1/°3I/O.I. 7 23 I/OsVss 8 22 VeeIs 9 21 Vss16 10 20 1/°67 11 19 1/°712 13 14 15 16 17 18.!'.!'I~~~~~PLCCPinout8_~ O_N..:"")~d!S~~0101-141/°3I/0.I/osVeevssI/O,1/071/ 0 "1/°10 1/°9 vssVce 1/°5 1/°10101-1.!'~~~~~~0101-15Selection GuideCY7C330-S0 CY7C330-40 CY7C330-33 CY7C330-28Maximum Operating Frequency (MHz) 50 40 33 28Maximum Operating Current (mA) I Commercial 120 120Military 150 15014-70

~ CY7C330~~~UaoR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Product Characteristics (Continued)Macro Cell Input MultiplexerThe major functional blocks of the CY7C330 are (1) the Each pair of I/O macro cells share a Macro Cell Inputinput registers and (input) clock multiplexers, (2) theMultiplexer which selects the output of one or the other ofEPROM (AND) cell array, (3) the twelve I/O macrocells the pair's input registers to be fed to the input array. Thisand (4) the four hidden registers.multiplexer is shown in Figure 3. The Macro Cell InputMultiplexer allows the input pin of a macro cell, for whichInput Registers and Clock Multiplexersthe state register has been hidden by feeding back its inputThere are a total of eleven dedicated Input Registers. Each to the input array, to be preserved for use as an input pin.Input Register consists of a D flip-flop and a clock multiplexer.The clock multiplexer is user-programmable to se­not needed as a input or does not require State RegisterThis is possible as long as the other macro cell of the pair islect either CK1 or CK2 as the clock for the flip-flop. CK2 feed back. The input pin input register output which wouldand OE can alternatively be used as inputs to the array. normally be blocked by the hidden State Register feed backThe twenty-two outputs of the registers (i.e. the Q and Q can be routed to the array input path of the companionoutputs of the input registers) drive the array of EPROM macro cell for use as array input.cells.An architecture configuration bit (C4) is reserved for eachState RegistersDedicated Input Register cell to allow selection of either By use of the exclusive or gate the State Register may beinput clock CK1 or CK2 as the input register clock for configured as a JK, RS or T Register. The default is aeach Dedicated Input Cell. If the CK2 clock is not needed D-Type register. For the D-Type register, the exclusive orthat input may also be used as a general purpose arrayfunction can be used to select the polarity or the registerinput. In this case the Input Register for this input canoutput.only be clocked by input clock CKl. Figure 1 illustrates The set and reset of the State Register are global synchronoussignals which are controlled by the logic of two globalthe Dedicated Input Cell composed of input register, InputClock Multiplexer, and architecture configuration bit C4 product terms for which input signals are clocked throughwhich determines the input clock selected.the input registers by either of the input clocks, CKI orI/O Macro CellCK2.The logic diagram of the CY7C330 I/O macro cell isHidden Registersshown in Figure 2. There are a total of twelve indenticalIn addition to the twelve macro cells, which contain a totalmacro cells.oftwenty-four registers, there are four hidden registersEach macro cell consists of:whose outputs are not brought out to the device output- An Output State Register which is clocked by the globalstate counter clock, CLK (PIN 1). The State Registerpins. The Hidden State Register Macro Cell is shown inFigure 4.can be configured as a D, JK, RS, or T flip-flop (default The four hidden registers are clocked by the same clock asis a D-type flip-flop). Polarity can be controlled in the the macrocell state registers. All of the hidden register flipflopsha~e a common, synchronous set, S, as well as a com­D flip-flop implementation by use of the exclusive orfunction. Data is sampled on the LOW to HIGH clock mon, synchronous reset, R, which oer-ride the data at thetransition. All of the State Registers have a common D input. The Sand R signals are PRODUCT TERMS thatreset and set which are controlled asynchronously by are generated in the array and are the same signals used toProduct Terms which are generated in the EPROM cell preset and reset the state register flip-flops.array.Macrocell Product Term Distribution- A Macro Cell Input Register which may be clocked byeither the CKI or CK2 input clock as programmed by Each pair of macrocells has a total of thirty-two productthe user by use of architecture configuration bit C2 terms. Two product terms of each macrocell pair are usedwhich controls the I/O Macro Cell Input Clock Multiplexer.The Macro Cell Input Registers are initialized product terms are also used as one input to each of the twofor the output enables (OEs) for the two output pins. Twoon power up such that all of the Q outputs are at logic exclusive OR gates in the macrocell pair. The number ofLOW level and the Q outputs are at a logic HIGH level. product terms available to the designer is then 32 - 4 =28 for each macrocell pair. These product terms are dividedbetween the macro cell state register flip-flops as shown- An Output Enable Multiplexer (OE), which is user-programmable,by architecture configuration bit CO, to selecteither the common OE signal from pin 14 or, forin Table 1.each cell individually, the signal from the Output EnableTable 1. Product Term Distributionproduct term associated with each macro cell. TheMacro Cell Pin No. Product TermsOutput Enable input signal to the array product term is0 28 9clocked through the input register by the selected input1 27 19register clock, CK 1 or CK2.2 26 11- An input Feed Back Multiplexer which is user-programmableto select either the output of the State Regis­4 24 133 25 17ter or the output of the Macro Cell Input Register to be5 23 15fed back into the array. This option is programmed by6 20 15architecture configuration bit Cl. If the output of the7 19 13Macro Cell Input Register is selected by the Feed Back8 18 17MUltiplexer, the I/O pin becomes bi-directional.9 17 1110 16 1911 15 94-71II

Product Characteristics (Continued)Hidden State Register Product Term DistributionEach pair of hidden registers also has a total of 32 productterms. Two product terms are used as one input to each ofthe exclusive OR gates. However, because the register outputsdo not go to any output pins, output enable productterms are not required. Therefore, 30 product terms areavailable to the designer for each pair of hidden registers.The product term distribution for the four hidden registersare shown in Table 2.Table 2. Hidden State Register Product Term DistributionHidden Register CellProduct Terms0 191 112 173 13Architecture Configuration BitsThe architecture configuration bits are used to program themultiplexers. The function of the architecture bits is outlinedbelow.coClC2C3C4ArchitectureConfiguration BitOutput EnableSelectMUXState RegisterFeed Back MUXI/O MacroCell InputRegister ClockSelectMUXI/O Macro CellPair InputSelectMUXDedicated InputRegister ClockSelectMUXTable 3. Architecture Configuration BitsNumberof BitsValueFunction12 Bits, 1 Per 0---Virgin State Output Enable Controlled by Product TermI/O Macro Cell I-Programmed Output Enable Controlled by Pin 1412 Bits, 1 Per 0---Virgin State State Register Output is Fed Back to Input ArrayI/O Macro Cell I-Programmed I/O Macro Cell is Configured as an Inputand Output of Input Register is Fed to Array12 Bits, 1 Per 0---Virgin State CKI Input Register Clock (Pin 2) is ConnectedI/O Macro Cellto I/O Macro Cell Input Register Clock InputI-Programmed CK2 Input Register Clock (Pin 3) is Connectedto I/O Macro Cell Input Register Clock Input6 Bits, 1 Per 0---Virgin State Selects Data from I/O Macro Cell Input RegisterI/O Macro Cellof Macro Cell A of Macro Cell PairPair I-Programmed Selects Data from I/O Macro Cell Input Registerof Macro Cell B of Macro Cell Pair11 Bits, 1 Per 0---Virgin State CKI Input Register Clock (Pin 2) is ConnectedDedicated Inputto Dedicated Input Register Clock InputCell I-Programmed CK2 Input Register Clock (pin 3) is Connectedto Dedicated Input Register Clock Input~~------------~D QINPUTREGISTERINPUT TOLOGICARRAYC4CKl(PIN 2)CK2(PIN 3)REGISTER INITIALIZED ON POWER UPTO Q EQUAL TO LOGIC LOWFigure 1. Dedicated Input Cell0101-54-72

~~~~~~~==============================~C~Y~7~C~33~OTOMACRO CEllINPUT MUXGlOBAL STATEREGISTER CLOCKClK(PIN 1)Figure 2. I/O Macro CellINPUTCLOCKS CK2 CK1(PIN 3)(PIN 2)0101-6OUTPUT FROMlOGIC ARRAYFEEDBACK TO ---..,LOGIC ARRAY __.cT"....INPUT TO ---..,lOGIC ARRAY __.cT"....MACRO CEll Aa - OUTPUT FROMINPUT REGISTER OFI/O MACRO CELL Aoa - OUTPUT FROMINPUT REGISTER OFI/o MACRO CELL BGLOBAL SYNCHRONOUS SETOUTPUT FROMlOGIC ARRAYFEEDBACK TO --_....LOGIC ARRAY __.-~ IMACRO CEll BFigure 3. I/O Macro Cell Pairwith Shared Input MUX0101-7GLOBAL STATEREGISTER CLOCKCLK(PIN 1)Figure 4. Hidden State Register Macro Cell0101-84-73

~ CY7C330~~~~==============================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150"CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 24 to Pin 12) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to + 7.0VStatic Discharge Voltage ..................... > 2001V(per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 mAOperating RangeRangeAmbientTemperatureDC Input Voltage ................... -3.OVto +7.0V Commerical O°Cto +70°C 5V ±1O%Output Current into Outputs (Low) ..... , ........ 16 mA Military [5] - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over Operating Range[6]Parameters Description Test Conditions Min. Max. UnitsVOH Output HIGH Voltage Vee = Min., IOH = -3.2rnA COM'LVIN = VIH or VILIOH = -2mA MILVOL Output LOW Voltage Vee = Min., IOL = 12mA COM'LVIN = VIH or VIL IOL = SmA MILVIH Input HIGH Level Guaranteed Input Logical HIGH Voltagefor All Inputs [1]VIL Input LOW Level Guaranteed Input Logical LOW Voltagefor All Inputs [I]Vee2.4 V0.5 V2.0 VIIX Input Leakage Current Vss ~ VIN ~ Vee, Vee = Max. -10 10 p.AIoz Output Leakage Current Vee = Max. Vss ~ VOUT ~ Vee -40 40 p.AIsc Output Short Circuit Current Vee = Max., VOUT = 0.5V[2] -30 -90 rnAIcc Power Supply Current Vee = Max., VIN = GND, COM'L 120 mAOutputs OpenDevice Operating @ fmaxMIL 150 mACapacitance [3]Parameters Description Test Conditions Min Max UnitsCIN Input Capacitance VIN = 2,OV @ f = 1 MHz 7pFCoUT Output Capacitance VOUT = 2.0V @ f = 1 MHz SNotes:1. These are absolute values with respect to device ground and all overshootsdue to system or tester noise are included.affect these parameters.3. Tested initially and after any design or process changes that may2. Not more than one output should be tested at a time. Duration of the 4. Figure 5a test load used for all parameters except tcEA. tCER. tpzxshort circuit should not be more than one second. V OUT = O.5V has and tpxz. Figure 5b test load for tCEA, tCER, tpzx. tpxz.been chosen to avoid test problems caused by tester ground degradation.6. See the last page of this specification for Group A subgroup testing5. T A is the "instant on" case temperature.information.O.SV4-74

~ CY7C330~~~================================================================Switching Characteristics Over the Operating Range[4, 6]ParametersDescription -50CommercialNo. Ref. Min. Max. Min.1 tISU Input or Feedback Setupto Input Register Clock2 tosu Input Register Clock toOutput Register Clock3 teo Output RegisterClock to Output4 tH Hold Time fromInput Register Clock5 tcEA Input Register Clockto Output Enable6 tcER Input Register Clockto Output Disable7 tpzx Pin 14 Enable toOutput Enable8 tpxz Pin 14 Disable toOutput Disable9 tw Input or OutputClock Width10 tp Input or OutputClock Period11 fmax Input or OutputClock Maximum FrequencyAC Test Loads and Waveforms (Commercial)5 1020 30155 52020202010 1520 3050 33-33Max.2030303030Military-40 -28Min. Max. Min. Max.5 1025 3520 255 525 3525 3525 3525 3512.5 17.525 3540 28UnitsnsnsnsnsnsnsnsnsnsnsMHzR1313.0.5Vj1(470.o. MIL)R1313.0.5VT-l(470.o. MIL)INPUT PULSES3.0 v----...Ir!=-==::---~LOUTPUTOUTPUTGNO--~50pF ~~s.o.5pF~~8.o.INCLUDING I (319.0. MIL)JIG AND~ -= (319.0. MIL)SCOPE -= -=Figure 60101-9Figure SaFigure SbEquivalent to: THEVENIN EQUIVALENT (Commercial) Equivalent to: THEVENIN EQUIVALENT (Military)0101-10125.0. 190.0.OUTPUT o-JVtIIt-O 2.00 VOUTPUT o-JVtIIt-O 2.02 V0101-11Switching WaveformsI/o INPUTS, REGISTERED --~~.v--"'"'\J.~~-------------­FEEDBACK INPUTS ---'-~1'---'l~~--------------INPUT CLOCK-----",1OUTPUT CLOCK-----------"'1OUTPUTS ~ K'{< ____ '-__ ~~pxz tpzx\.:PIN14~ -------------------4-750101-120101-13

~ CY7C330~~~U~==============================================================Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENTVS. SUPPLY VOLTAGE1~r---'---~----~--~NORMALIZED SUPPLY CURRENTVS. AMBIENT TEMPERATURE1~r-------~--------,1.1NORMALIZED PROPAGATIONDELAYvs. SUPPLY VOLTAGE_1:3Q10.1!:I-

~ CY7C330~~~~U~R================================================================Ordering Informationf max Icc OrderingOperating(MHz)Package(mA) Code Range50 120 CY7C330-50 P21 CommercialCY7C330-50CY7C330-50W22J6440 150 CY7C330-4O D22 MilitaryCY7C330-4OCY7C330-4OW22L6433 120 CY7C330-33 P21 CommercialCY7C330-33CY7C330-33W22J6428 150 CY7C330-28 D22 MilitaryCY7C330-28CY7C330-28W22L644-77

MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3fIx 1,2,3IOZ 1,2,3lee 1,2,3SubgroupsSwitching CharacteristicsParametersSubgroupstISU 9,10,11tosu 9,10,11teo 9,10,11tH 9,10,11teEA 9,10,11tpzx 9,10,11Document #: 38-00064-A4-78

Features• 12 I/O macrocells each having:- One state Flip-Flop with anXOR sum or products input- One feedback Flip-Flop withinput coming from the I/Opin- Independent (product term)set, reset, and clock inputs onall registers- Asynchronous bypasscapability on all registers,under product term control(r = s = 1)- Global or local output enableon tristate I/O- Feedback from either registerto the array• 192 product terms with variabledistribution to macrocellsCYPRESSSEMICONDUCTOR• 13 inputs, 12 feedback I/O pins,plus 6 shared I/O macrocellfeedbacks for a total of 31 trueand complementary inputs• High speed: 25 ns maximum• Security bit• Space saving 28 pin slim-lineDIP package; also available in28 pin PLCC• Low power- 90 mA typical Icc quiescent- 180 mA ICC maximum- UV-Eraseable andreprogrammable- Programming and operation100% testablePRELIMINARYCY7C331Asynchronous RegisteredEPLDProduct CharacteristicsThe CY7C331 is the most versatilePLD available for asynchronous designs.Central resources include 12 fullD-type Flip-Flops with separate set, resetand clock capability. For increasedutility, XOR gates are provided at theD-inputs and the product term allocationper Flip-Flop is variably distributed.I/O ResourcesPins 1 through 7 and 9 through 14serve as array inputs; pin 14 may alsobe used as a global output enable forthe I/O macrocell tristate outputs. Pins15 through 20 and 23 through 28 areconnected to I/O macrocells and maybe managed as inputs or outputs dependingon the configuration and themacrocell OE terms.IIIiiiBlock Diagram and DIP PinoutPLCCPinoutO"'N -ooco-':---00- I~~~~~0100-20100-1Selection GuideGeneric IccmA tpD/tconsPart NumberCom Mil Com7C331-25 120 257C331-30 1507C331-35 120 357C331-40 150Mil3040Com1215tORS nsMil15204-79

~ PRELIMINARY CY7C331~~~============================================================~I/O Resources (Continued)It should be noted that there are two ground connections(pins 8 and 21) which, together with Vee (pin 22) arelocated centrally on the package. The reason for this placementand dual ground structure is to minimize the groundloopnoise when the outputs are driving simultaneouslyinto a heavy capacitive load.OUTPUT FROMLOGIC ARRAYFEEDBACK TOLOGIC ARRAYINPUT TOLOGIC ARRAYI/OPINQ - OUTPUT FROMINPUT REGISTER OFI/O MACRO CELL AQ - OUTPUT FROMINPUT REGISTER OFI/o MACRO CELL BI/O PINOUTPUT FROMLOGIC ARRAYTo Shored Array Input MUXFigure 1. Macrocell0100-3The CY7C331 has 12 macrocells. Each macrocell has twoD-type Flip-Flops. One is fed from the array, and one is fedfrom the I/O pin. For each Flip-Flop there are 3 dedicatedproduct terms driving the R, S, and Clock inputs respectively.Each macrocell has one input to the array and foreach pair of macrocells there is one shared input to thearray. The macrocell input to the array may be configuredto come from the 'Q' output of either Flip-Flop.The D-type Flip-Flop which is fed from the array (i.e., thestate Flip-Flop) has a logical XOR function on its inputwhich combines a single product term with a sum (OR) ofa number of product terms. The single product term is usedto set the polarity of the output or to implement toggling(by including the current output in the product term).The Rand S inputs to the Flip-Flops override the currentsetting of the 'Q' output. The S input sets 'Q' true and theR input 'resets' 'Q' (sets it false). Ifboth R and S are asserted(true) at once, then the output will follow the input('Q' = 'D').Shared Input MultiplexerTable 1R S Q1 0 00 1 11 1 DR-S Truth TableThe input associated with each pair of macrocells may beconfigured by the shared input multiplexer to come fromeither macrocell; the 'Q' output of the Flip-Flop comingfrom the I/O pin is used as the input signal source.Product Term DistributionThe product terms are distributed to the macrocells suchthat 32 product terms are distributed between two adjacentmacrocells. The pairing of macrocells is the same as it is for4-80FEEDBACK TOLOGIC ARRAYFigure 2. Shared Input Multiplexer0100-4the shared inputs. 8 of the product terms are used in eachmacrocell for set, reset, clock, OE and the upper part of theXOR gate. This leaves 16 product terms per pair of macrocellsto be divided between the sum-of-product inputs tothe two state registers. The following table shows the I/Opin pairing for shared inputs, and the product term(P-Term) allocation to macrocells associated with the I/Opins.Table 2Macrocell Pin Number Product Terms0 28 41 27 122 26 63 25 104 24 85 23 86 20 87 19 88 18 109 17 610 16 1211 15 4The CY7C331 is configured by three arrays of configurationbits (CO, Cl, C2). For each macrocell, there is one CObit and one Cl bit. For each pair of macro cells, there is oneC2 bit.There are 12 CO bits. If CO is programmed for a macrocell,then the tristate enable (OE) will be controlled by pin 14(the global OE). If CO is not programmed, then the OEproduct term for that macrocell will be used.There is one C 1 bit for each macrocell. The C 1 bit selectsinput for the product term (PT) array from either the stateregister (if the bit is unprogrammed) or the input register.There are 6 C2 bits, providing one C2 bit for each pair ofmacrocells. The C2 bit controls the shared input Multiplexer(Mux); if the C2 bit is not programmed, then theinput to the product term array comes from the upper macrocell(A). If the C2 bit is programmed, then the inputcomes from the lower macrocell (B).The timing diagrams for the CY7C331 cover state register,input register, and various combinational delays. Since internalclocks are the outputs of product terms, all timing isfrom the transition of inputs causing the clock transition.

~ PRELIMINARY CY7C331~~~~==================================~~~~~~~~~~~~~==Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150"CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Group Potential(Pin 22 to Pins 8 or 21) .......... , .... -0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current into Outputs (Low) .............. 8 rnAElectrical Characteristics Over the Operating Range[6]Static Discharge Voltage ..................... > 2001 V(per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureVeeCommercial O°Cto + 70°C SV ±1O%Military [5] - SsoC to + 12SoC SV ±1O%Parameters Description Test Conditions Min. Max. UnitsVOHVOLOutput HIGH VoltageOutput LOW VoltageVee = Min., IOH = -3.2mA CommercialVIN = VIH or VILIOH = -2mA MilitaryVee = Min., IOL = 8mA CommercialVIN = VIH or VILIOL = 8mA Military2.4 VVIH Input HIGH Level Guaranteed HIGH Input, all Inputs[l] 2.0 VVIL Input LOW Level Guaranteed LOW Input, all Inputs[l] 0.8 VIIX Input Leakage Current VSS < VIN < Vee, < Vee = Max. -10 10 p.AIOZ Output Leakage Current Vee = Max., VSS < VOUT < Vee -40 40 p.AIse Output Short Circuit Current Vee = Max., VOUT = 0.SV[2] -30 -90 rnAIccCapacitance [3]Power Supply CurrentVee = Max., VIN = GND, Commercial 120 rnAOutputs OpenMilitary ISO rnAParameters Description Test Conditions Min. Max. UnitsCIN Input Capacitance VIN = 2.0V @ f = 1 MHz 7pFCoUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 8Notes:1. These are absolute values with respect to device ground and all overshootsdue to system or tester noise are included.3. Tested initially and after any design or process changes that mayaffect these parameters.2. Not more than one output should be tested at a time. Duration of theshort circuit should not be more than one second. VOUT = O.5V has4. Figure 3a test load used for all parameters except tpzXI. tPXZI. tpzxand tpxz. Figure 3b test load for tPZXI • tpXZI. tpzx and tpxz.been chosen to avoid test problems caused by tester ground degradation.5. T A is the "instant on" case temperature.6. See the last page of this specification for Group A subgroup testinginformation.O.SV4-81

Switching Characteristics [6]CommercialMilitaryParameter Description -25 -35 -30 -40Min. Max. Min. Max. Min. Max. Min. Max.tpD Input to Output Propagation Delay[7] 25 35 30 40tlCOInput Clock to CombinatorialOutput Delay[S]40 55 50 65tlRS Input Register Input Setup Time[S] 2 2 5 5tlRR Input Register Input Hold Time[S] 13 15 15 20tlRtiSInput to Input RegisterAsynchronous Reset Delay[S]Input to Input RegisterAsynchronous Set Delay[S]40 55 50 6540 55 50 65tco Output Register Clock to Output Delay[9] 25 35 30 40tORS Output Register Input Setup Time [9] 12 15 15 20tORR Output Register Input Hold Time[9] 8 10 10 12tORtosInput to Output RegisterAsynchronous Reset Delay[9]Input to Output RegisterAsynchronous Set Delay[9]25 35 30 4025 35 30 40tw Clock Width[S, 9] 15 20 20 25tCEA Input to Output Enable Delay[4, 10] 25 35 30 40tCER Input to Output Disable Delay[4, 10] 25 35 30 40tpzx Pin 14 to Output Enable Delay[4, 11] 20 30 25 35tpxz Pin 14 to Output Disable Delay[4, II] 20 30 25 35fMAX Maximum Frequency (l/(tORS + teo» 27 20 22 16Notes:7. Refer to Figure 5 configuration 1.S. Refer to Figure 5 configuration 2.9. Refer to Figure 5 configuration 3.AC Test Loads and Waveformsft ftR1 457.0. R1 457.0.(470.0. MIL) (470.0. MIL)OUTP~~ OUTP~~R2INCLUDINGEquivalent to:R250 pF 270.0. 5 pF· 270.0.IJIGAND - -(319.0. MIL) I=(319.0. MIL)=SCOPEFigure3aTHEVENIN EQUIVALENT170.(1OUTPUT o--JIIVV--O 1.86VFigure 3b0100-710. Refer to Figure 5 configuration 4.11. Refer to Figure 5 configuration 5.0100-5Equivalent to:INPUT PULSES3.0 V ----~~ ___ --~~GND -_...... iII!Figure 4THEVENIN EQUIVALENT190.(1OUTPUTo--JIIVV--O 2.02VUnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsMHz~ 5ns0100-60100-84-82

~ PRELIMINARY CY7C331~~~~====================~==~~~~==~~~==============~======Switching WaveformsINPUT ORI/O PINI/O INPUTREGISTERCLOCK (12)OUTPUTREGISTERCLOCK (12)OUTPUT1+----t ICO(13)1+-----t pO(15),------+I~---------tco----~SET ANDRESETINPUTS (12)0100-9OE PRODUCTTERM INPUT (12)PIN 14 AS OEOUTPUT:::!::::::::::~------------~::::::::::::~r-------------~,-------IIOUTPUT REGISTERRESET INPUT (12) _______________ -'1OUTPUT SETINPUT(12) REGISTER ___________________ ~--~INPUT REGISTERRESET INPUT (12) _________________________ "1INPUT REGISTERSET INPUT (12) _________________ _Notes:12. Because these input signals are controlled by product terms, activeinput polarity may be of either polarity. Internal active input polarityhas been shown for clarity.13. Output register is set in Transparent Mode. Set and Reset inputs arein a HIGH state.14. Dedicated input or input register is set in Transparent Mode. Set andReset inputs are in a HIGH state.'---0100-1015. Combinatorial Mode. Reset and Set inputs of the input and outputregisters should remain in a HIGH state at least until the outputresponds at tpD. When returning Set and Reset inputs to a LOWstate, one ofthese signals should go LOW a'MINIMUM of tOR priorto the other. This guarantees predictable register states upon exitfrom Combinatorial Mode.16. When entering the Combinatorial Mode, input and output registerSet and Reset inputs must be stable in a HIGH state a MINIMUMof toR prior to application of logic input signals.17. When returning to the input and/or output Registered Mode, registerSet and Reset inputs must be stable in a LOW state a MINI­MUM of toR prior to the application of the register clock input.4-83

~crPRJSS PRELIMINARY CY7C331WnlCONDUCTOR ========================::;:;;~;:;;=::;;;;;;;:~~~CONFIGURATION 11-------.f''5'''--; PRODUCTPIN TERM ...... -----1INPUT OR I/O PINARRAY0100-11CONFIGURATION 2PIN I-_-....;C;.;;L~OC~K+./~S/~R~INPUTUNREGISTEREDINPUT OR I/O PINV1D----I PRODUCTTERMARRAY0100-12CONFIGURATION 3PINUNREGISTEREDINPUT OR I/O PINPINUNREGISTEREDINPUT OR I/O PINCLOCK/SIRINPUTPRODUCTTERMARRAY0100-13PINPRODUCTCONFIGURATION 4 INPUT OR I/O PIN TERMARRAYPININPUT OR I/o PINI/O PIN0100-14CONFIGURATION 5PIN14INPUT OR I/o PINPININPUT OR I/O PINFigure 5. Timing ConfigurationsPRODUCTTERMARRAY0100-154-84

~ PRELIMINARY CY7C331~~~~UaoR================================================================Ordering InformationICC tpD tsUI teoPackage OperatingOrdering Code(rnA) (ns) (ns) (ns) Type Range180 25 20 25 CY7C331-25PC P21 CommercialCY7C331-25WCCY7C331-25JC200 30 25 30 CY7C331-300MB 022 MilitaryCY7C331-30WMBCY7C331-30LMB180 35 25 35 CY7C331-35PC P21 CommercialCY7C331-35WCCY7C331-35JC200 40 30 40 CY7C331-400MB 022 MilitaryCY7C331-40WMBCY7C331-40LMBW22J64W22Q64W22J64W22Q644-85

~ PRELIMINARY CY7C331~~~~u~============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3hx 1,2,3Ioz 1,2,3Ise 1,2,3lee 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstsUl 9,10,11tHI 9,10,11tWH 9,10,11tWL 9,10,11teo 9,10,11tpD 9,10,11tR 9,10,11ts 9,10,11tpxz 9,10,11tpzx 9,10,11tPXZI 9,10,11tpzxI 9,10,11tsu 9,10,11tH 9,10,11Document #: 38-000664-86

CYPRESSSEMICONDUCTORPRELIMINARYCY7C332Registered Combinatorial PLDFeatures• 12 I/O macrocells each having:- Registered, latched, ortransparent array input- A choice of two clock sources- Global or local output enable(OE)- Up to 19 product terms (PT)per output- Product term (PTI outputpolarity control• 192 product terms with variabledistribution to macrocells- An average of 14 PT's permacrocell sum node- Up to 19 PT's maximum forselect nodes• 2 clock inputs with configureablepolarity controlBlock Diagram and Pinout• 13 input macrocells, each having:- Complementary input- Register, latch, or transparentaccess- Two clock sources• 20 ns max. delay• Low power- 120 rnA typical IcC quiescent-180 rnA max.• Security fuse• 28 pin slim-line package; alsoavailable in 28 pin PLC• UV-Eraseable andreprogrammable• Programming and operation100% testableProduct CharacteristicsThe CY7C332 is a versatile combinatorialPLO with I/O registers onboard.There.are 25 array inputs; each has amacrocell which may be configured asa register, latch or simple buffer. Outputshave polarity and tristate controlproduct terms. The allocation of productterms to I/O macrocells is varied sothat functions of up to 19 productterms can be accommodated.I/O ResourcesPins 1 through 7 and 9 through 14function as dedicated array inputs. Pins1 and 2 function as input clocks as wellas normal inputs. Pin 14 functions as aglobal output enable as well as a normalinput.LCC and PLCC PinoutII0134-20134-1Selection GuideGenericPart NumberComICC mAMiltlco/tpDnsComMilComtIRS nsMil7C332-20 1202057C332-251502577C332-30 1203057C332-351503574-87

~ PRELIMINARY CY7C332~,-~~~~~~================================I/O Resources (Continued)PIN101-----~--tD-CK1PIN1.50PIN2 O----r'-tD_CK2PIN2.50Figure 1. CKI and CK20134-3Pins 15 through 20 and 23 through 28 are connected toI/O macro cells and may be combinatorial outputs as wellas registered or direct inputs.Input MacrocellINPUT 0----""0CK1CK2Figure 2. Input MacrocellARRAY• ...... ---INPUT0134-4There are 13 input macrocells, corresponding to pins 1through 7 and 9 through 14. Each macrocell has a clockwhich is selected to come from either pin 1 or pin 2 byconfiguration bit S2. Pins 1 and 2 are clocks as well asnormal inputs. There is no S2 configuration bit for either ofthese two input macrocells. Macrocells connected to pins 1and 2 do not have a clock choice, but each has a clockcoming from the other pin.Each input macrocell can be configured as a register, latchor a simple buffer (transparent path) to the product termarray. For a register the configuration bit, SO, is 0 (unprogrammed)and Sl is o. For a Latch, SO is 1 and Sl is O. Ifboth SO and S 1 are 1 (programmed) then the macrocell iscompletely transparent.I/O MacrocellThere are 12 I/O macrocells corresponding to pins 15through 20 and 23 through 28. Each macrocell has a tristateoutput control, an XOR product term to dynamicallycontrol polarity, and a configureable feedback path.For each I/O macrocell, the tristate control for the outputmay be configured two ways. lethe configuration bit, S2, isa 1 (programmed), then the global OE signal is selected.Otherwise, the OE product term is used.For each I/O macrocell, the input/feedback path may beconfigured as a register, latch, or shunt. There are twoconfiguration bits per I/O macrocell which configure thefeedback path. These are programmed in the same way asfor the input macrocells.For each I/O macrocell, the input register clock (or LatchEnable) which is used for the input/feedback path may beselected as pin 1 (select bit, S3, not programmed) or pin 2(select bit, S3, programmed).Array Allocation to Output MacrocellThe number of product terms in each output macrocellsum is position dependent. The table below summarizes theallocation:Table 1MacroceU Pin Number Product Terms0 28 191 27 92 26 173 25 114 24 155 23 136 20 137 19 158 18 119 17 1710 16 911 15 19PIN14'>c~'-I/O PINO~----------~CK1CK253Figure 3. I/O Macrocell0134-54-88

~ PRELIMINARY CY7C332~,-~~==========================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150"CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 21 to Pins 8 or 22) ............... -0.5V to + 7.0VDC Input Voltage ................... -3.0V to +7.0VOutput Current into Outputs (Low) .............. 8 rnAStatic Discharge Voltage ............ " ....... > 2001V(per MIL-STD-883, Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureVeeCommercial O°Cto + 70°C 5V ±1O%Military[S] - 55°C to + 125°C 5V ± 10%Electrical Characteristics Over the Operating RangeParameter Description Test Conditions Min. Max. UnitsVOHVOLOutput HIGH VoltageOutput LOW VoltageVee = Min., IOH = -3.2mA CommercialVIN = VIH or VILIOH = -2mA MilitaryVee = Min., IOL = 12mA CommercialVIN = VIH or VILIOL = SmA Military2.4 V0.5 VVIH Input LOW Level Guaranteed HIGH Input, all Inputs[I] 2.0 VVIL Input LOW Level Guaranteed LOW Input, all Inputs[I] O.S VIIX Input Leakage Current VSS < VIN < Vee, Vee = Max. -10 10 p.AIoz Output Leakage Current Vee = Max., Vss < VOUT < Vee -40 40 p.AIse Output Short Circuit Current Vee = Max., VOUT = 0.5V[2] -30 -90 rnAleePower Supply CurrentVee = Max., Commercial 120 rnAVIN = GND, Outputs Open Military 150 rnAaCapacitance [3]Parameters Description Test Conditions Min. Max. UnitsCIN Input Capacitance VIN = 2.0V @ f = 1 MHz 7CoUT Output Capacitance VOUT = 2.0V @ f = 1 MHz SNotes:1. These are absolute values with respect to device ground and all overshootsdue to system or tester noise are included.2. Not more than one output should be tested at a time. Duration of theshort circuit should not be more than one second. VOUT = O.SV hasbeen chosen to avoid test problems caused by tester ground degradation.3. Tested initially and after any design or process changes tha may affectthese parameters.4. Figure 4a test load used for all parameters except tEA. tER. tpzx andtpxz. Figure 4b test load for tEA. tER, tpzx, tpxz.S. TA is the "instant on" case temperature.pF4-89

~ PRELIMINARY CY7C332~~~U~==================================================================Switching Characteristics Over the Operating Range[1]Parameters Description -20tPDtICOInput to OutputPropagation Delay[6]Input Clock toCombinatorial Output Delay[7]Min.tIRS Input Register Input Setup Time[7] 5tIRH Input Register Input Hold Time[7] 5tw Clock Width[7] 10CommercialMax.tCEA Input to Output Enable Delay[4, 8] 20tCER Input to Output Disable Delay[4, 8] 20tpzx Pin 14 to Output Enable Delay[4, 9] 15tpxz Pin 14 to Output Disable Delay[4, 9] 15Notes:6. Refer to Figure 6 configuration 1.7. Refer to Figure 6 configuration 2.AC Test Loads and Waveforms (Commercial)ft nR1 313.0. R1 313.0.(470.0. MIL) (470.0. MIL)OUTP~~ OUTP~~R2R250 PF"I 208.0. 5 pF" 208.0.(319.0. MIL) I (319.0. MIL)INCLUDING _ _JIG AND -SCOPEFigure 48Figure 4bEquivalent to: THEVENIN EQUIVALENT (Commercial)20200134-6Military-30 -25 -35Min. Max. Min. Max. Min. Max.30 25 3530 25 357 5 77 5 714 10 1430 25 3530 25 3525 20 3025 20 308. Refer to Figure 6 configuration 3.9. Refer to Figure 6 configuration 4.INPUT PULSES3.0 V---~± __ ----iGND---~Figure 5. Input PulsesEquivalent to: THEVENIN EQUIVALENT (Military)s: 5 nsUnitsnsnsnsnsnsnsnsnsns0134-7125.0.OUTPUT~2.00VSwitching WaveformsINPUTOR 1/0(10)INPUTCLOCK (11)PIN 14AS i5EOUTPUT-0134-83 ... J'f-I---tCEA-~K-tpxz- !.=tpzx -I+--tCER-Notes:10. Because OE can be controlled by the OE product term, input signalpolarity for control of OE can be of either polarity. Internally theproduct term OE signal is active high.~(~tIRS -r-tIRH-:.j.190.0.OUTPUT~2.02VI,1"-~ ~tw J tw JtpDtlco- r.11. Since the input register clock polarity is programmable, the inputclock may be rising or falling edge triggered.0134-90134-104-90

fir~PRELIMINARY CY7C332PRODUCTCONFIGURATION 1 PIN TERMARRAYINPUT OR I/O PININPUT REGISTERPRODUCTTERMARRAYCLOCK 1 OR 2PINCONFIGURATION 3PININPUT OR I/O PINPRODUCTTERMARRAYCONFIGURATION 4N14PININPUT OR I/O PINPRODUCTTERMARRAYFigure 6. Timing ConfigurationsI/O PIN0134-11IIOrdering InformationIcc (max) tICO/tpD (os) tIRS(OS) tlRH (os) Ordering CodePackage OperatingType Range120 20 5 5 CY7C332-20PC P21 CommercialCY7C332-20WC W22CY7C332-20JC J64150 25 7 7 CY7C332-250MB 022 MilitaryCY7C332-25WMB W22CY7C332-25LMB Q64120 30 5 5 CY7C332-30PC P21 CommercialCY7C332-30WC W22CY7C332-30JC J64150 35 7 7 CY7C332-350MB 022 MilitaryCY7C332-35WMB W22CY7C332-35LMB Q644-91

~ PLD Programming Information~~~U~========================~======================================IntroductionPLDs or Programmable Logic Devices provide an attractivealternative to logic implemented with discrete devices.Because the primary requirements for this logic has been toprovide high performance and increased functional density,in the past all programmable logic functions have been implementedin a bipolar technology. Bipolar technology usesa fuse for the programming mechanism. The fuses are intactwhen the product is delivered to the user, and may beprogrammed once, then read and used indefinitely. Thefuses are literally blown using a high current supplied by aprogramming system. Programming or blowing a fuse is aone time event, once blown the fuse is forever open. A fusetherefore may not be tested to see that it will blow or programproperly before it is delivered to the user. This difficultyin testing fuses for programming results in less than100% programming yield in the field, and this fallout fallsinto three categories.A certain percentage of the product simply fails to program.These devices are easily identified, and may be returnedfor replacement. A small percentage of the productwill program and verify correctly, but fail to function properlyas a logic element. This can happen because, withoutprogramming each location, the connection between theprogrammed cell and the logic it is to control cannot beverified. Some programmers can test for this conditionthrough the use of a set of test vectors for each unique codeor part. Additional material will be lost, however, even if astructured set of test vectors is used due to the device functioningtoo slow. This failure is much more subtle and canonly be found by 100% AC testing of the programmeddevice, or worse yet by troubleshooting an assembled boardor system.Cypress PLDs use an EPROM programming mechanism.This technology has been available since the early 1970's,however, as with most MOS technologies, the emphasis hasbeen on density, not performance. CMOS at Cypress is asfast as or faster than Bipolar and coupled with EPROMprogramming, offers a viable alternative to bipolar programmablelogic from a performance point of view. In addition,CMOS EPROM technology offers other overwhelmingadvantages. EPROM cells are programmed byinjecting charge on an electrically isolated gate which causesthe transistor to be permanently turned off. This mechanismmay be reversed by irradiating the cell with ultravioletlight. This feature totally changes the testing philosophyand provides a new feature for the user. All programmablecells may now be tested by the manufacturer prior to deliveryto the customer. This provides an easy methodology tocertify programming, functionality, and performance. Withbuilt in test arrays, functionality and performance may betested even if the device is packaged in a non-windowedpackage. Devices packaged in a windowed package may beprogrammed and erased indefinitely providing the designera tool for the development of his logic without throwingaway devices that are programmed incorrectly as the designproceeds.Programmable TechnologyEPROM Process TechnologyEPROM technology employs a floating or isolated gatebetween the normal control gate and the source/drain regionof a transistor. This gate may be charged with electronsduring the programming operation and whencharged with electrons, the transistor is permanentlyturned off. When uncharged (the transistor is unprogrammed)the device may be turned on and off normallywith the control gate. The state of the floating gate,charged or uncharged, is permanent because the gate isisolated in an extremely plJre oxide. The charge may beremoved if the device is irradiated with ultraviolet energyin the form of light. This ultraviolet light allows the electronson the gate to recombine and discharge the gate. Thisprocess is repeatable and therefore can be used during theprocessing of the device, repeatedly if necessary, to assureprogramming function and performance.Two Transistor CellsIn order to provide an EPROM cell that is as fast as thefuse technology employed in bipolar processes, Cypressuses a two transistor EPROM cell. One transistor is optimizedfor reliable programming, and one transistor is optimizedfor high speed. The floating gates are connectedsuch that charge injected on the floating gate of the programmingtransistor is conducted to the read transistor biasingit off.Programming AlgorithmByte Addressing and ProgrammingAll Cypress Programmable Logic Devices are addressedand programmed on BYTE or EXTENDED BYTE basiswhere an EXTENDED BYTE is a field that is as wide asthe output path of the device. Each device or family ofdevices has a unique address map which is available in theproduct data sheet. Each BYTE or EXTENDED BYTE iswritten into the addressed location from the pins that serveas the output pins in normal operation. To program a cell,a "1" or HIGH is placed on the input pin and a "0" orLOW is placed on pins corresponding to cells that are notto be programmed. Data is also read from these pins inparallel for verification after programming. A "1" orHIGH during program verify operation indicates an unprogrammedcell, while a "0" or LOW indicates that thecell accessed has been programmed.Blank CheckBefore programming all Programmable Logic Devices maybe checked in a conventional manner to determine thatthey have not been previously programmed. This is accomplishedin a program verify mode of operation by readingthe contents of the array. During this operation, a "1" orHIGH output indicates that the addressed cell is unprogrammed,while a "0" or LOW indicates a programmedcell.4-92

~ PLD Programming Information (Continued)~~~U~==~~~~~~~~~==~~~~~~~~~~~~~~==~====~====Programming The Data ArrayProgramming is accomplished by applying a supervoltageto one pin of the device causing it to enter the programmingmode of operation. This also provides the programmingvoltage for the cells to be programmed. In this modeof operation, the address lines of the device are used toaddress each location to be programmed, and the data ispresented on the pins normally used for reading the contentsof the device. Each device has a READ/WRITE pinin the programming mode. This signal causes a write operationwhen switched to a supervoltage, and a read operationwhen switched to a logic "0" or LOW. In the logicHIGH state "I" the device is in a program inhibit conditionand the output pins are in a high impedance· state.During a WRITE operation, the data on the output pins iswritten into the addressed array location. In a READ operationthe contents of the addressed location are present onthe output pins and may be verified. Programming thereforeis accomplished by placing data on the output pins,and writing it into the addressed location. Verification ofdata is accomplished by examining the information on theoutput pins during a READ operation.The timing for actual programming is supplied in theunique programming specification for each device.Phantom Operating ModesAll Cypress Programmable Logic Devices contain aPHANTOM ARRAY for the purposes of post assemblytesting. This array is accessed, programmed and operatedin a special PHANTOM mode of operation. In this mode,the normal array is disconnected from control of the logic,and in its place the PHANTOM ARRAY is connected. Innormal operation the PHANTOM ARRAY is disconnectedand control is only via the normal array. This specialfeature allows every device to be tested for both functionalityand performance after packaging and, if desired, by theuser before programming and use. The PHANTOM modesare entered through the use of supervoltages and areunique for each device or family of devices. See specificdata sheets for details.Special FeaturesCypress Programmable Logic devices, depending on thedevice, have several special features. For example the securitymechanism defeats the verify operation and thereforesecures the contents of the device against unauthorizedtampering or access. In advanced devices such as the PALC 22VlO, PLD C 20GlO, and the CY7C330 the MACRO­CELLs are programmable through the use of the architecturebits. This allows the user to more effectively tailor thedevice architecture to his unique system requirements.These features are also programmed though the use ofEPROM cells. Specific programming is detailed in the devicedata sheet.Programming SupportProgramming support for Cypress CMOS ProgrammableLogic Devices is available from a number of programmermanufacturers, some of which are listed as follows. Thehardware module version number listed is the earliest versionqualified by Cypress. Any subsequent version is alsoqualified unless otherwise specifically noted.Data 1/0 Corporation10525 Willows Rd. N.E.P.O. Box 97046Redmond, WA98073-9746(206) 881-6444Data 1/0 29BLOGICPAK V04GenericCypressPartPart NumberNumberPALC16R8 l6R8 [I] 28PALC16R6 l6R6 [1] 28PALC1 6R4 l6R4 [I] 28PALC16L8 l6L8 [I] 28PALC22VlO 22VlO 28PLDC20G10 20010 28PLDC20GIO 20R4 28PLDC20GlO 20R6 28PLDC20GlO 20R8 28PLDC20GlO 20L8 28PLDC20GlO 20LlO 28PLDC20GlO 20Ll 28PLDC20GlO l8L4 28PLDC20GlO l6L6 28PLDC2ool0 l4L8 28PLDC20GlO l2LlO 28Note:1. Requires Design Adapter 100.Data I/O Model60A, 60HCypressPart NumberPALC16R8PALC16R6PALC16R4PALC1 6L8PALC22V10PLDC2oolOFamilyCode andPinoutGenericPart Numberl6R8l6R6l6R4l6L822VlO20010Stag Microsystems1600 Wyatt Dr.Santa Clara, CA 95054(408) 988-1118STAG ZL32 Rev. 30A0324242417285665662726654321Adapters:PT Generic303A·009 303A·OUA/BRevision RevisionV03V03V03V03V04V04V04V04V04V04V04V04V04V04V04V04VOlVOlVOlVOlVOlVOlV02V02V02VOlVOlV02VOlVOlVOlVOlFamily Codeand PinoutRevision28 24 V0528 24 V0528 24 V0528 17 V0528 28 V0828 56 V08STAG PPZ Zm2200 Rev. 18ZL32 Rev. 30A03CypressGeneric Family CodePart Number Part Number and PinoutPALC16R8 l6R8PALC16R6 l6R6MenuPALC1 6R4 l6R4DrivenPALC16L8l6L8PALC22VlO 22VlOII4-93

~ PLD Programming Information (Continued)~~~U~====================~~==============================~====~==~Cypress Semiconductor Inc.3901 North First StreetSan Jose, CA 95134(408) 943-2600Cypress CY3000 QuickPro Rev. PLD 2.0CypressPart NumberPALC16R8PALC16R6PALC16R4PALC16L8PALC22V1OPLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0PLDC20GI0CY7C330Digelec Corporation1602 Lawrence Ave.Suite 113Ocean, NJ 07712(201) 493-2420GenericPart Number16R816R616R416L822V1O20G1O20R420R620R820L820L1O20L218U16L614L812L1O7C330Family Codeand PinoutMenuDrivenDIGELEC 803 FAM-S2 Rev. A-6.0Cypress Generic Family Code AdapterPart Number Part Number and Pinout Rev.A-3PALC16R8 16R8DA-53PALC16R6 16R6DA-53MenuPALC16R4 16R4DA-53DrivenPALC16L8 16L8DA-53PALC22V1O 22V1ODA-53Logical Devices Inc.1321 N.W. 65th PlaceFt. Lauderdale, FL 33309(305) 974-0975Logical Devices ALLPRO Rev. Vl.4Cypress Generic Family CodePart Number Part Number and PinoutPALC16R816R8PALC16R616R6MenuPALC16R416R4DrivenPALC16L816L8PALC22V1O22V1OKontron Electronics1230 Charleston RoadMountain View, CA94039-7230(415) 965-7020Kontron EPP 80 UPM·PCypressPart NumberPALC16R8PALC16R6PALC16R4PALC16L8PALC22VI0Development SoftwareABELTMData I/O Corporation10525 Willows Rd. N.E.P.O. Box 97046Redmond, WA98073-9746(206) 881-6444CUPLTMAssisted Technology1290 Parkmoor Ave.San Jose, CA 95126(800) 523-5207(800) 628-8748 CAGenericPart Number16R816R616R416L822V1OLOG/iCTMISDATAGmbHHaid-und-Neu-Strasse 7D-75oo Karlsruhe 1 West Germany(0721) 693092Family Codeand PinoutMenuDrivenSupported Devices:PALC16R8PALC16R6PALC16R4PALC16L8PALC22V1OPLDC20GI0CY7C330PALC16R8PALC16R6PALC16R4PALC16L8PALC22V1OPALC16R8PALC16R6PALC16R4PALC16L8PALC22V1OABELTM is a trademark of Data I/O Corporation.CUPLTM is a trademark of Assisted Technology.ISDAT A ® is a registered trademark of ISDATA GmbH.LOG/iCTM is a trademark ofISDATA GmbH.4-94

PRODUCTINFORMATIONSTATIC RAMSPROMSEPLDSLOGICRISCBRIDGEMOSQUICKPROQUALITY ANDRELIABILITYAPPLICATION BRIEFS•III••DJPACKAGES

LOGICDevice NumberCY2901CCY2909ACY2911ACY2910ACY3341CY7C401CY7C402CY7C403CY7C404CY7C408CY7C409CY7C420CY7C421CY7C424CY7C425CY7C428CY7C429CY7C51OCY7C516CY7C517CY7C901CY7C909CY7C911CY7C91OCY7C9101CY7C9116CY7C9117DescriptionPage NumberCMOS 4-Bit Slice ............................................................ 5-1CMOS Microprogram Sequencer ............................................... 5-9CMOS Microprogram Sequencer ............................................... 5-9CMOS Microprogram Controller .............................................. 5-1464 x 4 FIFO Serial Memory .................................................. 5-19Cascadeable 64 x 4 FIFO .................................................... 5-24Cascadeable 64 x 5 FIFO .................................................... 5-24Cascadeable 64 x 4 FIFO with Output Enable ................................... 5-24Cascadeable 64 x 5 FIFO with Output Enable ................................... 5-24Cascadeable 64 x 8 FIFO with Output Enable ................................... 5-34Cascadeable 64 x 9 FIFO .................................................... 5-34Cascadeable 512 x 9 FIFO ................................................... 5-48Cascadeable 512 x 9 FIFO ................................................... 5-48Cascadeable 1024 x 9 FIFO .................................................. 5-48Cascadeable 1024 x 9 FIFO .................................................. 5-48Cascadeable 2048 x 9 FIFO .................................................. 5-48Cascadeable 2048 x 9 FIFO .................................................. 5-4816 x 16 Multiplier Accumulator ............................................... 5-5916 x 16 Multiplier ........................................................... 5-7116 x 16 Multiplier ........................................................... 5-71CMOS 4-Bit Slice ........................................................... 5-83Microprogram Sequencer .................................................... 5-98Microprogram Sequencer .................................................... 5-98Microprogram Controller ................................................... 5-109CMOS 16-Bit Slice ......................................................... 5-120CMOS 16-Bit Microprogrammed ALU ........................................ 5-137CMOS 16-Bit Microprogrammed ALU ........................................ 5-137

Features• Pin compatible and functionalequivalent to AMD AM2901C• Low power• Vee margin- SV ±lO%- All parameters guaranteedover commercial and militaryoperating temperature range• Eight function ALUPerforms eight operations ontwo 4-bit operands• ExpandableInfinitely expandable in 4-bitincrements• Four status flagsCarry, overflow, negative, zeroLogic Block DiagramCYPRESSSEMICONDUCTOR• ESD protectionCapable of withstandinggreater than 2000V staticdischarge voltageFunctional DescriptionThe CY2901 is a high-speed, expandable,4-bit wide ALU that can be usedto implement the arithmetic section ofa CPU, peripheral controller, or programmablecontroller. The instructionset of the CY2901 is basic but yet soversatile that it can emulate the ALUof almost any digital computer.The CY2901, as illustrated in the blockdiagram, consists of a 16-word by 4-bitdual-port RAM register file, a 4-bitALU and the required data manipulationand control logic.CY2901CCMOS Four-Bit SliceThe operation performed is determinedby nine input control lines (10 to 18)that are usually inputs from an instructionregister.The CY2901 is expandable in 4-bit increments,has three-state data outputsas well as flag outputs, and can use eithera full-look ahead carry or a ripplecarry.The CY2901 is a pin compatible, functionalequivalent, improved performancereplacement for the AM2901.The CY2901 is fabricated using an advanced1.2 micron CMOS process thateliminates latchup, results in ESD protectionover 2000V and achieves superiorperformance at a low power dissipation.Pin ConfigurationTop ViewCLOCKOEV3A, V2'A'IREADIADDRESS'S'IREADIWRITEIADDRESS16 VoIsPOVRCn +4G10 CnCARRV IN12CPQ3DoSo 0,02S2 03S30007-2DATA OUT0007-1Selection Guide See last page for ordering information.Read Modify-Write Cycle (Min.) in ns Operating IcC (Max.) in mA Operating Range Part Number31 140 Commercial CY2901C32 180 Military CY2901C5-1

~ CY2901C~~~~================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 10 to Pin 30) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current into Outputs (Low) ............. 30 mAPin DefinitionsSignalName I/O10-lgDo-D:ICPDescriptionThese 4 address lines select one of the registers inthe stack and output its contents on the (internal)A port.These 4 address lines select one of the registers inthe stack and output is contents on the (internal)B port. This can also be the destination addresswhen data is written back into the register file.These 9 instruction lines select the ALU datasources (10, 1, 2), the operation to be performed(13.4. s) and what data is to be written into eitherthe Q register or the register file (16, 7, g).These are 4 data input lines that may be selectedby the 10,1, 2 lines as inputs to the ALU.These are three-state data output lines that, whenenabled, output either the output of the ALU orthe data in the A latches, as determined by thecode on the 16, 7, glines.Output Enable. This is an active LOW input thatcontrols the y 0-y 3 outputs. When this signal isLOW the Y outputs are enabled and when it isHIGH they are in the high impedance state.Clock Input. The LOW level ofthe clock writesdata to the 16 x 4 RAM. The HIGH level oftheclock writes data from the RAM to the A-portand B-port latches. The operation of the Qregister is similar. Data is entered into the masterlatch on the LOW level of the clock andtransferred from master to slave when the clock isHIGH.I/O These two lines are bidirectional and arecontrolled by the 16, 7, g inputs. Electrically theyare three-state output drivers connected to theTTL compatible CMOS inputs.Static Discharge Voltage ..................... > 2001 V(Per MIL-STD-883 Method 3015)Latchup Current (Outputs) .................. > 200 mAOperating RangeRangeAmbientTemperatureVeeCommercial O°Cto + 70°C 5V ±10%Military[!] - 55°C to + 125°C 5V ±10%Note:1. TA is the "instant on" case temperature.SignalName I/ODescriptionQ3 I/O Outputs: When the destination code on linesRAM3 16,7, g indicates a shift left (UP) operation the(Cont.) three-state outputs are enabled and the MSB ofthe Q register is output on the Q3 pin and theMSB of the ALU output (F3) is output on theRAM 3 pin.Inputs: When the destination code indicates ashift right (DOWN) the pins are the data inputsto the MSB of the Q register and the MSB of theRAM.Qo I/O These two lines are bidirectional and function in aRAMo manner similar to the Q3 and RAM3 lines, exceptthat they are the LSB of the Q register and RAM.en I The carry-in to the internal ALU.C n +4 0 The carry-out from the internal ALU.G, P 0 The carry generate and the carry propagateoutputs of the ALU, which may be used toperform a carry look-ahead operation over the 4bits of the ALU.OVR 0 Overflow. This signal is logically the exclusive­OR of the carry-in and the carry-out of the MSBof the ALU. This pin indicates that the result ofthe ALU operation has exceeded the capacity ofthe machine. It is valid only for the sign bit andassumes two's complement coding for negativenumbers.F = 0 0 Open collector output that goes HIGH if the dataon the ALU outputs (Fa, 1,2, 3) are all LOW. Itindicates that the result of an ALU operation iszero (positive logic).F3 0 The most significant bit of the ALU output.5-2

~ CY2901C~~~~==============================================================Electrical Characteristics Over Commercial and Military Operating Range[3]V cc Min. = 4.5V, V cc Max. = 5.5VParameters Description Test Conditions Min. Max. UnitsVOHOutput HIGH VoltageVee = Min.IOH = -3.4mA2.4 VVee = Min.VOL Output LOW Voltage IOL = 20 rnA Commercial 0.4 VIOL = 16 rnA MilitaryVIH Input HIGH Voltage 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 VIIHIlLIOHIOLlozInput HIGH CurrentInput LOW CurrentOutput HIGH CurrentOutput LOW CurrentOutput Leakage CurrentVee = Max.VIN = VeeVee = Max.VIN = GND10 p.A-10 p.AVee = Min.-3.4 rnAVOH = 2.4VVee = Min. I Commercial 20 rnAVOL = O.4VMilitary 16 rnAIVee = Max. +40 p.AVOUT = GND to Vee -40 p.AVee = Max.IseOutput Short Circuit Current[l]-30 -85 rnAVOUT = OVlee Supply Current Vee = Max. I Commercial 140 rnAMilitary 180 rnACapacitance [2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f= 1 MHz 5pFCoUTOutput CapacitanceVee = 5.0V7Notes:1. Not more than one output should be tested at a time. Duration of the 3. See the last page of this specification for Group A subgroup testingshort circuit should not be more than one second.information.2. Tested initially and after any design or process changes that mayaffect these parameters.Output Loads used for AC Performance Characteristics0007-3All outputs except open drainNotes:1. CL = 50 pF includes scope probe, wiring and stray capacitance.2. CL = 5 pF for output disable tests.3. Loads shown above are for commercial (20 rnA) IOL specificationsonly.CommercialMilitaryRl 203.0. 252.0.R2 148.0. 174.0.5-3J+5 Vvo~VOllCLJOpen drain (F = 0)0007-4

CP:- .~t-~ CY2901C~~~U~================================================================CY2901C Guaranteed CommercialRange AC Performance CharacteristicsThe tables below specify the guaranteed AC performanceof these devices over the Commercial (O°C to 70°C) operatingtemperature range with V cc varying from 4.5V to5.5V. All times are in nanoseconds and are measured betweenthe 1.5V signal levels. The inputs switch between OVand 3V with signal transition rates of 1 V per nanosecond.All outputs have maximum DC current loads. See previouspage for loading circuit information.This data applies to parts with the following numbers:CY2901CPC CY2901CDC CY2901CLCCycle Time and Clock CharacteristicsCY2901-Read-Modify-Write Cycle (fromselection of A, B registers toend of cycle).Maximum Clock Frequency to shift Q(50% duty cycle, I = 432 or 632)Minimum Clock LOW TimeMinimum Clock HIGH TimeMinimum Clock PeriodFor faster performance see CY7C901-23 specification.C31 ns32 MHz15 ns15 ns31 nsCombinational Propagation Delays. CL = 50 pFTo OutputFrom InputY F3 C n + 4A, BAddress 40 40 40D 30 30 30C n 22 22 201012 35 35 351345 35 35 351678 25 - -ABypassALU(I = 2XX)35 - -Clock....tr 35 35 35G,P F=O OVR RAMoRAM3QoQ337 40 40 40 -30 38 30 30 -- 25 22 25 -37 37 35 35 -35 38 35 35 -- - - 26 26- - - - -35 35 35 35 28Set-up and Hold Times Relative to Clock (CP) InputInputSet-upTime Hold Time Set-upTime Hold TimeBefore H --+ L AfterH --+ L Before L --+ H After L --+ HA, B Source Address15 1 30,15 + tPWL(Note 3) (Note 4)1B Destination Address 15 +- Do Not Change --+ 1D - - 25 0C n - - 20 01012 - - 30 01345 - - 30 01678 10 +- Do Not Change --+ 0RAMo, 3,Qo, 3 - - 12 0Output Enable/Disable TimesOutput disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage level.Notes:1. A dash indicates a propagation delay path or set-up time constraintdoes not exist.2. Certain signals must be stable during the entire clock LOW time toavoid erroneous operation. This is indicated by the phrase "do notchange".3. Source addresses must be stable prior to the clock H ---. L transitionto allow time to access the source data before the latches close. The Aaddress may then be changed. The B address could be changed if it isnot a destination; i.e. if data is not being written back into the RAM.Normally A and B are not changed during the clock LOW time.4. The set-up time prior to the clock L ---. H transition is to allow timefor data to be accessed, passed through the ALU, and returned to theRAM. It includes all the time from stable A and B addresses to theclock L ---. H transition, regardless of when the clock H ---. Ltransition occurs.5-4

~ CY2901C~~~U~==============================================================CY2901C Guaranteed MilitaryRange AC Performance CharacteristicsThe tables below specify the guaranteed AC performanceof these devices over the Military ( - 55°C to + 125°C) operatingtemperature range with V cc varying from 4.5V to5.5V. All times are in nanoseconds and are measured betweenthe 1.5V signal levels. The inputs switch between OVand 3V with signal transition rates of 1 V per nanosecond.All outputs have maximum DC current loads. See "ElectricalCharacteristics" of this data sheet for loading circuitinformation.This data applies to parts with the following numbers:CY2901CDMBCycle Time and Clock Characteristics [5]CY2901-Read-Modify-Write Cycle (fromselection of A, B registers toend of cycle).Maximum Clock Frequency to shift Q(50% duty cycle, I = 432 or 632)Minimum Clock LOW TimeMinimum Clock HIGH TimeMinimum Clock PeriodFor faster performance see CY7C901-27 specification.C32ns31 MHz15 ns15 ns32 nsCombinational Propagation Delays CL = 50 pp[5]To OutputFrom InputY F3 Co + 4A, B Address 48 48 48D 37 37 37Cn 25 25 211012 40 40 401345 40 40 401678 29 - -A Bypass ALU(I = 2XX)40 - -Clock~ 40 40 40G,P F=O OVR RAMo QoRAM3 Q344 48 48 48 -34 40 37 37 -- 28 25 28 -44 44 40 40 -40 40 40 40 -- - - 29 29- - - - -40 40 40 40 33Set-up and Hold Times Relative to Clock (CP) Input[5]CP:-------I.-~InputSet-upTime Hold Time Set-upTime Hold TimeBeforeH .... L AfterH .... L BeforeL .... H AfterL .... HA, B Source Address 15 2 30,15 + tpWL 2(Note 3) (Note 4)B Destination Address 15 ~ Do Not Change .... 2D - - 25 0Cn - - 20 01012 - - 30 01345 - - 30 01678 10 ~ Do Not Change .... 0RAMo, 3,Qo, 3 - - 12 0Output EnablelDisable Times [5]Output disable tests performed with CL = 5 pP and measured to 0.5V change of output voltage level.Notes:1. A dash indicates a propagation delay path or set-up time constraintdoes not exist.2. Certain signals must be stable during the entire clock LOW time toavoid erroneous operation. This is indicated by the phrase "do notchange".3. Source addresses must be stable prior to the clock H -+ L transitionto allow time to access the source data before the latches close. The Aaddress may then be changed. The B address could be changed if it isnot a destination; i.e. if data is not being written back into the RAM.Normally A and B are not changed during the clock LOW time.4. The set-up time prior to the clock L -+ H transition is to allow timefor data to be accessed, passed through the ALU, and returned to theRAM. It includes all the time from stable A and B addresses to theclock L -+ H transition, regardless of when the clock H -+ Ltransition occurs.5. See the last page of this specification for Group A subgroup testinginformation.5-5

Ordering InformationReadModify-Package OperatingOrdering CodeWrite Type RangeCycle (ns)31 CY2901 CPC P17 Commercial31 CY2901CDC 018 Commercial32 CY2901 CDMB 018 Military5-6

MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIH 1,2,3IlL 1,2,3IOH 1,2,3IOL 1,2,3Ioz 1,2,3IsC 1,2,3Icc 1,2,3SubgroupsCycle Time and Clock CharacteristicsParametersSubgroupsMinimum Clock LOW Time 1,8,9,10,11Minimum Clock HIGH Time 1,8,9,10,11Combinational Propagation DelaysParametersSubgroupsFrom A, B Address to Y 1,8,9,10,11From A, B Address to F3 1,8,9,10,11From A, B Address to C n + 4 1,8,9,10,11From A, B Address to G, P 1,8,9,10,11From A, B Address to F = ° 1,8,9,10,11From A, B Address to OVR 1,8,9,10,11From A, B Address to RAMo, 3 1,8,9,10,11FromDtoY 1,8,9,10,11FromDtoF3 1,8,9,10,11From D to C n + 4 1,8,9,10,11From DtoG, P 1,8,9,10,11FromDtoF = ° 1,8,9,10,11FromDtoOVR 1,8,9,10,11From D to RAMo, 3 1,8,9,10,11Combinational Propagation Delays (Continued)ParametersSubgroupsFromCn toY 1,8,9,10,11FromC n toF3 1,8,9,10,11From C n to C n + 4 1,8,9,10,11From Cn to F = ° 1,8,9,10,11From Cn to OVR 1,8,9,10,11From C n to RAMo, 3 1,8,9,10,11From 1012 to Y 1,8,9,10,11From 1012 to F3 1,8,9,10,11From 1012 to Cn + 4 1,8,9,10,11From 1012 to G, P 1,8,9,10,11From 1012 to F = ° 1,8,9,10,11From 1012 to OVR 1,8,9,10,11From 1012 to RAMo, 3 1,8,9,10,11From 1345 to Y 1,8,9,10,11From 1345 to F3 1,8,9,10,11From 1345 to Cn + 4 1,8,9,10,11From 1345 to G, P 1,8,9,10,11From 1J45 to F = ° 1,8,9,10,11From 1345 to OVR 1,8,9,10,11From 1345 to RAMo, 3 1,8,9,10,11From 1678 to Y 1,8,9,10,11From 1678 to RAMo, 3 1,8,9,10,11From 1678 to Qo, 3 1,8,9,10,11From A Bypass ALU to Y 1,8,9,10,11(I = 2XX)From Clock -' to Y 1,8,9,10,11From Clock -' to F3 1,8,9,10,11From Clock -' to C n + 4 1,8,9,10,11From Clock -' to G, P 1,8,9,10,11From Clock -' to F = ° 1,8,9,10,11From Clock -' to OVR 1,8,9,10,11From Clock -' to RAMo, 3 1,8,9,10,11From Clock -' to Qo, 3 1,8,9,10,115-7

~ CY2901C~~~~~================================~~~==~~~~~~~~==Set-up and Hold Times Relative to Clock (CP) InputParameters Subgroups Parameters SubgroupsA, B Source Address " 7,8,9,10,11 D Hold Time After L -+ H 7,8,9,10,11Set-up Time"Before H -+ LC n Set-up Time Before L -+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11C n Hold Time After L -+ H 7,8,9,10,11Hold Time After H -+ L1012 Set-up Time Before L -+ H 7,8,9,10,11A, J3 Source Address 7,8,9,10,11Set-up Time Before L -+ H 1012 Hold Time After L -+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11 1345 Set-up Time Before L -+ H 7,8,9,10,11Hold Time After L -+ H 1345 Hold Time After L -+ H 7,8,9,10,11B Destination Address 7,8,9,10,11 1678 Set-up Time Before H -+ L 7,8,9,10,11Set-up Time Before H -+ L1678 Hold Time After H -+ L 7,8,9,10,11B Destination Address 7,8,9,10,11Hold Time After H -+ L1678 Set-up Time Before L -+ H 7,8,9,10,11B Destination Address 7,8,9,10,111678 Hold Time After L -+ H 7,8,9,10,11Set-up Time Before L -+ H RAMo, RAM3, Qo, Q3 7,8,9,10,11B Destination Address 7,8,9,10,11Set-up Time Before L -+ HHold Time After L -+ H RAMo, RAM3, Qo, Q3 7,8,9,10,11D Set-up Time Before L -+ H 7,8,9,10,11Hold Time After L -+ HDocument #: 38-00008-B!5-8

CYPRESSSEMICONDUCTORCY2909ACY2911ACMOS Micro ProgramSequencersFeatures• Fast- CY2909A/llA has a 40 ns(min.) clock to output cycletime; commercial- CY2909/11 has a 40 ns(min.) clock to output cycletime; military• Low power- Icc (max.) = 70 mAcommercial- ICC (max.) = 90 mAmilitary• Vee margin- 5V ±10%- All parameters guaranteedover commercial and militaryoperating temperature range• ExpandableInfinitely expandable in 4-bitincrements• ESD protectionCapable of withstanding greaterthan 2000V static dischargevoltage• Pin compatible andfunctional equivalent toAMD AM2909A/ AM2911ADescriptionThe CY2909 A and CY2911 A are highspeed,four-bit wide address sequencersintended for controlling the sequenceof execution of microinstructions containedin microprogram memory. Theymay be connected in parallel to expandthe address width in 4 bit increments.Both devices are implemented in highperformance CMOS for optimumspeed and power.The CY2909A can select an addressfrom any of four sources. They are:1) a set of four external direct inputs(Dj); 2) external data stored in an internalregister (Ri); 3) a four word deeppush/pop stack; or 4) a program counterregister (which usually contains thelast address plus one). The push/popstack includes control lines so that itcan efficiently execute nested subroutinelinkages. Each of the four outputs(Yi) can be OR'ed with an external inputfor conditional skip or branch instructions.A ZERO input line forcesthe outputs to all zeros. The outputsare three state, controlled by theOutput Enable (OE) input.The CY2911A is an identical circuit tothe CY2909A, except the four OR inputsare removed 'and the D and R inputsare tied together. The CY2911A isavailable in a 20-pin, 300-mil package.The CY2909 is available in a 28-pin,600-mil package.Logic Block DiagramPin ConfigurationsREGISTERENABLE ,RE) :o AND R 'CONNECTED } 4ON 2~~~~ ,DIRECTINPUTSR (2909A ONLY)1,------t4i,,0>----4-+-.So>---"S1>---+IFILEENABLECLOCKRER3R2R1RoOR 30 3OR 2O 2OR 10 1ORoDoGNDVeeCPPUPFECn+4C n6E:Y 3Y 2Y 1Yo51SoZEROCPPUPVCCFERE C n+ 40 3 C nO 2Of0 , Y 300 Y 2GNDY IZEROYoSo S,0066-30066-2 D..ar ~orl~;}'~ ~I~ D..>u ~ ~I~OUTPUTENABLEOfen ...0066-1ROOR 3 603 7OR 2°2OR 1°1o 0010 0_ 0o::ozo::cncn>oc) ...NFE24 Cn+423 C n22 Or21 Y 320 Y 2Y 10066-40 3 C n+4O 2C n0 1 6EDo Y 3GNO 8 Y 210 [5cncn>->- 0 - 0 -N0066-55-9

finCY2909A. CY2911A~~~~~~~~~~~~~~~~~~================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage .................. '" >2001VAmbient Temperature with(per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-Up Current ......................... > 200 rnASupply Voltage to Ground Potential .... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VDC Input Voltage ................... -3.0V to +7.0VOutput Current, into Outputs (Low) ............. 30 mAElectrical Characteristics Over Operating Range[4]Operating RangeRangeAmbientTemperatureVeeCommercial O"Cto +70"C 5V ±1O%Military!3] - 55°C to + 125°C 5V ±1O%Parameters Description Test Conditions Min. Max. UnitsVOHOutput HIGH VoltageVee = Min.,IOH = -2.6 mA (Cornm.) 2.4 VVee = Min., IOH = - 1.0 mA (Mil.) 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 16.0 rnA 0.4 VVIH Input High Voltage 2.0 Vee VVIL Input Low Voltage -2.0 0.8 VIIX Input Load Current GND::;;: VI::;;: Vee -10 +10 ,..,AOutput LeakageGND::;;: Vo::;;: VeeIOZ-20 +20 ,..,ACurrentOutput DisabledlosIccCapacitance [2]Output ShortCircuit Current!l]Vee = Max. VOUT = GND -30 -85 rnAVee Operating Vee = Max. I Commercial 70 rnASupply Current lOUT = OmAI Military 90Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = I MHz 5pFCoUTOutput CapacitanceVee = 5.0V 7Notes:1. Not more than 1 output should be shorted at one time. Duration of3. T A is the "instant on" case temperature.the short circuit should not exceed 30 seconds.4. See the last page of this specification for Group A subgroup testing2. Tested initially and after any design or process changes that mayinformation.affect these parameters.AC Test Loads and WaveformsnR15VOUTPUT50pfR2INCLUDING I _JIG AND - -SCOPEFigure laCommercialnR15VOUTPUT5pfINCLUDING IJIG AND - -SCOPEFigure IbMilitaryRl 2540 2580R2 1870 2160_R20066-63.0V ---~!!'""----~GND5ns-10066-7Figure 25-10

WnCY2909A. CY2911A~~UcrOR====================================~~~~~========~==========Switching Characteristics Over Operating Range[4]2909A2911ACommercial2909A2911AMilitaryMinimum Clock Low Time 20 20 nsMinimum Clock High Time 20 20 nsMAXIMUM COMBINATIONAL PROPAGATION DELAYSFrom Input To: Y CN + 4 Y CN + 4 nsDi 17 n 20 25 nsSO, SI 29 34 29 34 nsORi CY2909A 17 22 20 25 nsCN - 14 - 16 nsZERO 29 34 30 35 nsOE Low to Output 25 - 25 - nsOE High to High Z[5] 25 - 25 - nsClock High, So, SI = LH 39 44 45 50 nsClock High, So, SI = LL 39 44 45 50 nsClock High, So, SI = HL 44 49 53 58 nsMINIMUM SET-UP AND HOLD TIMES (All Times Relative to Clock LOW to HIGH Transition)From Input Set-up Hold Set-up HoldRE 19 4 19 5 nsRi[6] 10 4 12 5 nsPush/Pop 25 4 27 5 nsFE 25 4 27 5 nsCN 18 4 18 5 nsDi 25 0 25 0 nsORi (CY2909A) 25 0 25 0 nsSo, SI 25 0 29 0 nsZERO 25 0 29 0 nsNotes:5. Output Loading as in Figure 1 h. 6. Rj and Dj are internally connected on the CY2911A. Use Rj set-upand hold times for Dj inputs.Switching Waveforms-MIN CLOCK LOWUnitsCLOCKINPUT(EXCEPT DE)~INPUT TO OUTPUTl~----CLOCK TO OUTPUT --HOLD----.1 TIMES--(Y. ~~T:~)XXXXXXXXXXXXXXXXX :::::::::::::0066-85-11

(;nCY2909A. CY2911A~============================================================~Ordering InformationOrdering CodePackageTypeOperatingRangeOrdering CodePackageTypeOperatingRangeCY2909APC P15 Commercial CY2911APC P5 CommercialCY2909ADC D16 CY2911ADC D6CY2909ALC L64 CY2911ALC L61CY2909ADMB D16 Military CY2911ADMB D6 MilitaryCY2909ALMB L64 CY2911ALMB L615-12

5nCY2909A. CY2911A~~UcrOR==================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIR 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3los 1,2,3IcC 1,2,3Switching CharacteristicsParametersSubgroupsMinimum Clock Low Time 7,8,9,10,11Minimum Clock High Time 7,8,9,10,11MAXIMUM COMBINATIONALPROPAGATION DELAYSOjtoY 7,8,9,10,11OJ to CN+4 7,8,9,10,11So, S1 to Y 7,8,9,10,11So, S1 to CN +4 7,8,9,10,11ORj (CY2909A) to Y 7,8,9,10,11ORj (CY2909A) to CN +4 7,8,9,10,11CN toCN+4 7,8,9,10,11ZEROtoCN+4 7,8,9,10,11Clock High, So, S1 = LH 7,8,9,10,11toYClock High, So, S 1 = LH 7,8,9,10,11to CN+4Clock High, So, S1 = LL 7,8,9,10,11toYClock High, So, S1 = LL 7,8,9,10,11to CN+4Clock High, So, S1 = HL 7,8,9,10,11toYClock High, So, S1 = HL 7,8,9,10,11toCN + 4Document #: 38-00009-BParametersMINIMUM SET-UPAND HOLD TIMESSubgroupsRE Set-up Time 7,8,9,10,11RE Hold Time 7,8,9,10,11Push/Pop Set-up Time 7,8,9,10,11Push/Pop Hold Time 7,8,9,10,11FE Set-up Time 7,8,9,10,11FE Hold Time 7,8,9,10,11CN Set-up Time 7,8,9,10,11CNHold Time 7,8,9,10,11OJ Set-up Time 7,8,9,10,11OJ Hold Time 7,8,9,10,11ORj (CY2909A) 7,8,9,10,11Set-up TimeORj (CY2909A) 7,8,9,10,11Hold TimeSo, S1 Set-up Time 7,8,9,10,11So, S1 Hold Time 7,8,9,10,11ZERO Set-up Time 7,8,9,10,11ZERO Hold Time 7,8,9,10,115-13

Features• Fast- CY2910AC has a 50 ns (min.)clock cycle; commercial- CY2910AM has a 51 ns(min.) clock cycle; military• Low power- Icc (max.) = 170 mA• Vee Margin 5V ± 10%commercial and military• Sixteen powerfulmicroinstructions• Three output enable controls forthree-way branch• Twelve-bit address word• Four sources for addresses:microprogram counter (MPC),branch address bus, 9-wordstack, internal holding register• Internal 9-word by 12-bit stackThe internal stack can be usedfor subroutine return address ordata storageCYPRESSSEMICONDUCTOR• 12-bit Internal loop counter• ESD protectionCapable of withstanding over2000 volts static dischargevoltage• Pin compatible and functionalequivalent to Am2910AFunctional DescriptionThe CY29 lOA is a stand-alone microprogramcontroller that selects, stores,retrieves, manipulates and tests addressesthat control the sequence of executionof instructions stored in an externalmemory. All addresses are 12-bitbinary values that designate an absolutememory location.The CY291OA, as illustrated in theblock diagram, consists of a 9-word by12-bit LIFO (Last-In-First-Out) stackand SP (Stack Pointer), a 12-bit RC(Register/Counter), a 12-bit MPC (MicroprogramCounter) and incrementer,a 12-bit wide by 4-input multiplexerCY2910ACMOS MicroprogramControllerand the required data manipUlationand control logic.The operation performed is determinedby four input instruction lines (10-13)that in tum select the (internal) sourceof the next micro-instruction to befetched. This address is output on theYO-Yll pins. Two additional inputs(CC and CCEN) are provided that areexamined during certain instructionsand enable the user to make the executionof the instruction either unconditionalor dependent upon an externaltest.The CY29 lOA is a pin compatible,functional equivalent, improved performancereplacement for theAm29 lOA.The CY29 lOA is fabricated using anadvanced 1.2 micron CMOS processthat eliminates latch up, results in ESDprotection of over 2000 volts andachieves superior performance and lowpower dissipation.Logic Block DiagramPin ConfigurationY 40 30 4Y 3Y 5O 20 5Y 2VECT 0 1~Pl Y 1MAPDO13 Yo12 CIVCCCP11 GNO10 OECCEN Y 11cc 011RLD Y 10fUll 0 10OsYgY sOg0 7Y aY 7 °a0040-2Top View0040'-3Selection GuideQock Cycle (Min.) in ns5051Stack Deptb Operating Range Part Number9 words Commercial CY2910AC9 words Military CY2910AM5-14

~ CY2910A~~~U~==================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... > 2001VAmbient Temperature with (Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latchup Current (Outputs).................. > 200 mASupply Voltage to Ground Potential(Pin 10 to Pin 30) .................... -O.SV to + 7.0VOperating RangeDC Voltage Applied to OutputsAmbientRangein High Z State ...................... -0.5V to + 7.0VTemperatureVeeDC Input Voltage ................... - 3.0V to + 7.0VCommercialOOC to +700C 5V ±10%Output Current into Outputs (Low) ............. 30 mA Military [3] - 55°C to + 125°C 5V ±10%Electrical Characteristics Over Commercial and Military Operating Range[4]V CC Min. = 4.SV, V CC Max. = 5.5VParameter Description Test ConditionVOH Output HIGH Voltage Vee = Min., lOR = -1.6rnAVOL Output LOW Voltage Vee = Min.,loL = 8 rnAVIHVILInput HIGH VoltageInput LOW VoltageIIH Input HIGH Current Vee = Max., VIN = VeeIlL Input LOW Current Vee = Max., VIN = GNDlOR Output HIGH Current Vee = Min., VIR = 2.4VIOL Output LOW Current Vee = Min., VOL = O.SVlozOutput Leakage CurrentVee = Max.,VOUT = GNDlVeeIse Output Short Circuit Current Vee = Max., VOUT = OVlee Supply Current Vee = Max.Min. Max.2.4O.S2.0 Vee-3.0 0.810-10-1.68+40-40-85170UnitsVVVVJJ-AJJ-ArnArnAJJ-AJJ-ArnArnACapacitance [2]Parameters Description Test ConditionsCIN Input Capacitance TA = 25°C, f = 1 MHzCoUT Output Capacitance Vee = 5.0VNotes:1. Not more than one output should be tested at a time. Duration of theshort circuit should not exceed one second.2. Tested initially and after any design or process changes that mayaffect these parameters.Output Load for AC PerformanceCharacteristics~~'All Outputs+5 Vi=ic ,0040-4Notes:CL = 50 pF includes scope probe, writing and stray capacitance.eL = 5 pF for output disable tests.Max.3. TA is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.Switching Waveforms810UnitspFpF3.0V---------"'I,-----"""'"',I,---INPUTS~---------~I'---------J'I~---3.0VCLOCKOV_________________ JI~ __________OUTPUTS0040-55-15

Guaranteed AC Performance CharacteristicsThe tables below specify the guaranteed AC performanceof the CY2910A over the commercial (O°C to + 70°C) andthe military (-55°C to + 125°C) temperature ranges withVec varying from 4.5V to 5.5V. All times are in nanosecondsand are measured between the 1.5V signal levels.Clock Requirements [1, 4]Minimum Clock LOWMinimum Clock HIGHMinimum Clock Period I = 14Minimum Clock PeriodI = 8,9, 15 (Note 2)Combinational Propagation Delays. CL = 50 pp[4]To OutputCommercialFrom Input Y PI:, VEer, MApDO-Dll 20 -IO-I3 35 30CC 30 -CCEN 30 -CPI = 8,9, 15 40 -(Note 2)CPAll Other I40OE 25(Note 3) 27--The inputs switch between OV and 3V with signal transitionrates of 1 Volt per nanosecond. All outputs havemaximum DC current loads.CommercialMilitary20 2520 2550 51SOMilitarySOFULL Y PL, VEC'f, MAp FUll- 25 - -- 40 35 -- 36 - -- 36 - -31 - - 3531 46 - 3525- - -30Minimum Set-up and Hold Times Relative to clock LOW to HIGH Transition. CL = 50 pp[4]InputSet-upDI -+ RC 16DI -+ MPC 30IO-I3 35CC 24CCEN 24CI 18RLD 19CommercialNotes:l. A dash indicates that a propagation delay path or set-up time does notexist.2. These instructions are dependent upon the register/counter. Use theshorter delay times if the previous instruction either does riot changethe register/counter or could only decrement it. Use the longer delayif the instruction prior to the clock was 4 or 12 or if'RLD was LOW.MilitaryHold Set-up Hold0 16 00 30 00 38 00 35 00 35 00 18 00 20 03. The enable/disable times are measured to a 0.5 Volt change on theoutput voltage level with CL = 5 pF.4. See the last page of this specification for Group A subgroup testinginformation.5-16

~ CY2910A~~~~~==================================================================Table of InstructionsREG/RESULTCNTR FAIL PASS13-10 MNEMONIC NAMECON- CCEN = LandCC = H CCEN = HorCC = L REG/TENTS CNTRY STACK Y STACKENABLE0 JZ Jump Zero X 0 Clear 0 Clear Hold PL1 CJS CondJSBPL X PC Hold D Push Hold PL2 JMAP Jump Map X D Hold D Hold Hold Map3 CJP CondJumpPL X PC Hold D Hold Hold PL4 PUSH Push/Cond LD CNTR X PC Push PC Push (Note 1) PL5 JSRP Cond JSB R/PL X R Push D Push Hold PL6 CJV Cond Jump Vector X PC Hold D Hold Hold Vect7 JRP Cond Jump R/PL X R Hold D Hold Hold PL8 RFCTRepeat Loop, *0 F Hold F Hold Dec PLCNTR*O =0 PC POP PC Pop Hold PL9 RPCTRepeatPL, *0 D Hold D Hold Dec PLCNTR* 0 =0 PC Hold PC Hold Hold PL10 CRTN CondRTN X PC Hold F Pop Hold PL11 CJPP Cond Jump PL & Pop X PC Hold D Pop Hold PL12 LDCT LD Cntr & Continue X PC Hold PC Hold Load PL13 LOOP Test End Loop X F Hold PC Pop Hold PL14 CONT Continue X PC Hold PC Hold Hold PL15 TWB Three-Way Branch*0 F Hold PC Pop Dec PL=0 D Pop PC Pop Hold PLNotes:1. If CCEN = Land CC = H, hold; else load. H = HIGH L= LOW x = Don't CareOrdering InformationOockPackage OperatingCycle Ordering CodeType Range(ns)50 CY2910ADC D18 CommercialCY2910AJC J67CY2910ALC L67CY2910APC P1751 CY2910ADMB D18 MilitaryCY2910ALMB L675-17

~ CY2910A~~~UQDR================================================================~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIH 1,2,3IlL 1,2,3IOH 1,2,3SubgroupsIOL 1,2,3loz 1,2,3Isc 1,2,3Icc 1,2,3Clock RequirementsParametersSubgroupsMinimum Clock LOW 7,8,9,10,11Minimum Set-u, aM Hold TimesParametersSubgroupsDI ~ RC Set-up Time7,~,9,1O,11DI ~ RC Hold Time 7,8,9,10,11DI ~ MPC Set-up Time 7,8,9,10,1101 ~ MPCHo1dTime 7,8,9,10,1110-13 Set-up Time 7,8,9,10,1110-13 Hold Tinie 7,8,9, io, 11CC Set-up Time 7,8,9,10,11CCHoldTime 7,8,9,10,11CCEN Set-up Time 7,8,9,10,11CCEN Hold Time 7,8,9,10,11CI Set-up Time 7,8,9,10,11CIHold Time 7,8,9,10,11RLD Set-up Time 7,8,9,10,11RLD Hold Time 7,8,9,10,11Combinational Propagation DelaysParametersSubgroupsFrom DO-Dll to Y 7,8,9,10,11From 10-13 to Y 7,8,9,10,11From 10-13 to PL, VECT, MAP 7,8,9,10,11FromCCtoY 7,8,9,10,11From CCEN to Y 7,8,9,10,11From CP (I = 8,9,15) to FULL 7,8,9,10,11From CP (All Other I) to Y 7,8,9,10,11From CP (All Other I) to FULL 7,8,9,10,11Document #: 38-0001O-B5-18

Features• 1.2/2 MHz data rate• Fully TIL compatible• Independent asynchronous inputsand outputs• Direct replacement for PMOS3341• Expandable in word length antiwidth• CMOS for optimum speed/power• Capable of withstanding greaterthan 2000V electrostaticdischargeFunctional DescriptionThe 3341 is a 64-word x 4-bit First-InFirst-Out (FIFO) Serial Memory. Theinputs and outputs are completely independent(no common clocks) makingthe 3341 ideal for asynchronous bufferapplications.Control signals are provided for bothvertical and horizontal expansion.The 3341 is manufactured using CypressCMOS technology and is availablein both ceramic and plastic packages.CYPRESSSEMICONDUCTORData InputThe four bits of data on the Do throughD3 inputs are entered into the first locationwhen both Input Ready (IR)and Shift In (SI) are HIGH. This causesIR to go LOW but data will staylocked in the first bit location untilboth IR and SI are LOW. Then datawill propagate to the second bit location,provided the location is empty.When data is transferred, IR will goHIGH indicating that the device isready to accept new data. If the memoryis full, IR will stay LOW.Data TransferOnce data is entered into the secondcell, the transfer of any full cell to theadjacent (downstream) empty cell isautomatic, activated by an on-chip control.Thus, data will stack up at the endof the device while empty locations will"bubble" to the front. tBT defines thetime r~ql1ired for the first data to travelfrom theillput to the output of a previouslyempty device, or for the firstempty space to travel from the outputto the input of a previously full device.Data OutputWhen data has been transferred intothe last cell, Output Ready (OR) goesCY334164 x 4 FIFO Serial MemoryHIGH, indicating the presence of validdata at the output pins Qo through Q3.The transfer of data is initiated whenboth the Output Ready output fromthe device and the Shift Out (SO) inputto the device are HIGH. This causesOR to go LOW; output data, however,is maintained until both OR and SOare LOW. Then the content of the adjacent(upstream) cell (provided it is full)will be transferred into the last cell,causing OR to go HIGH again. If thememory has been emptied, OR willstay LOW.Input Ready and Output Ready mayalso be used as status signals indicatingthat the FIFO is completely full (InputReady stays LOW for at least tBT) orcompletely empty (Output Ready staysLOW for at least tBT).ResetWhen Master Reset (MR) goes LOW,the control logic is cleared, and thedata outputs enter a LOW state. WhenMR returns HIGH, Output Ready(OR) stays LOW, and Input Ready(IR) goes HIGH if Shift In (SI) wasLOW.IILogic Block DiagramPin Configuration81IRWRITE POINTERWRITE MULTIPLEXER000,020380ORVGG*VssIR 8081 ORDOCo0, 0,O 2 020 3 03VooMR-Internally not connected0004-20004-1Selection GuideMaximum Operating FrequencyMaximum OperatingCurrent (rnA)CommercialMilitary5-193341 3341-21.2 MHz 2.0 MHz45 4560 60

Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 16 to Pin 8) ..................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VStatic Discharge Voltage ..................... > 2oo1V(per MIL-STD-883 Method 3015)Latchup Current .......................... > 200 rnAOperating RangeRangeAmbientTemperatureVSS VDD VGG*DC Input Voltage ................... - 3.0V to + 7.0V Commercial O°Cto + 70°C 5V ±1O% GND NCOutput Current, into Outputs (Low) ............. 20 rnA Militaryl3] - 55°C to + 125°C 5V ± 10% GND NCElectrical Characteristics Over the Operating Rangel4]*Internally Not Connected.Parameters Description Test Conditions Min. Max. UnitsVOH Output HIGH Voltage Vss = Min.,IOH = -0.3 rnA 2.4 VVOL Output LOW Voltage VSS = Min.,IOL = 1.6 rnA 0.4 VVIR Input HIGH Voltage 2.0 VSS VVIL Input LOW Voltage -3.0 0.8 VIIX Input Leakage Current VDD S VI S Vss -10 +10 p,AlOSOutput ShortCircuit Current[l]Vss = Max., VOUT = VDD -90 rnAVss = Max.,IDDPower Supply CurrentI Commercial 45 rnAlOUT = OmAI Military 60IGG VGGCurrent 0 rnACapacitance [2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 7COUT Output Capacitance Vss = 5.0V 10Notes:1. Not more than 1 output should be shorted at one time. Duration ofthe short circuit should not exceed 30 seconds.2. Tested initially and after any design or process changes that mayaffect these parameters.AC Test Loads and WaveformsR12.42 Kf!5V~------~~~,3. TA is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.ALL INPUT PULSES3.0V-----.z~---~lpFOUTPUT ~---.-------t130 pF ~.~8 KHINCLUDINGJIG AND":.- SCOPE ":.-Equivalent to:THEVENIN EQUIVALENT0004-3GND10 ns 10 ns0004-51.05 Kf!OUTPUT ~ 2.08 V0004-45-20

~ CY3341~~~UcrOR ==================================================================~Switching Characteristics Over the Operating Range[4, 51ParametersDescriptionTestConditionsfMAX Operating Frequency Note 6tpHSISI HIGH TimetpLSItDDtHSItIR+tlR-tpHSOtPLSOtoR +tOR-tDAtDHtBTtMRWtDSItDORtDIRSILOWTimeData Setup to SIData Hold from SIDelay, SI HIGH to IR LOWDelay, SI LOW to IR HIGHSO HIGH TimeSO LOW TimeDelay, SO HIGH to OR LOWDelay, SO LOW to OR HIGHData Setup to OR HIGHData Hold from OR LOWBubble through TimeMR Pulse WidthMR HIGH to SI HIGHMR LOW to OR LOWMR LOW to IR HIGH3341 3341-2Min. Max. Min. Max.1.2 280 8080 800 0200 10020 350 20 16020 450 20 20080 8080 8020 370 20 16020 450 20 2000 075 201000 500400 20030 30400 200400 200UnitsMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsNotes:5. Test conditions assume signal transitions of 10 ns or less. Timingreference levels of 1.5V and output loading of the specified lor/IOHand 30 pF load capacitance.Switching WaveformsData In Timing Diagram6. l/fMAX > tpHSI + tIR -, l/fMAX > tpHSO + tOR -.-----~-----1/fMAX-----....SHIFT ININPUT READYDATA INPUT____ xxxxxxxx'---__0004-6Data Out Timing DiagramSHIFT OUTOUTPUT READYDATA OUTPUT0004-75-21

~ CY3341·~~~NDU~ ~~~~~~~~~~~~~~~======~~==========================Switching Waveforms (Continued)Master Reset Timing DiagramtMRW .MASTER RESET )~ } if.tDIRINPUT READYJ'-100ROUTPUT READY.. tDSISHIFT IN 1.--_---J!DATA OUTPUT\Ordering InformationOrdering Code Package Operating Ordering Code Package Operating(1.2 MHz) Type Range (2 MHz) Type RangeCY334lPCCY334lDCPID2Commercial~t-~CY3341-2PCPICY3341-2DC 02CommercialCY334lDMB D2 Military CY3341-2DMB D2 Military0004-85-22

~ CY3341~~~~~==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3100 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupsfMAX 7,8,9,10,11tpHSI 7,8,9,10,11tpLSI 7,8,9,10,11too 7,8,9,10,11tHSI 7,8,9,10,11tIR+ 7,8,9,10,11tIR- 7,8,9,10,11tpHSO 7,8,9,10,11tpLSO 7,8,9,10,11toR + 7,8,9,10,11tOR- 7,8,9,10,11tOA 7,8,9,10,11tOH 7,8,9,10,11tBT 7,8,9,10,11tMRw 7,8,9,10,11tOSI 7,8,9,10,11tOOR 7,8,9,10,11tDIR 7,8,9,10,11Document #: 38-00011-BIII5-23

Features• 64 x 4 (CY7C401 and CY7C403)64 x 5 (CY7C402 and CY7C404)High speed first-in first-outmemory (FIFO)• Processed with high-speedCMOS for optimumspeed/power• 25 MHz data rates available onCY7C403 and CY7C404• 50 ns bubble-through time-25 MHz• Expandable in word widthand/or length• 5 volt power supply ± 10%tolerance both commercial andmilitary• Independent asynchronous inputsand outputs• TTL compatible interface• Output enable function availableon CY7C403 and CY7C404• Capable of withstanding greaterthan 2000V electrostaticdischargeLogic Block DiagramSIIR( ) • 7C402. 7C404[ I • 7C403. 7C404CYPRESSSEMICONDUCTORWRITE POINTERREAD POINTER• Pin compatible with MMI67401A/67402AFunctional DescriptionThe CY7C401 and CY7C403 are asynchronousfirst-in first-out memories(FIFOs) organized as 64 four bitwords. The CY7C402 and CY7C404are similar FIFOs organized as 64 fivebit words. Both the CY7C403 andCY7C404 have an Output Enable (OE)function.The devices accept 4/5 bit words at thedata input (Dlo-Dln) under the controlof the Shift In (SI) input. Thestored words stack up at the output(DOo-DOn) in the order they were entered.A read command on the ShiftOut (SO) input causes the next to lastword to move to the output and alldata shifts down once in the stack. TheInput Ready (IR) signal acts as a flagto indicate when the input is ready toaccept new data (HIGH), to indicatewhen the FIFO is full (LOW), and toprovide a signal for cascading. The[O'EJSOOR0014-1CY7C401/CY7C403CY7C402/CY7C404Cascadeable 64 X 4 FIFO and64 x 5 FIFOPin ConfigurationsCY7C401 NCCY7C403 OEIRSIOutput Ready (OR) signal is a flag toindicate the output contains valid data(HIGH), to indicate the FIFO is empty(LOW), and to provide a signal for cascading.Parallel expansion for wider words isaccomplished by logically ANDing theInput Ready (IR) and Output Ready(OR) signals to form composite signals.Serial expansion is accomplished by tyingthe data inputs of one device to thedata outputs of the previous device.The Input Ready (IR) pin of the receivingdevice is connected to the Shift Out(SO) pin of the sending device, and theOutput Ready (OR) pin of the sendingdevice is connected to the Shift In (SI)pin of the receiving device.Reading and writing operations arecompletely asynchronous, allowing theFIFO to be used as a buffer betweentwo digital machines of widely differingoperating frequencies. The 25 MHz operationmakes these FIFOs ideal forhigh speed communication and controllerapplications.VCC g~~g:g~ ~soIROR01 0 00001, 00,01 2 00201 3 003GNOI~",u~ ~ ~ >(.)~MR0014-23 2 ~l20'9'51 4 18 NC01 0 5 7C401 17 OR01, 6 7C403 16 00001 2 7 15 001NC 8 14 0029101112'3,0014-16SI01 001,01 201 3014GNO5101 001,01 201 3VCCsoOR00000,002003004MR0014-33212019418 OR517 007C402 07C40416 00,15 00 2814 00 39 101112132S"'~I~ g"'~0014-17Selection GuideMaximum Shift Rate (MHz)Maximum OperatingCurrent (mA)CommercialMilitary7C401/2·5 7C40X·IO 7C40X-155 10 1575 75 75- 90 907C403/4·252575905-24

5ACY7C401/CY7C403. CY7C402/CY7C404~UcroR =====================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential .... - O. 5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to +7.0VDC Input Voltage ................... - 3.0V to + 7.0VPower Dissipation ............................. 1.0WOutput Current, into Outputs (Low) ............. 20 rnAStatic Discharge Voltage ..................... > 2oo1V(per MIL-STD-883 Method 3015)Latch-up Current .......................... > 200 rnAOperating RangeRangeElectrical Characteristics Over Operating Range (Unless Otherwise Noted)[4]Parameters Description Test ConditionsAmbientTemperatureVeeCommercial QOCto +700C 5V ±1O%Military [3] - 55°C to + 125°C 5V ±1O%7C40X-I0, 15, 25VOH Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 rnA 0.4 VVIH Input HIGH Voltage 2.0 6.0 VVIL Input LOW Voltage -3.0 0.8 VIIX Input Leakage Current GND ~ VI ~ Vee -10 +10 #LAVeD[1]IozInput Diode Clamp Voltage[l]Output Leakage CurrentGND ~ VOUT ~ Vee, Vee = 5.5VOutput Disabled (CY7C403 and CY7C404)Min.Max.Units-50 +50 #LAlOS Output Short Circuit Current[2] Vee = Max., VOUT = GND -90 rnAVee = Max., Commercial 75 rnAleePower Supply CurrentlOUT = OmA I Military 90 rnACapacitance [5)Parameters Description Test Conditions Max. UnitsCIN Input Capacitance T A = 25°C, f = 1 MHz 5pFCOUT Output Capacitance Vee = 4.5V 7Notes:1. The eMOS process does not provide a clamp diode. However, the3. TA is the "instant on" case temperature.FIFO is insensitive to - 3V dc input levels and - SV undershoot4. See the last page of this specification for Group A subgroup testingpulses ofless than 10 ns (measured at 50% point).information.2. For test purposes, not more than one output at a time should be5. Tested initially and after any design or process changes that mayshorted. Short circuit test duration should not exceed 30 seconds.affect these parameters.Note:For more information on FIFOs, please refer to the FIFO Application Brief in the Appendix of this book.5-25

finCY7C401/CY7C403. CY7C402/CY7C404~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===AC Test Load and WaveformEquivalent to:R1437n5Vo-------~~~OUTPUT o---"""""'i~-----"30 pF R22720INCLUDINGI JIG AND"::" SCOPE -=Figure laTHEVENIN EQUIVALENT16mOUTPUT O~---'·'Y tpHSI + tOHIR, lifo> tpHSO + tOHOR8. tSSI and tHSI apply when memory is not full.9. tSIR and tHIR apply when memory is full, SI is high and minimumbubble through (tBT) conditions exist.R227200014-47C40X·IOMin.2030040202505Max.104045405510 95530202030354040403530ALL INPUT PULSES3.0V----1r!~---..GND--=".. 5 "I0014-57C40X·157C403·25 (12)7C404-25UnitsMin. Max. Min. Max.15 25 MHz20 11 ns25 20 ns0 0 ns30 20 ns35 21/22 ns40 28/30 ns20 11 ns25 20 ns35 19/21 ns40 34/37 ns0 0 ns5 5 ns10 65 10 50/60 ns5 5 ns30 20 ns20 15 ns20 15 ns25 25 ns25 10 ns35 35 ns35 35 ns35 25 ns30 20 ns25 15 ns10. All data outputs will be at LOW level after reset goes high until datais entered into the FIFO.11. HIGH-Z transitions are referenced to the steady-state VOH - 500m V and VOL + 500 m V levels on the output. tHZOE is tested with 5pF load capacitance as in Figure 1 h.12. CommerciaVMilitary5-26

(iACY7C401/CY7C403. CY7C402/CY7C404. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~==~~~======Operational DescriptionCONCEPTUnlike traditional FIFOs these devices are designed using adual port memory, read and write pointer, and control logic.The read and write pointers are incremented by theShift Out (SO) and Shift In (SI) respectively. The availabilityof an empty space to shift in data is indicated by theInput Ready (IR) signal, while the presence of data at theoutput is indicated by the Output Ready (OR) signal. Theconventional concept of bubble through is absent. Instead,the delay for input data to appear at the output is the timerequired to move a pointer an~ propagate an Output Ready(OR) signal. The Output Enab e (OE) signal provides thecapability to OR tie multiple FIFOs together on a commonbus.RESETTING THE FIFOUpon power up, the FIFO must be reset with a MasterReset (MR) signal. This causes the FIFO to enter an emptycondition signified by the Output Ready (OR) signal beingLOW at the same time the Input Ready (IR) signal isHIGH. In this condition, the data outputs DOo-DOn) willbe in a LOW state.SHIFTING DATA INData is shifted in on the rising edge of the Shift In (SI)signal. This loads input data into the first word location ofthe FIFO. On the falling edge of the Shift In (SI) signal,the write pointer is moved to the next word position andthe Input Ready (IR) signal goes HIGH indicating thereadiness to accept new data. If the FIFO is full, the InputReady (IR) will remain LOW until a word of data is shiftedout.SHIFTING DATA OUTData is shifted out of the FIFO on the falling edge of theShift Out (SO) signal. This causes the internal read pointerto be advanced to the next word location. If data is present,valid data will appear on the outputs and the OutputReady (OR) signal will go HIGH. If data is not present,the Output Ready (OR) signal will stay LOW indicatingthe FIFO is empty. Upon the rising edge of Shift Out (SO),the Output Ready (OR) signal goes LOW. The data outputsof the FIFO should be sampled with edge sensitivetype D flip-flop (or equivalent), using the SO signal as theclock input to the flip-flop.BUBBLE THROUGHTwo bubble through conditions exist. The first is when thedevice is empty. After a word is shifted into an empty device,the data propagates to the output. After a delay, theOutput Ready (OR) flag goes HIGH indicating valid dataat the output.The second bubble through condition occurs when the deviceis full. Shifting data out creates an empty locationwhich propagates to the input. After a delay, the InputReady (IR) flag goes HIGH. Ifthe Shift In (SI) signal isHIGH at this time, data on the input will be shifted in.APPLICATION OF THE 7C403-25/7C404-25AT 25 MHzApplication of the CY7C403 or CY7C404 Cypress CMOSFIFO's requires attention to characteristics not easily spec-ified in a Datasheet, but necessary for reliable operationunder all conditions.When an empty FIFO is filled with initial information, atmaximum "shift in" SI frequency, followed by immediateshifting out of the data also at maximum "shift out" SOfrequency, the designer must be aware of a window of timewhich follows the initial rising edge ofthe "output Ready"OR signal during which the SO signal is not recoginized.This condition exists only at high speed operation wheremore than one SO may be generated inside the prohibitedwindow. This condition does not inhibit the operation ofthe FIFO at full frequency operation, but rather delays thefull 25 MHz operation until after the window has passed.There are several implementation techniques to manage thewindow so that all SO signals are recognized:1. The first involves delaying SO operation such that itdoes not occur in the critical window. This can be accomplishedby causing a fixed delay of 40 ns "initiatedby the SI signal only when the FIFO is empty" to inhibitor gate the SO activity. This however requires that theSO operation at least temporarily be synchronized withthe input SI operation. In synchronous applications thismay well be possible and a valid solution.2. Another solution not uncommon in synchronous applicationsis to only begin shifting data out of the FIFOwhen it is greater than half full. This is a common methodof FIFO application, as earlier FIFOs could not beoperated at maximum frequency when near full or empty.Although Cypress FIFOs do not have this limitation, ~any system designed in this manner will not encounter 1:1the window condition described above.3. The window may also be managed by not allowing thefirst SO signal to occur until the window in question haspassed. This can be accomplished by delaying the SO40 ns from the rising edge of the initial OR "outputready" signal. This however involves the requirementthat this only occurs on the first occurance of data beingloaded into the FIFO from an empty condition andtherefore requires the knowledge of "input ready" IRand SI conditions as well as SO.4. Handshaking with the OR signal can be a third methodof avoiding the window in question. With this techniquethe rising edge of SO, or the fact that the SO signal isHIGH, will cause the OR signal to go LOW. The SOsignal is not taken low again, advancing the internalpointer to the next data, until the OR signal goes LOW.This assures that the SO pulse that is initiated in thewindow will be automatically extended sufficient time tobe recognized.5. There remains the decision as to what signal will be usedto latch the data from the output of the FIFO into thereceiving source. The leading edge of the SO signal ismost appropriate because data is guaranteed to be stableprior to and after the SO leading edge for each FIFO.This is a solution for any number of FIFOs in parallel.Any of the above solutions will provide a solution for correctoperation of a Cypress FIFO at 25 MHz. The specificimplementation is left to the designer and dependent on thespecific application needs.5-27

WACY7C401/CY7C403. CY7C402/CY7C404~~~~~~~~~~~==========~================================Switching WaveformsData In Timing DiagramI+-------I/FO------... ------I/FO-------+ISHIFT ININPUT READYDATA IN0014-7Data Out Timing Diagramt------I/FO-----...... _----I/FO------

5A• CYPRESSCY7C401/CY7C403CY7C402/CY7C404SEMICONDUCTOR =============================================================Switching Waveforms (Continued)Bubble Through, Data In To Data Out DiagramSHWTW ~~~~~.,,~o'" -./OUTPUT READYDATA OUTMaster Reset Timing Diagram__ 1+---1" _t_BT-J-I+--'!' tPOR=1wR_________:'=-tL~--------------------------0014-10MASTER RESET\:I---tPMR_-ftD!RINPUT READYItDORI ~OUTPUT READY \- 1\SHIFT INf-!. ___ tLZMR ___ ""~los!-ItDATA OUT0014-11Output Enable Timing DiagramOUTPUT ENABLE _________4_;...~_zotDATA OUT --NOTE 9b~,,=(----------0014-125-29

fiiiCY7C401/CY7C403CY7C402/CY7C404~U~~~~~~~~~~~~~~~~====~==~==~======================Typical DC and AC CharacteristicsNORMALIZED SUPPLY CURRENT1.2 rv..;;;s.;..;;S;...;U;.;;P-;;P-=L;.;;Y;...V.;..O;;,L::.T;;.;A;.;;.G.;;;;E::.,.._---,1.0 t----f---+--2fL-----I0.8 t----f-~'9---+------I0.6 t--~-f---+--+------IVIN =5.0VTA = 25 D C0.4~ _ __L__-L..__....L__~4.0 4.5 5.0 5.5 6.0SUPPLY VOLTAGE (VI] 1.2owN::;~a:~NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.4 r-----r---------,Vee a5.5VVIN =5.0V0.6'--____ '--____---'-55 25 125AMBIENT TEMPERATURE (DCICo)zw::l0wif0wN:::;c(:!a:0z1.31.21.1NORMALIZED FREQUENCYvs. SUPPLY VOLTAGE1.00.9 L0.8~---~0.74.0 4.5 5.0 5.5SUPPLY VOLTAGE (VI6.0NORMALIZED FREQUENCYvs. AMBIENT TEMPERATURE1.6>~ 1.4 t-----.--,f---------Iw~a: 1.2 po.,~--.--,f---------III.oW~ 1.01----....::3001o=------i~a:~ 0.81------1---------10.6_ ....5 - 5 ---- 2 '-5-----...... 125AMBIENT TEMPERATURE (DC I

(inCY7C401/CY7C403. CY7C402/CY7C404~NDUcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==~=====FIFO Expansion128 x 4 ApplicationSHIFT ININPUT READYORSOSIIRORsoOUTPUT READYSHIFT OUTDODDIDDODDATAIN{001002011012DO,002} DATA OUT00301 3MR 003~o---------~----------------~ 0014-14FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of thedevices.192 x 12 ApplicationIR so IR so IR SO-SI OR SI OR SI OR- 010 000 01 0 000 010 000 ~- 011 DO, 01, DO, 011 DO, r-- 01 2 002 01 2 002 01 2 002 I--- 01 3 MR 003 01 3 MR D03 01 3 r;m 003 r-COMPOSITE I )' 1INPUT READY,.-,.-SOSHIFT IN'-I---IR SO IR SO IR r----~SI OR SI OR SI OR- 010 000 010 000 010 000 I--- 01, DO, 01, DO, 01, DO, r-- 012 002 01 2 002 012 0021--- 01 3 r;m D03 01 3 MR D03 01 3 MA DOJ I--I ~ 1IR so IR so IR so -SI OR SI OR SI ORSHIFT OUTCOMPOSITEOUTPUT READY~r-L-'- 010 000 010 DOo 010 000 -- 01, DO, 011 DO, 01, DO, -- 01 2 002 012 002 012 002 -- 0 13 MR DOJ 01 3 MA D03 013 MA DOJ r-'J' y 1MRFIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite Input and OutputReady flags. This need is due to the variation of delays of the FIFOs.0014-15User Notes:1. When the memory is empty the last word read will remain on theoutputs until the master reset is strobed or a new data word bubblesthrough to the output. However, OR will remain LOW, indicatingdata at the output is not valid.2. When the output data changes as a result of a pulse on SO, the ORsignal always goes LOW before there is any change in output data andstays LOW until the new data has appeared on the outputs. AnytimeOR is HIGH, there is valid stable data on the outputs.3. If SO is held HIGH while the memory is empty and a word is writteninto the input, that word will ripple through the memory to the output.OR will go HIGH for one internal cycle (at least toRL) and thengo back LOW again. The stored word will remain on the outputs. Ifmore words are written into the FIFO, they wi11line up behind thefirst word and will not appear on the outputs until SO has beenbrought LOW.4. When the master reset is brought LOW, the outputs are cleared toLOW, IR goes HIGH and OR goes LOW. IfSI is HIGH when themaster reset goes HIGH then the data on the inputs will be writteninto the memory and IR will return to the LOW state until SI isbrought LOW. If SI is LOW when the master reset is ended, then IRwill go HIGH, but the data on the inputs will not enter the memoryuntil SI goes HIGH.•5. All Cypress FIFOs will cascade with other Cypress FIFOs. However,they may not cascade with pin-compatible FIFO's from other manufacturers.5-31

~. CY7C401/CY7C403. CY7C402/CY7C404~U~================================================================Ordering InformationOrdering Code Package Operating Ordering Code Package Operating Ordering Code Package Operating(25 MHz) Type Range (l5MHz) Type Range (lOMHz) Type RangeCY7C403-2SPC PI Com. CY7C401-1SPC PI Com. CY7C401-lOPC PI Com.CY7C404-2SPC P3 CY7C402-1SPC P3 CY7C402-lOPC P3CY7C403-2S0C 02 CY7C403-1SPC PI CY7C403-lOPC PICY7C404-2S0C 04 CY7C404-1SPC P3 CY7C404-lOPC P3CY7C403-2SLC L61 CY7C401-1S0C 02 CY7C401-100C 02CY7C404-2SLC L61 CY7C402-1S0C 04 CY7C402-100C 04CY7C403-2S0MB 02 Mil. CY7C403-1S0C 02 CY7C403-100C 02CY7C404-2S0MB 04 CY7C404-1S0C 04 CY7C404-100C 04CY7C403-2SLMB L61 CY7C401-1SLC L61 CY7C401-lOLC L61CY7C404-2SLMB L61 CY7C402-1SLC L61 CY7C402-lOLC L61CY7C403-1SLC L61 CY7C403-lOLC L61CY7C404-1SLC L61 CY7C404-lOLC L61CY7C401-1S0MB 02 Mil. CY7C401-100MB 02 Mil.CY7C402-1S0MB 04 CY7C402-100MB 04CY7C403-1S0MB 02 CY7C403-100MB 02CY7C404-1S0MB 04 CY7C404-100MB 04CY7C401-1SLMB L61 CY7C401-lOLMB LuiCY7C402-1SLMB L61 CY7C402-lOLMB L61CY7C403-1SLMB L61 CY7C403-lOLMB L61CY7C404-1SLMB L61 CY7C404-10LMB L61Ordering Code Package Operating(5 MHz) Type RangeCY7C401-SPC PI Com.CY7C402-SPC PI5-32

WACY7C401/CY7C403. CYPRESS CY7C402/CY7C404s~~u~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~==========MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3IOZ 1,2,3lOS 1,2,3Icc 1,2,3SubgroupsSwitching CharacteristicsParameters Subgroupsfo 7,8,9,10,11tpHSI 7,8,9,10,11tpLSI 7,8,9,10,11tSSI 7,8,9,10,11tHSI 7,8,9,10,11tOUR 7,8,9,10,11tOHIR 7,8,9,10,11tpHSO 7,8,9,10,11tpLSO 7,8,9,10,11tOLOR 7,8,9,10,11tOHOR 7,8,9,10,11tSOR 7,8,9,10,11tHSO 7,8,9,10,11tBT 7,8,9,10,11tSIR 7,8,9,10,11tHIR 7,8,9,10,11tpIR 7,8,9,10,11tpOR 7,8,9,10,11tpMR 7,8,9,10,11tOSI 7,8,9,10,11tOOR 7,8,9,10,11tDIR 7,8,9,10,11tLzMR 7,8,9,10,11Document #: 38-00040-CParameters SubgroupstooE 7,8,9,10,11tHZOE 7,8,9,10,115-33

Features• 64 x 8 and 64 x 9 first-in firstout(FIFO) buffer memory• 35 MHz shift-in and shift-outrates• 50 MHz burst mode capability• Almost Full/Almost Empty andHalf Full flags• Dual port RAM architecture• Fast, 50 ns, bubblethrough• Independent asynchronous inputsand outputs• Output Enable (CY7C408)• Expandable in word width andFIFO depth• 5V ± 10% supply• TIL compatible• Capable of withstanding greaterthan 2000V electrostaticdischarge voltage• 300 mil, 28-pin DIPFunctional DescriptionThe CY7C408 and CY7C409 are 64-word deep by 8- or 9-bit wide first-infirst-out (FIFO) buffer memories. Inaddition to the industry standard handshakingsignals Almost Full/ AlmostEmpty (AFE) and Half Full (HF) flagsare provided.CYPRESSSEMICONDUCTORAFE is HIGH when the FIFO is almostfull or almost empty. OtherwiseAFE is LOW. HF is HIGH when theFIFO is half full, otherwise HF isLOW.The CY7C408 has an Output Enable(OE) function.The memory accepts 8- or 9-bit parallelwords at its inputs (010-018) underthe control of the Shift-In (SI) inputwhen the Input-Ready (IR) control signalis HIGH. The data is output, in thesame order as it was stored, on the000-008 output pins under the controlof the Shift-Out (SO) input whenthe Output-Ready (OR) control signalis HIGH. If the FIFO is full (IR LOW)pulses at the SI input are ignored: if theFIFO is empty (OR LOW) pulses atthe SO input are ignored.The IR and OR signals are also used toconnect the FIFO's in parallel to makea wider word, or in series to make adeeper buffer, or both.Parallel expansion for wider words isimplemented by logically ANDing theIR and OR outputs (respectively) ofthe individual FIFOs together. TheAND operation insures that all of theFIFOs are either ready to accept moreCY7C408CY7C409Cascadeable 64 X 8 FIFOCascadeable 64 X 9 FIFOdata (IR HIGH) or are ready to outputdata (OR HIGH) and thus compensatefor variations in propagation delaytimes between devices.Serial expansion for deeper buffermemories is accomplished by connectingthe data outputs of the FIFO closestto the data source (upstream device)to the data inputs of the following(downstream) FIFO. In addition, to insureproper operation, the SO signal ofthe upstream FIFO must be connectedto the IR output of the downstreamFIFO and the SI signal of the downstreamFIFO must be connected to theOR output of the upstream FIFO. Inthis serial expansion configuration(called cascade) the IR and OR signalsare used to pass data through full andempty FIFOs.Reading and writing operations arecompletely asynchronous, allowing theFIFO to be used as a buffer betweentwo digital machines of widely differingoperating frequencies. The high shift-inand shift-out rates of these FIFOs, andtheir high throughput rate due to thefast bubblethrough time, which is dueto their dual port RAM architecture,make them ideal for high speed communicationsand controllers.Logic Block DiagramPin ConfigurationsWRITE POINTER51IRAFEHFWRITE MULTIPLEXER~III01 7(7C409)DlaMEMORYARRAYDOa (7C409)READ MULTIPLEXER0E(7C408)MRREAD POINTERORSO0065-2in ~ ~ $ ~I~ gFlag DefinitionsAFE Words Stored0065-101. 54 3 i 1TI28272~S OR01, 6 24 DO.GNO 7 23 DO,HFLLHHHLLH0-89-3132-5556-64012 8 ~~g~ 22 GNO013 9 21 D0 2014 '0 20 D03DIS '''2'314'51617,~9 D0 4-£.g~~88g~I~ 0065-35-34

finCY7C408. CY7C409Selection Guide~ucrOR================================================================7C408-15 7C408-25 7C408-357C409-15 7C409-25 7C409-35Maximum Shift Rate (MHz) 15 25 35Maximum Operating Commercial 115 125 135Current (mA)!2]Military 140 150 N/AMaximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°C Static Discharge Voltage ..................... > 2001 VAmbient Temperature with(per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°COperating RangeSupply Voltage to Ground Potential .... -0.5V to + 7.0VAmbientDC Voltage Applied to OutputsRangeVeeTemperaturein High Z State ...................... -0.5V to + 7.0VCommercial O°Cto + 70°C 5V ±1O%DC Input Voltage ................... -3.0Vto +7.0VMilitary!4] - 55°C to + 125°C 5V ±1O%Power Dissipation ............................. 1.0WOutput Current, into Outputs (Low) ............. 20 mAElectrical Characteristics Over Operating Range (Unless Otherwise Noted)[5]CY7C408Parameters Description Test Conditions CY7C409 UnitsVOH Output HIGH Voltage Vee = Min.,IOH = -4.0 rnA 2.4 VVOL Output LOW Voltage Vee = Min., 10L = 8.0 rnA 0.4 VVIH Input HIGH Voltage 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 VIlx Input Leakage Current GND:::;; VI:::;; Vee -10 +10 ,..,Alos Output Short Circuit Current!l] Vee = Max., VOUT = GND -90 rnAleeQQuiescent Power Supply CurrentMin.Max.Vee = Max., lOUT = 0 rnA Commercial 100 rnAVIN :::;; VIL, VIN ~ VIH Military 125 rnAIcc Power Supply Current Icc = leeQ + I rnA/MHz X (fsl + fso)/2Capacitance [3]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = I MHz 5pFCOUT Output Capacitance Vee = 4.5V 7Notes:1. For test purposes, not more than one output at a time should be3. Tested initially and after any design or process changes that mayshorted. Short circuit test duration should not exceed 30 seconds.affect these parameters.2. Icc = Ic~ + 1 mAIMHz X (fsl + fso)/24. TA is the "instant on" case temperature.5. See the last page of this specification for Group A subgroup testinginformation.AC Test Load and WaveformsR143705Vo---....... ,."..,-...,DUTPUTo--..... ----tEquivalent to:R1500.o.5VO--"""".--""OUTPUT 0-.----+30 pI' ;~3.o.CL 130 pF ~~20.LNCLUOINGINCLUDING _ JIG AND -JIG AND- SCOPE -":" SCOPE ":"Figure 180065-4THEVENIN EQUIVALENT16mOUTPUT o~-~·."'·.,...,-~o 1.73VFigure Ib0065-60065-215-353.0 V----tr~--...".GNDFigure 2. All Input Pulses0065-5

5ACY7C408. CY7C409~==============================================================Switching Characteristics Over the Operating Range[5. 6]ParametersDescriptionTestConditionsfo Operating Frequency Note 7tpHSItPLSISIHIGHTimeSILOWTimetSSI Data Setup to SI Note 8tHSI Data Hold from SI Note 8tOLIR Delay, SI HIGH to IR LOWtOHIR Delay, SI LOW to IR HIGHtpHSO SO HIGH TimetPLSO SO LOW TimetOLOR Delay, SO HIGH to OR LOWtOHOR Delay, SO LOW to OR HIGHtSOR Data Setup to OR HIGHtHSO Data Hold from SO LOWtBT Bubblethrough TimetSIR Data Setup to IR Note 9tHIR Data Hold from IR Note 9tpIR Input Ready Pulse HIGHtPOR Output Ready Pulse HIGHtOLZOE OE LOW to LOW Z (7C408) Note 12tOHZOE OE HIGH to HIGH Z (7C408) Note 12tOHHF SI LOW to HF HIGHtOLHF SO LOW to HF LOWtOLAFE SO or SI LOW to AFE LOWtOHAFE SO or SI LOW to AFE HIGHtpMR MR Pulse WidthtOSItOORtDIRMR HIGH to SI HIGHMR LOW to OR LOWMR LOW to IR HIGHtLZMR MR LOW to Output LOW Note 10tAPE MR LOW to AFE HIGHtHF MR LOW to HF LOWfB Burst Mode Frequency Note 13too SO to Data Out ValidNotes:6. Test conditions assume signal transition time of 5 ns or less. timingreference levels of 1.5V and output loading ofthe specified IorJIOHand 30 pF load capacitance. as in Figure 1.7. 1!fo> tpHSI + tOHIR. lifo> tpHSO + tOHOR.8. tSSI and tHSI apply when memory is not full.9. tSIR and tHIR apply when memory is full. SI is HIGH and minimumbubblethrough (taT) conditions exist.CY7C408·15 CY7C408·25 CY7C408·35CY7C409·15 CY7C409·25 CY7C409·35 UnitsMin. Max. Min. Max. Min. Max.15 25 35 MHz16 11 9 ns16 11 9 ns0 0 0 ns30 20 12 ns35 21 15 ns40 23 16 ns16 11 9 ns16 11 9 ns35 21 15 ns40 23 16 ns0 0 0 ns0 0 0 ns10 65 10 60 10 50 ns5 5 5 ns30 20 20 ns16 11 9 ns16 11 9 ns35 30 25 ns35 30 25 ns65 55 45 ns65 55 45 ns65 55 45 ns65 55 45 ns55 45 35 ns25 10 10 ns55 45 35 ns55 45 35 ns55 45 35 ns55 45 35 ns55 45 35 ns30 40 50 MHz28 20 16 ns10. All data outputs will be at LOW level after reset goes HIGH untildata is entered into the FIFO.11. For 7C408 only.12. TOHZOE and TOZOE are specified with CL = 5 pF as in Figure lb.TOHZOE transition is measured ± 500 mV from steady state voltage.TOLZOE transition is measured ± 100 mV from steady state voltage.These parameters are guaranteed and not 100% tested.13. lIfa = tpHSI + tpLSI. lIfa = tpHSO + tpLSO·5-36

~ CY7C408_r.~NDUcroR =================================================================~C~Yg7C~40~9Switching WaveformsData In Timing Diagramt-------Fo------~f-------I/FO---------+ISHIFT ININPUT READYDATA INAFEHF

~CY7C408• CYPRFSSCY7C409s~oo~u~================================================================Switching Waveforms (Continued)Data In Timing Diagramt-------Fo--------

(inCY7C408. CYPRESS CY7C409S~OO~UcrOR ========================================~~==~====~====~~~~Switching Waveforms (Continued)Data In Timing Diagramt-------I/FO-------+-_-_____ I/FO ______ -+ISHIFT ININPUT READYDATA INHFAFE® FIFO Contains 55 Words0065-16Data Out Timing DiagramI------I/FO------I------I/FO-----.tSHIFT OUTOUTPUT READYDATA OUTAFEHF(HIGH)@ FIFO Contains 56 WordsBubblethrough, Data Out to Data In DiagramSHIFTOUT .J,.....------tt_-------,.1 \...-------,",n" ~INPUT READY"{tBT .=t'_tpIR0065-17DATA IN ~~~I)r..Ji---tsiRtHIR0065-95-39

WnCY7C408.. CY7C409~UaoR============~~~~~~==========~~~~~~~~~~~~~~~==Switching Waveforms (Continued)Fallthrough, (Bubblethrough) Data In to Data Out DiagramSHIFT INSHIFT OUTOUTPUT READY___ __:-=--=-tB_T-_-]--'--~'=1~____________________________ ~-tS-OR-~------------------------------------DATA OUT0065-10Master Reset Timing DiagramI+---tPMR_MASTER RESET ~r- -~1\ JINPUT READYtOIR}'ltOOROUTPUT READY~~1\SHIFT INtOSI}ItLZMRDATA OUT~l\HFtOHFr\AFEtOAFEV-;0065-115-40

CY7C408~ CY7C409~~~UaoR================================================================Shifting Words InEMPTYFULL1 2 8 9 10 31 32 33 55 56 57 64SHIFTINnn •••HF ________________ ~------------~... ~_... -+--.. _.nAFE0065-18Shifting Words OutFULL64 63 56 55 54SHIFT OUT nn ...HF32EMPTY31 30 9 8 7 1... nAFE0065-19Architecture of the CY7C408 and CY7C409The CY7C408 and CY7C409 FIFOs consist of an array of64 words of 8- or 9-bits each (which are implemented usinga dual port RAM cell), a write pointer, a read pointer andthe control logic necessary to generate the handshaking(SI/IR, SOIOR) signals as well as the Almost Fulll AlmostEmpty (AFE) and the Half Full (HF) flags. The handshakingsignals operate in a manner identical to those of theindustry standard CY7C40 1/402/403/404 FIFOs.Dual Port RAMThe dual port RAM architecture refers to the basic memorycell used in the RAM. The cell itself enables the readand write operations to be independent of each other,which is necessary to achieve truly asynchronous operationof the inputs and outputs. A second benefit is that the timerequired to increment the read and write pointers is muchless than the time that would be required for data to propagatethrough the memory, which would be the case if t~ememory were implemented using the conventional regIsterarray architecture.Bubblethrough and FallthroughThe time required for data to propagate from the input tothe output of an initially empty FIFO is defined as theFallthrough time.The time required for an empty location to propagate fromthe output to the input of an initially full FIFO is definedas the Bubblethrough time.The maximum rate at which data can be passed throughthe FIFO (called the throughput) is limited by the fallthroughtime when it is empty (or near empty) and by thebubblethrough time when it is full (or near full).The conventional definitions of fallthrough and bubblethroughdo not apply to the CY7C408 and CY7C409FIFOs because the data is not physically propagated 5through the memory. The read and write pointers are incrementedinstead of moving the data. However, the parameteris specified because it does represent the worst casepropagation delay for the control signals. That is, the timerequired to increment the write pointer and propagate asignal from the SI input to the OR output of an emptyFIFO or the time required to increment the read pointerand propagate a signal from the SO input to the IR outputof a full FIFO.Resetting the FIFOUpon power up the FIFO must be reset with a MasterReset (MR) signal. This causes the device to enter the emptycondition, which is signified by th.e OR. signal being .LOW at the same time that the IR sIgnal IS HIGH. In thIScondition, the data outputs (DOO-D08) will be LOW.The AFE flag will be HIGH and the HF flag will be LOW.Shifting Data Into the FIFOThe availability of an empty location is indicated by theHIGH state of the Input Ready (IR) signal. When IR isHIGH a LOW to HIGH transition on the Shift-In (SI) pinwill load the data on the DIO-DI8 inputs into the FIFO.The IR output will then go LOW, indicating that the datahas been sampled. The HIGH to LOW transition of the SIsignal initiates the LOW to HIGH transition of the ~~ .signal, as well as the AFE flag LOW to HIGH transItIon Ifthe FIFO is almost full or almost empty.5-41

~CY7C408. CY7C409~U~.==~~~~~~~~~~~~~~~~~~~~~==~====~====~====Shifting Data Out of the FIFOHF AFE Words ConditionThe availability of data at the outputs of the FIFO is indicatedby the HIGH state of the Output Ready (OR) signal.After the FIFO is reset all data outputs (DOO-D08) willbe in the LOW state. As long as the FIFO remains emptythe OR signal will be LOW and all Shift Out (SO) pulsesapplied to it will be ignored. After data is shifted into theFIFO the OR signal will go HIGH. The external controllogic (designed by the user) should use the HIGH state ofthe OR signal to generate a SO pulse. The data outputs ofthe FIFO should be sampled with edge sensitive type Dflip-flops (or equivalent), using the SO signal as the clockinput to the flip-flop.Interfacing to the FIFO Application BriefSee the application brief in the back of this databook forinformation regarding interfacing to the FIFO under asynchronousoperating conditions.AFE and HF FlagsTwo flags, Almost Full/Almost Empty (AFE) and HalfFull (HF), describe how many words are stored in theFIFO. AFE is HIGH when there are eight or less, or 56 ormore, words stored in the FIFO. Otherwise the AFE flag isLOW. HF is HIGH when there are 32 or more wordsstored in the FIFO, otherwise the HF flag is LOW. Flagtransitions occur relative to the falling edges of SI and SO.Burst Mode OperationThe CY7C408 and CY7C409 support a burst mode of operationwhich allows data to be shifted in and shifted out at50, 40 and 30 MHz for CY7C480X-35, CY7C480X-25,CY7C480X-15 respectively. Burst Mode takes advantageof the new flags HF (Half Full) and AFE (Almost Full/Empty) and the IR and OR flags are not used. In the BurstMode the relative fullness or emptiness of the FIFO is decodedand data is shifted in and out as long as the FIFO isless than ALMOST FULL or less than ALMOST EMP­TY.Burst FillBurst mode fill operation is proper only when the AL­MOST FULL condition is NOT present. If the ALMOSTFULL condition exists, normal shift in operation may resumeusing IR, SI synchronization or shift in operationmay be terminated entirely until the ALMOST FULL conditionno longer exists.0 10 01 01 10-89-3132-5556-64Burst FillBurst FillBurst FillSync FillBurst Fill to Almost Full orShift Out, or Shift in NormalBurst EmptyBurst empty is proper only when the ALMOST EMPTYcondition is NOT present. If the ALMOST EMPTY conditionexists, normal shift out operation may resume usingOR, SO synchronization or shift out operation may be terminatedentirely until the ALMOST EMPTY condition nolonger exists.HF AFE Words Condition1 1 56-64 Burst Empty Burst Empty to Almost Empty1 0 32-55 Burst Emptyor Shift Out, or Shift in Normal0 0 9-31 Burst Empty0 1 0-8 Sync EmptyCascaded FIFO Operation at High Frequencyand Burst Mode OperationThere are two factors that limit data throughput when twoor more FIFOs are cascaded to make a deeper FIFO. Theyare: (1) the physical movement of data from FIFO toFIFO, and (2) the handshaking mechanism between theFIFOs.To overcome the handshaking throughput limitation in theCY7C408 and CY7C409 operating above 25 MHz, andthereby maximize the data throughput in cascaded configurations,simply invert the IR signal of the downstreamFIFO before applying that signal to the SO input of theupsteam FIFO.Figure 1 illustrates how n-I inverters are required when nFIFOs are cascaded. Additionally, for every cascadedFIFO that has an inverter, the depth capacity of that FIFOis decreased by one.: A c:IR x : IR IR IR SO : SOxISix:SI SISI ORI: ORxD~: :~II 1 2 n I~---------------------------------------.4 UPSTREAMDOWNSTREAM ----+0065-22Figure 1. Burst Mode Operation in Cascaded ConfigurationI5-42

FIFO Expansion128 x 9 ConfigurationHF,/AFESHIFT ININPUT READYDATA IN01 8 00 8HF/AFESIIR01 001101 201 301 401501 601 7ORSO0000°10°200 3DO"0°50°60°7SIIR01 001101 201 301 401501 6tiRY01 701 8tiRyOROUTPUT READYSOSHIFT OUT00 0--'-0°10°2 ..00 30°4DATA OUT0°500 600 700 80065-12FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of thedevices.User Notes:1. When the memory is empty the last word read will remain on theoutputs until the master reset is strobed or a new data word bubblesthrough to the output. However, OR will remain LOW, indicatingdata at the output is not valid.2. When the output data changes as a result of a pulse on SO, the ORsignal always goes LOW before there is any change in output data andstays LOW until the new data has appeared on the outputs. AnytimeOR is HIGH, there is valid stable data on the outputs.3. If SO is held HIGH while the memory is empty and a word is writteninto the input, that word will ripple through the memory to the output.OR will go HIGH for one internal cycle (at least tDLOiU andthen go back LOW again. The stored word will remain on the out-puts. Ifmore words are written into the FIFO, they will line upbehind the first word and will not appear on the outputs until SO hasbeen brought LOW.4. When the master reset is brought LOW, the outputs are cleared toLOW, IR goes HIGH and OR goes LOW. IfSI is HIGH when themaster reset goes HIGH then the data on the inputs will be writteninto the memory and IR will return to the LOW state until SI is 5brought LOW. IfSI is LOW when the master reset is ended, then IRwill go HIGH, but the data on the inputs will not enter the memoryuntil SI goes HIGH.5. All Cypress FIFOs will cascade with other Cypress FIFOs. However,they may not cascade with FIFOs from other manufacturers.5-43

5nCY7C408. . CY7C409~==========~~======~~==~========~~==FIFO Expansion (Continued)192 x 27 ConfigurationHF/AF'E+---------,SHIFT OUTCOMPOSITEINPUT READYCOMPOSITEOUTPUT READYSHIFT INFIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite Input and OutputReady flags. This need is due to the variation of delays of the FIFOs.0065-13User Notes:1. When the memory is empty the last word read will remain on theoutputs until the master reset is strobed or a new data word bubblesthrough to the output. However, OR will remain LOW, indicatingdata at the output is not valid.2. When the output data changes as a result of a pulse on SO, the ORsignal always goes LOW before there is any change in output data andstays LOW until the new data has appeared on the outputs. AnytimeOR is HIGH, there is valid stable data on the outputs.3. If SO is held HIGH while the memory is empty and a word is writteninto the input, that word will ripple through the memory to the output.OR will go HIGH for one internal cycle (at least tDLOIU andthen go back LOW again. The stored word will remain on the out-puts. If more words are written into the FIFO, they will line upbehind the first word and will not appear on the outputs until SO hasbeen brought LOW.4. When the master reset is brought LOW, the outputs are cleared toLOW, IR goes HIGH and OR goes LOW. If SI is HIGH when themaster reset goes HIGH then the data on the inputs will be writteninto the memory and IR will return to the LOW state until SI isbrought LOW. If SI is LOW when the master reset is ended, then IRwill go HIGH, but the data on the inputs will not enter the memoryuntil SI goes HIGH.5. All Cypress FIFOs will cascade with other Cypress FIFOs. However,they may not cascade with FIFOs from other manufacturers.5-44

~CY7C408. CY7C409~UcrOR ============================~~~==~====~~~~~~~~~~~~~Typical DC and AC Characteristicsu.!:cwN::i«~a:0zNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.2 r----..,r---"""T---,..--...1.00.8VIN =5.0VTA = 25°C0.44.0 4.5 5.0 5.5SUPPLY VOLTAGE (V)6.0u.!:cwN::i«~a:0ZNORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.4 r-----r--------,1.2Vee =5.5 VVIN =5.0 V0.6-55 25 125AMBIENT TEMPERATURE (DC)(Jzw~CwfEcwN::i«~a:0Z1.31.21.1NORMALIZED FREQUENCYvs. SUPPLY VOLTAGE1.00.9 L" ..--0.8---~0.74.0 4.5 5.0 5.5SUPPLY VOLTAGE (V)1.6> 1.5(J~~ 1.4w6.0NORMALIZED FREQUENCYvs. AMBIENT TEMPERATURE1.6>~ 1.4i-----t-------tw~CwfEcwN::i«~a:ozTYPICAL FREQUENCY CHANGEvs. OUTPUT LOADING--- ./VCfEc 1.3wN::i« 1.2~a:0 /z 1.1//LV1.0o 200 400 600 800 1000CAPACITANCE (pF)0.6 '------'--------'-55 25 125AMBIENT TEMPERATURE (DC)t.l.::cwN::i«

5nCY7C408. CY7C409~U~==========================================================~======Ordering InformationFrequencyPackage OperatingOrdering Code(MHz) Type RangeFrequencyPackage OperatingOrdering Code(MHz) Type Range35 CY7C408-35PC P21 Commercial 35 CY7C409-35PC P21 CommercialCY7C408-35DC D22 CY7C409-35DC D22CY7C408-35LC L64 CY7C409-35LC L64CY7C408-35VC V21 CY7C409-35VC V2125 CY7C408-25PC P21 Commercial 25 CY7C409-25PC P21 CommercialCY7C408-25DC D22 CY7C409-25DC D22CY7C408-25LC L64 CY7C409-25LC L64CY7C408-25VC V21 CY7C409-25VC V21CY7C408-25DMB D22 Military I CY7C409-25DMB D22 MilitaryCY7C408-25LMB L64 CY7C409-25LMB L6415 CY7C408-15PC P21 Commercial 15 CY7C409-15PC P21 CommercialCY7C408-15DC D22 CY7C409-15DC D22CY7C408-15LC L64 CY7C409-15LC L64CY7C408-15VC V21 CY7C409-15VC V21CY7C408-15DMB D22 Military CY7C409-15DMB D22 MilitaryCY7C408-15LMB L64 CY7C409-15LMB L645-46

finCY7C408. CY7C409~~UcrOR================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3los 1,2,3ICCQ 1,2,3Switching CharacteristicsParameters Subgroupsfo 7,8,9,10,11tpHSI 7,8,9,10,11tpLSI 7,8,9,10,11tSSI 7,8,9,10,11tHSI 7,8,9,10,11tDLlR 7,8,9,10,11tDHIR 7,8,9,10,11tpHSO 7,8,9,10,11tPLSO 7,8,9,10,11tDLOR 7,8,9,10,11tDHOR 7,8,9,10,11tSOR 7,8,9,10,11tHSO 7,8,9,10,11tBT 7,8,9,10,11tSIR 7,8,9,10,11tHlR 7,8,9,10,11tpIR 7,8,9,10,11tpOR 7,8,9,10,11tDLZOE 7,8,9,10,11tDHZOE 7,8,9,10,11tDHHF 7,8,9,10,11tDLHF 7,8,9,10,11tDLAFE 7,8,9,10,11tDHAFE 7,8,9,10,11Document #: 38-00059-BParameters SubgroupstB 7,8,9,10,11tOD 7,8,9,10,11tpMR 7,8,9,10,11tDSI 7,8,9,10,11tDOR 7,8,9,10,11tDIR 7,8,9,10,11tLZMR 7,8,9,10,11tAFE 7,8,9,10,11tHF 7,8,9,10,115-47

Features• 512 x 9, 1024 x 9, 2048 x 9FIFO buffer memory• Dual port RAM cell• Asynchronous read/write• High speed 25 MHz read/writeindependent of depth/width• Low operating powerIcc (max.) = 100 mA commercialIcc (max.) = 120 mA military• Lower standby powerIcc (max.) = 15 mA commercialIcc (max.) = 20 mA military• Half full flag in standalone• Empty and full flags• Retransmit in standalone• Expandable in width and depth• Parallel Cascade minimizesbubblethrough• 5V ± 10% supply• 300 mil DIP packaging• TTL compatible• Three-state outputsPRELiMINARYCYPRESSSEMICONDUCTOR• CY7C421 pin compatible andfunctional equivalent to IDT7201Functional DescriptionThe (CY7C420, CY7C421,)(CY7C424, CY7C425,) and(CY7C428, CY7C429) are, respectively,512, 1024 and 2048 words by 9-bitwide first-in first-out (FIFO) memoriesoffered in 300 mil wide and 600 milwide packages, respectively. EachFIFO memory is organized such thatthe data is read in the same sequentialorder that it was written. Full andEmpty flags are provided to preventover-run and under-run. Three additionalpins are also provided to facilitateunlimited expansion in width,depth, or both. The depth expansiontechnique steers the control signalsfrom one device to another in parallel,thus eliminating the serial addition ofpropagation delays so that throughputis not reduced. Data is steered in a similarmanner.The read and write operations may beasynchronous; each can occur at a rateof 25 MHz. The write operation occursCY7C420, CY7C421, CY7C424CY7C425, CY7C428, CY7C429Cascadeable 512 X 9 FIFOCascadeable 1024 X 9 'FIFOCascadeable 2048 X 9 FIFOwhen the Write (W) signal is LOW.Read occurs when Read (R) goesLOW. The 9 data outputs go to thehigh impedance state when R isHIGH.A Half-Full (lIP) output flag is providedthat is valid in the standalone andwidth expansion configurations. In thedepth expansion configuration this pinprovides the expansion out (XO) informationwhich is used to tell the nextFIFO that it will be activated.In the standalone and width expansionconfigurations a LOW on the Retransmit(RT) input causes the FIFO's toretransmit the data. Read Enable (R)and Write Enable (W) must both beHIGH during a retransmit cycle, andthen R is used to access the data.The CY7C420, CY7C421, CY7C424,CY7C425, CY7C428 and CY7C429are fabricated using an advanced 0.8micron N-well CMOS technology. InputESD protection is greater than2000V and latchup is prevented bycareful layout, guard rings and a substratebias generator.Logic Block DiagramPin ConfigurationsDATA INPUTS(00-08)PLCC/LCCTop View"~ ~I:r:: ~;;,~:g02 5 43 2 032313~901 6 28DO 7 27Xi ~8 26IT ~9 2500 10 2401 )11 23NC )12 2202 ~13 21'" 14151617181920tot') 00 c OIl:r "'It It)OO~Z 000607NCF'L/RTi.4RITXliiHi'07060081-3Vi08020101020308GNODIPTop ViewVee04050607FLIRT'ITXliiHi'070605040081-2Xi-----+t0081-15-48

fWlCY7C420, CY7C421, CY7C424. PRELIMINARY CY7C425, CY7C428, CY7C429Selection Guide~aID~======================================================~======~7C420·30, 7C421·30 7C420·40,7C421·40 7C420.65,7C421·657C424-30, 7C425·30 7C424-40, 7C425·40 7C424-65, 7C425·657C428·30, 7C429·30 7C428-40, 7C429·40 7C428·65, 7C429·65Frequency (MHz) 25 20 12.5Access Time (ns) 30 40 65Maximum Operating I Commercial 100 90 80Current (mA)I Military 120 110 100Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ............... '" ... >2001VAmbient Temperature with(per MIL·STD·883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-up Current .......................... > 200 rnASupply Voltage to Ground Potential .... -0.5V to + 7.0VOperating RangeDC Voltage Applied to Outputsin High Z State ...................... -0.5V to +7.0VAmbientRangeTemperatureVeeDC Input Voltage ................... -3.0Vto +7.0VCommercial O°Cto +70°C 5V ± 10%Power Dissipation ............................. 1.0WMilitary [3] - 55°C to + 125°C 5V ±10%Output Current, into Outputs (Low) ............. 20 rnAElectrical Characteristics Over Operating Range[4]CY7C420·30 CY7C420·40 CY7C420·65CY7C421·30 CY7C421·40 CY7C421·65Parameters Description Test ConditionsCY7C424-30 CY7C424-40 CY7C424-65 UnitsCY7C425·30 CY7C425·40 CY7C425·65CY7C428·30 CY7C428·40 CY7C428·65CY7C429·30 CY7C429·40 CY7C429·65Min. Max. Min. Max. Min. Max.VOH Output HIGH Voltage Vee = Min.,loH = -2mA 2.4 2.4 2.4 VVOL Output LOW Voltage Vee = Min., IOL = 8.0 mA 0.4 0.4 0.4 VVIH Input HIGH VoltageCommercial 2.0 Vee 2.0 Vee 2.0 Vee VMilitary 2.2 Vee 2.2 Vee 2.2 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIIX Input Leakage Current GND S VI S Vee -10 +10 -10 + 10 -10 +10 p,Alee Operating CurrentVee = Max., Commercial[S] 100 90 80 mAlOUT = OmA Military [6] 120 110 100 mAISB} Standby CurrentCommercial 15 8 8 mAR=W=MR=FLIRT=VIHMilitary 20 20 15 mAISB2All Inputs Commercial 5 5 5 mAPower Down Current Vee -0.2V Military 9 9 9 mAlosOutput Short CircuitCurrent [1] Vee = Max., VOUT = GND -90 -90 -90 mACapacitance [2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 5pFCOUTOutput CapacitanceVee = 4.5V 7Notes:1. For test purposes, not more than one output at a time should beshorted. Short circuit test duration should not exceed 30 seconds.2. Tested initially and after any design or process changes that mayaffect these parameters.3. TA is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.5. IcC

finCY7C420, CY7C421, CY7C424. PRELIMINARY CY7C425, CY7C428, CY7C429~DUcroR =====================================================================AC Test Load and WaveformEquivalent to:R1 500.0.5V 0---1+1..,.,.--,OUTPUT 0-.... ---....L30 PFINCLUDING- JIG AND _- SCOPEFigure 1THEVENIN EQUIVALENTR2333.0.0081-43.0V----j~~--........5 ns .. 5nlFigure 2. All Input Pulses0081-5200.0.OUTPUT~2V0081-6Switching Characteristics Over the Operating Range[l, 3]ParameterDescription7C420·30,7C421.307C424·30, 7C425·307C428·30, 7C429·30Min.tRe Read Cycle Time 40Max.tA Access Time 30tRR Read Recovery Time 10tpR Read Pulse Width 30tLZR Read LOW to Low Z 3tDVR Read HIGH to Data Valid 3tHzR Read HIGH to High Z 20twc Write Cycle Time 40tpw Write Pulse Width 30tHWZ Write HIGH to Low Z 10tWR Write Recovery Time 10tSD Data Set-Up Time 18tHD Data Hold Time 0tMRSC MR Cycle Time 40tPMR MR Pulse Width 30tRMR MR Recovery Time 10tRPW Read HIGH to MR HIGH 30twpw Write HIGH to MR HIGH 30tRTc Retransmit Cycle Time 40tpRT Retransmit Pulse Width 30tRTR Retransmit Recovery Time 10tEFL MRto EF LOW 40tHPH MR to IfF HIGH 40tFFH MR to FF HIGH 40tREF Read LOW to EF LOW 30tRFF Read HIGH to FF HIGH 30tWEP Write HIGH to EF HIGH 30twpp Write LOW to FF LOW 307C420·40,7C421·40 7C420·65,7C421·657C424·40, 7C425·40 7C424-65, 7C425·657C428·40, 7C429·40 7C428.65, 7C429·65UnitsMin. Max. Min. Max.50 80 ns40 65 ns10 15 ns40 65 ns3 3 ns3 3 ns25 30 ns50 80 ns40 65 ns10 10 ns10 15 ns20 30 ns0 10 ns50 80 ns40 65 ns10 15 ns40 65 ns40 65 ns50 80 ns40 65 ns10 15 ns50 80 ns50 80 ns50 80 ns35 60 ns35 60 ns35 60 ns35 60 ns5·50

5ACY7C420, CY7C421, CY7C424. PRELIMINARY CY7C425, CY7C428, CY7C429~U~~================================================================Switching Characteristics Over the Operating Range[l, 3] (Continued)ParametertWHFtRHFtRAEtRPEtWAFtWPFtXOLtXOH[2]DescriptionWrite LOW to HF LOWRead HIGH to HF HIGHEffective Read from Write HIGHEffective Read PulseWidth after EF HIGHEffective Write from Read HIGHEffective Write PulseWidth after FF HIGHExpansion Out LOWDelay from ClockExpansion Out HIGHDelay from Clock7C420.30, 7C421·30 7C420·40,7C421·40 7C420.65,7C421.657C424-30, 7C425·30 7C424·40, 7C425·40 7C424·65, 7C425·657C428·30, 7C429·30 7C428·40, 7C429·40 7C428.65, 7C429·65Min.Notes:1. Test conditions assume signal transition time of 5 ns or less, timingreference levels of l.5V and output loading of the specified lor/IOHand 30 pF load capacitance, as in Figure 1 a.Switching WaveformsAsynchronous Read and Write Timing Diagram3030Max. Min. Max. Min. Max.40403040505035658080603035 6040 65252535 5535 60Unitsnsnsns2. tXOH is guaranteed to be greater than or equal to tXOL under allconditions.3. See the last page of this specification for Group A subgroup testinginformation.nsnsnsnsnsQO-Qa-----------lXy ,~',~_________J,~~,'~________J-----------1 ~ _________ l--------....j( DATA IN VALID »)0-------0081-7Master Reset Timing Diagram1------tt.lRSC [1J -------11+-----tpt.lR -----~MR -------~II_--~---------------HF________ ~----------J'Notes:1. tMRSC = tpMR + tRMR.IT____________________ J2. Wand R = V IH around the rising edge of MR.0081-85-51

~CY7C420, CY7C421, CY7C424. PRELIMINARY CY7C425, CY7C428, CY7C429~U~ ~================================================================Switching Waveforms (Continued)Half-Full Flag Timing DiagramHALF-FULL HALF-FULL + 1 HALF-FULLtRHF l+--RiI-twHF-HF " JIr--0081-9Last WRITE to First READ Full Flag Timing DiagramADDITIONALLAST WRITE FIRST READ READS FIRST WRITE0081-10Last READ to First WRITE Empty Flag Timing DiagramADDITIONALLAST READ FIRST WRITE WRITES FIRST READDATA OUT -...... --C~rl''---J0081-11Retransmit Timing Diagram,1\t pRT -t RTC'IjR.WNotes:1. tRTC = tRT + tRTR·j.--tRTR -"0081-122. EF. HF and FF may change state during retransmit as a result oftheoffset of the read and write pointers, but flags will be valid at tRTC.5-52

5nCY7C420, CY7C421, CY7C424. PRELIMINARY CY7C425, CY7C428, CY7C429~~UcrOR~~~~~~~~~~~~~~~~~~~======~==============~=========Switching Waveforms (Continued)Empty Flag and Read Bubble-Through Mode Timing DiagramDATA IN--~I~------------------------------------------DATAOUT---1--------------11~~~~~~~~~>--------------------0081-13Full Flag and Write Bubble-Through Mode Timing DiagramFF--~------------~----,.DATA IN --+-------------------C 1'---.oJ1t~DATA OUT -----~DATA OUT VALlO)@----------------0081-14Expansion Timing DiagramsWRITE TO LAST PHYSICALLOCATION OF DEVICE 1-----'\.,WRITE TO FIRST PHYSICALLOCATION OF DEVICE 20081-15READ FROM LAST PHYSICALLOCATION OF DEVICE 1READ FROM FIRST PHYSICALLOCATION OF DEVICE 2*Expansion Out of Device 1 (XOt) is connected to Expansion In of Device 2 (X02).0081-165-53

(;nCY7C420, CY7C421, CY7C424. CYPRFSS PRELIMINAR Y CY7C425, CY7C428, CY7C429ArchitectureSEMICONDUCTOR :;::;;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:=;:;;;;;;:;:;;;;;;:;:;;;;;;:;:;;;;;;:;;;;;;:;;;;;;:;:;;;;;;:;:;;;;;;:;:::;::The CY7C420/421/424/425/428/429 FIFOs consist of anarray of 512/1024/2048 words of 9-bits each (implementedby an array of dual port RAM cells), a read pointer, a writepointer, control signals (W, R, XI, XO, FL, RT, MR) andFull, Half Full, and Empty flags.Dual Port RAMThe dual port RAM architecture refers to the basic memorycell used in the RAM. The cell itself enables the readand write operations to be independent of each other,which is necessary to achieve truly asynchronous operationof the inputs and outputs. A second benefit is that the timerequired to increment the read and write pointers is muchless than the time that would be required for data to propagatethrough the memory, which would be the case if thememory were implemented using the conventional registerarray architecture.Resetting the FIFOUpon power up, the FIFO must be reset with a MasterReset (MR) cycle. This causes the FIFO to enter the emptycondition signified by the Empty flag (EF) being LOW,and both the H~lf-Full (HF) and Full flag (FF) resetting toHIGH. Read (R) and Write (W) must be HIGHtRPW /twpw before and tRMR after the rising edge of MRfor a valid reset cycle.Writing Data to the FIFOThe availability of an empty location is indicated by theI:!!GH state of the Full flag (FF). A falling edge of Write(W) initiates a write cycle. Data appearing at the inputs(DO-D8) tSD before and tHD after the rising edge ofWwill be stored sequentially in the FIFO.The Empty flag (EF) LOW to HIGH transition occurstWEF after the first LOW to HIGH transition on the writeclock of an empty FIFO. The Half-Full flag (HF) will goLOW on the falling edge of the write clock following theoccurrence of half full. HF will remain LOW while lessthan one half of the total memory of this device is availablefor writing. The LOW to HIGH transition of the HF flagoccurs on the rising edge of Read (R). HF is available inSingle Device Mode only. The Full flag (FF) goes low onthe falling edge of W during the cycle in which the lastavailable location in the FIFO is written, prohibiting overflow.FF goes HIGH tRFF after the completion of a validread of a full FIFO.Reading Data from the FIFOThe falling edge of Read (R) initiates a read cycle if theEmpty flag (EF) is not LOW. Data outputs (QO-Q8) are ina high impedance condition between read operations(R HIGH), when the FIFO is empty, or when the FIFO isin the Depth Expansion Mode but is not the active device.The falling edge ofR during the last read cycle before theempty condition triggers a HIGH to LOW transition ofEF, prohibiting any further read operations until tWEF aftera valid write.RetransmitThe Retransmit feature is beneficial when transferringpackets of data. It enables the receipt of data to be interrogatedby the receiver and retransmitted if necessary.The Retransmit (R T) input is active in the Single DeviceMode only. A LOW pulse on RT resets the internal readpointer to the first physical location of the FIFO. The writepointer is unaffected. Rand W must both be HIGH duringa retransmit cycle. Full, Half Full and Empty flags aregoverned by the relative locations ofthe Read and Writepointers and will be updated by a retransmit operation.Single DeviceIWidth Expansion ModesSingle Device and Width Expansion Modes are entered bygrounding XI during a MR cycle. During these modes theHF and RT features are available. FIFOs can be expandedin width to provide word widths greater than 9 in incrementsof9. During Width Expansion Mode all control lineinputs are common to all devices and flag outputs from anydevice can be monitored.Depth Expansion Mode (Figure 3)Depth Expansion Mode is entered when, during a MR cycle,Expansion Out (XO) of one device is connected toExpansion In (XI) of the next device, with XO of the lastdevice connected to XI of the first device. In the DepthExpansion Mode the First Load (FL) input, when grounded,indicates that this part is the first to be loaded. Allother devices must have this pin HIGH. To enable thecorrect FIFO, XO is pulsed LOW when the last physicallocation of the previous FIFO is written to and is pulsedLOW again when the last physical location is read. Onlyone FIFO is enabled for read and one is enabled for writeat any given time. All other devices are in standby.FIFOs can also be expanded simultaneously in depth andwidth. Consequently, any depth or width FIFO can be createdof word widths in increments of9. When expanding indepth, a composite FF must be created by OR-ing the FFstogether. Likewise, a composite EF is created by OR-ingthe EFs together. HF and RT functions are not available inDepth Expansion Mode.5-54

(inCY7C420, CY7C421, CY7C424• CYPRFSS PRELIMINAR Y CY7C425, CY7C428, CY7C429S~CaIDUcrOR ================================================================Architecture (Continued)XC)ViRFF CY7C420 EF9 1 9, .. CY7C421 9,CY7C424-'"D I I CY7C425 I Qf-->, , r CY7C428 r~ CY7C429 I~ f'[ VeeXiFULL ~XC):~u~ EMPTYFF CY7C420...9, .. CY7C421CY7C424 I--I, rCY7C425 I--CY7C428I~ f'[~ CY7C429 !--'"'"""XiRSXC)...... • I~u -FF CY7C420---9, .. CY7C421CY7C424I CY7C425' r CY7C428CY7C429~~~Xi-Figure 3. Depth Expansion• FIRST DEVICE0081-175-55

finCY7C420, CY7C421, CY7C424. . PRELIMINARY CY7C425, CY7C428, CY7C429~UcrOR==================================================================Ordering InformationSpeedPackage Operating(ns)Ordering CodeSpeedPackage OperatingType RangeOrdering Code(ns) Type Range30 CY7C420-30PC P15 Commercial 30 CY7C421-30PC P21 CommercialCY7C420-30DC D16 CY7C421-30JC J65CY7C420-30DMB D16 Military CY7C421-30VC V2140 CY7C420-40PC P15 Commercial CY7C421-30DC D22CY7C420-40DC D16CY7C421-30LC L55CY7C420-40DMB D16 MilitaryCY7C421-30DMB D22 Military65 CY7C420-65PC P15 CommercialCY7C421-30LMB L55CY7C420-65DC D1640 CY7C421-40PC P21CY7C420-65DMB D16 MilitaryCY7C421-40JC J65CommercialCY7C421-40VC V21CY7C421-40DC D22CY7C421-40LC L55CY7C421-40DMB D22 MilitaryCY7C421-40LMB L5565 CY7C421-65PC P21 CommercialCY7C421-65JC J65CY7C421-65VC V21CY7C421-65DC D22CY7C421-65LC L55CY7C421-65DMB D22 MilitaryCY7C421-65LMB L55SpeedPackage OperatingSpeedPackage Operating(ns)Ordering CodeOrdering CodeType Range(ns) Type Range30 CY7C424-30PC P15 Commercial 30 CY7C425-30PC P21 CommercialCY7C424-30DC D16 CY7C425-30JC J65CY7C424-30DMB D16 Military CY7C425-30VC V2140 CY7C424-40PC P15 Commercial CY7C425-30DC D22CY7C424-40DC D16 CY7C425-30LC L55CY7C424-40DMB D16 Military CY7C425-30DMB D22 Military65 CY7C424-65PC P15 Commercial CY7C425-30LMB L55CY7C424-65DC D16 40 CY7C425-40PC P21 CommercialCY7C424-65DMB D16 Military CY7C425-40JC J65CY7C425-40VC V21CY7C425-40DC D22CY7C425-40LC L55CY7C425-40DMB D22 MilitaryCY7C425-40LMB L5565 CY7C425-65PC P21 CommercialCY7C425-65JC J65CY7C425-65VC V21CY7C425-65DC D22CY7C425-65LC L55CY7C425-65DMB D22 MilitaryCY7C425-65LMB L555-56

(;JlCY7C420, CY7C421, CY7C424. PRELIMINARY CY7C425, CY7C428, CY7C429~~================================================================Ordering Information (Continued)SpeedPackage OperatingOrdering Code(ns) Type RangeSpeedPackage OperatingOrdering Code(ns) Type Range30 CY7C428-30PC P15 Commercial 30 CY7C429-30PC P21 CommercialCY7C428-300C 016 CY7C429-30JC J65CY7C428-300MB 016 Military CY7C429-30VC V2140 CY7C428-4OPC P15 Commercial CY7C429-300C 022CY7C428-400C 016 CY7C429-30LC L55CY7C428-400MB 016 Military CY7C429-300MB 022 Military65 CY7C428-65PC P15 Commercial CY7C429-30LMB L55CY7C428-650C 016 40 CY7C429-4OPC P21 CommercialCY7C428-650MB 016 Military CY7C429-4OJC J65CY7C429-4OVCV21CY7C429-400C 022CY7C429-4OLCL55CY7C429-400MB 022 MilitaryCY7C429-4OLMBL5565 CY7C429-65PC P21 CommercialCY7C429-65JCCY7C429-65VCJ65V21CY7C429-650C 022CY7C429-65LCL55CY7C429-650MB D22 MilitaryCY7C429-65LMBL555-57

(inCY7C420, CY7C421, CY7C424. PRELIMINARY CY7C425, CY7C428, CY7C429~UaDR~============================================~============~MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IIX 1,2,3Icc 1,2,3ISBI 1,2,3ISB2 1,2,3los 1,2,3SubgroupsSwitching CharacteristicsParameters SubgroupstRC 9,10,11tA 9,10,11tRR 9,10,11tpR 9,10,11tLZR 9,10,11tovR 9,10,11tHZR 9,10,11twc 9,10,11tpw 9,10,11tHWZ 9,10,11tWR 9,10,11tso 9,10,11tHO 9,10,11tMRSC 9,10,11tpMR 9,10,11tRMR 9,10,11tRPW 9,10,11twpw 9,10,11tRTC 9,10,11tpRT 9,10,11tRTR 9,10,11tEFL 9,10,11tHFH 9,10,11tFFH 9,10,11Document #: 38-00079Parameters SubgroupstREF 9,10,11tRFF 9,10,11tWEF 9,10,11tWFF 9,10,11tWHF 9,10,11tRHF 9,10,11tRAE 9,10,11tRPE 9,10,11tWAF 9,10,11tWPF 9,10,11tXOL 9,10,11tXOH 9,10,11tXCH 9,10,11tPXF 9,10,11tXIR 9,10,11tXIS 9,10,115-58

CYPRESSSEMICONDUCTORCY7C51016 X 16 MultiplierAccumulatorFeatures• Fast- CY7C510·45 has a 45 ns(max.) clock cycle(commercial)- CY7C510·55 has a 55 ns(max.) clock cycle (military)• Low Power- Icc (max. at 10 MHz)100 mA (commercial)- Icc (max. at 10 MHz)110 mA (military)• Vee Margin- 5V ± 10%- All parameters guaranteedover commercial and militaryoperating temperature range• 16 X 16 bit parallelmultiplication with accumulationto 35·bit result• Two's complement or unsignedmagnitude operation• ESD Protection- Capable of withstandinggreater than 2000V staticdischarge voltage• Pin compatible and functionallyequivalent to Am29510 andTMC2110Functional DescriptionThe CY7C51O is a high·speed 16 X 16parallel multiplier accumulator whichoperates at 45 ns clocked multiply ac·cumulate (MAC) time (22 MHz multi·ply accumulate rate). The operandsmay be specified as either two's com·plement or unsigned magnitude 16·bitnumbers. The accumulator functionsinclude loading the accumulator withthe current product, adding or subtractingthe accumulator contents andthe current product, or preloading theaccumulator from the external world.All inputs (data and instructions) andoutputs are registered. These independentlyclocked registers are positiveedge triggered D-type flip-flops. The35-bit accumulator/output register isdivided into a 3-bit extended product(XTP), a 16-bit most significant prod·uct (MSP), and a 16-bit least significantproduct (LSP). The XTP andMSP have dedicated ports for threestateoutput; the LSP is multiplexedwith the V-input. The 35-bit accumulator/outputregister may be preloadedthrough the bidirectional output ports.Logic Block DiagramCLKX >--_---_t;;:-;;;;;;,CLKY '>--....!-------4---.JTCRNOACC350057-1Selection Guide7C510·457C510·557C510·65 7C510·75Maximum Multiply-Accumulate Time (ns)CommercialMilitary45555565 7565 755-59

~ CY7C510~~~~u~================================================================Maximum Ratings(Above which the useful life may be impaired. For userguidelines, not tested.)Ambient Temperature Under Bias .... - 55°C to + 125°CSupply Voltage to Ground Potential .... - O. 5V to + 7.0VDC Input Voltage ................... -0.5V to + 7.0VDC Voltage Applied to Outputs ..... - 0.5V to Vee Max.Output Current, into Outputs (low) .............. 10 rnAStatic Discharge Voltage ..................... >2001V(per MIL-STD-883 Method 3015)Pin ConfigurationsOperating RangeRange Temperature VeeCommercial O°C to +70°C 5V ±1O%Military [1] - 55° to + 125°C 5V ±1O%Note:1. T A is the "instant on" ease temperature.X6 X 7X5XaX 4XgX3X l0X 2X llXl X 12XoX13YO' Po X 14Y l ,P l X 15Y 2 ,P 2OElY 3 ,P 3RNDY 4 ,P 4SUBY 5 ,P 5ACeY 6 ,P 6ClKXY 7 ,P 7ClKYGNDVeeYa'PaTCYg.PgOEXYl0·Pl0PRElY ll ,P 1lOEMY 12 ,P 12ClKP0-• ..., N __ 0>:>:-----~m~~~~...,N-OOxxxxxxxxxxxxxxx~~a 7 6 5 4 3 2 l!.J68 67 66 65 6463 62 61XIS 60 P2'Y2on. 59 P3'Y3RNOP4'Y4SUBPs·YsACCP6'Y6CLKX 55 P7'Y7CLKY 54 GNOVee 53 GNOVee 52 Ps·YsVee 51 Pg.YgVee 50 PIO·YIOTC 49 Pll' Y l1OEX 48 P12'Y12PREL 47 P13'Y13OEM 46 P14'Y14CLKP 45 P 1S·Y1SP 34 44 P 162728293031 323334353637383940414243tt)N_OCftCO"CO&t) .... f'I')N_OCftCO .....tt)...,....,...,NNNNNC'lNNNN---~~~~~~~~~~~~~~~~~0057-3Y 13 ,P 13 P 34Yu • P u P 33Y 15 ,P 15 P 32P 16P 3lP 17P 30PIa P 29P 19P 28P 20P 27P 21P 26P 22P 25P 23P 240057-25-60

5r~CY7C510Pin Configurations (Continued)Pin Configuration for 68·Pin Grid Array0) 8 e e 8 G 8 8 e51 50 48 46 44 42 40 38 368 8 8 e 8 e 8 G e e 0)53 52 49 47 45 43 41 39 37 35 34(0 8 8 e55 54 32 330 e e eG 0e e0 0 e e57 56 30 3159 58 28 2961 60 26 27G 0 e 88 8 e e8 0 e ee 8 8 8 8 8 8 8 8 e e63 62 24 2565 64 22 2367 66 20 211 3 5 7 9 11 13 15 18 198 8 8 e 8 8 8 8 e2 4 6 8 10 12 14 16 170057-135·61

~ CY7C510~~~NDUcrOR ========================================================~========~~=Pin DefinitionsSignalNameI/ODescriptionSignalNameI/ODescriptionX15-0 I X-Input Data. This 16-bit number may be OEL I Output Enable Least. When LOW, theinterpreted as two's complement orLSP bidirectional port is enabled forunsigned magnitude.output. When HIGH, the output driversY15-0 I/O Y-Input Data/LSP Output Data. Whenare disabled (high impedance) and the(PIS-O) this port is used to input a Y value, theMSP port may be used for preloading. See16-bit number may be interpreted as two'sPreload Function Table.complement or unsigned magnitude. This PREL I Preload. When HIGH, the threebidirectional port is multiplexed with thebidirectional ports may be used to preloadLSP output (PIS-O), and can also be useddata into the accumulator register at theto preload the LSP register.rising edge of CLKP. The three-stateP34-32 I/O Extended Product (XTP) Output Data.controls (OEX, OEM, OEL) must beThis port is bidirectional. The extendedHIGH to preload data.product emerges through this port. TheWhen LOW, the accumulated product isXTP register may also be preloadedloaded into the accumulator/outputthrough this port.register at the rising edge of CLKP. Theoutput drivers must be enabled (OEX,P31-I6 I/O MSP Output Data. This port isOEM, OEL must be LOW) for thebidirectional. The most significantaccumulated product to be output.product emerges through this port. TheOrdinarily, PREL, OEX, OEM, and OELMSP register may also be preloadedare tied together. See accumulatorthrough this port.function table.PI5-0 I/O LSP Output Data. This port isbidirectional. The least significantproduct emerges through this port. TheLSP register may also be preloadedthrough this port.CLKX I X-Register Clock. X-Input Data arelatched into the X-register at the risingedge of CLKX.CLKY I Y-Register Clock. Y-Input Data arelatched into the Y-register at the risingedge ofCLKY.CLKP I Product Register Clock. XTP, MSP, andLSP are latched into their respectiveregisters at the rising edge ofCLKP. Ifpreload is selected, these registers areloaded with the preload data at the outputpins via the bidirectional ports. If preloadis not selected, these registers are loadedwith the current accumulated product.OEX I Output Enable Extended. When LOW,the extended product bidirectional port isenabled for output. When HIGH, theoutputs drivers are disabled (highimpedance) and the XTP port may beused for preloading. See Preload FunctionTable.OEM I Output Enable Most. When LOW, theMSP bidirectional port is enabled foroutput. When HIGH, the output driversare disabled (high impedance) and theMSP port may be used for preloading. SeePreload Function Table.5-62TC I Two's Complement Control. WhenHIGH, the 7C510 is in two's complementmode, where the input and output dataare interpreted as two's complementnumbers. The device is in unsignedmagnitude mode when TC is LOW. Thiscontrol is loaded into the instructionregister at the rising edge of CLKX +CLKY.RND I Round Control. When HIGH, roundingis enabled and a "I" is added to the MSBofthe LSB (PIS). When LOW, theproduct is unchanged. This control isloaded into the instruction register at therising edge ofCLKX + CLKY.ACC I Accumulate Control. When HIGH, theaccumulator/output register contents areadded to or subtracted from the currentproduct (XY) and this result is storedback into the accumulator/outputregister. When LOW, the product isloaded into the accumulator register,overwriting the current contents. Thiscontrol is loaded into the instructionregister at the rising edge of CLKX +CLKY. See accumulator function table.SUB I Subtract Control. When both ACC andSUB are HIGH, the accumulator registercontents are subtracted from the currentproduct XY and this result is written backinto the accumulator register. When ACCis HIGH and SUB is LOW, theaccumulator register contents and currentproduct are summed, then written back tothe accumulator register. This control isloaded into the instruction register at therising edge of CLKX + CLKY. Seeaccumulator function table.

~RE$CY7C510.nEMICONDUcrOR ====================================================================Functional DescriptionThe CY7C51O is a high-speed 16 X 16-bit mUltiplier accumulator(MAC). It comprises a 16-bit parallel multiplierfollowed by a 35-bit accumulator. All inputs (data and instructions)and outputs are registered. The 7C51O is dividedinto four sections: the input section, the 16 X 16 asynchronousmultiplier array, the accumulator, and the output/preloadsection.The input section has two 16-bit operand input registers forthe X and Y operands, clocked by the rising edge of CLKXand CLKY, respectively. The four-bit instruction register(TC, RND, ACC, SUB) is clocked by the rising edge of thelogical OR of CLKX, CLKY.The 16 X 16 asynchronous multiplier array produces the32-bit product of the input operands. Either two's complementor unsigned magnitude operation is selected, based oncontrol TC. If rounding is selected, (RND = 1), a "1" isadded to the MSB of the LSP (position PIS). The 32-bitproduct is zero-filled or sign-extended as appropriate andpassed as a 35-bit number to the accumulator section.The accumulator function is controlled by ACC, SUB, andPREL. Four functions may be selected: the accumulatormay be loaded with the current product; the product maybe added to the accumulator contents; the accumulatorcontents may be subtracted from the current product; orthe accumulator may be preloaded from the bidirectionalports.The output/preload section contains the accumulator/outputregister and the bidirectional ports. This section is controlledby the signals PREL, OEX, OEM, and OEL. WhenPREL is HIGH, the output buffers are in high impedancestate. When the controls OEX, OEM, and OEL are alsohigh, data present at the output pins will be preloaded intothe appropriate accumulator register at the rising edge ofCLKP. When PREL is LOW, the signals OEX, OEM, andOEL are enable controls for their respective three-stateoutput ports.Preload Function TablePREL OEX OEM OELOutput RegisterXTP MSP LSP0 0 0 0 Q Q Q0 0 0 1 Q Q z0 0 1 0 Q z Q0 0 1 1 Q z z0 1 0 0 z Q Q0 1 0 1 Z Q z0 1 1 0 Z z Q0 1 1 1 Z Z Z1 0 0 0 Z Z Z1 0 0 1 Z Z PL1 0 1 0 Z PL Z1 0 1 1 Z PL PL1 1 0 0 PL Z Z1 1 0 1 PL Z PL1 1 1 0 PL PL Z1 1 1 1 PL PL PLZ = Output butTers at High impedance (disabled.)Q = Output butTers at Low impedance. Contents of output registeravailable through output ports.PL = Output disabled. Preload data supplied to the output pins will beloaded into the output register at the rising edge of CLKP.Accumulator Function TablePREL ACC SUB P OPERATIONL L X Q LoadL H L Q AddL H H Q SubtractH X X PL Preload5-63

~ CY7C510~~~U~==================================================================CY7C510Input FormatsFractional Two's Complement Input115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ° I 11_5_14_1_3_12_1_1_10_9 ..... ___ 7 __ 6_5 __ 4_3 __ 2 __ 0 ........ 1-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-1°2-11 2-122-13 2-14 2- 15(Sign)-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-112-12 2-13 2- 14 2- 15(Sign)Integer Two's Complement Input1-11_5_14_1_3_12_1_1_10_9 __ 8_7 __ 6 __ 4 ___ 2 ___ 0---11 115 14 13 12 11 10 9 8 7 6 5 4 2 01_2 15 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20(Sign)Unsigned Fractional Input_215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20(Sign)115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ° I ,-11_5_14_1_3_1_2,,--11_1_0_9___7 _6_5__4_3_2 ___ 0--,12-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-142-152-16 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-13 2-14 2-15 2- 16Unsigned Integer Input,-11_5_14_13_1_2_11_10 __ 9_8_7 __ 6 __ 4 ___ 2 ___ 0-,1 115 14 13 12 11 10 9 7 6 4 2 01215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20YINCY7C510Output FormatsTwo's Complement Fractional OutputXTP MSP LSP134 33 3211313029 28 27 26 25 24 23 22 21 20 19 18 17 161115 14 13 12 11 10 9 6 4 2 ° I-242322 21 2°2-1 2-22-32-42-52-62-72-82-92-10 2-11 2-122-13 2-14 2-152-162-172-182-192-202-212-222-232-242-252-26 2-27 2-28 2-29 2-30(Sign)Two's Complement Integer OutputXTP MSP LSP134 33 321 131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I_234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20(Sign)Unsigned Fractional OutputXTP MSP LSP13433321131 302928 2726252423 22 21 20 19 18 17 161115 14 13 12 11 10 9 6 4 2 012221 20 2-12-22-32-42-52-62-72-82-92-10 2-11 2-122-13 2-142-152-16 2-172-182-192-202-212-222-232-242-252-262-272-28 2-29 2-30 2-31 2-32Unsigned Integer OutputXTP MSP LSP134 33 321 131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 205-64

~ CY7CS10~~~UaoR==================================================================Electrical Characteristics Over Operating Range[4]ParametersVOHVOLVIHVILIOHIOLIIXIIIOSH]IOZLIOZHIcc (Ql)[2]Icc (Q2)[2]DescriptionOutput HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageOutput HIGH CurrentOutput LOW CurrentInput Leakage CurrentInput Current, Max. Input VoltageOutput Short Circuit CurrentOutput OFF (Hi-Z) CurrentOutput OFF (Hi-Z) CurrentSupply Current (Quiescent)Supply Current (Quiescent)IcC (Max.)[2] Supply Current I CommercialI MilitaryCapacitance [3]ParametersDescriptionTest Conditions Min. Max. UnitsVee = Min., IOH = -0.4mA 2.4 VVee = Min., IOL = 4.0 rnA 0.4 V2.0 V0.8 VVee = Min., VOH = 2.4V -0.4 rnAVee = Min., VOL = O.4V 4.0 rnAGND ~ VI ~ Vee -to +to JJ.AVee = Max., VIN = 7.0V to rnAVee = Max., VOUT = 0.5V -3 -30 rnAVee = Max., OE = 2.0V -25 JJ.AVee = Max., OR = 2.0V 25 JJ.AVee = Max.,VIN = [GND to vId or [VIR to VedVee = Max Commercial 20Vee:2: VIN :2: 3.85V0.4V :2: VIN :2: GNDMilitary 25Vee = Max., feLK = 10 MHz30 rnACINInput CapacitanceTA = 25°C, f = 1 MHz 8pFCOUTOutput CapacitanceVee = 5.0VtoNotes:1. Not more than one output should be tested at a time. Duration of the 3. Tested initially and after any design or process changes that mayshort circuit should not be more than one second.affect these parameters.2. For Icc measurements, the outputs are three-stated. Two quiescent 4. See the last page of this specification for Group A subgroup testingfigures are given for different input voltage ranges. To calculate Icc at information.any given clock frequency, use 30 rnA + Icc (A.e.), where Icc(A. C.) = (7 mAIMHz) X Clock Frequency for the Commercial temperaturerange. Icc (A.c.) = (8 rnA/MHz) X Clock Frequency forMilitary temperature range.Output Loads Used for A.C. Performance Characteristics100ItoTest Conditions Max. UnitsNormal Load (Load 1) Three-State Delay Load (Load 2)rnArnAR1n1025.0.5VOUTPUTR240pf I 817.0.R3TO 500.0.OUTPUT~PIN __ -L5.-LP'4V'Equivalent to:THEVENIN EQUIVALENT0057-40057-5455.0.OUTPUT ~ 2.22V0057-65-65

~ CY7C510~~~U~==================================================================Switching Characteristics Over Operating Range[3]ParametersDescription7C510·45 7C510·55 7C510·65 7C510·75Min. Max. Min. Max. Min. Max. Min. Max.tMA Multiply Accumulate Time 45 55 65 75 nsts Setup Time 20 20 25 25 nstH Hold Time 3 3 3 3 nstpw Clock Pulse Width 25 25 30 30 nstPDP Output Clock to P 30 30 35 35 nstpDY Output Clock to Y 30 30 35 35 nstPHZ OEX, OEM to P; HIGHtoZ 25 25 30 30 nstPLZOEL to Y (Disable Time) LOWtoZ 25 25 30 30 nstPZH OEX, OEM to P; ZtoHIGH 30 30 35 35 nstPZLOEL to Y (Enable Time) ZtoLOW 30 30 35 35 nstHCL Relative Hold Time 0 0 0 nsTest WaveformsUnitsTEST Vx OUTPUT WAVEF'OR~ - ~EASURE~ENT LEVELALL tpo'sVeeV OHVOL*1.5VV OH~tpHZ O.OV ~O.5VtpLZ 2.6VtpZHO.OVVOLO.OVO.5V~O.OV2.6V~VOH1.5VSetup and Hold TimeDATAiNPUTtpzL 2.6VXX>

OE~ ___~ CY7C510~~~~u~================================================================CY7C510 Timing DiagramClKXClKYt--- Tpw ----+IClKPOUT~~~TpDPI----+jTpDy-r-XX"""""'X"'"X"'"X"'"X"'"X"'"X"'"X"'"X"'"X"'"X"'"X"'"X"'"X""'X""'X""'X""'X""'X""'X"""X"""X""X""X""X""X""X""X"""X~xxm:::::::::0057-10Preload Timing DiagramClKP/+--- Tpw ---.jPRElOEXOEl~OUTPUT~~~~~--------~~~~~~~~~~~~~~~~~~~~~PINS ~~~~~ ________ .jII\U~llJ~~~~~~~~~QL~~llJ~~~~Three-State Timing Diagram0057-113-STATECONTROL(HIGH LEVEL)~tpHZ-(DISABLE)-'~V OH -O.5VI--tpzH-(ENABLE)f-VOH1.5VVOLVOH1.5V3-STATEOUTPUT(HIGH IMPEDANCE)(LOW LEVEL)f-I--tpLZ-(DISABLE) .VOL +O.5VI--tpZL -ENABLE~1.5VVOL0057-125-67

~ CY7CSIO~~~NDUCTOR =====================================================================Typical AC and DC Characteristics~0.....N~0enI-::::>0-I-::::>0OUTPUT SOURCE CURRENT30 vs OUTPUT VOLTAGE25201510~vee l5VT A=25 O C-'" ~o ~o5O.B 1.6 2.43.2SUPPLY VOLTAGE(V)AMBIENT TEMPERATURE(°C)OUTPUT VOLTAGE (V)1.3NORMALIZED FREQUENCYvs. SUPPLY VOLTAGENORMALIZED FREQUENCYvs. AMBIENT TEMPERATURE1.6 ,...-------r--------,OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE35~.....z::::>8e:.....o!:::!....I0:.::ziiiI-::::>0-l- ::::>03025201510SI/V/"./ ~// Vee = 5.0VTA = 25 0 C-o o 1.0 2.0 3.0 4.0SUPPLY VOLTAGE(V)AMBIENT TEMPERATURE (OC)OUTPUT VOLTAGE(V)NORMALIZED OUTPUT DELAYNORMALIZED Iccvs. OUTPUT LOADINGvs FREQUENCY4.0 1.6",i~ 3.51.4(.)>-

~ CY7C510~~~~UcrOR==================================================================Ordering InformationSpeed (ns) Ordering Code Package Type Operating Range45 CY7C510-45 PC P29 CommercialCY7C510-45 LCL81CY7C51O-45 JCJ81CY7C51O-45 DCD30CY7C51O-45 GCG6855 CY7C51O-55 PC P29 CommercialCY7C51O-55 LCL81CY7C510-55 JCJ81CY7C51O-55 DCD30CY7C51O-55 GCG68CY7C51O-55 LMB L81 MilitaryCY7C510-55 DMBD30CY7C51O-55 GMBG6865 CY7C51O-65 PC P29 CommercialCY7C51O-65 LCL81CY7C51O-65 JCJ81CY7C510-65 DCD30CY7C51O-65 GCG68CY7C510-65 LMB L81 MilitaryCY7C51O-65 DMBD30CY7C51O-65 GMBG6875 CY7C510-75 PC P29 CommercialCY7C51O-75 LCL81CY7C510-75 JCJ81CY7C51O-75 DCD30CY7C51O-75 GCG68CY7C51O-75 LMB L81 MilitaryCY7C51O-75 DMBD30CY7C510-75 GMBG685-69

~ CY7CSI0~~~aIDUcrOR~~~~~~~====~====~====~==~====~======================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IOH 1,2,3IOL 1,2,3IIX 1,2,3II 1,2,3los 1,2,3IOZL 1,2,3IOZH 1,2,3SubgroupsSwitching CharacteristicsParametersSubgroupstMA 7,8,9,10,11ts 7,8,9,10,11tH 7,8,9,10,11tpw 7,8,9,10,11tPDP 7,8,9,10,11tpDY 7,8,9,10,11tpHZ 7,8,9,10,11tpLZ 7,8,9,10,11tpzH 7,8,9,10,11tpZL 7,8,9,10,11tHCL 7,8,9,10,11Document #: 38-00014-BParametersIcC (Q1) 1,2,3ICC (Q2) 1,2,3ICC (Max.) 1,2,3Subgroups5-70

CYPRESSSEMICONDUCTORCY7C516CY7C51716 X 16 MultipliersFeatures• Fast- 38 ns clock cycle(commercial)- 42 ns clock cycle (military)• Low Power- ICC (max. at 10 MHz)100 mA (commercial)- ICC (max. at 10 MHz)110 mA (military)• Vee Margin- 5V ±10%- All parameters guaranteedover commercial and militaryoperating temperatnre range• 16 x 16 bit parallelmultiplication with full precision32-bit product output• Two's complement, unsignedmagnitude, or mixed modemultiplication• CY7C516 pin compatible andfunctionally equivalent toAm29516, MPYOI6K,MPY016H• CY7C517 pin compatible andfunctionally equivalent toAm29517Functional DescriptionThe CY7C516/517 are high-speed 16 x16 parallel multipliers which operate at38 ns clocked multiply times (26 MHzmultiplication rate). The two input operandsmay be independently specifiedas either two's complement or unsignedmagnitude numbers. Controls are providedfor rounding and format adjustmentof the full precision 32-bit product.On the 7C516, individually clocked inputand output registers are providedto maximize throughput and to simplifybus interfacing. On the 7C517, a singleclock (CLK) is provided, alongwith three register enables. This facilitatesthe use of the 7C517 in microprogrammedsystems. The input and outputregisters are positive edge triggeredD-type flip-flops. The output registermay be made transparent for asynchronousoutput.Logic Block DiagramsCY7C516CY7C517TCX X-IN ClKX RND ClKYY-IN/lSP OUTTCYX-INENX ENY Y-IN/lSP OUTClK>1p---t---;---"'"---f-----'32FAFTENPt.tSPSElt.tSP OUT /lSP OUT 0054-1t.tSP OUT/lSP OUT 0054-12Selection Guide7C516-387C517-387C516-427C517-427C516-457C517-457C516-55 7C516-757C517-55 7C517-75Maximum Multiply Time (ns) Commercial 38/58Clocked/UnclockedMilitary42/6545/6555/75 75/10055/75 75/1005-71

5ACY7CS16. CY7CS17~~UcrOR=====================================================================Functional Description (Continued)Two output modes may be selected by using the outputmultiplexer control, MSPSEL. Holding MSPSEL LOWcauses the most significant product (MSP) to be availableat the dedicated output port. The LSP is simultaneouslyavailable at the bidirectional port shared with the Y -inputs.Pin ConfigurationsThe other mode of output involves toggling of theMSPSEL control, allowing both the MSP and LSP to beavailable for output through the dedicated 16-bit outputport.X 4XsX3XsX 2 X 7XlXsXoXgOEl X 10(ClK) ClK lX ll(ENY) ClKY X 12YO' Po X 13Y l ,P l X 14 P1S ,P 31Y 2 ,P 2 X 1S P14·P30Y 3 ,P 3 ClKX (ENX) P13• P29Y 4 ,P 4 RND P12• P2SYs·PslCXP l1 ,P 27Pl0·P2SYs·Ps lCY Pg• P 2SY 7 ,P 7 Vee P S ,P 24Ys·Ps Vee P7• P23Yg.Pg GND Ps• P22PY10·P10GNDS ,P 2lP4• P20Yll' Pl1MSPSElP3·P19Y12• P12 FT P2·P1SY 13 ,P 13 FA P l ,P 17Y 14 ,P 14 OEP PO·P1SY1S·P1S ClK M (ENP) NCPO·P1SP 3l .P 1SP l ,P 17 P 3o ,P 14P2• P1S P 29 ,P 13P 3 ,P 19 P 2S ,P 12P 4 .P 20P 27 ,P llPs • P2lP2S' P10Ps • P22P2S' P9P7• P23P24·PS0054-2I ~ ~::::E Vl x~ Ill.. Il.. 0 0 u u >- x 0 ~ It) ~ tI)O...JIoJ

5r~CXX

(;ACY7C516. CY7C517~~~================================================================Maximum Ratings(Above which the useful life may be impaired. For userguidelines, not tested.)Ambient Temperature Under Bias .... - 55°C to + 125°CSupply Voltage to Ground Potential .... -0.5V to + 7.0VDC Input Voltage ................... - O. 5V to + 7.0VDC Voltage Applied to Outputs ..... - O. 5V to Vee Max.Output Current, into Outputs (low) .............. 10 rnAStatic Discharge Voltage ..................... > l000V(per MIL-STD-883 Method 3015)Operating RangeRange Temperature VeeCommercial O°C to +70°C 5V ± 10%Military[l] - 55°C to + 125°C 5V ±1O%Note:1. T A is the "instant on" case temperature.Pin DefinitionsSignalName I/O DescriptionX1S-OY1S-O(P1S-O)P31-16(P1S-O)FfFARNDTCXX.Input Data. This 16-bit number may beinterpreted as two's complement or unsignedmagnitude.I/O Y·lnputlLSP Output Data. This 16-bitnumber may be interpreted as two'scomplement or unsigned magnitude. TheY -input port may be multiplexed with the LSPoutput (P1S-O).o Output Data. This 16-bit port may carry eitherthe MSP (P31-16) or the LSP (P1S-O).The MSP and LSP registers are madetransparent (asynchronous operation) if FT isHIGH.Format Adjust Control. If FA is HIGH, a full32-bit product is output. If FA is LOW, a leftshiftedproduct is output, with the sign bitreplicated in the LSP. FA must be HIGH fortwo's complement integer, unsignedmagnitude, and mixed mode multiplication.Output Multiplexer Control. When MSPSELis LOW, the MSP is available for output at theMSP output port, and the LSP is available atthe Y -input/LSP output port. When MSPSELis HIGH, the LSP is available at both ports(above) and the MSP is not available.Round Control. When RND is HIGH, a one isadded to the MSB of the LSP. This position isdependent on the FA control; FA = HIGHmeans RND adds to the 2- 1S bit (P1S),FA= LOW means RND adds to the 2-16 bit(P14).Two's Complement Control X. X-input dataare interpreted as two's complement whenTCX is HIGH. TCX LOW means the data areinterpreted as unsigned magnitude.SignalNameTCYI/ODescriptionTwo's Complement Control Y. V-Input dataare interpeted as two's complement whenTCY is HIGH. TCY LOW means the dataare interpreted as unsigned magnitude.P31.16l'PlS-O Output Port Three·StateControl. When OEP is LOW, the output portis enabled; when OEP is HIGH, the driversare in a high impedance state.Y ·in/Pls.o Port Three State Control. WhenOEL is LOW, the timeshared port is enabledfor LSP output. When OEL is HIGH, theoutput drivers are in a high impedance state.This is required for Y -input.CY7C516 OnlyCLKX I X·Register Clock. X-input data and TCX arelatched in at the rising edge of CLKX.CLKYCLKMCLKLV-Register Clock. V-input data and TCY arelatched in at the rising edge ofCLKY.MSP Register Clock. The most significantproduct (MSP) is latched in at the MSPRegister at the rising edge of CLKM.LSP Register Clock. The least significantproduct (LSP) is latched in at the LSPRegister at the rising edge of CLKL.CY7C517 OnlyCLK I Clock. All enabled registers latch in their dataat the rising edge of CLK.ENXENYX·Register Enable. When ENX is LOW, theX-Register is enabled. X-input data and TCXwill be latched in at the rising edge of CLKwhen the register is enabled. When ENX isHIGH, the X-Register is in hold mode.X·Register Enable. ENY enables theV-Register. (See ENX.)ENPProduct Register Enable. ENP enables theproduct register. Both the MSP and LSPSections are enabled by ENP. (See ENX.)5-74

WACY7C516. CY7C517~NDUcroR ~~~~~~~~~~~~~~~~~~~~==~~~~~~~~~~~~===Input Formats (All Devices)TCX, TCY = 1XINFractional Two's Complement Input FormatYIN115 14 13 12 11 10 9 7 6 4 2 01 115 14 13 12 11 10 9 7 6 4 2 01-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-142-15 -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-11 2-122-13 2- 14 2- 15(Sign)(Sign)TCX, TCY = 1XINInteger Two's Complement Input Format115 14 13 12 11 10 9 7 6 4 2 01 115 14 13 12 11 10 9 7 6 4 2 01_215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 2° _2 15 214 213 212 211 210 29 28 27 26 25 24 23 22 21 2°(Sign)(Sign)TCX, TCY = 0XINUnsigned Fractional Input Format115 14 13 12 11 10 9 7 6 4 2 01 115 14 13 12 11 10 9 8 7 6 4 2 012-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-112-122-132-142-152-16 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-13 2-14 2- 15 2- 16YINYINUnsigned Integer Input FormatTCX, TCY = 0XINYIN115 14 13 12 11 10 9 7 6 4 2 01 115 14 13 12 11 10 9 7 6 4 2 01215 214 213 212 211 210 29 2 8 27 2 6 25 24 23 22 21 2° 215 214 213 212 211 210 29 2 8 27 2 6 25 24 23 22 21 2°II5-75

finCY7C516- CY7C517~U~================================================================Output Formats (All Devices)FA = 0MSPFractional Two's Complement (Shifted)* Format131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 ~I 1_5 __ 1_4 __ 13 __ 1_2 __ 1_1 __ 10 ___ 9 _____ 7 __ 6 ______ 4 _____ 2 _____-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-142-15(Sign)LSP-20 2-162-172-182-192-202-212-222-232-242-252-262-27 2-28 2-29 2-30(Sign)0~1FA = 1MSPFractional Two's Complement OutputLSP131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10 9 8 7 6 5 4 2 01_21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-112-122-132-14 2-152-162-172-182-192-202-21 2-222-232-242-252-262-272-282-292-30(Sign)FA= 1MSPInteger Two's Complement Output131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10 9 8 7 6 5 4 2 01_231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20(Sign)FA = 1MSPUnsigned Fractional Output131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10 9 8 7 6 4 2 012-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-142-152-16 2-172-182-192-202-212-222-232-242-252-262-272-28 2-29 2-30 2-312-32LSPLSPFA = 1MSPUnsigned Integer Output131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1611 ~ 1_5 __ 1_4 __ 13 __ 1_2 __ 1_1 __ 10 __ 9 ______ 7 __ 6 ______ 4 _____ 2 _____231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20*In this format an overflow occurs in the attempted multiplication of the two's complement number 1.000 ... (-I) with itself, yielding a product of 1.000... 0r-1.LSP0~15-76

WACY7C516. CY7C517~NDUcrOR ==================================================================~Electrical Characteristics Over Operating Range[4]ParametersVOHVOLVIRVIL10H10LIIXlOS [1]10ZL10ZHIcc (Qt)[2]IcC (Q2)[2]Icc (Max.) [2]Capacitance [3]DescriptionOutput HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageOutput HIGH CurrentOutput LOW CurrentInput Leakage CurrentOutput Short Circuit CurrentOutput OFF (Hi-Z) CurrentOutput OFF (Hi-Z) CurrentSupply Current(Quiescent)Supply Current(Quiescent)Supply CurrentCommercial (-38)Military (-42)All OthersCommercialMilitaryCommercialMilitaryTest Conditions Min. Max. UnitsV cc = Min., 10H = - 0.4 rnA 2.4 VV cc = Min., 10L = 4.0 rnA 0.4 V2.0 V0.8 VVcc=Min., VOH=2.4V -0.4 rnAVcc= Min., VOL=0.4V 4.0 rnAVSS :0;; VIN :0;; Vcc, Vcc = Max. -10 10 p,AVcc=Max., VOUT = OV -3 -30 rnAVcc=Max., OE=2.0V -25 p,AVcc = Max., OE=2.0V 25 p,AGND :0;; VIN :0;; VIL or 40VIR :0;; VIN :0;; Vcc;

finCY7C516. CY7C517~UcroR ~~~~~========================================================~Switching Characteristics Over Operating Range[2]ParametersDescription7C516·38 7C516·42 7C516·45 7C516·55 7C516·75Test 7C517·38 7C517·42 7C517·45 7C517·55 7C517·75 UnitsConditionsMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.tMUC Unclocked Multiply Time 58 65 65 75 100 nstMC Clocked Multiply Time 38 42 45 55 75 nsILS Xi, Yi, RND, TCX, TCY Set·up Time 7 8 20 20 25 nstH Xi, Yi, RND, TCX, TCY Hold Time 3 3 3 3 3 nstSE ENX, ENY, ENP Set-up Time (7C5t7 Only) 10 15 20 20 25 nsLoad 1HE ENX, ENY, ENP Hold Time (7C517 Only) 3 3 3 3 3 nsPWH, tPWL Clock Pulse Width (HIGH and LOW) 10 10 20 25 30 nstpDSEL MSPSEL to Product Out 18 21 25 25 30 nsPDP Output Clock to P 25 30 30 30 35 nstpDY Output Clock to Y 25 30 30 30 35 nstpHZOEP Disable TimeHIGHtoZ 15 17 25 25 30 nsPLZ LOWtoZ 15 17 25 25 30 nstPZHOEP Enable TimeZtoHIGH 23 25 30 30 35 nsPZLZtoLOWLoad 223 25 30 30 35 nsPHZOEL Disable TimeHIGHtoZ 15 17 25 25 30 nstPLZ LOWtoZ 15 17 25 25 30 nstPZHOEL Enable TimeZtoHIGH 23 25 30 30 35 nsPZL ZtoLOW 23 25 30 30 35 nsHCLClock Low Hold Time CLKXYRelative to CLKMLll]Notes:1. To ensure that the correct product is entered in the output registers,new data may not be entered into the input registers before the outputregisters have been clocked.Load 10 00 0 02. See the last page of this specification for Group A subgroup testinginformation.nsTest Waveforms (All Devices)TEST Vx OUTPUT WAVEFORM - MEASUREMENT LEVELALL tpo's VeeVOH~V 1.5VOLItpHZ O.OV VOH~O.OVtpLZ 2.6V~2.6VVOL O.5V~VOHtpZH O.OV 1.5VO.OVtPZL2.6V~2.6V 1.5V VOL0054-7Setup and Hold Time (All Devices)':::~--'}:'"~~'TIMINGINPUT-----------3VNotes: 0054-81. Diagram shown for HIGH data only. Output transition may be oppositesense.~:VPulse Width (All Devices)LOW-HI~G-LOW_ PULSE 1 -1.5V= ~2. Cross hatched area is don't care condition.TpWH --~~-- TpWL0054-95-78

~ CY7C516~~~®ucr~================================================~C~Y~7~C~5~1~7Three-State Timing Diagram3-STATECONTROL(HIGH LEVEL)t---tpHZ---

(fACY7C516. CY7C517~NDUcroR ==================================================================~Typical DC and AC Characteristics~0t.JN:::i0t.JN:::i

WACY7C516. CY7C517~~ucr~==================================================================Ordering InformationSpeed Ordering Package Operating Speed Ordering Package Operating(ns) Code Type Range (ns) Code Type Range38 CY7C516-38PC P29 Commercial 55 CY7C516-55PC P29 CommercialCY7C517-38PCCY7C517-55PCCY7C516-38LC L81 CY7C516-55LC L81CY7C517-38LCCY7C517-55LCCY7C516-38JC J81 CY7C516-55JC J81CY7C517-38JCCY7C517-55JCCY7C516-38DC D30 CY7C516-55DC D30CY7C517-38DCCY7C517-55DCCY7C516-38GC G68 CY7C516-55GC G68CY7C517-38GCCY7C517-55GC42 CY7C516-42LMB L81 Military CY7C516-55LMB L81 MilitaryCY7C517-42LMBCY7C517-55LMBCY7C516-42DMB D30 CY7C516-55DMB D30CY7C517-42DMBCY7C517-55DMBCY7C516-42GMB G68 CY7C516-55GMB G68CY7C517-42GMBCY7C517-55GMB45 CY7C516-45PC P29 Commercial 75 CY7C516-75PC P29 CommercialCY7C517-45PCCY7C517-75PCCY7C516-45LC L81 CY7C516-75LC L81CY7C517-45LCCY7C517-75LCCY7C516-45JC J81 CY7C516-75JC J81CY7C517-45JCCY7C517-75JCCY7C516-45DC D30 CY7C516-75DC D30CY7C517-45DCCY7C517-75DCCY7C516-45GC G68 CY7C516-75GC G68CY7C517-45GCCY7C517-75GCCY7C516-75LMB L81 MilitaryCY7C517-75LMBCY7C516-75DMB D30CY7C517-75DMBCY7C516-75GMB G68CY7C517-75GMB5-81

(fACY7C516. . CY7C517~~UaoR~==============================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3IOH 1,2,3IOL 1,2,3IIX 1,2,3los 1,2,3IOZL 1,2,3IOZH 1,2,3IcC (Qt) 1,2,3SubgroupsSwitching CharacteristicsParametersSubgroupstMUC 7,8,9,10,11tMC 7,8,9,10,11ts 7,8,9,10,11tH 7,8,9,10,11tSE 7,8,9,10,11tHE 7,8,9,10,11tPWH, tpwL 7,8,9,10,11tpDSEL 7,8,9,10,11tPDP 7,8,9,10,11tpDY 7,8,9,10,11tpHZ 7,8,9,10,11tpLZ 7,8,9,10,11tPZH 7,8,9,10,11tPZL 7,8,9,10,11tpHZ 7,8,9,10,11tPLZ 7,8,9,10,11tPZH 7,8,9,10,11tpzL 7,8,9,10,11tHCL 7,8,9,10,11Document #: 38-00018-CParametersIcc (Q2) 1,2,3Icc (Max.) 1,2,3Subgroups5-82

Features• FastCY7C901·23 has a 23 nsRead Modify. Write Cycle;Commercial 25% Fasterthan "C" Spec 2901CY7C901·27 has a 27 nsRead Modify·Write Cycle;Military 15% Fasterthan "C" Spec 2901• Low Power70 rnA (commercial)90 rnA (military)• Vee 5V ±10%Commercial and military• Eight Function ALU• Infinitely expandable in 4·bitincrements• Four Status Flags:Carry, overflow, negative, zero• Capable of withstandinggreater than 2000V staticdischarge voltageLogic Block DiagramCYPRESSSEMICONDUCTOR• Pin Compatible and FunctionalEquivalent to Am2901B, CFunctional DescriptionThe CY7C901 is a high-speed, expandable,4-bit wide ALU that can be usedto implement the arithmetic section ofa CPU, peripheral controller, or programmablecontroller. The instructionset of the CY7C901 is basic but yet soversatile that it can emulate the ALUof almost any digital computer.The CY7C901, as illustrated in theblock diagram, consists of a 16-wordby 4-bit dual-port RAM register file, a4-bit ALU and the required data manipulationand control logic.The operation performed is determinedby nine input control lines (10 to Is)CLOCK -~-=-=-=-=.:::-rr===~CY7C901CMOS Four-Bit Slicethat are usually inputs from a microinstructionregister.The CY7C901 is expandable in 4-bitincrements, has three-state data outputsas well as flag output, and can. useeither a full look ahead carry or a nppIecarry.The CY7C901 is a pin compatible,functional equivalent, improved performancereplacement for the Am2901.The CY7C901 is fabricated using anadvanced 1.2 micron CMOS processthat eliminates latchup, results in ESDprotection over 2000V and achieves superiorperformance with low powerdissipation.Pin ConfigurationTop View'A' (READ)ADDRESS'B'(READIWRITE)ADDRESSCARRY IN0030-2DATA OUT0030-15-83

~ CY7C901~~~wu~================================================================Selection Guide See last page for ordering information.Read Modify-Write Cycle (Min.) in ns Operating ICC (Max.) in mA Operating Range ParlNumber23 80 Commercial CY7C901-2327 90 Military CY7C901-2731 70 Commercial CY7C901-Jl32 90 Military CY7C901-32Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°CAmbient Temperature withPower Applied .................... - 55°C to + 125°CSupply Voltage to Ground Potential(Pin 10 to Pin 30) .................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... -0.5V to +7.0VDC Input Voltage ................... -3.0V to +7.0VOutput Current into Outputs (Low) ............. 30 rnAPin DefinitionsSignalNameAo-A3Bo-B310-18Do-D3YO-Y3OECPI/ODescriptionThese 4 address lines select one of the registers inthe stack and output its contents on the (internal)Aport.These 4 address lines select one of the registers inthe stack and output is contents on the (internal)B port. This can also be the destination addresswhen data is written back into the register file.These 9 instruction lines select the ALU datasources (10, 1,2), the operation to be performed(13, 4, 5) and what data is to be written into eitherthe Q register or the register file (16, 7, 8).These are 4 data input lines that may be selectedby the 10, t, 2 lines as inputs to the ALU.0 These are three-state data output lines that, whenenabled, output either the output of the ALU orthe data in the A latches, as determined by thecode on the 16, 7, 8 lines.Output Enable. This is an active LOW input thatcontrols the Y 0-Y 3 outputs. When this signal isLOW the Y outputs are enabled and when it isHIGH they are in the high impedance state.Clock Input. The LOW level of the clock writedata to the 16 x 4 RAM. The HIGH level of theclock writes data from the RAM to the A-portand B-port latches. The operation of the Qregister is similar. Data is entered into the masterlatch o~ the LOW level ofthe clock andtransferred from master to slave when the clock isHIGH.I/O These two lines are bidirectional and arecontrolled by the 16, 7, 8 inputs. Electrically theyare three-state output drivers connected to theTTL compatible CMOS inputs.Static Discharge Voltage ..................... >2oo1V(Per MIL-STD-883 Method 3015)Latchup Current (Outputs) .................. > 200 mAOperating RangeRangeAmbientTemperatureVeeCommercial O°Cto + 70°C 5V ± 10%Military [I] - 55°C to + 125°C 5V ± 10%Note:I. T A is the "instant on" case temperature.SignalName I/ODescriptionQ3 I/O Outputs: When the destination code on linesRAM3 16,7,8 indicates a shift left (UP) operation the(Cont.) three-state outputs are enabled and the MSB ofthe Q register is output on the Q3 pin and theMSB of the ALU output (F3) is output on theRAM 3 pin.Inputs: When the destination code indicates ashift right (DOWN) the pins are the data inputsto the MSB of the Q register and the MSB of theRAM.Qo I/O These two lines are bidirectional and function in aRAMo manner similar to the Q3 and RAM3 lines, exceptthat they are the LSB of the Q register and RAM.C n I The carry-in to the internal ALU.C n +4 0 The carry-out from the internal ALU.G, P 0 The carry generate and the carry propagateoutputs of the ALU, which may be used toperform a carry look-ahead operation over the 4-bits of the ALU.OVR 0 Overflow. This signal is logically the exclusive­OR of the carry-in and the carry-out of the MSBof the ALU. This pin indicates that the result ofthe ALU operation has exceeded the capacity ofthe machine. It is valid only for the sign bit andassumes two's complement coding for negativenumbers.F = 0 0 Open drain output that goes HIGH if the data onthe ALU outputs (Fo, 1,2, 3) are all LOW. Itindicates that the result of an ALU operation iszero (positive logic).F3 0 The most significant bit of the ALU output.5-84

RAMoAACLOCKCP~ r- "RAM31~-~I 1-3-IN 3-IN 3-IN 3_~AMUX MUX MUX MUX..... B WORD; ADDRESSI I I TDO 0, 02 03)~00~16-WORD BY 4-BIT 2-PORT RAM f-

~ CY7C901~~~NDUcrOR ========================~~====~====~====~~====~======~=======Functional TablesMnemonicMicro CodeOctal12 11 10 CodeALUSourceOperandsRSMicroCodeALUMnemonic Octal Function Symbol15 14 13 CodeADD L L L 0 R Plus S R+SAQ L L L 0 A Q SUBR L L H 1 SMinusR S - RAB L L H 1 A B SUBS L H L 2 RMinusS R-SZQ L H L 2 0 Q OR L H H 3 RORS RVSZB L H H 3 0 B AND H L L 4 RANDS RASZA H L L 4 0 A NOTRS H L H 5 RANDS RASDA H L H 5 D A EXOR H H L 6 REX-ORS RVSDQ H H L 6 D Q EXNOR H H H 7 REX-NORS RVSDZ H H H 7 D 0Figure 3. ALU Function ControlFigure 2. ALU Source Operand ControlMnemonicQ-Reg.RAMMicroCode RAM FunctionQ ShifterFunction Y ShifterOctalOutputIs 1 7 1 6 Shift Load Shift LoadCodeRAMo RAM3 Qo Q3QREG L L L 0 X None None F~Q F X X X XNOP L L H 1 X None X None F X X X XRAMA L H L 2 None F~B X None A X X X XRAMF L H H 3 None F~B X None F X X X XRAMQD H L L 4 DOWN F/2 ~ B DOWN Q/2 ~ Q F Fo IN3 Qo IN3RAMD H L H 5 DOWN F/2 ~ B X None F Fo IN3 Qo XRAMQU H H L 6 UP 2F ~ B UP 2Q ~ Q F INO F3 INo Q3RAMU H H H 7 UP 2F ~ B X None F INo F3 X Q3x = Don't care. Electrically, the input shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.A = Register Addressed by A inputs.B = Register Addressed by B inputs.UP is toward MSB, DOWN is toward LSB.Figure 4. ALU Destination Control1210 Octal 0 1 2 3 4 5 6 7ALUSourceOctal ALU1543 Function A,Q A,B O,Q O,B O,A D,A D,Q D,O0 C n = L A+Q A+B Q B A D+A D+Q DRplus SC n = H A+Q+1 A+B+1 Q+1 B+1 A+1 D+A+1 D+Q+1 D+11 C n = L Q-A-1 B-A-1 Q-1 B-1 A-I A-D-1 Q-D-1 -D-1SminusRC n = H Q-A B-A Q B A A-D Q-D -D2 C n = L A-Q-1 A-B-1 -Q-1 -B-1 -A-1 D-A-1 D-Q-1 D-1RminusSC n = H A-Q A-B -Q -B -A D-A D-Q D3 RORS AVQ AVB Q B A DVA DVQ D4 RANDS AAQ AAB 0 0 0 DAA DAQ 05 RANDS AAQ AAB Q B A DAA DAQ 06 REX-ORS AVQ AVB Q B A DVA DVQ D7 REX-NORS AVQ AVB Q B A DVA nVQ D+ = Plus; - = Minus; V =OR; 1\ = AND; V = EX-ORFigure 5. Source Operand and ALU Function Matrix5-86

Cr!lF'"CY7C901~ SEMICONDUcrOR ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;====Description of ArchitectureGeneral DescriptionA block diagram of the CY7C901 is shown in Figure 1.The circuit is a 4-bit slice consisting of a register file (16 x 4dual port RAM), the ALU, the Q register and the necessarycontrol logic. It is expandable in 4-bit increments.RAMThe RAM is addressed by two 4-bit address fields (Ao-A3,Bo-B3) that cause the data to appear at the A or B (internal)ports. If the A and B addresses are the same, the dataat the A and B ports will be identical.New data is written into the RAM location specified by theB address when the RAM write enable (RAM EN) is activeand the clock input is LOW. Each of the four RAMinputs is driven by a 3-input multiplexer that allows the~utputs of the ALU (Fo, 1,2,3') to be shifted one bit positIOnto the left, the right, or not to be shifted. The otherinputs to the multiplexer are from the RAM3 and RAMo110 pins.For a shift left (up) operation, the RAM3 output buffer isenabled and the RAMo multiplexer input is enabled. For ashift right (down) operation the RAMo output buffer isenabled and the RAM3 multiplexer input is enabled.The data to be written into the RAM is applied to the Dinputs of the CY7C901 and is passed (unchanged) throughthe ALU to the RAM location addressed by the B wordaddress.The outputs of the RAM A and B ports drive separate 4-bit latches that are enabled (follow the RAM data) whenthe clock is HIGH. The outputs of the A latches go tothree multiplexers whose outputs drive the two inputs tothe ALU (Ro, 1,2,3) and (So, 1,2,3) and the (Yo, 1,2, 3) chipoutputs.ALU (Arithmetic Logic Unit)The ALU can perform three arithmetic and five logicaloperations on two 4-bit input words, Rand S. The R inputsare driven from four 2-input multiplexers whose inputs arefrom either the (RAM) A-port or the external data (D)inputs. The S inputs are driven from four 3-input multiplexerswhose inputs are from the A-port, the B-port, orthe Q register. Both multiplexers are controlled by the10,1,2 inputs as shown in Figure 2. This configuration ofmultiplexers on the ALU Rand S inputs enables the userto select eight pairs of combinations of A, B, D, Q and "0"(unselected) inputs as 4-bits operands to the ALU. Thelogical and arithmetic operations performed by the ALUupon the data present at its Rand S inputs are tabulated inFigurfl}. The ALU has a carry-in (Cn) input, carry-propagate(P) output, carry-generate (0) output, carry-out(Cn + 4) and overflow (OVR) pins to enable the user to (1)speed up arithmetic operations by implementing carrylook-ahead logic and (2) determine if an arithmetic overflowhas occurred.The ALU data outputs (Fo, 1,2,3) are routed to the RAM,the Q register inputs and the Y outputs under control ofthe 16, 7, 8 control signal inputs as shown in Figure 4. Inaddition, the MSB of the ALU is output as F3 so that theuser can examine the sign bit without enabling the threestateoutputs. The F = 0 output, used for zero detection, isHIGH when all bits of the F output are LOW. It is anopen-drain output which may be wire OR'ed across multiple7C901 processor slices.Q RegisterThe Q register functions as an accumulator or temporarystorage register. Physically it is a 4-bit register implementedwith master-slave latches. The inputs to the Q registerare driven by the outputs from four 3-input multiplexersunder control of the 16, 7, 8 inputs. The Qo and Q3 I/O pinsfunction in a manner similar to the RAMo and RAM3pins. The other inputs to the multiplexer enable the con- 5tents of the Q register to be shifted up or down, or theoutputs of the ALU to be entered into the master latches.Data is entered into the master latches when the clock isLOW and transferred from master to slave (output) whenthe clock changes from LOW to HIGH.ALU Source Operand and ALU FunctionsThe ALU source operands and ALU function matrix issummarized in Figure 5 and separated by logic operationor arithmetic operation in Figures 6 and 7, respectively.The 10, 1, 2 lines select eight pairs of source operands andthe 13, 4, 5 lines select the operation to be performed. Thecarry-in (Cn) signal affects the arithmetic result and theinternal flags; not the logical operations.5-87

~ CY7C901~~~DUcrOR=====================================================================Conventional Addition and Pass-Increment/DecrementWhen the carry-in is HIGH and either a conventional additionor a PASS operation is performed, one (1) is addedto the result. If the DECREMENT operation is performedwhen the carry-in is LOW, the value of the operand isreduced by one. However, when the same operation is performedwhen the carry-in is HIGH, it nullifies the DEC­REMENT operation so that the result is equivalent to thePASS operation.Octal1543,1210GroupFunction40 AND AAQ41 AAB45 DAA46 DAQ30 OR AVQ3 1 AVB35 DVA36 DVQ60 EX-OR A¥Q61 A¥B65 D¥A66 D¥Q70 EX-NOR A¥Q71 A¥B75 D¥A76 D¥Q72 INVERT Q73 B74 A77 D62 PASS Q63 B64 A67 D32 PASS Q33 B34 A37 D42 "ZERO" 043 044 047 050 MASK AAQ5 1 AAB55 DAA56 DAQFigure 6. ALU Logic Mode FunctionsSubtractionRecall that in two's complement integer coding - 1 isequal to all ones and that in one's complement integer codingzero is equal to all ones. To convert a positive integer toits two's complement (negative) equivalent, invert (complement)the number and add 1 to it; i.e., TWC = ONC + 1.In Figure 7 the symbol - Q represents the two's complementof Q so that the one's complement of Q is then-Q -1.Octal C n = 0 (Low) C n = 1 (High)1543,1210 Group Function Group Function00 A+Q A+Q+l01A+B ADD plus A+B+lADD05 D+A one D+A+l06 D+Q D+Q+l02 Q Q+l03BB+lPASSIncrement04 A A+l07 D D+l12 Q-l Q1 3B-1BDecrementPASS14 A-I A27 D-l D22 -Q-1 -Q23-B-1 2's Compo -Bl's Compo24 -A-l (Negate) -A1 7 -D-1 -D10 Q-A-l Q-A1 1 B-A-l B-A15 A-D-l A-D16 Subtract Q-D-1 Subtract Q-D20 (1's Comp.) A-Q-l (2's Comp.) A-Q21 A-B-l A-B25 D-A-1 D-A26 D-Q-1 D-QFigure 7. ALU Arithmetic Mode Functions5-88

~ CY7C901~~~~UcrOR =====================================================================Logic Functions for G, P, C n + 4, and OVRThe four signals G, P, Cn + 4, and OVR are designed toindicate carry and overflow conditions when the CY7C901is in the add or subtract mode. The table below indicatesthe logic equations for these four signals for each of theeight ALU functions. The Rand S inputs are the two inputsselected according to Figure 2.Definitions (+ = OR)Po = Ro SoGo = ROSOPI = Rl + SlGl = RlSlP2 = R2 S2G2 = R2S2P3 = R3 + S3G3 = R3S3C4 = G3 + P3G 2 + P3P2G l + P3P2GO + P3P2P IPOCnC3 = G2 + P2G l + P2P IGO + P2P IPOCn1 543 Function P G CN+4 OVR0 R+S P3P2PIPO G3 + P3G2 + P3P2G l + P3P2PIGO C4 C3 ¥ C41 S-R +- Same as R + S equations, but substitute Rj for Rj in definitions --.2 R-S +- Same as R + S equations, but substitute Sj for Sj in definitions --.3 RVS LOW P3P2P IPO P3P2PIPO+ C n P3P2P 1 Po + Cn4 RAS LOW G3+ G2+Gl +GO G3+ G2+Gl +GO+C n G3+G2+Gl +GO+C n5 RAS LOW +- Same as R A S equations, but substitute Rj for Rj in definitions6 R¥S +- Same as R ¥ S, but substitute Ri for Rj in definitions7 R¥S G3+G2+Gl +Go G3 + P3G2 + P3P2Gl + P3P2P IPONotes:[P2 + G2P} + G2G}PO + G2G}GoCn1 ¥ [P3 + G3P2 + G3G2P} + G3G2G}PO + G3G2G}GoCn1+ = ORFigure 8G3 + P3G2 + P3P2Gl+ P3P2P IPO (GO+C n)See note--.--.5-89

~ CY7C901~~~NDUcrOR =====================================================================Electrical Characteristics Over Commercial and Military Operating Range[3]Vee Min. = 4.5V, Vee Max. = 5.5V.Parameters Description Test Conditions Min. Max. UnitsVOHOutput HIGH VoltageVee = Min.IOH = -3.4mA2.4 VVee = Min.VOL Output LOW Voltage IOL = 20 mA Commercial 0.4 VIOL = 16 mA MilitaryVIR Input HIGH Voltage 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 VIIXIOHIOLlozIseInput Leakage CurrentOutput HIGH CurrentOutput LOW CurrentOutput Leakage CurrentOutput Short Circuit eurrent[l]Vss :::;: VIN :::;: VeeVee = Max.Vee = Min.VOH = 2.4VVee = Min. Commercial 20VOL = O.4VMilitary 16-10 10 p.A-3.4 mAVee = Max. +40 p.AVOUT = Vss to Vee -40 p.AVee = Max.VOUT = OVCommercial -31 70mA-85 mAIce Supply Current Vee = Max. Commercial-23 80 mAMilitary -27, -32 90VIR ~ Vee - 1.2V, 10 MHz Commercial 26.5Icel Supply Current mAVIL :::;: O.4V Military 31Capacitanc~[2]Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f= 1 MHz 5COUTOutput CapacitanceVee = 5.0V7Notes:1. Not more than one output should be tested at a time. Duration of theshort circuit should not be more than one second.2. Tested initially and after any design or process changes that mayaffect these parameters.Output Loads used for AC Performance Characteristics3. See the last page of this specification for Group A subgroup testinginformation.pFVOUTlCC+5 V_"OSly{200n0030-4All outputs except open drainNotes:I. CL = 50 pF includes scope probe, wiring and stray capacitance.2. CL = 5 pF for output disable tests.3. Loads shown above are for commercial (20 rnA) IOL spec only.+5 V!VOSlVO~J;CLOpen drain (F = 0)0030-55-90

~ CY7C901~~~~UcrOR =====================================================================CY7C901-23 Commercial andCY7C901-27 Military AC PerformanceCharacteristicsThe tables below specify the guaranteed AC performanceof these devices over the Commercial (O°C to 70°C) andMilitary ( - 55°C to + 125°C) operating temperature rangewith Vcc varying from 4.5V to 5.5V. All times are innanoseconds and are measured between the 1.5V signal levels.The inputs switch between OV and 3V with signal transitionrates of 1 V per nanosecond. All outputs have maximumDC current loads. See "Electrical Characteristics"for loading circuit information.This data applies to parts with the following numbers:CY7C901-23PC CY7C901-23DC CY7C901-23LCCY7C901-23JC CY7C901-27DMB CY7C901-27LMBCombinational Propagation Delays. CL = 50 pp[5]Cycle Time and Clock Characteristics [5]CY7C901 -23 -27Read-Modify-Write Cycle (from 23 ns 27 nsselection of A, B registers toend of cycle).Maximum Clock Frequency to shift Q 43 MHz 37 MHz(50% duty cycle, I = 432 or 632)Minimum Clock LOW Time 13 ns 15 nsMinimum Clock HIGH Time IOns 12 nsMinimum Clock Period 23 ns 27 nsTo OutputY F3 Cn+4 G,P F=O OVRRAMo QoFrom Input RAM3 Q3CY7C901 23 27 23 27 23 27 23 27 23 27 23 27 23 27 23 27A, BAddress 30 33 30 33 30 33 28 33 30 33 30 33 30 33 - -Data 21 24 20 23 20 23 20 21 24 25 21 24 22 25 - -C n 17 18 16 17 14 14 - - 18 19 16 17 18 19 - -1 012 26 28 25 27 24 26 24 28 25 29 24 27 25 27 - -1 345 26 27 24 27 24 26 24 26 26 27 24 26 26 27 - -1 678 16 18 - - - - - - - - - - 21 21 21 21A Bypass ALU(I = 2XX)24 26 - - - - - - - - - - - - - -Clock""'-- 24 27 23 26 23 26 23 25 24 27 24 26 24 27 19 20Set-up and Hold Times Relative to Clock (CP) Input[5]InputCP:.):- -f----~--Set-up Time Hold Time Set-up Time Hold TimeBeforeH ~ L AfterH ~ L BeforeL ~ H AfterL ~ HCY7C901 23 27 23 I 27 23 I 27 23 I 27A, B Source Address 10 120(Note 3)21,10+ tPWL(Note 4)0B Destination Address 10 12 +- Do Not Change ~ 0Data - - - 16 0C n - - - 13 01 012 - - - 19 01 345 - - - 19 01 678 7 9 +- Do Not Change ~ 0RAMo, 3,QO, 3 - - - 9 0Output Enable/Disable Times [5]Output disable tests performed with CL = 5 pP and measured to 0.5V change of output voltage level.Device Input Output Enable DisableCY7C901-23 OE Y 14 16CY7C901-27 OE Y 16 18Notes:1. A dash indicates a propagation delay path or set-up time constraintdoes not exist.2. Certain signals must be stable during the entire clock LOW time toavoid erroneous operation. This is indicated by the phrase "do notchange".5-913. Source addresses must be stable prior to the clock H -+ L transitionto allow time to access the source data before the latches close. The Aaddress may then be changed. The B address could be changed if it isnot a destination; i.e. if data is not being written back into the RAM.Normally A and B are not changed during the clock LOW time.4. The set-up time prior to the clock L -+ H transition is to allow timefor data to be accessed, passed through the ALU, and returned to theRAM. It includes all the time from stable A and B addresses to theclock L -+ H transition, regardless of when the clock H -+ Ltransition occurs.5. See the last page of this specification for Group A subgroup testinginformation.

~ CY7C901~~~~UcrOR =====================================================================CY7C901-31 Commercial andCY7C901-32 Military AC PerformanceCharacteristicsThe tables below specify the guaranteed AC performanceof these devices over the Commercial (O°C to 70°C) andMilitary (- 55°C to + 125°C) operating temperature rangewith V cc varying from 4.5V to 5.5V. All times are innanoseconds and are measured between the 1.5V signal leve1s.The inputs switch between OV and 3V with signal transitionrates of 1 V per nanosecond. All outputs have maximumDC current loads. See "Electrical Characteristics"for loading circuit information.This data applies to parts with the following numbers:CY7C901-31PC CY7C901-31DC CY7C901-31LC CY7C901-31JCCombinational Propagation Delays. CL = 50 pp[5]Cycle Time and Clock Characteristics [5]CY7C901- -31 -32Read-Modify-Write Cycle (from 31 ns 32 nsselection of A, B registers toend of cycle).Maximum Clock Frequency to shift Q 32 MHz 31 MHz(50% duty cycle, I = 432 or 632)Minimum Clock LOW Time 16 ns 17 nsMinimum Clock HIGH Time 15 ns 15 nsMinimum Clock Period 31 ns 32 nsFor faster performance see CY7C901-23 specification on page 9.CY7C901-32DMBCY7C901-32LMBTo Output Y F3 Cn +4 G,P F=O OVRRAMO QoRAM3 Q3From Input -31 -32 -31 -32 -31 -32 -31 -32 -31 -32 -31 -32 -31 -32 -31 -32A, B Address 40 48 40 48 40 48 37 44 40 48 40 48 40 48 - -D 30 37 30 37 30 37 30 34 38 40 30 37 30 37 - -C n 22 25 22 25 20 21 - - 25 28 22 25 25 28 - -1012 35 40 35 40 35 40 37 44 37 44 35 40 35 40 - -1345 35 40 35 40 35 40 35 40 38 40 35 40 35 40 - -1678 25 29 - - - - - - - - - - 26 29 26 29A BypassALU(I = 2XX)35 40 - - - - - - - - - - - - - -Clock""'- 35 40 35 40 35 40 35 40 35 40 35 40 35 40 28 33Set-up and Hold Times Relative to Clock (CP) Input[5]CP:-~-'" --- 1---InputSet-up Time Hold TimeBeforeH -+ L AfterL -+ HHold TimeAfterH -+ LSet-up TimeBeforeL -+ HA, B Source Address 150 30,15 + tpWL(Note 3) (Note 4)0B Destination Address 15 +- Do Not Change -+ 0D - - 25 0C n - - 20 01012 - - 30 01345 - - 30 01678 10 +- Do Not Change -+ 0RAMo, 3,QO, 3 - - 12 0Output Enable/Disable Times [5]Output disable tests performed with CL = 5 pP and measured to 0.5V change of output voltage level.Device Input Output Enable DisableCY7C901-31 OE Y 23 23CY7C901-32 OE Y 25 25Notes:1. A dash indicates a propagation delay path or set-up time constraintdoes not exist.2. Certain signals must be stable during the entire clock LOW time toavoid erroneous operation. This is indicated by the phrase "do notchange".3. Source addresses must be stable prior to the clock H ~ L transitionto allow time to access the source data before the latches close. The Aaddress may then be changed. The B address could be changed if it isnot a destination; i.e. if data is not being written back into the RAM.Normally A and B are not changed during the clock LOW time.4. The set-up time prior to the clock L ~ H transition is to allow timefor data to be accessed, passed through the ALU, and returned to theRAM. It includes all the time from stable A and B addresses to theclock L ~ H transition, regardless of when the clock H ~ Ltransition occurs.5. See the last page of this specification for Group A subgroup testinginformation.5-92

LACY7C901~ ~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Minimum Cycle Time Calculations for 16-Bit SystemsSpeed used in calculations for parts other than CY7C901 are representative for MSI parts.r-----------------MC NWIRED "OR" F=OFROM OTHER CY7C901 sG.PF=OH ........... ..,CY7C901(4)C n+4OVR I---r---+IF34DATAREGISTERPipelined System, Add without Simultaneous Shift0030-11CY7C245CY7C901Carry LogicCY7C901RegisterData LoopControl LoopClock to Output 12 CY7C245 Clock to OutputA. BtoG. P 28 MUX Select to OutputGo. Po to Cn + Z 9 CY7C91O CC to OutputCn to Worst Case 18 CY7C245 Access TimeSetup 471 nsMinimum Clock Period = 71 ns1212222066 nsPipelined System, Simultaneous Add and Shift Down (RIGHT)0030-12CY7C245CY7C901Carry LogicCY7C901XOR and MUXCY7C901Data LoopClock to OutputA. BtoG, PGo,PotoCn+zCn to Worst CaseProp. Delay, Selectto OutputRAM3 Setup122891820CY7C245MUXCY7C91OCY7C245996nsMinimum Clock Period = 96 nsControl LoopClock to OutputSelect to OutputCC to OutputAccess Time1212222066 ns5-93

~ CY7C901~~~NDUcrOR=====================================================================Typical DC and AC Characteristics0.90wN::J~~ct::0zNORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENTvs. SUPPLY VOLTAGEvs. AMBIENT TEMPERATUREvs. OUTPUT VOLTAGE1.2 .------r----,---..-----, 1.4 .--------,--------, 60I1.0 1.2 0.20w0.8N::::i 1.00.6~~ct::0z0.8V IN =5.0VTA = 25°C0.4 0.64.0 4.5 5.0 5.5 6.0 -55 125SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE (OC)~5I-ZWct::ct::::::lUwuct::::::l0(/)I-::::lQ.I-::::l050'"40302010o oVcc =5.0VTA = 25°C -~'" I'"1.0 2.0 3.0 4.0OUTPUT VOLTAGE (V)NORMALIZED FREQUENCYvs. SUPPLY VOLTAGE1.3NORMALIZED FREQUENCYvs. AMBIENT TEMPERATURE1.6OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE140>­uzw::::lowct::....owN::J~~ct::oz1.21.11.00.90.8/"0.74.04.5 5.0 5.5 6.00,~r--TA = 25°C>-uzw::::lwct::....0wN::J~~ct::0z1.4"1.21.00.80.6-55~'----V cc =5.0V25 125~5I-zwct::ct::::::lU:.::zViI-::::lQ.I-::::l0120100".,-~/VVcc =5.0VT A=250C -o o 1.08060/40/20//2.0 3.0 4.0SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (OC) OUTPUT VOLTAGE (V)>-~...Jw0I-::::lQ.I-::::l00wN::::i~~ct::0zNORMALIZED OUTPUT DELAYvs. OUTPUT LOADING1.61.5 ..--1.4/ /"1.3/ V/1.21.1/ Vcc =5.0VTA =25°C-1.0o/I200 400 600 800 10001.11.00.20w 0.9N::::i~~ 0.8ct::0z0.7oNORMALIZED Iccvs. FREQUENCY/V// Vcc/ =5.5VTA = 25°C -1/ VIN =OV OR 3VI IIo 5 10 15 20 25 30 35CAPACITANCE (pF)FREQUENCY (MHz)0030-105-94

~~ CY7C901~~~NDUaOR =====================================================================Ordering InformationReadModify-WriteCycle (ns)Ordering CodePackageType23 CY7C901-23PC P17CY7C901-23DC D18CY7C901-23JC J67CY7C901-23LC L6727 CY7C901-27DMB D18CY7C901-27LMB L6731 CY7C901-31PC P17CY7C901-31DC D18CY7C901-3IJC J67CY7C901-31LC L6732 CY7C901-32DMB D18CY7C901-32LMB L67OperatingRangeCommercialCommercialCommercialCommercialMilitaryMilitaryCommercialCommercialCommercialCommercialMilitaryMilitaryPin ConfigurationIS1 7RAM3RAMoVee 11F=O 121 0 131112CP 16NC 175 4 3Top View1819202122232425262728NCPOVRCn + 4GF3GNDC n31 14Is1 30030-95-95

Si~CY7C901. ~~~NDUcroR =====================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsCombinational Propagation Delays (Continued)Parameters Subgroups Parameters SubgroupsVOH 1,2,3 From Cn to Cn+4 7,8,9,10,11VOL 1,2,3 From Cn to F = 0 7,8,9,10,11VIR 1,2,3 From Cn to OVR 7,8,9,10,11VIL 1,2,3 From Cn to RAMo, 3 7,8,9,10,11IIX 1,2,3 From IOl2 to Y 7,8,9,10,11IOZ 1,2,3 From IOl2 to F3 7,8,9,10,11Isc 1,2,3 From IOl2 to Cn+4 7,8,9,10,11Icc 1,2,3 From IOl2 to G, P 7,8,9,10,11ICCI 1,2,3 From IOl2 to F=O 7,8,9,10,11Cycle Time and Clock CharacteristicsParametersSubgroupsMinimum Clock LOW Time 7,8,9,10,11Minimum Clock HIGH Time 7,8,9,10,11Combinational Propagation DelaysParametersSubgroupsFrom A, B Address to Y 7,8,9,10,11From A, B Address to F3 7,8,9,10,11From A, B Address to Cn + 4 7,8,9,10,11From A, B Address to G, P 7,8,9,10,11From A, B Address to F = 0 7,8,9,10,11From A, B Address to OVR 7,8,9,10,11From IOl2 to OVR 7,8,9,10,11From IOl2 to RAMo, 3 7,8,9,10,11From 1345 to Y 7,8,9,10,11From 1345 to F3 7,8,9,10,11From 1345 to Cn+4 7,8,9,10,11From 1345 to G, P 7,8,9,10,11From 1345 to F = 0 7,8,9,10,11From 1345 to OVR 7,8,9,10,11From 1345 to RAMo, 3 7,8,9,10,11From 1678 to Y 7,8,9,10,11From 1678 to RAMO, 3 7,8,9,10,11From 1678 to Qo, 3 7,8,9,10,11From A Bypass ALU to Y 7,8,9,10,11(I = 2XX)From A, B Address to RAMo, 3 7,8,9,10,11 From Clock ....r to Y 7,8,9,10,11From DtoY 7,8,9,10,11FromDtoF3 7,8,9,10,11From Clock ....r to F3 7,8,9,10,11From Clock ....r to Cn + 4 7,8,9,10,11From D to Cn+4 7,8,9,10,11 From Clock ....r to G, P 7,8,9,10,11FromDtoG, P 7,8,9,10,11From Clock ....r to F = 0 7,8,9,10,11FromDtoF = 0 7,8,9,10,11 From Clock ....r to OVR 7,8,9,10,11From Dto OVR 7,8,9,10,11From D to RAMo, 3 7,8,9,10,11FromCn to Y 7,8,9,10,11From Cn to F3 7,8,9,10,11From Clock ....r to RAMo, 3 7,8,9,10,11From Clock ....r to Qo, 3 7,8,9,10,115-96

~ CY7C901~~~~UcrOR=====================================================================Set-up and Hold Times Relative to Clock (CP) InputParameters Subgroups Parameters SubgroupsA, B Source Address 7,8,9,10,11 D Hold Time After L ---+ H 7,8,9,10,11Set-up Time Before H ---+ LC n Set-up Time Before L ---+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11C n Hold Time After L ---+ H 7,8,9,10,11Hold Time After H ---+ L1012 Set-up Time Before L ---+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11Set-up Time Before L ---+ H 1012 Hold Time After L ---+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11 1345 Set-up Time Before L ---+ H 7,8,9,10,11Hold Time After L ---+ H 1345 Hold Time After L ---+ H 7,8,9,10,11B Destination Address 7,8,9,10,11 1678 Set-up Time Before H ---+ L 7,8,9,10,11Set-up Time Before H ---+ L1678 Hold Time After H ---+ L 7,8,9,10,11B Destination Address 7,8,9,10,11Hold Time After H ---+ L1678 Set-up Time Before L ---+ H 7,8,9,10,11B Destination Address 7,8,9,10,111678 Hold Time After L ---+ H 7,8,9,10,11Set-up Time Before L ---+ H RAMo, RAM3, Qo, Q3 7,8,9,10,11B Destination Address 7,8,9,10,11Set-up Time Before L ---+ HHold Time After L ---+ H RAMo, RAM3, Qo, Q3 7,8,9,10,11D Set-up Time Before L ---+ H 7,8,9,10,11Hold Time After L ---+ HDocument #: 38-00021-B5-97

Features• Fast- CY7C909/11 has a 30 ns(min.) clock to output cycletime; commercial and military• Low Power- ICC (max.) = 55 mA;commercial and military• Vee margin- 5 V ± 10%- All parameters guaranteedover commercial and militaryoperating temperature range• ExpandableInfinitely expandable in 4-bitincrementsLogic Block DiagramREGISTERENABLERE)D AND R :CONNECTED )'4ON 7g~~~ IIDIRECTINPUTS IOUTPUTENABLEorR (7C909 ONLY),.------II: '50>---"5 1>---"CYPRESSSEMICONDUCTORCY7C909CY7C911CMOS Micro ProgramSequencers• Capable of withstanding greaterthan 2000V static dischargevoltage1) a set of four external direct inputs(Di)j 2) external data stored in an internalregister (Ri); 3) a four word deep• Pin compatible and functionalpush/pop stack; or 4) a program counterregister (which usually contains theequivalent to 2909A/2911Alast address plus one). The push/popDescriptionstack includes control lines so that itcan efficiently execute nested subroutinelinkages. Each of the four outputsThe CY7C909 and CY7C911 are highspeed,four-bit wide address sequencers (Yi) can be OR'ed with an external inputfor conditional skip or branch in­intended for controlling the sequenceof execution of microinstructions containedin microprogram memory. They the outputs to all zeros. The outputsstructions. A ZERO input line forcesmay be connected in parallel to expand are three state, controlled by thethe address width in 4 bit increments. Output Enable (OE) input.Both devices are implemented in highperformance CMOS for optimum The CY7C911 is an identical circuit tospeed and power.the CY7C909, except the four OR inputsare removed and the D and R inputsare tied together. The CY7C911 isThe CY7C909 can select an addressfrom any of four sources. They are: available in a 20-pin, 3OO-mil package.Pin ConfigurationsRE VCC CP PUPR3CPVCCFER2PUPRlFERE Cn+ 4Ro Cn+ 4 °3 C nOR 3 C nO 2 DE0 3 OE °1 Y 3OR 2 Y 3 Do Y 2O 2 Y 2 OND Y1CLOCKOR I YlZERO Yo0 1 YoORo 51So S1DO 50GNOZERO0042-30042-2U D..U D..r£ ",N",tt)I~ >u~ ~I~ >u:3 ~I~3ROFE2 ~20 19OR 3 Cn+ 4 4 C n + 4C°3n 5 C n28 DE 7C911 DE°2 9 Y 3 Y 3OR 1Y 2 Y 2°1Y 1o 0010 0 _ 0 10 o::cncn>->-0 - 0 -0:: OZ"'VI VI>- 1&1o C)I&I NN0042-40042-5en • 40042-15-98

finCY7C909. CY7C911~U~==================================================================Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... >2001VAmbient Temperature with (per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°C Latch-Up Current ......................... > 200 rnASupply Voltage to Ground Potential .... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VOperating RangeRangeAmbientTemperatureDC Input Voltage ................... - 3.0V to + 7.0V Commercial O°C to + 70°COutput Current, into Outputs (Low) ............. 30 rnA Military [31 - 55°C to + 125°CVee5V ± 10%5V ± 10%Electrical Characteristics Over Operating Range[4]Parameters Description Test Conditions Min.VOROutput HIGH VoltageVee = Min., lOR = -2.6 mA (Comm.) 2.4Vee = Min., lOR = -1.0 mA (Mil.) 2.4VOL Output LOW Voltage Vee = Min., IOL = 16.0mAVIR Input High Voltage 2.0VIL Input Low Voltage -2.0IIX Input Load Current GND:::;: VI:::;: Vee -10lozOutput LeakageGND:::;: Vo:::;: VeeCurrentOutput Disabled-20losleeleelOutput Shordl1Circuit CurrentVee = Max. VOUT = GND -30Vee Operating Vee = Max. CommercialSupply Current lOUT = OmA MilitaryVee Operating Vee = Max. CommercialSupply CurrentVIR 2 3.0V, VIL :::;: O.4VMilitaryMax. UnitsVV0.4 VVee V0.8 V+10 ""A+20 ""A-85 mA55553535mAmACapacitance [2]Parameters Description Test Conditions Max.CIN Input Capacitance TA= 25°C,f= 1 MHz 5COUTOutput CapacitanceVee = 5.0V 7Notes:1. Not more than 1 output should be shorted at one time. Duration of3. TA is the "instant on" case temperature.the short circuit should not exceed 30 seconds.2. Tested initially and after any design or process changes that mayaffect these parameters.svftOUTPUTSOpfR2AC Test Loads and WaveformssvftOUTPUT5 pf R2Units4. See the last page ofthis specification for Group A subgroup testinginformation.R1 R1 ALL INPUT PULSESINCLUDINGI _INCLUDING IJIG AND - - JIG AND - -SCOPESCOPEFigure laFigure Ib_0042-6pF3.0V~. ~GND 10% 10%~Sns -- ~ SnsFigure 20042-7ICommercial MilitaryRl 254.0 258.0I R2 187.0 216.0 5-99

(;nCY7C909. CY7C911~NDU~ =====================================================================Switching Characteristics Over Operating Range[4, 5]7C909-30 7C909-30 7C909-40 7C909-407C911-30 7C911-30 7C911-40 7C911-40Commercial Military Commercial MilitaryMioimum Clock Low Time 15 15 20 20 osMioimum Clock High Time 15 15 20 20 osMAXIMUM COMBINATIONAL PROPAGATION DELAYSFrom Input To: y CN +4 Y CN+4 y CN + 4 Y CN +4 osDi 17 18 18 19 17 22 20 25 osSO, S1 18 18 20 20 29 34 29 34 osORi (7C909) 16 16 17 17 17 22 20 25 osCN - 13 - 15 - 14 - 16 osZERO 18 18 20 20 29 34 30 35 osOE Low to Output 16 - 18 - 25 - 25 - osOE HIGH to HIGH Z[5] 16 - 18 - 25 - 25 - osClock HIGH, S1, So = LH 20 20 22 22 39 44 45 50 osClock HIGH, S1, So = LL 20 20 22 22 39 44 45 50 osClock HIGH, S1. So = HL 20 20 22 22 44 49 53 58 osMINIMUM SET-UP AND HOLD TIMES (All Times Relative to Clock LOW to HIGH Transition)From Input Set-up Hold Set-up Hold Set-up Hold Set-up HoldRE 11 0 12 0 19 0 19 0 osRi [6] 10 0 11 0 10 0 12 0 osPush/Pop 12 0 13 0 25 0 27 0 osFE 12 0 13 0 25 0 27 0 osCN 10 0 11 0 18 0 18 0 osDi 14 0 16 0 25 0 25 0 osORi (7C909) 12 0 14 0 25 0 25 0 osSo, S1 14 0 16 0 25 0 29 0 osZERO 12 0 13 0 25 0 29 0 osNotes:5. Output Loading as in Figure 1 h.6. Rj and Dj are internally connected on the CY7C911. Use Rj set-upand hold times when Dj inputs are used to load register.Switching Waveforms(Units7. System clock cycle time (Clock Low Time and Clock High Time)cannot be less than maximum propagation delay.-MIN CLOCK LOWCLOCKINPUT(EXCEPT OE):::5

finCY7C909. .. CY7C911¥ ~~NDUcrOR ~=====================================================================Functional DescriptionThe tables below define the control logic of the 7C909/911.Table 1 contains the Multiplexer Control Logic which selectsthe address source to appear on the outputs.Table 1. Address Source SelectionOcrAL SI So SOURCE FOR Y OUTPUTS0 L L Microprogram Counter (,uPC)1 L H Address/Holding Register (AR)2 H L Push-Pop stack (STK)3 H H Direct inputs (Di)Control of the Push/Pop Stack is contained in Table 2.FILE ENABLE (FE) enables stack operations, whilePush/Pop (PUP) controls the stack.Table 2. Synchronous Stack ControlFE PUP PUSH-POP STACK CHANGEH X No changeL H Push current PC into stackincrement stack pointerL L pop stack, decrement stack pointerTable 3 illustrates the Output Control Logic of the7C909/911. The ZERO control forces the outputs to zero.The OR inputs are OR'ed with the output of the multiplexer.Table 3. Output ControlORi ZERO OE YiX X H HighZX L L LH H L HL H L Source selected by So S 1Table 4 defines the effect of So, SI, FE and PUP controlsignals on the 7C909. It illustrates the Address Source onthe outputs and the contents of the Internal Registers forevery combination of these signals. The Internal Registercontents are illustrated before and after the Clock LOW toHIGH edge.CYCLE S1. So, FE, PUP,uPCN 0000 JN + 1 - J + 1N 0001 JN + 1 - J + 1N 00 1 X JN + 1 - J + 1N 0100 JN+l - K + 1N 0101 JN+l - K + 1N a 11 X JN+1 - K + 1N 1000 JN + 1 - Ra + 1N 1001 JN+l - Ra + 1N 101 X JN + 1 - Ra + 1N 1100 JN + 1 - D + 1N 1 10 1 JN + 1 - D + 1N 11 1 X JN + 1 - D+lJ = Contents of Microprogram CounterK = Contents of Address RegisterRa, Rh, Re, Rd = Contents in StackREG STKOSTKIK Ra RbK Rb RcK Ra RbK J RaK Ra RbK Ra RbK Ra RbK Rb RcK Ra RbK J RaK Ra RbK Ra RbK Ra RbK Rb RcK Ra RbK J RaK Ra RbK Ra RbK Ra RbK Rb RcK Ra RbK J RaK Ra RbK Ra RbTable 4STK2 STK3 YOUTCOMMENTPRINCIPLEUSERc Rd JEndPop StackRd Ra - LoopRc Rd JSet-upPush ,uPCRb Rc - LoopRc Rd JContinueContinueRc Rd -Rc Rd K Use AR for Address; EndRd Ra - Pop Stack LoopRc Rd K Jump to Address in AR;JSRARRb Rc - Push ,uPCRc Rd KJump to Address in AR JMPARRc Rd -Rc Rd Ra Jump to Address in STKO;RTSRd Ra - Pop StackRc Rd Ra Jump to Address in STKO;Rb Rc - Push ,uPCRc Rd RaStack RefJump to Address in STKORc Rd - (Loop)Rc Rd D Jump to Address on D; EndRd Ra - Pop Stack LoopRc Rd D Jump to Address on D;Rb Rc - Push ,uPCRc Rd DRc Rd -Jump to Address on DJSRDJMPD5-101

§IIIII.WnCY7C909CY7C911~ ~~NDUcrOR =====================================================================Functional Description (Continued)Two examples of Subroutine Execution appear below. Figure3 illustrates a single subroutine while Figure 4 illustratestwo nested subroutines.The instruction being executed at any given time is the onecontained in the microword register (IL WR). The contentsof the IL WR also controls the four signals So, S 1, FE, andPUP. The starting address of the subroutine is applied tothe D inputs of the 7C909 at the appropriate time.In the columns on the left is the sequence of microinstructionsto be executed. At address J + 2, the sequence controlportion of the microinstruction contains the commandCONTROL MEMORYExecuteMicroprogram Execute Cycle To TlCycleSequencerClockAddressInstruction Signals -J-IInputsShSo 0 0To JFE H H(fromT\ J+IPUP X,...WR)XT2 J+2 JSRAD X XT6 J+3T7 J+4 ,...PC J+ I J+2STKOInternalSTKIRegistersSTK2STK3"Jump to sub-routine at A". At the time T2, this instructionis in the IL WR, and the 7C909 inputs are set-up toexecute the jump and save the return address. The subroutineaddress A is applied to the D inputs from the IL WRand appears on the Y outputs. The first instruction of thesubroutine, I(A), is accessed and is at the inputs of theIL WR. On the next clock transition, I(A) is loaded into theIL WR for execution, and the return address J + 3 ispushed onto the stack. The return instruction is executed atTs. Figure 4 is a similar timing chart showing one subroutinelinking to a second, the latter consisting of only onemicroinstruction.Tz T3 T4 Ts T6 T7 Ts T9IL IL IL IL L IL IL -L IL IL3 0 0 2 0 0L H H L H HH X X L X XA X X X X X1+3 A+I A+2 A+3 J+4 J+5J+3 J+3 J+3T3 A I(A) Output Y J+I J+2T4 A+ITs A+2 RTS ROMOutput(Y) 1(1+1) JSRAA A+I A+2 J+3 J+4 1+5I(A) I(A+I) RTS I(J+3) 1(1+4) 1(1+5)Contentsof,...WR(Instruction ,...WR I(J) 1(1+1)beingexecuted)JSRA I(A) I(A+I) RTS 1(J+3) I(J+4)Figure 3. Subroutine Execution.0042-9C n = HIGHCONTROL MEMORYT7IL IU IU IL IL L IL -LExecuteMicroprogram Execute Cycle To Tl Tz T3 T4 Ts T6CycleSequencerQockAddressInstruction Signals --J-IInputsS\. So 0 0 3 0 0 3 2 0To JFE H H L H H L L H(fromT\ J+IPUP X X H X X H L X,...WR)T2 1+2 JSRAD X X A X X B X XT9 J+3,...PC J+I 1+2 1+3 A+I A+2 A+3 B+I A+4STKO 1+3 1+3 J+3 A+3 J+3InternalSTKI J+3RegistersSTK2T3 A STK3T4 A+ITS A+2 JSRB Output Y J+l J+2 A A+I A+2 B A+3 A+4T7 A+3T~ A+4 RTS ROMOutput(Y) 1(1+1) JSRA I(A) I(A+I) JSRB RTS I(A+3) RTSTs T9IU IL2 0L HL XX XA+5 J+41+3J+3 J+4I(J+3) 1(1+4)Contentsof,...WRT6 B RTS (Instruction ,...WR I(J) 1(1+1) JSRA I(A) I(A+I) JSRB RTSbeingexecuted)Figure 4. Two Nested Subroutines. Routine B is Only One Instruction.I(A+3)RTSI(J+3)0042-10C n = HIGH5-102

I~o·.. >---+---'",0 >-___ ---'It!I~Note: 0042-11Rj and Dj connected together and ORj Inputs removed on CY7C911Figure 5. Microprogram Sequencer Block Diagram5-103

5ACY7C909... CY7C911~ ~~NDUcroR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===Functional Description (Continued)ArchitectureThe CY7C909 and CY7C911 are CMOS microprogram sequencersfor use in high speed processor applications. Theyare cascadable in 4-bit increments. Two devices can address256 words of microprogram, three can address up to4K words, and so on. The architecture of theCY7C909/91I is illustrated in the logic diagram in Figure5. The various blocks are described below.MultiplexerThe Multiplexer is controlled by the So and SI inputs toselect the address source. It selects either the Direct Inputs(Dj), the Address Register (AR), the Microprogram Counter(I-tPC), or the stack (SP) as the source of the next microinstructionaddress.Direct InputsThe Direct Inputs (Dj) allow addresses from an externalsource to be output on the Y outputs. On the CY7C911,the direct inputs are also the inputs to the Address Register.Address RegisterThe Address Register (AR) consists of four D-type, edgetriggeredflip-flops which are controlled by the ReglsterEnable (RE) input. When Reglster Enable is LOW, newdata is entered into the register on the LOW to HIGHclock transition.Microprogram CounterThe Microprogram Counter (I-tPC) is composed of a 4-bitincrementer followed by a 4-bit register. The incrementerhas a Carry-in (CN) input and a Carry-out (CN + 4) outputto facilitate cascading. The Carry-in input controls the microprogramcounter. When Carry-in is HIGH the incrementercounts sequentially. The counter register is loadedwith the current Y output plus one (Y + I - > J,tPC) onthe next clock cycle. When Carry-in is LOW the incrementerdoes not count. The microprogram counter register isloaded with the same Y output (Y - > J,tPC) on the nextclock cycle.StackThe Stack consists of a 4 x 4 memory array and a built-inStack Pointer (SP) which always points to the last wordwritten. The Stack is used to store return addresses whenexecuting microsubroutines.The Stack Pointer is an up/down counter controlled byFile Enable (FE) and Push/Pop (PUP) inputs. The FileEnable input allows stack operations only when it is LOW.The Push/Pop input controls the stack pointer position.The PUSH operation is initiated at the beginning of a microsubroutine.Push/Pop is set HIGH while Ftle Enable iskept LOW. The stack pointer is incremented and the memoryarray is written with the microinstruction address followingthe subroutine jump that initiated the push.The POP operation is initiated at the end of a microsubroutineto obtain the return address. Both Push/Pop andFtle Enable are set LOW. The return address is alreadyavailable to the multiplexer. The stack pointer is decrementedon the next LOW to HIGH clock transition, effectivelyremoving old information from the top of the stack.The stack is configured so that data will roll-over if morethan four POPs are performed, thus preventing data frombeing lost.The contents of the memory position pointed to by theStack Pointer is always available to the multiplexer. Stackreference operations can thus be performed without a pushor a pop. Since the stack is four words deep, up to fourmicrosubroutines can be nested.The ZERO input resets the four Y outputs to a binary zerostate. The OR inputs (7C909 only) are connected to the Youtputs such that any output can be set to a logical one.The Output Enable (OE) input controls the Y outputs. AHIGH on Output Enable sets the outputs into a high impedancestate.Definition of TermsNameINPUTSSI, SoFEPUPREZEROOEORjC nRjDjCPDescriptionMultiplexer Control Lines, for Access Source SelectionFile Enable, Enables Stack Operation, Active LOWPush/Pop, Selects Stack OperationRegister Enable, Enables Address Register Active LOWForces Output to Logical ZeroOutput Enable, Controls Three-State Outputs Active LOWLogic OR Input to each Address Output Line (7C909 only)Carry-In, Controls Microprogram CounterInputs to the Internal Address RegisterDirect Inputs to the MultiplexerClock Input5-104

5JiCY7C909; CY7C911. ~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=Definition of Terms (Continued)NameOUTPUTSYjCN + 4INTERNAL SIGNALSJ-LPCARSTKO-STK3SPEXTERNAL SIGNALSAI(A)J-LWRTNAddress OutputsDescriptionCarry-Out from IncrementerContents of the Microprogram CounterContents of the Address RegisterContents of the Push/Pop StackContents of the Stack PointerAddress to the Counter MemoryInstruction in Control Memory at Address AContents of the Microword Register at theOutput of the Control MemoryTime Period (Cycle) n5-105

5ACY7C909. CY7C911~ucr~==================================================================Typical DC and AC Characteristics1l@N:::;,.~ 1.4~----+---------l:lfil~~N:::;,.

finCY7C909-.. CY7C911~ ~NDUcrOR=====================================================================Ordering InformationClockCycle(ns)Ordering CodePackageTypeOperatingRangeClockCycle(ns)Ordering CodePackageTypeOperatingRange30 CY7C909-30PC PIS Commercial 30 CY7C911-30PC PS Commercial40 CY7C909-40PC PIS Commercial 40 CY7C911-40PC PS Commercial30 CY7C909-30JC J64 Commercial 30 CY7C911-30JC J61 Commercial40 CY7C909-40JC J64 Commercial 40 CY7C911-40JC J61 Commercial30 CY7C909-300C 016 Commercial 30 CY7C911-300C D6 Commercial40 CY7C909-400C 016 Commercial 40 CY7C911-400C 06 Commercial40 CY7C909-40LC L64 Commercial 40 CY7C911-40LC L61 Commercial30 CY7C909-300MB 016 Military 30 CY7C911-300MB D6 Military40 CY7C909-400MB 016 Military 40 CY7C911-400MB D6 Military40 CY7C909-40LMB L64 Military 40 CY7C911-40LMB L61 Military5-107

5ACY7C909. CY7C911~~UcrOR==================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3Subgroups!Ix 1,2,3loz 1,2,3los 1,2,3Icc 1,2,3ICCI 1,2,3Switching CharacteristicsParametersSubgroupsMinimum Clock Low Time 7,8,9,10,11Minimum Clock High Time 7,8,9,10,11MAXIMUM COMBINATIONALPROPAGATION DELAYSDjtoY 7,8,9,10,11Dj toCN+4 7,8,9,10,11So, SI to Y 7,8,9,10,11So, SI to CN+4 7,8,9,10,11ORj (7C909) to Y 7,8,9,10,11ORj (7C909) to CN+4 7,8,9,10,11CNtoCN+4 7,8,9,10,11ZEROtoCN+4 7,8,9,10,11Clock High, So, SI = LH 7,8,9,10,11toYClock High, So, S 1 = LH 7,8,9,10,11to CN+4Clock High, So, S I = LL 7,8,9,10,11toYClock High, So, S 1 = LL 7,8,9,10,11to CN+4Clock High, So, SI = HL 7,8,9,10,11toYClock High, So, SI = HL 7,8,9,10,11to CN+4Document #; 38-00015-BParametersMINIMUM SET-UP ANDHOLD TIMESSubgroupsRE Set-up Time 7,8,9,10,11REHoldTime 7,8,9,10,11Push/Pop Set-up Time 7,8,9,10,11Push/Pop Hold Time 7,8,9,10,11FE Set-up Time 7,8,9,10,11FE Hold Time 7,8,9,10,11CN Set-up Time 7,8,9,10,11CNHoldTime 7,8,9,10,11Dj Set-up Time 7,8,9,10,11DjHold Time 7,8,9,10,11ORj (7C909) Set-up Time 7,8,9,10,11ORj (7C909) Hold Time 7,8,9,10,11So, SI Set-up Time 7,8,9,10,11So, SI Hold Time 7,8,9,10,11ZERO Set-up Time 7,8,9,10,11ZERO Hold Time 7,8,9,10,115-108

Features• Fast- CY7C910-40 has a 40 ns(min.) clock cycle;commercial- CY7C910-46 has a 46 ns(min.) clock cycle; military• Low power- ICC (max.) = 70 rnA• V CC margin 5V ± 10%commercial and military• Sixteen powerfulmicroinstructions• Three output enable controlsfor three-way branch• Twelve-bit address word• Four sources for addresses:microprogram counter (MPC),stack, branch address bus,internal holding register• 12-bit internal loop counter• Internal 17-word by 12-bit stackThe internal stack can be usedLogic Block DiagramCYPRESSSEMICONDUCTORfor subroutine return address ordata storage• ESD protectionCapable of withstanding over2000V static discharge voltage• Pin compatible and functionalequivalent to AM2910AFunctional DescriptionThe CY7C91O is a stand-alone microprogramcontroller that selects, stores,retrieves, manipulates and tests addressesthat control the sequence of executionof instructions stored in an externalmemory. All addresses are 12-bitbinary values that designate an absolutememory location.The CY7C91O, as illustrated in theblock diagram, consists ofa 17-wordby 12-bit LIFO (Last-In-First-Out)stack and SP (Stack Pointer), a 12-bitRC (Register/Counter), a 12-bit MPC(Microprogram Counter) and incrementer,a 12-bit wide by 4-input multi-Pin ConfigurationsCY7C910CMOS MicroprogramControllerplexer and the required data manipulationand control logic.The operation performed is determinedby four input instruction lines (10-I3)that in turn select the (internal) sourceof the next micro-instruction to befetched. This address is output on theyo-Yll pins. Two additional inputs(CC and CCEN) are provided that areexamined during certain instructionsand enable the user to make the executionof the instruction either unconditionalor dependent upon an externaltest.The CY7C91O is a pin compatible,functional equivalent, improved performancereplacement for theAM291OA.The CY7C91O is fabricated using anadvanced 1.2 micron CMOS processthat eliminates latchup, results in ESDprotection of over 2000 volts andachieves superior performance and lowpower dissipation.Y 4D3D4 Y 3RLo(j I~ It) It) ...... '" '" '" "'-z>o>-o>-o>-o>-o6 5 4 3 2 ~4443 424140.J:.l: 7 39 YlMAP 8 38 Do13 9 37 Yo12 10 36 NCVee 11 35 Cl11 12 34 CP10 13 33 GNDCCEN 14 32 NCee 15 31 OERLD 16 30 Y 11NC 17 29 D111819202122232425262728Y sD2Ds Y 2VECTD1PL Y 1MAPDO13 Yo12 CIVCCCP11 GND10 OECCEN Y 11ccDllRLo Y 10FULL D 10D6 Y 9Y 6 °9D7Y a==>OATAPATH--CONTROLLINES0041-10041-8Y 7Top ViewDa0041-2Selection GuideClockCycie(Min.) innsStackDepthOperating RangePart Number40 17 words Commercial CY7C91O-4046 17 words Military CY7C91O-4650 17 words Commercial CY7C91O-5051 17 words Military CY7C910-5193 17 words Commercial CY7C91O-9399 17 words Military CY7C91O-995-109

~ CY7C910~~~~UcrOR =====================================================================Pin DefinitionsSignalNameDO-Dl1RLDI/OII10-13 ICCCCENCPIIIDescriptionDirect inputs to the RC (Register/Counter) and multiplexer. DO is LSBand DII is MSB.Register load. Control input to RC that,when LOW, loads data on the DO-DIIpins into RC on the LOW to HIGHclock (CP) transition.Instruction inputs that select one ofsixteen instructions to be performed bythe CY7C91O.Control input that, when LOW,signifies that a test has passed.Enable for CC input. When HIGH CCis ignored and a pass is forced. WhenLOW the state of CC is examined.Clock input. All internal states arechanged on the LOW to HIGH clocktransitions.SignalNameCIOEYO-YIII/ODescriptionI Carry input to the LSB of theincrementer for the MPC.I Control for YO-Yll outputs. LOW toenable; High to disable.o Address output to microprogrammemory. YO is LSB and Y 11 is MSB.o When LOW indicates the stack is full.o When LOW selects the pipeline registeras the direct input (DO-DIl) source.o When LOW selects the MappingPROM (or PLA) as the direct inputsource.o When LOW selects the InterruptVector as the direct input source.5-110

~ CY7C910.n~NDUcrOR ======================================================================;;;;Architecture of the CY7C910IntroductionThe CY7C91O is a high performance CMOS microprogramcontroller that produces a sequence of 12-bit addresses thatcontrol the execution of a microprogram. The addressesare selected from one of four sources, depending upon the(internal) instruction being executed (10-13), and other externalinputs. The sources are (1) the (external) DO-Dllinputs, (2) the RC, (3) the stack and (4) the MPC. Twelvebit lines from each of these four sources are the inputs to amultiplexer, as shown in Figure 1, whose outputs are appliedto the inputs of the YO-Yll three-state output drivers.External Inputs: DO-DllThe external inputs are used as the source for destinationaddresses for the jump or branch type of instructions.These are shown as Ds in the two columns in the Table ofInstructions. A second use of these inputs is to load theRC.Register Counter: RCThe RC is implemented as 12 D-type, edge-triggered flipflopsthat are synchronously clocked on the LOW toHIGH transition of the clock, CPo The data on the D inputsis synchronously loaded into the RC when the loadcontrol input, RLD, is LOW. The output of the RC isavailable to the multiplexer as its R input and is output onthe Y outputs during certain instructions, as shown by R inthe Table of Instructions.The RC is operated as a 12-bit down counter and its contentsdecremented and tested if zero during instructions 8,9 and 15. This enables micro-instructions to be repeated upto 4096 times. The RC is arranged such that if it is loadedwith a number, N, the sequence will be executed exactlyN+ 1 times.The Stack and Stack Pointer: SPThe 17-word by 12-bit stack is used to provide return addressesfrom micro-subroutines or from loops. Intergal to itis a SP, which points to (addresses) the last word written.This permits reference to the data on the top of the stackwithout having to perform a POP operation.The SP operates as an up/down counter that is incrementedwhen a PUSH operation (instructions 1,4 or 5) is performedor decremented when a POP operation (instructions8, 10, 11, 13 or 15) is performed. The PUSH operationwrites the return address on the stack and the POPoperation effectively removes it. The actual operation occurson the LOW to HIGH clock transition following theinstruction.The stack is initialized by executing instruction zero(JUMP TO LOCATION 0 or RESET). Every time a"jump to subroutine" instruction (1, 5) or a loop instruction(4) is executed, the return address is PUSHed onto thestack; and every time a "return from subroutine (or loop)"instruction is executed, the return address is POPed off thestack.When one subroutine calls another or a loop occurs withina loop (or a combination), which is called nesting, the Logicaldepth of the stack increases. The physical stack depthis 17 words. When this depth occurs, the FULL signal goesLOW on the next LOW to HIGH clock transition. Anyfurther PUSH operations on a full stack will cause the dataat that location to be over-written, but will not incrementthe SP. Similarily, performing a POP operation on a emptystack will not decrement the SP and may result in nonmeaningfuldata being available at the Y outputs.The Microprocessor Counter: MPCThe MPC consists of a 12-bit incrementer followed by a12-bit register. The register usually holds the address of theinstruction being fetched. When sequential instructions arefetched, the carry input (CI) to the incrementer is HIGHand one is added to the Y outputs of the multiplexer, whichis loaded into the MPC on the next LOW to HIGH clocktransition. When the CI input is LOW, the Y outputs ofthe multiplexer are loaded directly into the MPC, so thatthe same instruction is fetched and executed.5-111

Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... -65°C to + 150°C Static Discharge Voltage ..................... > 2001VAmbient Te~perature with ° ° (Per MIL-STD-883 Method 3015)Power Apphed .................... - 55 C to + 125 CSupply Voltage to Ground PotentialOperating Range(Pin 10 to Pin 30) .................... -0.5V to + 7.OVAmbientRangeDC Voltage Applied to OutputsTemperatureVeein High Z State ...................... -0.5V to + 7.OVCommercial O°Cto + 70°C 5V ±1O%DC Input Voltage ................... - 3.0V to + 7.OVMilitary [3] - 55°C to + 125°C 5V ±1O%Output Current into Outputs (Low) ............. 30 rnAElectrical Characteristics Over Commercial and Military Operating Range, VCC Min. = 4.5V, VCC Max. = 5.5V[4]ParameterVOHVOLVIHVILIIHIlLIOHIOLIozIseIcelee!DescriptionOutput HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput HIGH CurrentInput LOW CurrentOutput HIGH CurrentOutput LOW CurrentOutput Leakage CurrentOutput Short Circuit CurrentSupply CurrentSupply CurrentCommercialMilitaryCommercialMilitaryTest Condition Min. Max. UnitsVee = Min.IOH = -1.6mAVee = Min.IOL = 12mAVee = Max.VIN = VeeVee = Max.VIN = VSSVee = Min.VIH = 2.4VVee = Min.VOL = 0.4V2.4 V0.4 V2.0 Vee V-3.0 0.8 V10 p,A-10 p,A-1.6 rnA12 rnAVee = Max. +40 p,AVOUT = Vss/Vee -40 p,AVee = Max.VOUT = OVVee = Max.-85 rnA70rnA35VIH ::::: 3.85V, VIL :::;; O.4V rnA5090Capacitance [2]ParametersCINCOUTDescriptionInput CapacitanceOutput CapacitanceNotes:1. Not more than one output should be tested at a time. Duration of theshort circuit should not exceed one second.2. Tested initially and after any design or process changes that mayaffect these parameters.Output Load used for AC PerformanceCharacteristicsAll Outputs+5 vvoTi~:.Notes: 0041-41. CL = 50 pF includes scope probe, writing and stray capacitance.2. CL = 5 pF for output disable tests.Test Conditions Max. UnitsTA = 25°C, f = 1 MHz 8 pFVee = 5.0V10 pF5-1123. T A is the "instant on" case temperature.4. See the last page of this specification for Group A subgroup testinginformation.Switching Waveforms3.0V ---------_1,.------_1,.---INPUTS 1.5VoV----------'I~------'I~--HOLD TIME3.0VCLOCKOVOUTPUTS-------------'I~-------0041-5

~RfSSCY7C910~~~CONDUcrOR =====================================================================Guaranteed AC Performance CharacteristicsThe tables below specify the guaranteed AC performanceof the CY7C91O over the commercial (O°C to + 70°C) andthe military (- 55°C to + 125°C) temperature ranges withVee varying from 4.SV to S.SV. All times are in nanosecondsand are measured between the 1.5V signal levels.Clock Requirements [1, 3]CommercialThe inputs switch between OV and 3V with signal transitionrates of 1 Volt per nanosecond. All outputs havemaximum DC current loads.MilitaryCY7C91O- 40 50 93 46 51 99Minimum Clock LOW 20 20 50 23 25 58Minimum Clock HIGH 20 20 35 23 25 42Minimum Clock Period I = 14 40 SO 93 46 51 100Minimum Clock Period 40 50 113 46 51 1141= 8,9,15Combinatorial Propagation Delays. CL = 50 pp[3]CommercialMilitaryFrom Input Y PL, VECf, MAP FULL Y PL, VECf, MAP FULLCY7C91O- 40 50 93 40 50 93 40 50 93 46 51 99 46 51 99 46 51 99DO-Dll 17 20 20 - - - - - - 21 25 25 - - - - - -IO-I3 25 35 50 20 30 51 - - - 30 40 54 25 35 58 - - -CC 22 30 30 - - - - - - 27 36 35 - - - - - -CCEN 22 30 30 - - - - - - 27 36 37 - - - - - -CPI = 8,9,15 30 40 75 - - - 25 31 60 35 46 77 - - - 30 35 67(Note 2)CP 30 40 55 - - - 25 31 60 35 46 61 - - - 30 35 67All Other IOE 21 25 35 - - - - - - 22 25 40 - - - - - -(Note 2) 21 27 30 - - - - - - 22 30 30 - - - - - -Minimum Set-Up and Hold Times Relative to clock LOW to HIGH Transition. CL =50 pp[3]CommercialInput Set-Up HoldCY7C91O- 40 50 93 40 50DI ----+ RC 13 16 24 0 0DI ----+ MPC 20 30 58 0 0IO-I3 25 35 75 0 0CC 20 24 63 0 0CCEN 20 24 63 0 0CI 15 18 46 0 0RLD 15 19 36 0 0Notes:1. A dash indicates that a propagation delay path or set-up time does notexist.Set-UpMilitaryHold93 46 51 99 46 51 990 13 16 28 0 0 00 20 30 62 0 0 00 27 38 81 0 0 00 25 35 65 0 0 00 25 35 63 0 0 00 15 18 58 0 0 00 15 20 42 0 0 02. The enable/disable times are measured to a 0.5 Volt change on theoutput voltage level with CL = 5 pF.3. See the last page of this specification for Group A subgroup testinginformation.5-113

Table of InstructionsReg!ResultCntr Fail Pass13-10 Mnemonic NameCon- CCEN = LandCC = H CCEN = HorCC = L Reg!tents yCntrStack Y StackEnable0 JZ Jump Zero X 0 Clear 0 Clear Hold PL1 CJS CondJSB PL X PC Hold D Push Hold PL2 JMAP Jump Map X D Hold D Hold Hold Map3 CJP CondJumpPL X PC Hold D Hold Hold PL4 PUSH Push/Cond LD CNTR X PC Push PC Push (Note 1) PL5 JSRP Cond JSB R/PL X R Push D Push Hold PL6 CJV Cond Jump Vector X PC Hold D Hold Hold Vect7 JRP Cond Jump R/PL X R Hold D Hold Hold PL8 RFCTRepeat Loop, *0 F Hold F Hold Dec PLCNTR *0 =0 PC POP PC Pop Hold PLRepeat PL,9 RPCT*0 D Hold D Hold Dec PLCNTR*O =0 PC Hold PC Hold Hold PL10 CRTN CondRTN X PC Hold F Pop Hold PL11 CJPP Cond Jump PL & Pop X PC Hold D Pop Hold PL12 LDCT LD Cntr & Continue X PC Hold PC Hold Load PL13 LOOP Test End Loop X F Hold PC Pop Hold PL14 CaNT Continue X PC Hold PC Hold Hold PL15 TWB Three-Way Branch *0 F Hold PC Pop Dec PL=0 D Pop PC Pop Hold PLNotes:1. If CCEN = Land CC = H, hold; else load. H = HIGH L= LOW x = Don't Care5-114

~ CY7C910~)r;~UaDR==========================================================~==CY7C910 CMOS Microprogram ControllerCY7C910 Flow DiagramsQ Jump Zero (JZ)1 Cond JSB PL (CJS)2 Jump Map (JMAP)66 68 STACK65M67 4068 4169 4270 436665L,6768 85863 Cond Jump PL (CJP)4 Push/Cond LD CNTR (PUSH)5 Cond JSB R/PL (JSRP)6665h6768 2569 2665k:6 STACK666768 f'N\ REGISTER/\V COUNTER6 Cond Jump Vector (CJV)6665h6768 3569 367 Cond Jump R/PL (JRP)20216566673031303132333440414243448 Repeat Loop, CNTRjiQ (RFCT)656667686970STACK66 (PUSH)N RESISTER/COUNTER11 Cond Jump PL & POP (CJPP)65 66 [~~~~)6667 4068(~-+-__ ..... 30 4169 31 4270 327114 Continue (CONT)65 66 t67689 Repeat PL, CNTRjiQ (RPCT)65~666768 ..12 LD CNTR & Continue (LDCT)65~COUNTER66676815 Three-Way Branch (TWB)~STACK65 67 (PUSH)66N REGISTER/67COUNTER68 7269 7310 Cond Return (CRTN)656667686970@STACK13 Test End Loop (LOOP)656667686970717230313233343536370041-95-115

~ CY7C910~~~U~==================================================================One Level Pipeline Based Architecture (Recommended)MAP......... -- CLOCKCY7C245REGISTERED PROM0041-6,.-------- 72 ns CYCLE TIME -------~CLOCK(CLOCK TO REGISTER OUTPUT)PIPELINE CY7C910 -----~~~~------------------_t_REGISTER OUTPUT • INSTRUCTION INPUT _____ ~~...w.;~ __________________ +_18 ns (MUX SELECT TO OUTPUT)OU~~~·g~~~~~ _____ ~~~~~~~ _______________ ~---.., (CC TO Y)CY7C910-----~~~~~~~~~~~~~~---------t-OUTPUT ______ ~~~~~~~~~~~~~~--------~-(PROM ADDRESS SETUP TIME) 20 ns -xxXXXXXXXXXXXXXXXXXXXXXXXXXXXXMICROPROGRAM -------~!"ft"''''''P''JIIP''ft''IIIP'9I''''''''''''ft''I''''''''!''ft''''''..,P''JIIP''fII!''ft'''.,...,P''JIIP''fllr''''ft'''''"''t''''''''r''''ft''~-MEMORYOUTPUT-------6---~,----~~-------~~...w.;~~~~~~~~~~~~~~~-0041-75-116

Typical DC and AC Characteristicsu..YClWN::::;..:(:::::EII::oZNORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE1.2 ,..-----r---,----r-----,1.0 I----+---+--~---j0.8 [-----t-~"+----t-------;0.6VIN =5.0VTA = 25°C0.44.0 4.5 5.0 5.56.0~ClWN::::;..:(:::::EII::oZNORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE1.4 ,..---------,.------,1.21------+-------11.0 \o;;;::-----t----------;0.8 1------+---=""""::------\0.6 '--------'--------'-55 25 125~5t- ZWII::II::::;)UwuII::::;)0Vlt-::;)a...t-::;)0OUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE60IVee = 5.0V50TA = 25°C -40 ~"~30"~20'~10"o o 1.0 2.0 3.0 4.0SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE (OC)OUTPUT VOLTAGE (V)" \NORMALIZED FREQUENCY )vs. SUPPLY VOLTAGE1.3NORMALIZED FREQUENCYvs. AMBIENT TEMPERATURE1.6 ,..---------,.------,OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE140u>-zL..J:::>0L..J0::"-0.........::::ic:(~:t::::>z1.21.11.0~0.90.80.74.0--~-TA = 25°C4.5 5.0 5.5-6.0u>­zw::;)oWII::Lo..ClWN::::;..:(:::::EII::oZ1.41------+-------11.2 I--~.,,----+-------j1.0 [-------+--------"=--+V ee =5.0V0.8 [-------t----------;0.6 L...-___ --..L._____--'-55 25 125~5t-zWII::II::::;)u:.::ziiit-::;)a...t-::;)012010080604020./ ~/ /'/ V ee =5.0VTA = 25°C -I/oVo 1.0 2.0 3.0 4.0SUPPLY VOLTAGE (V)AMBIENT TEMPERATURE (OC)OUTPUT VOLTAGE (V)>-..:(...JwClt-::;)a...t- :::>0ClL..JN::::;..:(:::::EII::0z1.6NORMALIZED OUTPUT DELAYvs. OUTPUT LOADING,,--1.51.4 /1.3 / ~V1.21.1 LV ee =5.0VTA =25 0 C-1.0 Io//"u_u200 400 600 800 1000ClwN::::;..:(:::::EII::0z1.11.00.90.80.7NORMALIZED Iccvs. FREQUENCYL///~/ V V ee =5.5VT A =250C -VIN =OVor3Vo I Io 5 10 15 20 25 30 35CAPACITANCE (pF)FREQUENCY (MHz)0041-105-117

~ CY7C910~~~NDUcrOR================================================================~Ordering InformationClockCycle(ns)Ordering CodePackageTypeOperatingRange40 CY7C91O-40PC P17 CommercialCY7C91O-40DC 018CY7C91O-40JCCY7C91O-40LCJ67L6746 CY7C910-46DMB 018 MilitaryCY7C91O-46LMBL6750 CY7C9IO-50PC PI7 CommercialCY7C910-50DC 018CY7C91O-50JCCY7C91O-50LCJ67L6751 CY7C91O-51DMB 018 MilitaryCY7C91O-51 LMBL6793 CY7C91O-93PC P17 CommercialCY7C910-93DC 018CY7C91O-93JCCY7C91O-93LCJ67L6799 CY7C91O-99DMB 018 MilitaryCY7C91O-99LMBL675-118

I• ~~~~~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==CY7C910MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3Vm 1,2,3VIL 1,2,31m 1,2,3IlL 1,2,3IOH 1,2,3IOL 1,2,3Ioz 1,2,3ISC 1,2,3Icc 1,2,3ICC! 1,2,3Clock RequirementsParametersSubgroupsSubgroupsMinimum Clock LOW 7,8,9,10,11Combinational Propagation DelaysParametersSubgroupsFrom DO-Dll to Y 7,8,9,10,11From IO-I3 to Y 7,8,9,10,11From IO-I3 to PL, VECT, MAP 7,8,9,10,11FromCCtoY 7,8,9,10,11From CCEN to Y 7,8,9,10,11From CP (I = 8,9,15) to FULL 7,8,9,10,11From CP (All Other I) to Y 7,8,9,10,11From CP (All Other I) to FULL 7,8,9,10,11)ocument #: 38-00016-BMinimum Set-up and Hold TimesParametersSubgroupsDI ---+ RC Set-up Time 7,8,9,10,11DI ---+ RC Hold Time 7,8,9,10,11DI ---+ MPC Set-up Time 7,8,9,10,11DI ---+ MPC Hold Time 7,8,9,10,11IO-I3 Set-up Time 7,8,9,10,11IO-I3 Hold Time 7,8,9,10,11CC Set-up Time 7,8,9,10,11CC Hold Time 7,8,9,10,11CCEN Set-up Time 7,8,9,10,11CCEN Hold Time 7,8,9,10,11CI Set-up Time 7,8,9,10,11CIHold Time 7,8,9,10,11RLD Set-up Time 7,8,9,10,11RLD Hold Time 7,8,9,10,115-119

Features• Fast- CY7C9101-30 has a 30 ns(max.) clock cycle(commercial)- CY7C9101-35 has a 35 ns(max.) clock cycle (military)• Low Power- IcC (max. at10 MHz) = 60 mA(commercial)- Icc (max. at10 MHz) = 85 mA(military)• Vee Margin- 5V ±10%• All parameters guaranteed overcommercial and militaryoperating temperature range• Replaces four 2901's with carrylook-ahead logic• Eight Function ALU- Performs three arithmeticand five logical operationson two 16-bit operandsCYPRESSSEMICONDUCTOR• Expandable- Infinitely expandable in16-bit increments• Four Status Flags- Carry, overflow, negative,zero• ESD Protection- Capable of withstandinggreater than 2000V staticdischarge voltage• Pin compatible and functionallyequivalent to AM29CI0lFunctional DescriptionThe CY7C9101 is a high-speed, expandable,16-bit wide ALU slice whichcan be used to implement the arithmeticsection of a CPU, peripheral controller,or programmable controller.The instruction set of the CY7C9101 isbasic, yet so versatile that it can emulatethe ALU of almost any digitalcomputer.CY7C9101CMOS Sixteen-Bit SliceThe CY7C9101, as shown in the blockdiagram, consists ofa 16-word by16-bit dual-port RAM register file, a16-bit ALU, and the necessary datamanipulation and control logic.The function performed is determinedby the nine-bit instruction word (18 to10) which is usually input via a microinstructionregister.The CY7C9101 is expandable in 16-bitincrements, has three-state data outputsas well as flag outputs, and canimplement either a full look-ahead carryor a ripple carry.The CY7C9101 is a pin compatible,functional equivalent of the Am29C101with improved performance. The7C9101 replaces four 2901's and includeson-chip carry look-ahead logic.Fabricated in an advanced 1.2 micronCMOS process, the 7C9101 eliminateslatchup, has ESD protection greaterthan 2000V, and achieves superior performancewith low power dissipation.Logic Block Diagram18- 0Pin ConfigurationTop ViewA (READ)0,5-0(DIRECTDATA-IN)Ys0 6OsO 20,Y,s-oDATA OUTFigure 10079-18 3CPRAt.40Qo0079-25-120

~ CY7C9101~~~NDUcrOR=======================================================================Selection Guide7C9101-30 7C9101-407C9101-35 7C9101-45Minimum Clock Commercial 30 40Cycle (ns)Military 35 45Maximum Operating Commercial 60 60Current at 10 MHz (mA)Military 85 85Maximum Ratings(Above which the useful life may be impaired. For user guidelines, not tested.)Storage Temperature ............... - 65°C to + 150°C Static Discharge Voltage ..................... > 2001 VAmbient Temperature with(Per MIL-STD-883 Method 3015)Power Applied .................... - 55°C to + 125°CSupply Voltage to GroundPotential ........................... -0.5V to + 7.0VDC Voltage Applied to Outputsin High Z State ...................... - 0.5V to + 7.0VDC Input Voltage ................... - 3.0V to + 7.0VOutput Current into Outputs (Low) ............. 30 rnAPin DefinitionsSignal I/OName18-0DI5-0YI5-0CPDescriptionRAM Address A. This 4-bit address word selectsone of the 16 registers in the register file foroutput on the (internal) A-port.RAM Address B. This 4-bit address word selectsone of the 16 registers in the register file foroutput on the (internal) B-port. When data iswritten back to the register file, this is thedestination address.Instruction Word. This nine-bit word is decodedto determine the ALU data sources (10,1,2), theALU operation (13, 4, 5), and the data to bewritten to the Q-register or register file (16, 7,8).Direct Data Input. This 16-bit data word may beselected by the 10, 1,2 lines as an input to theALU.Data Output. These are three-state data outputlines which, when enabled, output either theALU result or the data in the A latch, asdetermined by the code on 16, 7, 8.Output Enable. This is an active LOW inputwhich controls the Y 15-0 outputs. A HIGH levelon this signal places the output drivers at the highimpedance state.Clock. The LOW level of CP is used to write datato the RAM register file. A HIGH level of CPwrites data from the dual port RAM to the A andB latches. The operation of the Q register issimilar; data is entered into the master latch onthe LOW level of CP and transferred from masterto slave during CP = HIGH.These two lines are bidirectional and areI/O controlled by 16, 7, 8. They are three-state outputdrivers connected to the TTL compatible CMOSinputs.5-121Latchup Current (Outputs) .................. > 200 rnAOperating RangeRangeAmbientTemperatureVeeCommercial O°C to + 70°C 5V ±1O%Military[l] -55°C to + 125°C 5V ± 10%Note:1. T A is the "instant on" case temperature.Signal 110NameDescriptionQI5, Output Mode: When the destination code on linesRAMI5 I/O 16,7,8 indicates a left shift (UP) operation, the(Cont.) three-state outputs are enabled and the MSB ofthe Q register is output on the QI5 pin andlikewise, the MSB of the ALU output (FI5) isoutput on the RAM 15 pin.Input Mode: When the destination code indicatesa right shift (DOWN), the pins are the datainputs to the MSB of the Q register and theRAM, respectively.Qo, These two lines are bidirectional and functionRAMo I/O similarly to the QI5 and RAMI51ines. The Qoand RAMo lines are the LSB of the Q registerand the RAM.C n I Carry In. The carry in to the internal ALU.C n + 16 0 Carry Out. The carry out from the internal ALU.G, P 0 Carry Generate, Carry Propagate. Outputs fromthe ALU which may be used to perform a carrylook-ahead operation over the 16-bits of theALD.OVR 0 Overflow. This signal is the logical exclusive-ORof the carry-in and carry-out ofthe MSB of theALU. This indicates when the result of the ALUoperation exceeded the capacity of the machine'stwo's complement number range. It is valid onlyfor the sign bit.F = 0 0 Zero Detect. Open drain output which goesHIGH when the data on outputs (FI5-0) are allLOW. It indicates that the result of an ALUoperation is zero (positive logic assumed).FI5 0 Sign. The MSB of the ALU output.

~ CY7C9101~~~NDUcrOR =====================================================================Top ViewGGGG®8GGG51 50 48 46 44 42 40 38 36SGGGG@@G8@@53 52 49 47 45 43 41 39 37 35 34() 55 ~ 54 r-------------, ~ 32 G 3300 9857 56 30 3108 0059 58 28 29(08 0888 80~ ~ ~ ~GGG8~ ~ 'u eG G ------------- G G80888GGeeSe68 1 3 5 7 9 11 13 15 18 19·GGG@@(0)C9C92 4 6 8 10 12 14 16 17CY7C9101 Pinout for 68PGANC = No Connect0079-11Top ViewIt)'"J~~~~fJ~3~~~J~~~~9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61N,C. 10 60 Y 14014 11013 12012 130Il 14010 1559 Y 1358 Y 1257 Y 1156 l055 Yg09 1608 17Vce 1807 190 6 2005 2104 220 3 2302 2401 25°0 2~7 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4r~~m~~df8~~~~:~~~~'" ...CY7C9101 Pinout for LCC/PLCCNC = No Connect54 Y 853 GNO52 GNO51 or50 Y 749 Y 648 Ys47 Y 446 Y 345 Y 2Y 10079-35-122

~ CY7C9101~~~NDUcrOR =====================================================================Functional TablesMnemonicTable 1. ALU Source Operand ControlMicro CodeALUSourceOperandsTable 2. ALU Function ControlMicroCodeMnemonicALUOctal Symbol15Function14 13 CodeADD L L L 0 RPlusS R+S12 11 10OctalCodeR SAQ L L L 0 A Q SUBR L L H 1 SMinusR S-RAB L L H 1 A B SUBS L H L 2 RMinusS R-SZQ L H L 2 0 Q OR L H H 3 RORS RVSZB L H H 3 0 B AND H L L 4 RANDS RASZA H L L 4 0 A NOTRS H L H 5 RANDS RASDA H L H 5 D A EXOR H H L 6 REX-ORS RV-SDQ H H L 6 D Q EXNOR H H H 7 REX-NORS RV-SDZ H H H 7 D 0MnemonicMicro CodeIs 17 16OctalCodeTable 3. ALU Destination ControlRAM FunctionQ-Reg.RAMFunction Y ShifterQ ShifterOutputShift Load Shift Load RAMo RAM IS Qo QISQREG L L L 0 X None None F~Q F X X XNOP L L H 1 X None X None F X X XRAMA L H L 2 None F~B X None A X X XRAMF L H H 3 None F~B X None F X X XRAMQD H L L 4 DOWN F/2 ~ B DOWN Q/2 ~ Q F Fo IN15 QoRAMD H L H 5 DOWN F/2 ~ B X None F Fo IN15 QoRAMQU H H L 6 UP 2F ~ B UP 2Q ~ Q F INo F15 INoRAMU H H H 7 UP 2F ~ B X None F INo F15 Xx = Don't care. Electrically, the input shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.A = Register Addressed by A inputs.B = Register Addressed by B inputs.UP is toward MSB, DOWN is toward LSB.Table 4. Source Operand and ALU Function Matrix1210 Octal 0 1 2 3 4 5 6ALUSourceOctal ALU1 543 Function A,Q A,B O,Q O,B O,A D,A D,Q0 C n = L A+Q A+B Q B A D+A D+Q DRplus SC n = H A+Q+l A+B+l Q+l B+l A+l D+A+l D+Q+l D+l1 C n = L Q-A-l B-A-l Q-l B-1 A-I A-D-l Q-D-l -D-lSminusRC n = H Q-A B-A Q B A A-D Q-D -D2 C n = L A-Q-l A-B-l -Q-l -B-1 -A-l D-A-l D-Q-l D-lRminus SC n = H A-Q A-B -Q -B -A D-A D-Q D3 RORS AVQ AVB Q B A DVA DVQ D4 RANDS AAQ AAB 0 0 0 DAA DAQ 05 RANDS AAQ AAB Q B A DAA DAQ 06 REX-ORS AV-Q AV-B Q B A DV-A DV-Q D7 REX-NORS AV-Q AV-B Q B A DV-A DV-Q D+ = Plus; - = Minus; V = OR; 1\ = AND; ¥ = EX-OR5-123XXXXIN15XQ15Q157D,O

~ CY7C9101~~~NDUcrOR =====================================================================Description of ArchitectureGeneral DescriptionThe 7C9101 block diagram is shown in Figure 1. Detailedblock diagrams show the operation of specific sections asdescribed below. The device is a 16-bit slice consisting of aregister file (16-word by 16-bit dual port RAM), the ALU,the Q-register and the necessary control logic. It is expandablein 16-bit increments.Register FileThe dual port RAM is addressed by two 4-bit addressfields (A3-0 and B3-0) which cause the data to simultaneouslyappear at the A or B (internal) ports. Both the Aand B addresses may be identical; in this case, the samedata will appear at both the A and B ports.Data to be written to RAM is applied to the D inputs ofthe 7C9101 and is passed (unchanged) through the ALU tothe RAM location specified by the B-address word. Newdata is written into the RAM by specifying a B addresswhile RAM write enable (RAM EN) is active and theclock input is LOW. RAM EN is an internal signal decodedfrom the signals 16, 7,8. As shown below, each of the 16RAM inputs is driven by a three-input multiplexer thatallows the ALU output (FlS-0) to be shifted one bit positionto the left, right, or not shifted. The RAMlS andRAMo I/O pins are also inputs to the 16-bit, 3-input multiplexer.During the left shift (upshift) operation, the RAMlS outputbuffer and RAMo input multiplexer are enabled. Forthe down shift (right) operation, the RAMo output bufferand the RAMlS input multiplexer are enabled.The A and B outputs of the RAM drive separate 16-bitlatches that are enabled (track the RAM data) when theclock is HIGH. The outputs of the A latch go to threemultiplexers which feed the two ALU inputs (RlS-0 andSIS-0) and the chip output (Y 15-0). The B latch outputsare directed to the multiplexer which feeds the S input totheALU.A3A - ADDRESS[A2A1AoWE) "-ADDRESSFigure 2. Register File0079-45-124

~~~==============================================~C~Y~7~C~9~1~O~1Description of Architecture (Continued)Q-RegisterThe Q-register is mainly intended for use as a separateworking register for multiplication and division routines. Itmar also ~unction as an accumulator or temporary storageregIster. ~Ixteen master-slave latches are used to implementth~ Q-register. As shown below, the Q-register inputs arednven by the outputs of the Q-shifter (sixteen 3-input multiplexers,under the control of 16 7 8). The function of theQ-register input multiplexers is to ~llow the ALU output~F15-0) to be either shifted left, right, or directly enteredI~to t~e !llaster latches. The Q15 and Qo pins (1/0) functionsimllarly to the RAM15 and RAMo pins describedearlier. Data is entered into the master latches when theclock is LOW and transferred to the slave (output) at theclock LOW to HIGH transition .~>-..... ..,~~l?..&. ~f--•••......O-SHIFTER.-- ~ '. --I- • --I-~' ------ >. -1-- .. ---10 ~.ALU : ... - L... L... ........ - - L....... L... ID~"NATION~:.~~'DECODE MUX MUX MUX MUX MUX MUX I II•II · -----------(, ;;3:'~ -"~;) ---- ---- --·, D5 D14 D13 ••• D2 Dl DoOENCP >- ~O-REGISTER0 15 014 013 0 12 ••• 03 O 2 0 1 0 0..--,.., °0.~~IFigure 3. Q-Register0079-55-125

~ CYmSSCY7C9101'nEMICONOUcrOR ====================================================Description of Architecture (Continued)ALU (Arithmetic Logic Unit)The ALU can perform three arithmetic and five logicaloperations on the two 16-bit input operands, Rand S. TheR-input multiplexer selects between data from the RAMA-port and data at the external data input, 015-0. TheS-input multiplexer selects between data from the RAMA-port, the RAM B-port, and the Q-register. The Rand S~ultiplexers are controlled by the 10,1,2 inputs as shownm Table 1. The Rand S input multiplexers each have an"inhibit capability," offering a state where no data ispassed. This is equivalent to a source operand consisting ofall zeroes. The Rand S ALU source multiplexers are configuredto allow eight pairs of combinations of A, B, 0, Q,and "0" to be selected as ALU input operands.The A~U functions, which are controlled by 13,4, 5, areshown m Table 2. Carry lookahead logic is resident on the7C9101, using the ALU inputs carry in (C n ) and the ALUoutputs carry propagate (P), carry generate (G), carry out(Co + 16), and overflow to implement carry lookaheadarithmetic and determine if arithmetic overflow has occurred.Note that the carry in (C n ) signal affects the arithmeticresult and internal flags; it has no effect on the logicaloperations.Control signals 16,7,8 route the ALU data output (FlS-0)to the RAM, the Q-register inputs, and the Y -outputs asshown in Table 3. The ALU result MSB (FlS) is output sothe user may examine the sign bit without needing to enablethe three-state outputs. The F = 0 output, used forzero detection, is HIGH when all bits of the F output areLOW. It is an open drain output which may be wire OR'edacross multiple 7C9101 processor slices.°15 °14 ••• 0 1 DO8 15 8 14 ••• 8 18 0Q15A1AOA15A14••°1412111 0CnR1Ro16-BIT ARITHMETIC LOGIC UNIT (ALU)S15 S14 ••• Sl GF 15 F14 ••• F1 FoisCn+16OVRF 15 (SIGN)F=O•••1 71 61 8OE•••Y 15 Y 14 •••Y 1 YoFigure 4. ALU0079-65-126

CY7C9101Description of Architecture (Continued)Octal1543,1210Table 5. ALU Logic Mode FunctionsGroupFunction40 AAQ41AABAND45 DAA46 DAQ30 AVQ3 1AVBOR35 DVA36 DVQ60 AV-Q61AV-BEX-OR65 DV-A66 DV-Q70 A1TQ71AV-BEX-NOR75 DV-A76 DV-Q72 Q73BINVERT74 A77 D62 Q63BPASS64 A67 D32 Q33BPASS34 A37 D42 0430"ZERO"44 047 050 AAQ5 1AABMASK55 DAA56 DAQTable 6. ALU Arithmetic Mode FunctionsOctal C n = 0 (Low) C n = 1 (High)1543,1210 Group Function Group Function00 A+Q01A+B ADD plusADD05 D+A one06 D+Q02 Q03BPASS04 A07 D12 Q-l1 3B-1Decrement14 A-I27 D-lIncrementPASS22 -Q-l23-B-1 2'sComp.l's Compo24 -A-l (Negate)1 7 -D-l10 Q-A-l1 1 B-A-l1 5 A-D-l16 Subtract Q-D-l Subtract20 (l's Comp.) A-Q-l (2's Comp.)2 1 A-B-l25 D-A-l26 D-Q-lConventional Addition and Pass-Increment/DecrementA+Q+lA+B+lD+A+lD+Q+lQ+lB+lA+lD+lQBAD-Q-B-A-DQ-AB-AA-DQ-DA-QA-BD-AD-QWhen the carry-in is HIGH and either a conventional additionor a PASS operation is performed, one (l) is addedto the result. If the DECREMENT operation is performedwhen the carry-in is LOW, the value of the operand isreduced by one. However, when the same operation is performedwhen the carry-in is HIGH, it nullifies the DEC­REMENT operation so that the result is equivalent to thePASS operation. In logical operations, the carry-in (Cn)will not affect the ALU output.SubtractionRecall that in two's complement integer coding - 1 isequal to all ones and that in one's complement integer codingzero is equal to all ones. To convert a positive integer toits two's complement (negative) equivalent, invert (complement)the number and add 1 to it; i.e., TWC = ONC + 1.In Table 6 the symbol - Q represents the two's complementof Q so that the one's complement of Q is then-Q -1.5-127

~ CY7C9101~~~NDUcrOR =====================================================================Electrical Characteristics Over Commercial and Military Operating Range[4]V cc Min. = 4.5V, V cc Max. = 5.5VParameters Description Test Conditions Min. Max. UnitsVOHVOLOutput HIGH VoltageOutput LOW VoltageVee = Min.IOH = -3.4mAVee = Min.IOL = 16mA2.4 V0.4 VVIH Input HIGH Voltage 2.0 VCC VVIL Input LOW Voltage -3.0 0.8 VIIXIOHIOLIozISCICc(Q1) [2]ICc(Q2) [2]Icc(Max. )[2]Capacitance [3]Input Leakage CurrentOutput HIGH CurrentOutput LOW CurrentOutput Leakage CurrentOutput Short Circuit Current[1]Vss ~ VIN ~ VCCVCC = Max.VCC = Min.VOH = 2.4VVCC = Min.VOL = O.4V-10 10 J.LA-3.4 rnA16 rnAVCC = Max. +40 J.LAVOUT = VSS to Vcc -40 J.LAVcc = Max.VOUT = OVSupply Current Commercial VSS ~ VIN ~ VIL or 30(Quiescent) Military VIH ~ VIN ~ V cc; OE = HIGH 35Supply Current Commercial VSS ~ VIN ~ 0.4Vor 25(Quiescent) Military 3.85V ~ VIN ~ V cc; OE = HIGH 30Supply Current Commercial V ce = Max., fCLK = 10 MHz; 60Military OE = HIGH 85-85 rnAParameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f= 1 MHz 5pFCOUTOutput CapacitanceVCC = 5.0V7Notes:1. Not more than one output should be tested at a time. Duration of the 3. Tested initially and after any design or process changes that mayshort circuit should not be more than one second.affect these parameters.2. Two quiescent figures are given for different input voltage ranges. To 4. See the last page of this specification for Group A subgroup testingcalculate IcC at any given frequency, use Icc(Qt) + Icc(A.C.) where information.Icc(Qt) is shown above and Icc(A.C.) = (3 rnA/MHz) X ClockFrequency for the Commercial temperature range. Icc(A.C.) =(5 rnA/MHz) X Clock Frequency for Military temperature range.Output Loads used for AC Performance CharacteristicsYour+5 V252017500079-9All Outputs except Open DrainNotes:1. CL = 50 pF includes scope probe, wiring and stray capacitance.2. CL = 5 pF for output disable tests.+5 V~270l!VO~CLJOpen Drain (F = 0)0079-10rnArnArnA5-128

~ CY7C9101~~~NDU~ =====================================================================Table 7. Logic Functions for CARRY and OVERFLOW Conditions1543 Function P G C n +16 OVR0 R+S PO-PISGIS + PISGI4 + PISPI4GI3 +... + PI-IS GoCI6CI6 ¥ CIS1 S-R +- Same as R + S equations, but substitute Ri for Rj in definitions ~2 R-S +- Same as R + S equations, but substitute Si for Sj in definitions ~3 RVS4 RAS5 RAS HIGH HIGH LOW LOW6 R¥S7 R¥SDefinitions: + = ORPO-IS = PIS PI4 PI3 PI2 Pll PlO P9 Ps P7 P6 Ps P4 P3 P2 PI PoPo = Ro + SoPI = RI + S2P2 = R2 + S2P3 = R3 + S3, etc.GO-IS = GIS GI4 G13 GI2 Gll GlO G9 GS G7 G6 Gs G4 G3 G2 GI GOGO = RoSoGI = RISIG2 = R2 S2G3 = R3 S3, etc.CI6 = GIS + PIS GI4 + PIS Pl4 G13 + ... + PO-IS CnCIS = GI4 + PI4 G13 + PI4 P13 GI2 + ... + PO-I4 CnCY7C9101-30 and CY7C9101-40 GuaranteedCommercial Range AC PerformanceCharacteristicsThe tables below specify the guaranteed AC performanceof these devices over the Commercial (O"C to 70°C) andMilitary ( - 55°C to + 125°C) operating temperature rangewith Vee varying from 4.5V to 5.5V. All times are innanoseconds and are measured between the 1.5V signal levels.The inputs switch between OV and 3V with signal transitionrates of 1 V per nanosecond. All outputs have maximumDC current loads. See also loading circuit information.This data applies to parts with the following numbers:Cycle Time and Clock CharacteristicsCY7C9101- 30Read-Modify-Write Cycle (from 30nsselection of A, B registers toend of cycle).Maximum Clock Frequency to shift Q 33 MHz(50% duty cycle, I = 432 or 632)Minimum Clock LOW Time20nsMinimum Clock HIGH TimeIOnsMinimum Clock Period30nsCY7C9101-30PC CY7C9101-30DC CY7C9101-30LC CY7C9101-30JC CY7C9101-30GCCY7C9101-40PC CY7C9101-40DC CY7C9101-40LC CY7C9101-40JC CY7C9101-40GCCombinational Propagation Delays. CL = 50 pFTo OutputFrom InputY F15 Cn + 16 G,P F=O OVRRAMoRAM15CY7C9101· 30 40 30 40 30 40 30 40 30 40 30 40 30 40A, BAddress 37 47 36 47 35 44 32 41 35 46 32 42 32 40D 29 34 28 34 25 32 25 30 29 36 21 26 27 33Co 22 27 22 27 20 25 - - 22 26 22 26 24 3010,1,2 32 40 32 40 30 38 28 36 34 42 26 32 27 3513,4, S 34 43 33 42 33 42 27 35 34 40 32 42 29 3816,7,8 19 22 - - - - - - - - - - 22 26A Bypass ALU(I = 2XX)25 30 - - - - - - - - - - - -Clock...f 31 40 30 39 30 38 27 34 28 37 27 34 27 355-1294040ns25 MHz25 ns15 ns40nsQoQ1530 40- -- -- -- -- -22 26- -20 23

~ CY7C9101~~~U~==================================================================Set-Up and Hold Times Relative to Clock (CP) Input[t]CP:Input Set-UpTime Hold Time Set-upTime Hold TimeBeforeH ~ L AfterH ~ L BeforeL ~ H AfterL ~ HCY7C9101- 30 40 30 40 30 40 30 40A, B Source Address 10 15 3[3] 3[3] 30[4] 40[4] 0 0B Destination Address 10 15 +- Do Not Change[2] ~ 0 0D - - - - 22 28 0 0C n - - - - 16 22 0 010,1,2 - - - - 26 35 0 013,4,5 - - - - 29 37 0 016,7,8 10 12 +- Do Not Change[2] ~ 0 0RAMo, RAM15, Qo, Q15 - - - - 11 14 0 0Output Enable/Disable TimesOutput disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage level.Device Input Output Enable DisableCY7C9101-30 OE Y 18 16CY7C9101-4O OE Y 22 19Notes:1. A dash indicates a propagation delay path or set-up time constraintdoes not exist.2. Certain signals must be stable during the entire clock LOW time toavoid erroneous operation. This is indicated by the phrase "do notchange".3. Source addresses must be stable prior to the clock H --+ L transitionto allow time to access the source data before the latches close. The Aaddress may then be changed. The B address could be changed if it isnot a destination; i.e. if data is not being written back into the RAM.Normally A and B are not changed during the clock LOW time.4. The set-up time prior to the clock L --+ H transition is to allow timefor data to be accessed, passed through the ALU, and returned to theRAM. It includes all the time from stable A and B addresses to theclock L --+ H transition, regardless of when the clock H --+ Ltransition occurs.5-130

~ CY7C9101~~~NDU~ ~~~~~~~~~~~~~===========================================CY7C9101·35 and CY7C9101·45 GuaranteedMilitary Range AC PerformanceCharacteristicsThe tables below specify the guaranteed AC performanceof these devices over the Military (-55°C to + 125°C) operatingtemperature range with V cc varying from 4.5V to5.5V. All times are in nanoseconds and are measured betweenthe 1.5V signal levels. The inputs switch between OVand 3V with signal transition rates of 1 V per nanosecond.All outputs have maximum DC current loads. See alsoloading circuit information.This data applies to parts with the following numbers:CY7C9101-35DMB CY7C9101-35LMB CY7C9101-35GMBCY7C9101-45DMB CY7C9101-45LMB CY7C9101-45GMBCombinational Propagation Delays CL = 50 pF[5]Cycle Time and Clock Characteristics [5]To Output y F15 Cn + 16

~ CY7C9101~~~~UcrOR==~~~~~~~~~~~~~~~~~~======~======~========~=======ApplicationsMinimum Cycle Time Calculations for 16-Bit SystemsSpeeds used in calculations for parts other than CY7C9101 and CY7C91O are representative for available MSI parts.CY7C9101F=OCn+ 164OVRF 15Pipelined System, Add without Simultaneous Shift0079-15CY7C245CY7C901RegisterData LoopClock to OutputA, Bto Y, Cn+16,OVRSetupControl Loop12 CY7C245 Clock to Output37 MUX Select to Output4 CY7C91O CC to Output53 ns CY7C245 Access TimeMinimum Clock Period = 66 ns1212222066 nsRAM 15F15~------~--------~CY7C9101 F=O ...... --..... +--------'OVRCY7C245CY7C9101XOR and MUXCY7C9101Pipelined System, Simultaneous Add and Shift Down (RIGHT)Data LoopClock to OutputA, B to Y, C n + 16, OVRProp. Delay, Selectto OutputRAMlsSetup123720CY7C245MUXCY7C91OCY7C2451180 nsMinimum Clock Period = 80 nsControl LoopClock to OutputSelect to OutputCCtoOutputAccess Time0079-131212222066 ns5-132

~RL5SCY7C9101'nEMICONDUcrOR ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;=;;;;;;;;;=======;;;;;;;;;=====;;;;;;;;;==;;;;;;;;;=====Typical DC and AC Characteristicsu.90Lo..IN:J...:~0::0z1.61.41.21.0NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGEV///0.8f= 10MHzTA =r5OC0.64.0 4.5 5.0 5.56.0~oLo..IN:J«~0::oZNORMALIZED SUPPLY CURRENT1.2 vs. AMBIENT TEMPERATURE1.11------+------11.0 I-----~~----___l0.9 t------t------"'...--t0.8 '------"------........-55 25 1250::or::zViI-::::>a...I- ::::>017515012510075OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE/50 /V- .// VVee= 5.0V/ TA = 25°C -25Vo o 1.0 2.0 3.0 4.0tzLo..I::::>oLo..I0::Lo..oLo..IN:J«~0::oZNORMALIZED FREQUENCYvs. AMBIENT TEMPERATURE1.6,....------,---------,1.41------+------11.2 I----"'~-+------I1.0 I------+-----='-tV ee =5.0V0.8 1------+------10.6 '------'---------'-55 25 125

~ CY7C9101~~~~ucr~================================================================Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type Range30 CY7C9101-30 PC P29 CommercialCY7C9101-30 LC L81CY7C9101-30 JC J81CY7C9101-30 DC D30CY7C9101-30 GC G6840 CY7C9101-4O PC P29CY7C9101-40 LC L81CY7C9101-40 JC J81CY7C9101-40 DC D30CY7C9101-40 GC G6835 CY7C9101-35 LMB L81 MilitaryCY7C9101-35 DMB D30CY7C9101-35 GMB G6845 CY7C9101-45 LMB L81CY7C9101-45 DMB D30CY7C9101-45 GMB G685-134

~ CY7C9101~~~~==================================================================MILITARY SPECIFICATIONSGroup A Subgroup TestingDC CharacteristicsParametersVOH 1,2,3VOL 1,2,3VIH 1,2,3VIL 1,2,3SubgroupsIIX 1,2,3loz 1,2,3Isc 1,2,3ICC (Ql) 1,2,3Icc (Q2) 1,2,3ICC (Max.) 1,2,3Combinational Propagation DelaysParametersSubgroupsFrom A, B Address to Y 7,8,9,10,11From A, B Address to F15 7,8,9,10,11From A, B Address to en + 16 7,8,9,10,11From A, B Address to G, P 7,8,9,10,11From A, B Address to F = 0 7,8,9,10,11From A, B Address to OVR 7,8,9,10,11From A, B Address to RAMo, 15 7,8,9,10,11FromDtoY 7,8,9,10,11FromDtoF15 7,8,9,10,11From D to C n + 16 7,8,9,10,11FromD toG, P 7,8,9,10,11FromDtoF = 0 7,8,9,10,11FromDtoOVR 7,8,9,10,11From D to RAMo, 15 7,8,9,10,11FromC n toY 7,8,9,10,11From C n to F15 7,8,9,10,11From Cn to en + 16 7,8,9,10,11Combinational Propagation Delays (Continued)ParametersSubgroupsFrom C n to F = 0 7,8,9,10,11From C n to OVR 7,8,9,10,11From C n to RAMo, 15 7,8,9,10,11From 1012 to Y 7,8,9,10,11From 1012 to F15 7,8,9,10,11From 1012 to C n + 16 7,8,9,10,11From 1012 to G, P 7,8,9,10,11From 1012 to F = 0 7,8,9,10,11From 1012 to OVR 7,8,9,10,11From 1012 to RAMo, 15 7,8,9,10,11From 1345 to Y 7,8,9,10,11From 1345 to F15 7,8,9,10,11From 1345 to Cn + 16 7,8,9,10,11From 1345 to G, P 7,8,9,10,11From 1345 to F = 0 7,8,9,10,11From 1345 to OVR 7,8,9,10,11From 1345 to RAMo, 15 7,8,9,10,11From 1678 to Y 7,8,9,10,11From 1678 to RAMO, 15 7,8,9,10,11From 1678 to Qo, 15 7,8,9,10,11From A Bypass ALU to Y 7,8,9,10,11(I = 2XX)From Clock ..f to Y 7,8,9,10,11From Clock..f to F15 7,8,9,10,11From Clock..f to C n + 16 7,8,9,10,11From Clock ..f to G, P 7,8,9,10,11From Clock ..f to F = 0 7,8,9,10,11From Clock ..f to OVR 7,8,9,10,11From Clock ..f to RAMo, 15 7,8,9,10,11From Clock..f to Qo, 15 7,8,9,10,115-135

~ CY7C9101~~~NDUcrOR =======================================================================Set-up and Hold Times Relative to Clock (CP) InputParameters Subgroups Parameters SubgroupsA, B Source Address 7,8,9,10,11 D Hold Time After L -+ H 7,8,9,10,11Set-up Time Before H -+ LC n Set-up Time Before L -+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11C n Hold Time After L -+ H 7,8,9,10,11Hold Time After H -+ L1012 Set-up Time Before L -+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11Set-up Time Before L -+ H 1012 Hold Time After L -+ H 7,8,9,10,11A, B Source Address 7,8,9,10,11 1345 Set-up Time Before L -+ H 7,8,9,10,11Hold Time After L -+ H 1345 Hold Time After L -+ H 7,8,9,10,11B Destination Address 7,8,9,10,11 1678 Set-up Time Before H -+ L 7,8,9,10,11Set-upTime Before H -+ L1678 Hold Time After H -+ L 7,8,9,10,11B Destination Address 7,8,9,10,11Hold Time After H -+ L1678 Set-up Time Before L -+ H 7,8,9,10,11B Destination Address 7,8,9,10,111678 Hold Time After L -+ H 7,8,9,10,11Set-upTime Before L -+ H RAMo, RAM 15, Qo, Q15 7,8,9,10,11B Destination Address 7,8,9,10,11Set-up Time Before L -+ HHold Time After L -+ H RAMo, RAM15, Qo, Q15 7,8,9,10,11D Set-up Time Before L -+ H 7,8,9,10,11Hold Time After L -+ H,Document #: 38-00017-B5-136

PRELIMINARYCY7C9116CY7C9117Features• Fast- 45 ns worst case propagationdelay, I to Y• Low power CMOS- Icc (max. at 10 MHz)150 mA (commercial)- ICC (max. static) = 30 mA• CY7C9117 separate I/O- One and two operandarithmetic and logicaloperations- Bit manipulation, fieldinsertion/extractioninstructions(commercial) - Eleven types of instructions• VCC margin• Immediate instruction capability- 5V ±10%• 16-bit barrel shifter capability- All parameters guaranteed• 32-word x 16-bit register fileover commercial and militaryoperating temperature range• Instruction set and architectureoptimized for high speedcontroller applications• 8-bit status register- Four ALU status bits- Link bit and three userdefinable status bitsCMOS 16-BitMicroprogrammed ALU• ESD protection- Capable of withstandinggreater than 200lV staticdischarge voltage• Pin compatible and functionallyequivalent to 29116, 29116A,29C116, 29117, 29117A, 29C117Functional DescriptionThe CY7C9116 and CY7C9117 arehigh speed 16-bit microprogrammedArithmetic and Logic Units, (ALU).The architecture and instruction set ofthe devices are optimized for peripheralcontroller applications such as diskcontrollers, graphics controllers, communicationscontrollers, and modems ..---------

WAPRELIMINARYCY7C9116CY7C9117~~UaoR==================================================================Functional Description (Continued)When used with the CY7C517 multiplier, the CY7C9116and CY7C9117 also support microprogrammed processorapplications.The CY7C9116 and CY7C9117 are shown in the blockdiagram, consists ofa 32-word by 16-bit single-port RAMregister file, a 16-bit arithmetic unit and logic unit, an instructionlatch and decoder, a data latch, an accumulatorregister, a 16-bit barrel shifter, a priority encoder, a statusregister, a condition code generator and multiplexer, andthree-state output buffers.The instruction set of the CY7C9116 and CY7C9117 canbe divided into eleven instruction types: single-operand,two-operand, single-bit shifts, rotate and merge, rotate andPin Configurations CY7C9116Top Viewcompare, rotate by n-bits, bit oriented instructions, prioritize,Cyclic Redundancy Check (CRC), status, and NO­OP. Instruction execution occurs in a single clock cycleexcept for Immediate Instructions, which require two clockcycles to execute.The CY7C9116 and CY7C9117 are pin compatible, functionalequivalent of the industry standard 29116, 29116A,29C116, 29117, 29117 A, 29C117 with improved performance.Fabricated in an advanced 1.2 micron, two-level metalCMOS process, the CY7C9116 and CY7C9117 eliminateslatchup, has ESD protection greater than 2001V, andachieves superior performance with low power dissipation.Top View114 1 151 13 Yo~>-t')>-N.,:-~:P~ J!~ ::lJP_f1l ~~~~~~~~~~~~~~~:~9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 611121111Y 2Y sY 61 10 Y 3 GND19 Y 40EyY18 Y 75 Vee17 Y 6 Vee16 GND Y aYgIS OE y Y 10GND Y 7 !l..EVeeVeeGNDY 1114 Vee13 Y 812 Yg11 Y 1010 OLECPGNDiEN Y 11SRE Y 12CT Y 13OE r Y 14T4 Y 15T3Ne}GND NC RESERVEDT2Tl.J;;~.;F!i.!i..=-~g,!'~!fbLCCPLCC1716IsGIl)Vee1413121110CPiENSRf0085-3Y 3 10 60 190 7 11Y 4 12Ys 13Y& 14GND 15OE y 1&Y 7 17Vee 18Vee 19Ya 20Y 9 21Y l0 22OLE 23GND 24Y ll 25STANDARDY 12 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41PLCC59 la58 1757 1656 1555 GND54 Vee53 1452 1351 1250 1149 1048 CP47 iEN46 SRE45 CT42 43 44 CE T0085-22DIP0085-25-138

(;jiPRELIMINARYCY7C9116CY7C9117~~~UcrOR =======================================================================Pin Configurations CY7 C91179Y3 100 7 11Y 4 12Y 5 13Y 6 14GNO 15OC y 16Y7 17Vee 18Vee 19Y8 20Y 9 21Y l0 22OLE 23GNO 24Y ll 25Top ViewN_OU ~'i)""'pt)N_CDUl..".tt')N-O~ ~ ~ z c c c c c c c ::: - - -8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 6160 1959 1858 1757 1656 1555 GNO54 Vee53 1452 1351 1250 1149 1048 CP47 iEN46 SRE45 CTY 12 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 CE TLCC/PLCCNC = No ConnectTop View0085-6Ge8eeG8e851 ~ ~ • « G ~ ~ §(9

(;j]PRELIMINARYCY7C9116CY7C9117~~NDUcrOR =====================================================================Description of ArchitectureThe CY7C9116 and CY7C9117 are 16-bit microprogrammedarithmetic and logic units comprised of the followingsections (see block diagram):• 32 Word x 16-Bit Register File• Data Latch• Instruction Latch and Decoder• Accumulator• Logic Unit with a 16-bit Barrel Shift Capability• Arithmetic Unit• Priority Encoder• Condition Code Generator and Multiplexer• Status Register• Output Buffers32-Word x 16-Bit Register FileThe 32-word x 16-bit register file is a single port RAMwith a 16-bit latch at the output. The latch is transparentwhile CP is HIGH and latched when CP is LOW. IfIEN isLOW and the current instruction specifies the RAM at itsdestination, data is written into the RAM while CP isLOW. Word instructions write into all 16-bits of the RAMword addressed; byte instructions write into only the lowereight bits.Use of an external multiplexer on five of the instructioninputs makes it possible to select separate read and writeaddresses for the same NON-IMMEDIATE instruction.Immediate Instructions do not allow this two-address operationfor the 7C9116. The 7C9117 does support two-addressImmediate Instructions.Data LatchThe data latch holds the 16-bit input to the CY7C9116 andCY7C9117 from the Y (bidirectional) bus for the 7C9116and the data bus for the 7C9117. When DLE is HIGH, thelatch is transparent, it is latched when DLE is LOW.Instruction Latch and DecoderThe 16-bit instruction latch is always transparent, exceptwhen Immediate Instructions are executed. The InstructionDecoder decodes the instruction inputs into the internalsignals which control the CY7C9116 and CY7C9117.All instructions other than Immediate Instructions executein a single clock cycle.Execution of Immediate Instructions takes two clock cycles.During the first clock cycle, the Instruction Decoderidentifies the instruction as an Immediate Instruction andthe Instruction Latch captures the instruction at the instructioninputs. For Immediate Instructions, the data atthe instruction inputs during the second clock cycle is usedas one of the operands for the Immediate Instruction specifiedduring the first clock cycle. Upon completion of theImmediate Instruction (the end of the second clock cycle),the Instruction Latch again becomes transparent.AccumulatorThe accumulator is a 16-bit edge triggered register. If thelEN is LOW and the current instruction specifies the accumulatoras its destination, the accumulator accepts Y input5-140data at the clock LOW to HIGH transition. Word instructionswrite into all 16 bits of the accumulator, byte instructionswrite into the lower eight bits.16-Bit Barrel ShifterThe barrel shifter can rotate data input to it from either theregister file, the accumulator, or the data latch from 0 to 15bit positions. In word mode, the barrel shifter rotates a16-bit word; in byte mode, it only affects the lower eightbits. The barrel shifter is used as one of the ALU inputs.Arithmetic and Logic UnitThe CY7C9116 and the CY7C9117 have an arithmetic unitand a logic unit. The arithmetic unit is capable of operatingon one or two operands while the logic unit is capable ofoperating on one, two or three operands. The two units inparallel are able to execute the one and two operand instructionssuch as pass, complement, two's complement,add, subtract, AND, OR, EXOR, NAND, NOR, and EX­NOR. Three operand instructions include rotate/mergeand rotate/masked compare. There are three data typessupported by the CY7C9116 and CY7C9117; bit, byte, and16-bit word.All arithmetic and logic unit operations can be performedin either word or byte mode, with byte instructions performedonly on the lower eight bits.Three status output are generated by the arithmetic unit:carry (C), negative (N), and overflow (OVR). A zero flag(Z) detects a zero condition, though this flag is not generatedby the arithmetic unit or the logic unit. These flags aregenerated in either word or byte mode, as appropriate.The arithmetic unit uses full carry look-ahead across all 16bits during arithmetic operations. The carry input to thearithmetic unit comes from the carry multiplexer, whichcan select either zero, one, or a stored carry bit (QC) fromthe status register. Multiprecision arithmetic uses QC asthe carry input.Priority EncoderThe priority encoder generates a binary-weighted codebased on the location of the highest order ONE in its inputword or byte. The operand to be prioritized may beAND-ed with a mask to eliminate certain bits from thepriority encoding. This masking is performed by the logicunit.In word mode, the output is a binary one if bit 15 is thefirst (unmasked) HIGH encountered, a binary two if bit 14is the first HIGH and so on. If bit 0 is the only HIGH, theoutput of the priority encoder is binary 16. If no bits areHIGH, a binary zero is output.In byte mode, only bits 7 through 0 are examined. Bit 7HIGH produces a binary one, bit 6 a binary two, and soon. If bit 0 is the only HIGH, a binary eight is output; if nobits are HIGH, a binary zero is output.Condition Code Generator and MultiplexerThe twelve condition code test signals are generated in thissection. The multiplexer selects one of these twelve andplaces it at the CT output. The multiplexer is addressed byeither using the Test Instruction or by using the bidirec-

CY7C9116PRELIMINARY CY7C9117~~~ ~===================================================================Description of Architecture (Continued)Pin Definitionstional T bus as an input. The test instruction specifies thetest condition to be placed at the CT output, but it does notallow an ALU operation at the same time. Using the T busas input, the CY7C9116 and CY7C9117 may simultaneouslytest and execute an instruction. The test instructionlines (14-0) take precedence over T 4-1 for testingstatus.Status RegisterThe 8-bit status word is held by the status register. Thestatus register is updated at the end of all instructions exceptNO-OP, Save Status, and Test Status, provided thestatus register enable (SRE) and instruction enable (lEN)are both LOW. The status register is inhibited from changingif either SRE or lEN are HIGH.The lower four status bits are the ALU status: OVR (overflow),N (negative), C (carry), and Z (zero). The upper fourbits are a link bit and three user-defined status bits (Flagl,Flag2, Flag3).As stated above, when lEN and SRE are LOW, the statusregister is updated at the end of all instructions other thanNO-OP, Save Status, and Test Status. The lower fourstatus bits are updated under the above conditions, withthe additional exception of when lEN and SRE are LOWand the Status Set/Reset instruction is performed on theupper four bits. When lEN and SRE are LOW, the upperfour status bits are only changed during their correspondingStatus Set/Reset instructions and during Status Loadinstructions in word mode. The Link-Status bit is also updatedafter every shift instruction.The status register can be loaded via the internal Y bus; itcan also be selected as a source for the internal Y bus.Loading the status register in word mode updates all eightbits of the status register. In byte mode, only the lower fourbits are updated.Using the status register as a source in the word modeloads all eight bits into the lower byte of the destination;the upper byte is zero-filled. In byte mode, the status registerloads the lower byte of the destination; however theupper byte is unchanged. Interrupt and subroutine processingis facilitated by this store/load combination, which allowssaving and restoring the status register. The lowerfour bits of the status register can be read directly by outputtingthem to the T 4-1 outputs. These outputs are enabledwhen OET is HIGH.Output BuffersTwo sets of bidirectional buses exist on the CY7C9116.The bidirectional Y bus (16 bits) is controlled by OEy. Thethree state outputs are enabled when OEy is LOW, theyare at high impedance when OEy is HIGH. This will allowdata to be input to the data latch from the external world.The second bidirectional bus is the four-bit T bus. Thesethree state buffers are enabled by a HIGH on OET, whichwill output the internal ALU status bits (OVR, N, C, Z). IfOET is LOW, the T outputs are at high impedance, and atest condition can be input on the T bus to determine theCToutput.The 7C9117 has separate Y bus output and Data Inputbuses. All other pins are functionally equivalent to the7C9116.5-141Signal I/ONameDescriptionYlS-O I/O Data Input/Output. These bidirectional lines areused to directly load the 16-bit data latch whenOEy is HIGH. When OEy is LOW, the arithmeticunit or the logic unit output data is output onYlS-O·IlS-O Instruction Word. This 16-bit word selects thefunctions performed by the 7C9116. These linesare also used to input data when executing ImmediateInstructions.T4-1 I/O Status Input/Output. These bidirectional pins areused to output the lower four status bits (OVR,N, C, and Z) when OET is HIGH. When OET isLOW, these lines are used as inputs to generatethe conditional test (CT) output.CT a Conditional Test. One of twelve condition codesignals is selected by the condition code multiplexerto be placed on the CT output.CT = HIGH for a pass condition; CT = LOWfor a fail condition.DLE Data Latch Enable. The 16-bit data latch is transparentwhen DLE is HIGH and latched whenDLEisLOW.lEN Instruction Enable. The following occurs withlEN LOW: Data may be written into the RAMwhen the clock is LOW, the Accumulator canaccept data during the clock LOW to HIGHtransition, and the Status Register can be updatedwhen SRE is LOW. If lEN is HIGH, CT is disabledas a function of the instruction inputs. lENshould be LOW during the first half of the firstcycle of Immediate Instructions.SRE Status Register Enable. The Status Register isupdated at the end of all instructions except NO-OP, Save Status, and Test Status when SRE andlEN are both LOW. The Status Register is inhibitedfrom changing when either SRE or lEN areHIGH.OEy Y Output Enable. This controls the 16-bit Y lS-OI/O port. When OEy is LOW, the Y -outputs areenabled, when OEy is HIGH, the Y outputs aredisabled (high impedance).OET T Output Enable. The four bit T outputs are enabledwhen OET is HIGH: they are disabled(high impedance) when OET is LOW.CP Clock Pulse. The RAM output latch is transparentwhen CP is HIGH; the RAM output islatched when CP goes LOW. If lEN is LOW andthe current instruction specifies the RAM as thedestination, then data is written into the RAMwhile CP is LOW. If lEN is LOW, the Accumulatorand Status Register will accept data at theclock LOW to HIGH transition. The instructionlatch becomes transparent upon exiting an ImmediateInstruction during a LOW to HIGH clocktransition.DlS-O These input lines are used to directly load thedata latch.YlS-O I/O These output lines are used to present the arithmeticunit or the logic unit output when OEy isLOW. (CY7C9117 YlS-O and output only)B

(;APRELIMINARYCY7C9116CY7C9117~~NDUCTOR ==========================================================================Instruction SetThe instruction set of the CY7C9116 and CY7C9117 isoptimized for peripheral controller applications. It features:Bit Set, Bit Reset, Bit Test, Rotate and Merge, Rotateand Compare, and Cyclic-Redundancy-Check (CRC)generation, in addition to standard Single- or Two-Operandlogical and arithmetic instructions. A single clock cyclewill execute all but the Immediate Instructions whichtake 2 clock cycles.The CY7C9116 and CY7C9117 can operate in three differentdata modes: bit, byte and word (16 bits). The LSB ofSingle Bit ShiftRotate and Mergethe word is used for Byte Mode. Also in Byte Mode whenBit-Orientedthe status register is specified as the destination, only theRotate by n BitsLSH (OVR, N, C, Z) of the register is updated. Save StatusTable 1. Operand Source-Destination CombinationsInstruction Type Operand Combinations (Note 1)Source (R/S) DestinationSingle Operand RAM (Note 2) RAMSOR ACC ACCSONR D YBusD(OE)StatusD(SE)ACCandIStatus0Source (R) I Source (S) DestinationTwo Operand RAM ACC RAMTORI RAM I ACCTOR2 D RAM YBusTONR D ACC StatusACC I ACCandD I StatusSource (U)DestinationSingle Bit Shift RAM RAMSHFTR ACC ACCSHFTNR ACC YBusDRAMDACCDYBusSource (U)DestinationRotate n Bits RAM RAMROTRI ACC ACCROTR2 D YBusROTNRSource (R/S) DestinationBit Oriented RAM RAMBORI ACC ACCBOR2 D YBusBONRNon-RotatedRotated I Mask(S) Source/Source (U)Destination (R)Rotate and Merge D I ACCROTM D RAM ACCROTC D I RAMD ACC RAMACC I RAMRAM I ACCNotes:1. If there is no division between the R/S operand or SOURCE andDESTINATION, the two are a given pair. If a division exists, anycombination is possible.2. RAM cannot be used as source when both ACC and STATUS aredesignated as a DESTINATION.3. OPERAND and MASK must be different sources.5-142and Test Status instructions do not change the status register.During Test Status instructions the V-bus (or D-busfor the CY7C9117) is undefined; the result is in the CToutput.The eleven instruction types outlined below are describedin detail on the following pages.Single-OperandTwo-OperandRotate and ComparePrioritizeCRCStatusNo-OpInstruction Type Operand Combinations (Note 1)RotatedSource (U)Mask(S)Non-RotatedSource/Destination (R)Rotate and CompareCDAI D ICDRI D I RAMCDRA D ACC RAMCRAI RAM I ACCSource(R) Mask(S) DestinationPrioritize (Note 3) RAM RAM RAMPRTl ACC ACC ACCPRT2 D I YBusPRTNR 0Data In Destination PolynominalCyclic Redun- QLINK RAM ACCdancy CheckCRCFCRCRNo OperationNOOPSet Reset StatusSETSTRSTSTSVSTRSVSTNRTESTSource-Bits AffectedOVR,N,C,ZLINKFlag IFlag2Flag3DestinationStore Status Status RAMACCYBusSource(R) Source (S) DestinationStatus Load D ACC StatusACC I Status andACCDITest Condition (CT)Test Status (NEBOVR) + Z Z+CNEBOVRNZLINKOVRFlag ILowFlag2CFlag3

finCY7C9116.' PRELIMINARY CY7C9117. ~IfmNDUcrOR =======================================================================Instruction Set (Continued)OEy is assumed LOW for all cases, allowing ALU outputson the Y - or D-bus.Instructions are individually distinguished by usingOP-CODES and 2 assigned quadrant bits. Four quadrants,o to 3, have been assigned to each instruction type in orderto ease groupings of instructions and addressing modes.Single Operand InstructionsEach Single Operand Instruction contains four designators:1. Mode (Byte or Word)2.Opcode3. Source4. Address or DestinationThese designators are divided into two basic categories,those which use RAM addresses and those that do not.The instruction formats shown below are unique for eachcategory. In both cases the desired operation, controlled bythe instruction inputs, is performed on the source with theresult either placed on the V-bus or stored in the destinationor both. The functions of Extending Sign Bit (D(SE»and Binary Zero (D(OE» over 16 bits in the Word Modeare available for cases where 8-bit to 16-bit conversion isnecessary. The functions performed using Single Operandinstructions update the LSB of the Status Register (OVR,N, C, Z) but do not effect the MSB (FLAG 1, FLAG2,FLAG3, LINK). Single Operation instructions are limitedwhen both the ACC and Status Register are the destination,the source cannot be RAM.Single Operand Field Definitions15 14 13 12 9 8 5 4 0SOR B/W Quadrant Opcode SRC-Dest RAM Address15 14 13 12 9 8 5 4 0SONR B/W Quadrant Opcode SRC DestinationSingle Operand Instruction Set15 14 13 12 9 8 5 4 0Instruction [1] B/W[2] Quad [3] Opcode R/S[4] Dest[4] RAM Address/Destination1100 MOVE SRC ~ Dest 0000 SORA RAM RAM 00000 ROO RAM Reg 001101 COMP SRC~ Dest 0010 SORY RAM YBus . . . . ....1110 INC SRC + 1 ~ Dest 0011 SORS RAM Status 11111 R31 RAM Reg 311111 NEG SRC + 1 ~ Dest 0100 SOAR ACC RAMSOR O=B 10 0110 SODR D RAM1 = W 0111 SOIR I RAM1000 SOZR 0 RAM1001 SOZER D(OE) RAM1010 SOSER D(SE) RAM1011 SORR RAM RAMInstruction B/W Quad Opcode R/S[4] Destination1100 MOVE SRC ~ Dest 0100 SOA ACC 00000 NRY YBus1101 COMP SRC~ Dest 0110 SOD D 00001 NRA ACCSONR O=B 1110 INC SRC + 1 ~ Dest 0111 SOl I 00100 NRS Status[S]1 = W 11 1111 NEG SRC + 1 ~ Dest 1000 SOZ 0 00101 NRAS ACC, Status[s]1001 SOZE D(OE)1010 SOSE D(SE)Notes:1. Instruction mnemonic. 4. R = Source; S = Source; Dest = Destination.2. B = Byte Mode, W = Word Mode. S. Status is destination,3. Quadrant subdivides instuctions into categories.Status i ~ Yi i = 0 to 3 (byte mode)i = 0 to 7 (word mode)Y Bus and StatusInstruction Opcode Description B/W V-Bus Flag3 Flag2 Flag1 LINK OVR N C ZSORSONRSRC = SourceU = UpdateCOMPINCMOVENEGSCR~ DestSCR + 1 ~ DestSCR~ DestSCR + 1 ~ DestNC = No Change0= Reset1 = WO=BY~SRC NC NC NC NCY~SRC +1 NC NC NC NCY~SRC NC NC NC NCY~SRC +1 NC NC NC NC1 = Seti = 0 to IS when not specified0 U 0 UU U U U0 U 0 UU U U U5-143

5ACY7C9116PRELIMINARY CY7C9117~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=Instruction Set (Continued)Each Two Operand Instruction is constructed of 5 fields:1. Mode (Byte or Word)2.0pcode3. R Source4. S Source5. Address or DestinationThese instructions are further divided into those usingRAM addresses and those that do not. The first type usestwo formats which differ only by quadrant designator.InstructionTORIInstructionTOR2B/WNotes:1. R = SourceS = SourceDest = DestinationTORITOR2TONRQuadO=B 001 =WB/WQuadO=B 101 =WTwo Operand Field Definitions15 14 13 12 9 8B/W Quadrant Opcode SRC-SRC, Dest15 14 13 12 9 8B/W Quadrant Opcode SRC-SRC, Dest15 14 13 12 9 8B/W Quadrant Opcode SRC-SRC, DestTwo Operand Instruction SetFunctions are performed on the specified Rand S sourcesand results are stored in the specified destination and/orplaced on the Y -bus. Arithmetic functions update the leastsignificant nibble of the Status Register (OVR, N, C, Z)while logical functions affect only the Nand Z bits. Executionof logical functions clear the OVR and C bits of theStatus Register.R[l] S[l] Dest!l] Opcode0000 TORAA RAM ACC ACC 0000 SUBR0010 TORIA RAM I ACC 0001 SUBRc!2]0011 TODRA D RAM ACC1000 TORAY RAM ACC YBus 0010 SUBS1010 TORIY RAM I YBus 0011 SUBSC[2]1011 TODRY D RAM YBus1100 TORAR RAM ACC RAM 0100 ADD1110 TORIR RAM I RAM 0101 AD DC1111 TODRR D RAM RAM0110 AND0111 NAND1000 EXOR1001 NOR1010 OR1011 EXNORR[l] S[l] Dest[l] Opcode0001 TODAR D ACC RAM 0000 SUBR0010 TOAIR ACC I RAM 0001 SUBRC[2]0101 TODIR D I RAM0010 SUBS0011 SUBSC[2]2. For subtraction the carry is interpreted as borrow.5-1440100 ADD0101 ADDC0110 AND0111 NAND1000 EXOR1001 NOR1010 OR1011 EXNOR4 aRAM Address5 4 aRAM Address5 4 aDestinationRAM AddressS minusR 00000 ROO RAM Reg 00SminusR . . . . ....with carry 11111 R31 RAM Reg 31Rminus SRminus Swith carryRplus SRplus Swith carryReSReSResR+SR+SResRAM AddressSminus R 00000 ROO RAM Reg 00Sminus R .. . . . ...with carry 11111 R31 RAM Reg 31Rminus SRminus Swith carryRp1us SRplus Swith carryReSReSResR+SR+SRes

5JlCY7C9116; PRELIMINARY CY7C9117. ~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=Instruction Set (Continued)InstructionTONRB/WO=B1 = WQuad11 000100100101Notes:1. R = SourceS = Source2. Status is destination,Status i +- Yi, i = 0 to 3 (byte mode)i = 0 to 7 (word mode)3. For subtraction the carry is inverted.TODATOAITODIInstruction Opcode DescriptionADDADDCANDEXORRplus SR plus S with carryReSREElSTORIEXNOR REElSTOR2 NAND ReSTONR NORORSUBRSUBRCSUBSSUBSCR+SR+SSminus RS minus R with carryRminusSR minus S with carryU = UpdateNC = No Change0= Reset1 = Seti = 0 to 15 when not specifiedSingle Bit Shift Instructions are constructed of four fields:1. Mode (Byte or Word)2. Direction (up or down) and shift linkage3. Source4. DestinationThese instructions are further divided into those usingRAM addresses and those that do not. The shift linkageindicator indicates what is to be loaded into the vacant bit.During a shift up the LSB may be loaded with a zero, oneTwo Operand Instruction SetR[1) S[1) Opcode DestinationD ACC 0000 SUBR Sminus R 00000 NRY YBusACC I 0001 SUBRC S minus R with 00001 NRA ACCD I carry 00100 NRS Status [2)0010 SUBS RminusS 00101 NRAS ACC, Status[2)0011 SUBSC R minus S withcarry0100 ADD R plus S0101 ADDC R plus Swithcarry0110 AND ReS0111 NAND ReS1000 EXOR REElS1001 NOR R+S1010 OR R+S1011 EXNOR REElSY Bus and Status ContentsB/W V-Bus Flag3 Flag2 Flagl LINK OVR N C ZO=B Y+-R+S NC NC NC NC U U U U1 = W Y+-R+S+QC NC NC NC NC U U U UY+-RiANDSi NC NC NC NC 0 U 0 UYi +- Ri EXOR Si NC NC NC NC 0 U 0 UYi +- Ri EXNOR Si NC NC NC NC 0 0 0 UYi +- Ri NAND Si NC NC NC NC 0 U 0 UYi +- Ri NOR Si NC NC NC NC 0 U 0 UYi +-RiORSi NC NC NC NC 0 U 0 UY+-S+R:+1 NC NC NC NC U U U UY+-S+R:+QC NC NC NC NC U U U UY+-R+S+1 NC NC NC NC U U U UY+-R+S+QC NC NC NC NC U U U Uor with the link status bit (QLINK), while the MSB isshifted into the QLINK bit. During a shift down, the MSBis loaded with a zero, one, the Status Carry bit (QC), theExclusive-Or of the Negative-Status bit and the Overflow­Status bit (QN EEl QOVR), or the Link-Status bit. TheStatus Register's Nand Z bits are updated, while the OVRand C bits are reset. Shift down with QN EEl QOVR can beused in Two's Complement Multiplication.5-145

finCY7C9116PRELIMINARY CY7C9117~~DuaoR ================================~========~~~~~~~==~~~~===Instruction Set (Continued)Single Bit Shift Field Definitions15 14 13 12 9 8 5 4 0SHFTR I B/W I Quadrant I SRC-Dest I Opcode I RAM Address I~~====~====~====~====~SHFTNR IL.._B_/W_.L..I ---.::Q'-u_ad_r_an_t---'L....-_S_ou_r_ce_...l-_O~p_c_od_e_-II__D_e_st_in_a_ti_on-----llShift Up FunctionSOURCEMUXoQLlNKo1QCQNeQOVRQLlNKMUXShift Down FunctionDESTINATION0085-8DESTINATION0085-9Single Bit Shift Instruction SetInstruction B/W Quad U[l) Dest[l) Opcode RAM Address/DestinationSHFTR O=B 0110 SHRR RAM RAM 0000 SHUPZ Up 0 00000 ROO RAM Reg 00101 =W 0111 SHDR D RAM 0001 SHUP1 Up 1 . . . . ....0010 SHUPL Up QLINK 11111 R31 RAM Reg 310100 SHDNZ Down 00101 SHDN1 Down 10110 SHDNL Down QLINK0111 SHDNC Down QC1000 SHDNOV Down QNEB QOVRInstruction B/W Quad U[l) Opcode DestinationSHFTNR O=B 0110 SHA ACC 0000 SHUPZ Up 0 00000 NRY V-Bus111 = W 0111 SHD D 0001 SHUP1 Up 1 00001 NRA ACC0010 SHUPL Up QLINK0100 SHDNZ Down 00101 SHDN1 Down 10110 SHDNL Down QLINK0111 SHDNC Down QC1000 SHDNOV Down QNEB QOVRNote:1. U = SourceDest = DestinationY Bus and StatusInstruction Opcode Description B/W V-Bus Flag3 Flag2 Flag1 LINK OVR N CZSHR SHUPZ UpO l=W Yi ~ SRq-l, i = 1 to 15;NC NC NC SRCI5* 0 SRC14 OUSHNR SHUP1 Up 1 Y 0 ~ Shift InputSHUPL UpQLINK Yi ~ SRq -1. i = 1 to 7;O=B Y 0 ~ Shift Input; NCYg ~ SRC7, Yi ~ SRq-9NC NC SRC7* 0 SRC6 OUfori = 9 to 15SHDNZ Down 01 = W Yi ~ SRCi + 1. i = Oto14; ShiftNC NC NC SRCo· 0 OUSHDN1 Down 1 Y15 ~ Shift Input InputSHDNL DownQLINK Yi ~ SRCi+l,i = Ot06;SHDNC ShiftDownQC O=B Yi ~ SRq-7, i = 8 to 14; NC NC NC SRCo· 0 OUSHCNOV InputDown QNEBQOVR Y 7 15 ~ Shift Input'Shifted output is loaded into the QLINK.SRC = Source0 = ResetU = Update1 = SetNC = No Changei = 0 to 15 when not specified5-146

5nPRELIMINARYCY7C9116CY7C9117~~UcrOR =======================================================================Instruction Set (Continued)Bit-Oriented InstructionsBit-Oriented Instructions are constructed from four fields:1. Mode (Byte or Word)2. Operation3. Source or Destination4. Bit position operated on (0 = LSB)These instructions are further divided into those usingRAM addresses and those that do not. The specified functionoperates on the given source and the result is stored inthe specified destination and/or on the Y -bus.Set Bit n: Forces the nth bit to ONE without affectingother bit positions.Reset Bit n: Forces the nth bit to ZERO without affectingother bit positions.Test Bit n: Sets the Z status bit to the state of bit n.Load 2n: Loads ZERO in bit position n and sets all otherbits.Load 2n: Loads ONE in bit position n and clears all otherbits.Increment 2 0 : Adds 2 n to the operand.Decrement 2n: Subtracts 2n from the operand.Load, Set, Reset and Test instructions update Nand Zstatus bits while forcing OVR and C bits to ZERO. Arithmeticoperations affect the entire lower nibble of the StatusRegister (OVR, C, N, and Z).Bit Oriented Field Definitions15 14 13 12 98 54 0BOR1 I B/W I QuadrantINI Opcode RAM Address I15 14 1312 98 54 0BOR21 B/W I QuadrantIN Opcode RAM Address15 14 13 12 98 54 0BONR I B/W I QuadrantIN 1100 OpcodeIBit Oriented Instruction SetInstruction B/W Quadrant n Opcode RAM AddressBORIO=B1 = W1101 SETNR Set RAM, bit n 00000 ROO RAM Reg 0011 o to 15 1110 RSTNR Reset RAM, bit n . . ...1111 TSTNR Test RAM, bit n 11111 R31 RAM Reg 31Instruction B/W Quadrant n Opcode RAM Address1100 LD2NR 2 n ~ RAM00000 ROO RAM Reg 00BOR2 O=B 1101 LDC2NR 2n ~ RAM10 o to 151 =W1110 A2NR RAM plus 2 0 ~ RAM1111 S2NR RAM minus 2 n 11111 R31 RAM Reg 31~ RAM. . ...Instruction B/W Quadrant n Opcode OpcodeBONR00000 TSTNA Test ACC, bit n00001 RSTNA Reset ACC, bit n00010 SSTNA Set ACC, bit n00100 A2NA ACC plus 2n ~ ACC00101 S2NA ACC minus 2 n ~ ACC00110 LD2NA 2 n ~ ACCO=B00111 LDC2NA 2n ~ ACC11 o to 15 11001 = W 10000 TSTND Test D, bit n10001 RSTND Reset D, bit n10010 SETND Set D, bit n10100 A2NDY Dplus2 n ~ YBus10101 S2NDY D minus 2 n ~ Y Bus10110 LS2NY 2 n ~ YBus10111 LDC2NY 2n ~ YBus5-147

CY7C9116~ PRELIMINARY CY7C9117~~~~crOR==================================================================Instruction Set (Continued)Rotate By n Bits InstructionsThe Rotate by n Bits Instructions contain four indicators:byte or word mode, source, destination and the number.ofplaces the source is to be rotated. They are further subdIvidedinto two types. The first type uses RAM as a sourceand! or a destination and the second type does not useRAM as a source or destination. The first type has twodifferent formats and the only difference is in the quadrant.The second type has only one format as shown in the table.Under the control of instruction inputs, the n indicatorRotate By n Bits Field Definitions15 14 13 12 9 8ROTR1 B/WIQuadrant nISRC-DestROTR2 B/WIQuadrant nISRC-DestROTNRI B/WIQuadrant nI1100Rotate by n ExampleEXAMPLE: n = 4, Word ModeSource 0001 0011 0111Destination 0011 0111 1111EXAMPLE: n = 4, Byte ModeSource 0001 0011 0111Destination 0001 0011 1111Rotate By n Bits Instruction SetInstruction B/W Quadrant n U[l] Dest[l]ROTR1O=B1 = W1100 RTRA RAM ACC00 o to 15 1110 RTRY RAM YBus1111 RTRR RAM RAMInstruction B/W Quadrant n U[l] Dest[l]O=B 0000 RTAR ACC RAMROTR2 01 o to 151 = W0001 RTDR D RAMInstruction B/W Quadrant nO=BROTNR 11 o to 15 11001 = WNote:1. U = SourceDest = DestinationInstructionROTR1ROTR2ROTNROpcodeSRC = SourceU = No Change0= Reset1 = Seti = 0 to 15 when not specifiedB/W1- WO=BY Bus and StatusV-Bus Flag3 Flag2Yi +- SRC(i n)mod16 NC NCYi +- SRCi + 8 = SRC(i-n)mod8fori - Oto 7NC NCspecifies the number of bit positions the source is to berotated up (0 to 15), and the result is either stored in thespecified destination or placed on the Y bus or both. Anexample of this instruction is given in Figure 5. In theWord mode, all 16-bits are rotated up; while in the Bytemode, only the lower 8-bits (0-7) are rotated up. In theWord Mode, a rotate up by n bits is equivalent to a rotatedown by (16-n) bits. Similarly, in the Byte mode a r~tateup by n bits is equivalent to a rotate down by (8-n) bits.The Nand Z bits of the Status Register are affected andOVR and C bits are forced to ZERO.5 4 0RAM AddressII1111000111110111RAM AddressISRC-DestRAM Address00000 ROO RAM Reg 00. . . . ....11111 R31 RAM Reg 31RAM Address00000 ROO RAM Reg 00. . . . . . ....11111 R31 RAM Reg 31U[l] Dest[l]11000 RTDY D YBus11001 RTDA D ACC11100 RTAY ACC YBus11101 RTAA ACC ACCFlag! LINK OVR N C ZNC NC 0 SRC15-n 0 UNC NC 0 SRC6-n 0 U5-148

CY7C9116~P£§PRELIMINARY CY7C9117_~ICONDUcrOR ===================================;;;;;Instruction Set (Continued)Rotate and Merge InstructionsThe shift register rotates source U up n places. ANDingwith the mask causes any bit i to be passed from theEach Rotate and Merge instruction consists of five fields:rotated source that corresponds to a set bit in mask positioni. The R input is not shifted, but is masked by the1. Mode (Byte or Word)2. Rotated Source (U)compliment of mask S, so that a ZERO in mask bit i willpass bit i of R. The ORed result is stored in register R.3. Non-Rotated Source (R)Rotate and Merge operations update the Nand Z status4. Mask Location (S)bits, while clearing the OVR and C bits.5. Number of bits Rotated (n)Rotate and Merge FunctionuROR0085-10Rotate and Merge Field Definitions1514 1312 98 54ROTM I B/W I Quadrant I n I V,R,S IRAM AddressaIEXAMPLE: N = 4, Word ModeV 0011 0001 0101Rotated V 0001 0101 0110R 1010 1010 1010Mask (S) 0000 1111 0000Destination 1010 0101 1010Rotate and Merge Instruction SetInstruction B/W Quadrant n V[I) R/Dest[I)0111 MDAI D ACC1000 MDAR D ACCROTMO=B1001 MDRI D RAM01 a to 151 = W 1010 MDRA D RAM1100 MARl ACC RAM1110 MRAI RAM ACCNote:1. U = Rotated SourceR/Dest = Non-Rotated Source/DestinationS = MaskY Bus and StatusInstruction Opcode B/WV-Bus Flag3 Flag2ROTM1 = W Yi +-- (Non Rot 0p)i* (mask)i +NC NC(Rot 0p)(j-n)mod 16*(mask)jYi +-- (Non Rot 0p)I* (mask)j +O=BNC NC(Rot 0P)(i-n)mod 8* (mask)jU = UpdateNC = No Change0= Reset1 = Set5-14901100011101011110011S[I)RAM AddressIRAM 00000 ROO RAM Reg 00I. . .. ....ACC11111 R31 RAM Reg 31IIFlagl LINK OVR N C ZNC NC a V a VNC NC a V a V

{;nCY7C9116.' PRELIMINARY CY7C9117. ~~NDUcrOR ======================================================================;;;Instruction Set (Continued)Rotate and Compare InstructionsThe five fields of the Rotate and Compare instructions are:1. Mode (Byte or Word)2. Rotated Source (U)3. Non-Rotated Source (R)4. Mask (S)5. Number of bits Rotated (n)Input U is rotated n bits, ANDed with the inversion of Sand compared with the input R ANDed with the inversionof S. Thus, a zero in the mask S will allow that bit of bothinputs to be compared. The Z bit of the Status Register isset if the comparison passes, and reset if it does not. OVRand C bits are reset in the Status Register.RRotate and Compare FunctionuANDS(MASK)COMPARATOR(XOR)ANDRRotate and Compare Field Definitions15 14 13 12 98 54 0ROTC I B/W I Quadrant I n U,R,S RAM AddressEXAMPLE: N = 4, Word ModeURotated URMask (S)Z (Status) = 1001100010001000100010101010101010101011011111111Rotate and Compare Instruction SetInstruction B/W Quad n U[I] R[I] S[I] RAM AddressROTC0010 CDAI D ACC I00000 ROO RAM Reg 00O=B0011 CDRI D RAM I011 =o to 15.. . . ....W0100 CDRA D RAM ACC11111 R31 RAM Reg 310101 CRAI RAM ACC INote:1. U = Rotated SourceR Non-Rotated SourceS = MaskY Bus and StatusInstruction Opcode B/WV-Bus Flag3 Flag2 Flagl LINK OVR N C ZYj ~ (Non Rot Op)j* (mask)j E91 = W(Rot Op)(i - n) mod 16*(mask)jNC NC NC NC 0 U 0 UROTCYj ~ (Non Rot 0p)i* (mask)j E9O=B(Rot Op)(j - n) mod 8*(mask)jNC NC NC NC 0 U 0 UU = UpdateNC = No Change0= Reset1 = Setj = 0 to 15 when not specified01100011000011110085-115-150

5nCY7C9116. PRELIMINARY CY7C9117. ~~~UcrOR=======================================================================Instruction Set (Continued)Prioritize InstructionThe four fields of the Prioritize instruction are:1. Mode (Byte or Word)2. Mask Source (S)3. Operand Source (R)4. DestinationThe inverted mask, S is ANDed with R. A "one" in Sprohibits that bit from participating in the priority encoding.From the 16-bit input, the priority encoder outputs a5-bit binary weighted code indicating the bit-position of thehighest priority active bit. If there are no active bits, theoutput is zero. See Figure for operation in both word andbyte mode. Using Prioritize updates the Nand Z bits of theStatus Register, and forces C and OVR to zero. This instructionis limited in that the operand and the mask mustbe different sources.Prioritize Instruction Field Definitions1514 13 12 98 54I B/W I Quad Destination Source (R)Prioritize FunctionRAM Address/Mask (S)RAM Address/Source (R)RAM Address/DestinationDestinationWord ModeByte ModeHighestHighestEncoderEncoderPriorityPriorityOutputOutputBit ActiveBit ActiveNone 0 None 015 1 7 114 2 6 2********1 15 1 70 16 0 8*Bits 8 through 15 not available.Prioritize InstructionInstruction B/W Quad Destination Source (R) RAM AddresslMask (S)PRTl1000 PRIA ACC00000 ROO RAM Reg 00O=B0111 RPT1A ACC10 1010 PR1Y YBus1 = W1001 PR1D D · . · . · ...1011 PR1R RAM 11111 R31 RAM Reg 31Instruction B/W Quad Destination Source (R) RAM AddresslMask (S)PRT21000 PRA ACC00000 ROO RAM Reg 00O=B0000 PR2A ACC10 1010 PRZ 01 = W0010 PR2Y YBus · . · . · ...1011 PRI I 11111 R31 RAM Reg 31Instruction B/W Quad Destination Source (R) RAM AddresslMask (S)PRT3O=B1000 PRA ACC 0011 PR3R RAM 00000 ROO RAM Reg 001 = Wo0085-1210 1010 PRZ 0 0100 PR3A ACC · . · . · ...1011 PRI I 0110 PR3D D 11111 R31 RAM Reg 31Instruction B/W Quad Destination Source (R) RAM AddresslMask (S)1000 PRA ACCO=B0100 PRTA ACC 00000 NRY YBusPRTNR111 1010 PRZ 0= W0110 PRTD D 00001 NRA ACC1011 PRI I5-151

..(inCY7C9116; CYPRESS PRELIMINARY CY7C9117~ s~~O~UcrOR==================================================~~==~~~~~Instruction Set (Continued)Y Bus and Status-Prioritize InstructionInstruction Opcode B/W V-Bus Flag3 Flag2 Flagl LINK OVR N C ZYi ~ CODE (SCRn*maskn);PRTl 1= W Y m ~ 0; i = 0 to 4 and n = 0 to 15 NC NC NC NC 0 U 0 UPRT2 m = 5 to 15PRT3Yi ~ CODE (SCRn*maskn);PRTNR O=B Y m ~ 0; i = 0 to 3 and n = 0 to 7 NC NC NC NC 0 U 0 Um =4to 15* Q LINK is loade d with the shifted out bit from the checksum register.SRC = SourceU = Update0 = Reset1 = SetNC = No Changei = 0 to 15 when not specifiedCRC InstructionCyclic-Redundancy-Check Definitions15 14 13 12 98CRCF I 1 Quadrant 0110 I 0011CRCR I Quadrant 0110 I 1001CRC Forward FunctionThe single designator for this instruction is the address ofthe RAM location that is used as the check sum register.Two CRC instructions, CRC Forward and CRC Reverseare available. These instructions give the procedure for d~terminingthe check bits in a CRC calculation. Since theCRC standards do not specify which data bit is transmittedfirst, the MSB or the LSB, both Forward and Reverse optionsare available to the user. The process for generatingthe check bits for the CRC Forward and Reverse operationsare illustrated in the figures below. The ACC is usedas a polynomial mask while the RAM contains the partialsum and eventually the final check sum. The serial inputcomes from the QLINK bit of the Status Register. StatusRegister bits OVR and C are forced to zero while LINK Nand Z bits are updated.'54 0I RAM Address II RAM Address IPOLYNOMIAL MASK(ACC)SHIFTER N= 1'This bit must be transmitted first.0085-135-152

(;APRELIMINARYCY7C9116CY7C9117_. ~~~UcrOR ~=====================================================================Instruction Set (Continued)CRC Reverse FunctionPOLYNOMIAL MASK(ACC)QLlNK*This bit must be transmitted first.Instruction B/W QuadCyclic Redundancy Check Instruction Set00000CRCF 1 10 0110 0011 . .11111Instruction B/W Quad00000CRCR 1 10 0110 1001 . .11111Y Bus and StatusInstruction Opcode B/W V-Bus Flag3 Flag2Yi ~ [(QLINK E9 RAMlS)* AccdCRCF 1 = W E9 RAMi - 1 for i = 15 to 1 NC NCYo ~ [(QLINK E9 RAMlS)* ACCo] E9 0Yi ~ [(QLINK E9 RAMo)* AccdCRCR 1 = W E9 RAMi + 1 fori = 14toO NC NCYIS ~ [(QLINK E9 RAMo)* ACClS] E9 0*QLINK IS loaded with the shifted out bit from the checksum register.U = UpdateNC = No Change0 = Reset1 = Seti = 0 to IS when not specifiedRAM AddressROO RAM Reg 00. . ....R31 RAM Reg 31RAM AddressROO RAM Reg 00. . ....R31 RAM Reg 310085-14Flag! LINK OVR N C ZNC RAMlS* 0 U 0 UNC RAMo* 0 U 0 U5-153

5ACY7C9116. PRELIMINARY CY7C9117~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=Instruction Set (Continued)Status Instructions7 6 5 4 3 2 0I Flag3 I Flag2 I Flag 1 Link OVR NeZSet Status: Specifies which bits in the Status Register are tobe set.Reset Status: Specifies which bits in the Status Register areto be cleared.Store Status: Indicates byte or word and the destinationinto which the processor status is saved. The register isalways stored in the low byte of the destination. The highbyte is unchanged for RAM storage and is loaded withzeroes for ACC storage.Load Status: Imbedded in the Single- and Two-OperandInstructions.Test Status: Instructions specify which of the 12 possibletest conditions are to be placed on the conditional test output.In addition to the 8 status bits, four logical functionsmay be selected: N E9 OVR, (N E9 OVR) + Z, Z + C,and LOW. These functions are useful in testing two's complementand unsigned number arithmetic operations.15 14 13 12SETST I 0 I Quad IRSTST I 0 I Quad ISVSTR I B/W I QuadSVSTNR I B/w I QuadIStatus1011101001110111The status register may also be tested via the T bus asshown below. The instruction lines II thru 14 have buspriority for testing the status register on the CT output.T4 T3 T2 Tl14 13 12 11Cf0 0 0 0 (N EB OVR) + Z0 0 0 1 NEB OVR0 0 1 0 Z0 0 1 1 OVR0 1 0 0 LOW0 1 0 1 C0 1 1 0 Z+C0 1 1 1 N1 0 0 0 LINK1 0 0 1 Flag 11 0 1 0 Flag21 0 1 1 Flag39 8 5 4 0I 1010 I °Ecode II 1010 I °Ecode II1010I RAM Address/ Dest I1010 DestinationStatus Instruction SetInstruction B/W Quad Opcode00011 SONCZ Set OVR, N, C, Z00101 SL Set LINKSETST 0 11 1011 1010 00110 SFI Set Flagl01001 SF2 Set Flag201010 SF3 Set Flag3Instruction B/W Quad Opcode00011 RONCZ Reset OVR, N, C, Z00101 RL Reset LINKRSTST 0 11 1010 1010 00110 RFI Reset Flagl01001 RF2 Reset Flag201010 RF3 Reset Flag3Instruction B/W Quad RAM Address/DestinationSVSTRO=B1 =W00000 ROO RAM Reg 0010 0111 1010 .. . . ....11111 R31 RAM Reg 31Instruction B/W Quad DestinationSVSTNRO=B00000 NRY YBus11 0111 10101 = W 00001 NRA ACCInstruction B/W Quad Opcode(Cf)00000 TNOZ Test (N EB OVR) + Z00010 TNO TestNEBOVR00100 TZ TestZ00110 TOVR TestOVR01000 TLOW Test LOWTest 0 11 1001 101001010 TC TestC01100 TZC TestZ + C01110 TN TestN10000 TL Test LINK10010 TFI Test Flagl10100 TF2 Test Flag210110 TF3 Test Flag3Note: lEN * test status instruction has priority over T 1-4 instruction.5-154

5ACY7C9116__. PRELIMINARY CY7C9117~ ~~NDUcrOR =======================================================================Instruction Set (Continued)Y Bus and StatusInstruction Opcode Description B/W V-Bus Flag3 F1ag2 Flagl LINK OVR N C ZRONCZ Reset OVR, N, C, Z O=B Yi ~ Ofori = Oto 15 NC NC NC NC 0 0 0 0RL Reset LINK NC NC NC 0 NC NC NC NCRSTST RFI Reset Flagl NC NC 0 NC NC NC NC NCRF2 Reset Flag2 NC 0 NC NC NC NC NC NCRF3 Reset Flag3 0 NC NC NC NC NC NC NCSONCZ Set OVR, N, C, Z O=B Yi ~ 1 fori = 0 to 15 NC NC NC NC 1 1 1 1SL Set LINK NC NC NC 1 NC NC NC NCSETST SFI Set nagl NC NC 1 NC NC NC NC NCSF2 Set Flag2 NC 1 NC NC NC NC NC NCSF3 Set Flag3 1 NC NC NC NC NC NC NCSVSTRO=B Yi ~ Status for i ~ 0 to 7;Save Status*SVSTNR 1 = W Yi ~ Ofori = 8to 15TestU = UpdateNC = No Change0= ResetNC NC NC NC NC NC NC NCTNOZ Test (NE90VR) + Z O=B ** NC NC NC NC NC NC NC NCTNO Test (NE90VR) NC NC NC NC NC NC NC NCTZ Test Z NC NC NC NC NC NC NC NCTOVR Test OVR NC NC NC NC NC NC NC NCTLOW Test LOW NC NC NC NC NC NC NC NCTC Test C NC NC NC NC NC NC NC NCTZC Test Z + C NC NC NC NC NC NC NC NCTN Test N NC NC NC NC NC NC NC NCTL Test LINK NC NC NC NC NC NC NC NCTFI Test Flagl NC NC NC NC NC NC NC NCTF2 Test Flag2 NC NC NC NC NC NC NC NCTF3 Test Flag3 NC NC NC NC NC NC NC NC·In byte mode only the lower byte from the Y bus IS loaded mto theRAM or ACC and in word mode all 16-bits from the Y bus are loadedinto the RAM or ACe.1 = Set • "Y-Bus is Undefined.i = 0 to 15 when not specifiedNo-Op InstructionThe No-Op Instruction does not affect any internal registers;the Status Register, RAM register and AC register areleft unchanged. The 16-bit opcode is fixed.InstructionNo-OpNo-Op I15140 IB/W011No Operation Field Definition13 12 98I1000INo-Op InstructionQuad111010100054I000000 I1010 0000·Y-Bus is undefined.SRC = SourceU = UpdateNC = No Change0= Reset1 = Seti = 0 to 15 when not specified5-155

5nPRELIMINARYCY7C9116CY7C9117~~~UcrOR=====================================================================Electrical Characteristics Over Commerical and Military Operating Range Vee Min. = 4.5V, Vee Max. = 5.5VParameters Description Test Conditions Min. Max. UnitsVOHVOLOutput HIGH VoltageOutput LOW VoltageVee = Min.IOH = -3.4 rnAVee = Min.IOL = 16mA2.4 V0.4 VVIH Input HIGH Voltage 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 VIIXlozIsCIcdQl)[2]ledQ2)ledMax. )[2]Capacitance [3]Input Leakage CurrentOutput Leakage CurrentOutput ShortCircuit Current[l]Vss ~ VIN ~ VeeVec = Max.-10 10 fJ-AVee = Max. +40 fJ-AVOUT = VSS to Vee -40 fJ-AVee = Max.VOUT = OVSupply Current Commercial Vss ~ VIN ~ VIL or 110(Quiescent)MilitaryVIH ~ VIN ~ Vee; OEy = HIGH125Supply Current(Static)Supply Current-85 rnACommercial VIN = VCC or GND 30 rnAMilitaryVee = Max.IOPER = OfJ-A 40 rnACommercial Vee = Max., feLK = 10 MHz 150MilitaryOEy = HIGH210Parameters Description Test Conditions Max. UnitsCIN Input Capacitance TA = 25°C, f = 1 MHz 5COUTOutput CapacitanceVee = 5.0V7Notes:1. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second.2. To calculate Icc at any given frequency, use IcdQt) + IcdA.C.) where IcdQt) is shown above and IcdA.C.) = 4.0 rnA/MHz X Clock Frequencyfor the Commercial temperature range. IcdA.C.) = 8.5 rnA/MHz X Clock Frequency for Military temperature range.3. Tested on a sample basis.Output Loads Used for AC Performance CharacteristicsVOUTAll Outputs ExceptOpen Drain+5 v252nOpen Drain (F = 0)+5Vv~no!l0085-15Notes:1. eL = 50 pF includes scope probe, wiring and stray capacitance.2. CL = 5 pF for output disable tests.CLJ0085-16All Input Pulses3.0V----".~---'"'"GND---"I.;:505pFrnArnA0085-175-156

fiJiPRELIMINARYCY7C9116CY7C9117~~~UcrOR================================================================Commercial Switching CharacteristicsGuaranteed Commercial Range A.C. Performance Characteristics(TA = O°C to + 70°C, vee = 4.5V to 5.5V, CL = 50 pF)Combinational Propagation Delays (ns)To OutputFrom InputCY7C9116CY7C911710-4(ADDR)10-15(DATA)10-15(lNST)YO-ISTI-445 53 65 79 45 53 6545 53 65 79 52 60 7345 53 65 79 52 60 7345 53 65 79 52 60 73DLE* 32 39 55 58 32 39 55TI-4CP 32 39 60 63 32 41 66YO-IS 32 39 53 62 32 39 53lEN"DLE is guaranteed by other tests.CT79 45 53 65848484 25 29 356025 25 2769 25 26 376425 25 257948394043Enable/Disable Times (ns) (CL = 5 pF, Disable Only)EnableDisableFrom ToInput OutputTpZH TpZL TpHZ TpLZ45 53 65 79 45 53 65 79 45 53 65 79 45 53 65OEy YO-YI5 20 20 20 23 20 20 20 23 20 20 20 20 20 20 20OET TI-T4 25 25 25 23 25 25 25 23 25 25 25 25 25 25 25792025Clock and Pulse Requirements (ns)InputMinimum Low TimeMinimum High Time45 53 65 79 45 53 6SCP 20 20 20 20 30 30 30DLE 15 15 15lEN 20 20 20 227930155-157

WACY7C9116. PRELIMINARY CY7C9117~DUcrOR =====================================================================Set-up and Hold Times (ns)With High to Low Low to High[5] Input Respect Transition Transition CommentsToSet-up Hold Set-up HoldCY7C9116 and CY7C9117 45 53 65 79 45 53 65 79 45 53 65 79 45 53 65 791234510-4(RAM Addr)10-4 CP&(RAM Addr) lEN10-15(Data)10-4(RAM Addr)[2]10-15(lnstr)[3]CP 13 13 13 24 0 0 0 05 7 7 10 +- Do Not Change -+ 2 2 2 0CP 40 45 60 65 0 0 0 0lEN 18[1] 24[1] 24[1] 38[1] 5[1] 5[1] 10[1] 17[1]CP 18[1] 24[1] 24[1] 38[1] 5[1] 5[1] 10[1] 17[1] 40 45 60 65 0 0 0 06 IEN[2] CP 8 8 8 8Single Addr(Source)Two Addr(Destination)Two Addr(Immediate)Two Addr(Immediate)7 lEN HIGH CP 5 5 5 10 1 1 1 0 Disable8 lEN LOW CP 20 20 20 22 1 1 1 0 Enable9 IENLOW CP 7 7 7 20 1 1 0 0 Note 110 SRE CP 12 12 12 17 2 2 0 011 y[4] CP 25 32 42 44 0 0 0 012 y[4] DLE 6 6 6 10 6 6 6 713 DLE CP 25 30 42 44 0 0 0 0Notes:1. Timing for immediate instruction for first cycle.2. CY7C9117 only.3. CY7C9116 only.4. Y = D for CY7C9117.5. tsx and tHK referenced on the waveforms are looked up on this table by x = line number on the left. Ex: tS1 = 13 ns for - 53 ns devices.Military Switching CharacteristicsGuaranteed Military Range A.C. Performance Characteristics(TA = - 55°C to + 125°C, V cc = 4.5V to 5.5V, CL = 50 pF)Combinational Propagation Delays (os)To OutputFrom InputCY7C9116CY7C911710-4(ADDR)10-15(DATA)10-15(INST)YO-ISTI-465 79 100 65 7965 79 100 73 8465 79 100 73 8465 79 100 73 84DLE* 55 58 68 55 60TI-4CP 60 63 76 66 69YO-IS 53 62 70 53 64lEN*DLE is guaranteed by other tests.5-158CT100 65 79 100103103103 35 48 507027 39 4683 37 40 487225 43 50

(inCY7C9116. PRELIMINARY CY7C9117~NDUcrOR =====================================================================Military Switching Characteristics (Continued)Enable/Disable Times (ns) (CL = 5 pF, Disable Only)FromInputToOutputEnableDisableTpZH TpZL TpHZ TpLZ65 79 100 65 79 100 65 79 100 65 79 100OEy YO-YI5 20 23 25 20 25 25 20 20 25 20 20 25OET TI-T4 25 23 25 25 25 25 25 25 30 25 25 30Clock and Pulse Requirements (ns)InputMinimum Low TimeMinimum High Time65 79 100 65 79 100CP 20 20 33 30 30 50DLE 20 20 20lEN 20 22 22Set-up and Hold Times (ns)With High to Low Low to High[5] Input Respect Transition Transition CommentsToSet-up Hold Set-up HoldCY7C9116 and CY7C9117 65 79 100 65 79 100 65 79 100 65 79 100123410-4(RAM Addr)CP 13 24 24 0 0 0Single Addr(Source)10-4 CP&Two Addr7 10 10 +- Do Not Change ----+ 2 0 0(RAM Addr) lEN (Destination)10-15(Data)10-4(RAM Addr)[2]CP 45 65 78 0 0 3lEN 24 38[1] 57[1] 5 17[1] 17[1]5 10-15 (lnstr)[3] CP 24 38[1] 57[1] 5 17[1] 17[1] 45 65 78 2 0 36 IEN[2] CP 8 8 8Two Addr(Immediate)Two Addr(Immediate)7 lEN HIGH CP 5 10 10 1 0 1 Disable8 IENLOW CP 20 22 28 1 0 1 Enable9 lEN LOW CP 7 20 20 1 0 3 Note 110 SRE CP 12 17 19 2 0 011 y[4] CP 32 42 53 2 0 212 y[4] DLE 6 10 11 6 7 713 DLE CP 30 42 54 0 0 0Notes:1. Timing for immediate instruction for first cycle. 4. Y = DforCY7C9117.2. CY7C9117 only.5. tsx and tHX referenced on the waveforms are looked up on this table3. CY7C9116 only.by x = line number on the left. Ex: tS1 = 24 ns for - 79 ns devices.5-159

5ACY7C9116. PRELIMINARY CY7C9117~NDUcroR ========================================================================Switching WaveformsSingle Address Access TimingCP------'ONE CYCLE ---4-----_OLE _______..1If th 11 is satisfied, th 1 0 need not be satisfied 0085-18Double Address Access Timing----ONE CYCLE ---+-I1------.cp _____'""0085-19One-Address Immediate Instruction Cycle Timing0085-20Two-Address Immediate Instruction Timing (7C9117 Only)0085-215-160

~PRLSSPRELIMINARYCY7C9116CY7C9117~~~O~UaOR==================================================================Set-up and Hold Times (Cross Ref. Table)High to LowLow to High[1] Transition TransitionSet-up Hold Set-up Hold1 tSl thl2 tS2 th23 tS3 th34 tS5 th55 tS4 th4 tS13 th136 th67 tS7 th78 tS8 th89 tS14 th1410 tS9 th911 tSIO thlO12 tS11 thll13 tS12 th12Note:1. Refer to Set-up and Hold times shown on pages 22 & 23.Ordering InformationSpeedPackage OperatingOrdering Code(ns) Type RangeSpeedPackage OperatingOrdering Code(ns) Type Range45 CY7C9116-45LC L69 Commercial 45 CY7C9117-45GC G68 CommercialCY7C9116-45JC[2] J81 CY7C9117-45JC J81CY7C9116-45DC D28 CY7C9117-45LC L8153 CY7C9116-53LC L69 53 CY7C9117-53GC G68CY7C9116-53JC J81 CY7C9117-53JC J81CY7C9116-53DC D28 CY7C9117-53LC LSI65 CY7C9116-65LC L69 65 CY7C9117-65GC G68CY7C9116-65Jc[2] J81 CY7C9117-65JC J81CY7C9116-65DC D28 CY7C9117 -65LC L8179 CY7C9116-79LC L69 79 CY7C9117-79GC G68CY7C9116-79JC[2] J81 CY7C9117-79JC J81CY7C9116-79DC D28 CY7C9117-79LC L8165 CY7C9116-65LMB L69 Military 65 CY7C9117-65GMB G68 MilitaryCY7C9116-65DMB D28 CY7C9117-65LMB L8179 CY7C9116-79LMB L69 79 CY7C9117-79GMB G68CY7C9116-79DMB D28 CY7C9117-79LMB L81100 CY7C9116-99LMB L69 100 CY7C9117-99GMB G68CY7C9116-99DMB D28 CY7C9117-99LMB L81Note:2. 52 Pin PLCC version also available as package type J69.5-161

~ CY7C9116.~~NDUcrOR ==============================P='R=E=='L=IM==I=N.::::'A=R=Y===C=Y=7=C=9=1~1~7Military SpecificationsGroup A Subgroup TestingDC CharacteristicsParametersSubgroupsVOH 1,2,3VOL 1,2,3--Vm 1,2"VIL 1,2,3IIX 1,2,3Ioz 1,2,3Ise 1,2,3IedQI) 1,2,3led Max) 1,2,3Switching CharacteristicsParameters Subgroups10_4{Addr) 7,8,9,10,1110- Is(Data) 7,8,9,10,1110 15(lil,.l, i-..~7,lI,4,1O,11DJ F--_.- ...... _-- -~-+7,8,9,10,11tl-4. 7,8,9,10,11CP~7,8,9,10,11YO-IS 7,8,9,10,11lEN 7,8,9,10,11OEy 7,8,9,10,11OET 7,8,9,10,11CP 7,8,9,10,115-162

PRODUCT ~~~~~==========~ ..INFORMATIONSTATIC RAMS ,.PROMS ~~~~~~~~~~.LOGIC ~~~~~~~~~~~.~~~~~~~~~BRIDGEMOS ~~~~~~~~~=-QUICKPRO ---------..-.---.-....--.;:.------ ..--.--.- ...,:. -"~;~::'....";;.QUALITY AND ~~~~~~~~'4RELIABILITYAPPLICATION BRIEFS -. -III

~ Section Contents~~~~UcrOR==============================================================RIsePage NumberIntroduction to RISC .................................................................................... 6-1Device NumberCY7C601CY7C608Description32-Bit RISC Integer Unit ..................................................... 6-5Floating Point Controller .................................................... 6-11

CYPRESSSEMICONDUCTORIntroduction to RISeIntroductionScalable Processor ArchitectureCypress has implemented a RISC architecture with its7C600 family, called SPARC. SPARC stands for ScalableProcessor ARChitecture, emphasizing its applicability tolarge as well as small machines. SPARC systems have anopen computer architecture. The design specification ispublished, and other vendors are producing microprocessorsimplementing the design. We expect that the intelligentand aggressive nature of the SPARC design will makeit an industry standard. Because of its simplicity, the7C600 scales well. Consequently, 7C600 systems will getfaster as better chip-making techniques are perfected.What is RISC?RISC, an acronym for Reduced Instruction Set Computer,is a style of computer architecture emphasizing simplicityand efficiency. RISC designs begin with a necessary andsufficient instruction set. Typically, a few simple operationsaccount for almost all computations these operations mustexecute rapidly. The advantage of a RISC architecture isthe inherent speed of a simple design and the ease of implementinganddebugging this simple design. Currently,RISC machines are about two to five times faster thanmachines with comparable traditional architectures, andare easier to implement, resulting in shorter design cycles.RISC architecture can be thought of as a delayed reactionto the evolution from assembly language to high-level languages.Assembly language programs occasionally employelaborate machine instructions, whereas high-level languagecompilers generally do not. For example, Sun's Ccompiler uses only about 30% of the available Motorola68020 instructions. Studies show that approximately 80%of the computations for a typical program requires onlyabout 20% of a processor's instruction set.RISC is to hardware what the UNIX operating system is tosoftware. The UNIX system proves that operating systemscan be both simple and useful. Hardware studies suggestthe same conclusion. As technology reduces the cost ofprocessing and memory, overly complex instruction setsbecome a performance liability. The designers ofRISC machinesstrive for hardware simplicity, with close cooperationbetween machine architecture and compiler design. Ateach step, computer architects must ask: to what extentdoes a feature improve or degrade performance and is itworth the cost of implementation? Each additional feature,no matter how useful it is in an isolated instance, makes allothers perform more slowly by its mere presence.The goal of RISC architecture is to maximize the effectivespeed of a design by performing infrequent functions insoftware, including in hardware only features that yield anet performance gain. Performance gains are measured byconducting detailed studies of large high-level languageprograms. RISC improves performance by providing thebuilding blocks from which high-level functions can besynthesized without the overhead of general but complexinstructions.Portability is the real key to the commercial success ofUNIX, and the same is true for RISC architectures. RISCarchitectures are more portable than traditional architecturesbecause they are easier to implement, thus permittingthe rapid integration of new technologies as they becomeavailable. Users benefit because architectural portability allowsmore rapid improvements in the price/performance ofcomputing.RISC ArchitectureThe following characteristics are typical of RISC architectures,including the 7C600 design:Single-cycle execution. Most instructions are executed in asingle machine cycle.Hardwired control with little or no microcode. Microcodeadds a level of complexity and raises the number of cyclesper instruction.Load/Store, register-to-register design. All computationalinstructions involve registers. Memory accesses are madewith only load and store instructions.Simple fixed-format instructions with few addressingmodes. All instructions are the same length (typically 32bits) and have just a few ways to address memory.Pipelining. The instruction set design allows for the processingof several instructions at the same time.High-performance memory. RISC machines have at least32 general-purpose registers (the 7C601 has 136) and largecache memories.SPARCTM, Sun-4, and NFSTM are trademarks of Sun Microsystems, Inc.UNIX® is a registered trademark of AT&T Bell Laboratories.V AX® is a registered trademark of Digital Equipment Corporation.6-1

~ Introduction to RISe~~~~UcrOR=====================================================================Migration of functions to software. Only those featuresthat measurably improve performance are implemented inhardware. Software contains sequences of simple instructionsfor executing complex functions rather than complexinstructions themselves, which improves system efficiency.More concurrency is visible to software. For example,branches take effect after execution of the following instruction,permitting a fetch of the next instruction duringexecution of the current instruction.The real keys to enhanced performance are single-cycle executionand keeping the cycle time as short as possible.Many characteristics of RISC architectures, such as load/store and register-to-register design, facilitate single-cycleexecution. Simple fixed-format instructions, on the otherhand, permit shorter cycles by reducing decoding time.Note that some of these features, particularly pipeliningand high-performance memories, have been used in supercomputerdesigns for many years. The difference is that inRISe architectures these ideas are integrated into a processorwith a simple instruction set and no microcode.Moving functionality from run time to compile time alsoenhances performance functions calculated at compile timedo not require further calculating each time the programruns. Furthermore, optimizing compilers can rearrangepipelined instruction sequences and arrange register-to-registeroperations to reuse computational results.A new set of simplified design criteria has emerged:Instructions should be simple unless there is a good reasonfor complexity. To be worthwhile, a new instruction thatincreases cycle time by 10% must reduce the total numberof cycles executed by at least 10%.Microcode is generally no faster than sequences of hardwiredinstructions. Moving software into microcode doesnot make it better, it just makes it harder to modify.Fixed-format instructions and pipelined execution aremore important than program size. As memory gets cheaperand faster, the space/time tradeoff resolves in favor oftime. Reducing space no longer decreases time.Compiler technology should simplify instructions, ratherthan generate more complex instructions. Instead of substitutinga complicated microcoded instruction for severalsimple instructions, which compilers did in the 1970s, optimizingcompilers can form sequences of simple, fast instructionsout of complex high-level code. Operands can bekept in registers to increase speed even further.The term RISC was coined as part of David Patterson's1980 course in microprocessor design at the University ofCalifornia at Berkeley. The RISC-I chip design was completedin 1982, and the RISC-II chip design was completedin 1984.RISC's Speed AdvantageUsing any given benchmark, the performance, P, of a particularcomputer is inversely proportional to the product ofthe benchmark's instruction count, I, the average numberof clock cycles per instruction, C, and the inverse of theclock speed, S: Let's assume that a RISC machine runs atthe same clock speed as a corresponding traditional machine;S is identical. The number of clock cycles per instruction,I, is around 1.3 to 1.7 for RISC machines, butbetween 4 and 10 for traditional machines. This would6-2make the instruction execution rate of RISC machinesabout 3 to 6 times faster than traditional machines. But,because traditional machines have more powerful instructions,RISC machines must execute more instructions forthe same program, typically about 20% to 40% more.Since RISC machines execute 20% to 40% more instructions3 to 6 times more quickly, they are about 2 to 5 timesfaster than traditional machines for executing typical largeprograms.P=---- 1I X C X- SCompiled programs on RISC machines are larger thancompiled programs on traditional machines, partly becauseseveral simple instructions replace one complex instructionand partly because of decreased code density. All RISCinstructions are 32 bits wide, whereas some instructions ontraditional machines are narrower. But the number of instructionsactually executed may not be as great as theincreased program size would indicate. Global registers,for example, often simplify call/return sequences so thatcontext switches become les~ expensive.7C600 ArchitectureThe SPARC CPU is composed of an 7C601 Integer Unit(IU) that performs basic processing and a 7C608 Floating­Point Controller (FPC) interface to a standard floatingpoint unit that performs floating-point calculations. Althoughnot a formal part of the architecture, 7C600-basedcomputers typically have a memory management unit(MMU), a large virtual-address cache for instructions anddata, and are organized around a 32-bit data and instructionbus.The integer and floating-point units operate concurrently.The FPU performs floating-point calculations with a setnumber of floating-point arithmetic units. The 7C600 architecturealso specifies an interface for the connection ofan additional coprocessor.Instruction CategoriesThe 7C600 architecture has about 50 integer instructions, afew more than earlier RISC designs, but less than half thenumber of Motorola 68000 integer instructions. 7C600 instructionsfall into five basic categories:Load and store instructions (the only way to access memory).These instructions use two registers or a register and aconstant to calculate the memory address involved. Halfwordaccesses must be aligned on 2-byte boundaries, wordaccesses on 4-byte boundaries, and double-word accesseson 8-byte boundaries. These alignment restrictions greatlyspeed up memory access.Arithmetic/logical/shift instructions. These instructionscompute a result that is a function of two source operandsand then place the result in a register. They perform arithmetic,tagged arithmetic, logical, or shift operations.Tagged instructions are useful for implementing artificialintelligence languages such as LISP, because tags provideinterpreters with the type of arithmetic operands.Coprocessor operations. These include floating-point calculations,operations on floating-point registers, and instructionsinvolving the optional coprocessor. Floating-

~ Introduction to RISe~~~DUCTOR =======================================================================point operations execute concurrently with IU instructionsand with other floating-point operations when necessary.This architectural concurrency hides floating-point operationsfrom the applications programmer.Control-transfer instructions. These include jumps, calls,traps, and branches. Control transfers are usually delayeduntil after execution of the next instruction, so that thepipeline is not emptied every time a control transfer occurs.Thus, compilers can be optimized for delayed branching.Read/write control register instructions. These include instructionsto read and write the contents of various controlregisters. Generally the source or destination is implied bythe instruction.Register WindowsA unique feature contributing to the high performance ofthe 7C600 design is its overlapping register windows. Resultsleft in registers become operands for the next operation,obviating the need for extra load and store instructions.According to the architectural specification, there may beanywhere between 6 and 32 register windows, each windowhaving 24 working registers, plus 8 global registers. Thefirst implementation has 8 register windows with 24 registerseach (but count only 16 since 8 overlap), plus 8 globalregisters, for a total of 136 registers. Recent research suggeststhat register windows and tagged arithmetic, found in7C600 systems but not in other commercial RISC machines,are sufficient to provide excellent performance forexpert system development requiring AI languages such asLisp and Smalltalk.Traps and ExceptionsThe 7C600 design supports a full set of traps and interrupts.They are handled by a table that supports 128 hardwareand 128 software traps. Even though floating-pointinstructions can execute concurrently with integer instructions,floating-point traps are precise because the FPU supplies(from a table) the address of the instruction thatfailed.Memory ProtectionSome 7C600 instructions are privileged and can only beexecuted while the processor is in supervisor mode. Thisinstruction execution protection ensures that user programscannot accidentally alter the state of the machinewith respect to its peripherals and vice versa.The 7C600 design also provides memory protection, whichis essential for smooth multitasking operation. Memoryprotection makes it impossible for user programs that haverun amok to trash the system, other user programs, orthemselves.An Open ArchitectureAdvantages of Open ArchitectureThe 7C600 design is the first open RISC architecture, andone of the few open CPU architectures. Standard productsare more beneficial than proprietary ones, because standardsallow users to acquire the most cost-effective hardwareand software in a competitive multi-vendor marketplace.Integrated circuits would come from Semiconductorvendors, while software would be supplied by systems vendors.This advantage is lost when users are limited by aprocessor with proprietary hardware and software.RISC architectures, and the 7C600 design in particular, areeasy to implement because they are relatively simple. Sincethey have short design cycles, RISC machines can absorbnew technologies almost immediately, unlike more complicatedcomputer architectures.7C600 systems were designed to support:the C programming language and the UNIX operatingsystem,numerical applications (using FORTRAN), andartificial intelligence and expert system applicationsusing Lisp and Prolog.Supporting C is relatively easy; most modem hardware architecturesare able to do so. The one essential feature isbyte addressability. However, numerical applications requirefast floating point and artificial intelligence applicationsrequire large address spaces and interchangeability ofdata types.The floating-point processor, with pipelined floating-pointoperation capabilities, achieves the high performance neededfor numerical applications. Floating-point coprocessorsare generally not part of RISC machines, but they areavailable for microprocessors such as the Motorola 68020and the Intel 80386, and for 7C600 systems as well.For artificial intelligence and expert system applications,7C600 systems offer tagged instructions and word alignment.Because languages such as Lisp and Prolog are ofteninterpreted, word alignment makes it easier for interpretersto manipulate and interchange integers and different typesof pointers. In the tagged instructions, the two low-orderbits of an operand specify the type of operand. If an operandis an integer, most of the time it is added to (or subtractedfrom) a register. If an operand is a pointer, most ofthe time a memory reference is involved. Language interpreterscan leave operands in the appropriate registers,greatly improving the performance of exploratory programmingenvironments.The 7C600 architecture does not specify a memory managementunit (MMU) because we expect the same processorto be used in different types of machines. For example,a single-user machine with embedded applications does notneed an MMU. By contrast, a multitasking machine usedfor timesharing, such as a traditional UNIX box, needs apaging MMU and such a device, the 7C603, is provided asa part of the 7C600 family. Furthermore, a multiprocessorsuch as a vector machine or hypercube requires specializedmemory management facilities. The 7C600 architecturecan be implemented with a different MMU configurationfor each of these purposes, without affecting user programs.Speed Advantage of 7C600 SystemsThe performance of a processor is inversely proportional tothe product of a benchmark's instruction count, I, the averageclock cycle per instruction, C, and the inverse of theclock speed, S: Working this equation for 7C600 systemsand for two popular microprocessors, we come up withthese numbers (P indicates millions of instructions per second,MIPS).6-3

~ CYPRF!3SIntroduction to RISe~~~I~UcrOR============================================~~~~~~~~~~Processor PerformanceCPU I C S PMotorola 68030 1.0 5.2 16.67 3.21Intel 80386 1.1 4.4 16.67 3.447C600 1.2 1.3 16.67 10.69Thus, 7C600 systems have a considerable theoretical performanceadvantage over other microprocessors on themarket. The table compares three processors running atthe same clock speed; higher clock speeds are possible withall three processors.7C600 Machines and Other RISe MachinesThe 7C600 ~esign has more similarities to Berkeley'sR~SC-II architecture than to any other RISC architecture.Like the RISC-II architecture, it uses register windows inorder to reduce the number of load/store instructions. The~C6~O architecture allows 32 register windows, but the init~allmplem~ntation has 8 windows. The tagged instructionsare denved from SOAR, the "Smalltalk On A RISC"processor developed at Berkeley after implementingRISC-I1.7C600 systems are designed for optimal floating-point perf?f!Dance,and support single-, double-, and extended-precIsionoperands and operations, as specified by theA~SI/IEEE 754 floating-point standard. High floatingpomtperformance results from concurrency of the IV andFPV. The integer unit loads and stores floating-point operands,while the floating-point unit performs calculations. Ifan error (such as a floating-point exception) occurs, thefloating-point unit specifies precisely where the trap tookplace; execution is expediently resumed at the discretion ofthe integer unit. Furthermore, the floating-point unit hasan internal instruction queue; it can operate while the integerunit is processing unrelated functions.7C600 systems deliver very high levels of performance. Theflexib~lity. of the architecture makes future systems capableof dehvermg performance many times greater than the performanceof the initial implementation. Moreover, theopenness of the architecture makes it possible to absorbtechnological advances almost as soon as they occur.Copyright 1988 by Cypress Semiconductor Corporation and Sun Microsystems, Inc.6-4

Features• Reduced instruction setcomputer (RISe) architecture- Simple format instructions- Most instructions execute insingle cycle• Very high performance- 30 ns instruction cycle with4 stage pipeline- 25 million instructions persecond (MIPS)- 20 equivalent V AX MIPS• Large windowed register file- 136 general purpose 32·bitregisters- 8 overlapping windows of 24registers each• All pipeline interlocksimplemented in hardwareBlock DiagramsCYPRESSSEMICONDUCTOR• Large virtual address space- 32·bit virtual address bus- 8·bit address space identifier• Multitasking support- User/supervisor modes- Privileged instructions• Parallel processing support• Artificial intelligence support• High performance coprocessorinterface- Concurrent execution offloating point instructions• 0.8 micron 2·layer metal CMOStechnology• 207 pin grid array package• Power less than two wattsPRODUCT DESCRIPTIONCY7C601Very High Performance32-Bit RISe ProcessorOverviewThe CY7C601 Integer Unit is a highspeed CMOS implementation of thenew SPARC 32-bit RISC architecturemicroprocessor. This architecturemakes possible the implementation of amicroprocessor which can execute instructionsfor high level language programsat rates approaching one instructionper processor clock. The CY7C601supports a tightly-coupled floatingpoint coprocessor and a second implementation-definablecoprocessor. TheCY7C601 SPARC processor providesthe following features:Simple Instructions-Most instructionsrequire only a single arithmeticoperation.... A(0-31)...ASI(O-1)SIZE(O-1)MAO... 1)(0-31) ......MDS...MHOlDAMHOLnBBHOLDTOECOEClKIRlO-3INTACKMEXCRESETERRORRDWEWRTDXFERlDSTOINUllOCKJjQ[AOE1FT7C601SPARCInteger UnitFPFHOlDFEXCF"XACKFCC(O-nFCCVFINS1FINS2FPSYNINSTFLUSHCPCHOlDCEXCCXACKCCC(O-1)CCCVCINSICINS2ADDRESSDESTINATIONREGISTER FilE136 X 32INSTRUCTION/DATA0129-10129-2Selection GuideClock Frequency (MHz)Maximum Operating l CommercialCurrent (rnA)MilitarySP ARCTM and SunOS are trademarks of Sun Microsystems, Inc.V AX® is a registered trademark of Digital Equipment Corporation.Unix® is a registered trademark of AT&T.I7C601·25 7C601·3325 33TBD 600TBD6-5

~ PRODUCT DESCRIPTION CY7C601~~~~==========================================================Overview (Continued)Simple Instruction Format-All instructions are 32 bitswide and are aligned on 32-bit boundaries in memory.There are only three basic instruction formats which featureuniform placement of opcode and address fields.Register-Intensive Architecture-Most instructions operateon either two registers or one register and a constant,and place the result in a third register. Only load and storeinstructions access off chip memory.A Large "Windowed" Register File-The processor has onchip a large number of 32-bit registers configured as 8overlapping sets of 24 registers each. This scheme allowscompilers to cache local values across subroutine calls, andprovides a register-based parameter passing mechanism.Delayed Control Transfer-The processor always fetchesthe next instruction after a control transfer, and either executesit or annuls it depending on the state of a bit in thecontrol transfer instruction. This feature allows compilersto rearrange code to place a useful instruction after a delayedcontrol transfer and thereby take better advantage ofthe processor's pipeline.One Cycle Execution-The processor is capable of fetchinginstructions at a rate of one per processor cycle. Thisallows most instructions other than load/store and floatingpoint instructions, to execute in one cycle.Concurrent Floating Point-Floating point instructionscan execute concurrently with each other and with nonfloatingpoint instructions.Fast Interrupt Response-Interrupt inputs are sampled everycycle and can be acknowledged in one to three cycles.The first instruction of an interrupt service routine can beexecuted within 6 to 8 cycles of receiving the interruptrequest.The 7C600 FamilyThe SPARC processor family consists ofa CY7C601 IntegerUnit (IU) to perform all non-floating point operationsand a CY7C608 Floating Point Controller (FPC) whichinterfaces to a standard floating point unit to perform floatingpoint arithmetic concurrent with the IV. Support isalso provided for a second generic coprocessor interface.The IV communicates with external memory via a 32-bitaddress bus and a 32-bit data/instruction bus. In typicaldata processing applications, the IV and FPC are combinedwith a high performance CY7C603 Memory ManagementVnit and a cache memory implemented withCY7C152 Cache RAMs and the CY7C181 Cache TagRAM. In many dedicated controller applications the IVcan function by itself with high speed local memory.Coprocessor InterfaceThe IV is the basic processing engine which executes all ofthe instruction set except for floating point operations. TheFPC and IV operate concurrently. The FPC recognizesfloating point instructions and places them in a queuewhile the IV continues to execute non-floating point instructions.If the FPC encounters an instruction which willnot fit in its queue, the FPC holds the IV until the instructioncan be stored. The FPC contains its own set of registerson which it operates. The contents ofthese registersare transferred to and from external memory under control6-6ofthe IV via floating point load/store instructions. Processorinterlock hardware hides floating point concurrencyfrom the compiler or assembly language programmer. Aprogram containing floating point computations generatesthe same results as if instructions were executed sequentially.RegistersThe CY7C601 Integer Vnit contains a large 136 X 32 registerfile which is divided into 8 windows, each with twenty-four32-bit working registers, and each having access tothe same eight 32-bit global registers. A current windowpointer (CWP) field in the processor state register (PSR)keeps track of which window is currently active.The current window pointer is decremented when the processorexecutes a call to a subroutine and is incrementedwhen the processor returns.Previous Window·r(~1)INSr(24)r(~3)· LOCALSr(16)r(! 5)· OUTSr(8)Active Window··r(~1 )INSr(24)r(23)· LOCALSr(16)r(!5)· OUTSr(8)r(7): GLOBALSreO)Next Windowr(:1). INSr(24)r(~3). LOCALSr(16)r(!5)OUTSr(8)0129-3The registers in each window are divided into ins, outs, andlocals. The eight global registers are shared by all windowsand appear as registers 0-7 in each window. Registers8-15 serve as outs, registers 16-23 as locals, and 24-36 asins. Each window shares its ins and outs with adjacentwindows. The outs of a previous window are the ins of thecurrent window, and the outs of the current window arethe ins of the next window. The globals are equally availableto all windows and the locals are unique to each window.The windows are joined together in a circular stackwhere the outs of window 7 are the ins of register O.Multitasking SupportThe CY7C601 supports a multitasking operating system byproviding user and supervisor modes. Some instructionsare privileged and can only be executed while the processoris in supervisor mode. Changing from user to supervisormode requires taking a hardware interrupt or executing atrap instruction.

~ PRODUCT DESCRIPTION CY7C601~~~U~~~~~~~~~==================================================Interrupts and TrapsThe CY7C601 supports both asynchronous traps (interrupts)and synchronous traps (error conditions and trapinstructions). Traps transfer control to an offset within atable (vectored traps). The base address is specified by aTrap Base Register and the offset is a function of the typeof trap. Traps are taken before an instruction causes anychanges visible to i,he programmer and therefore can beconsidered to occur "between" instructions.Pin SummaryMemory Interface SignalsA(O-31) Address BusASI(O-7) Address Space IdentifierD(0-31) Data BusMEXC Memory Exception InputMHOLDA/B Hold from MemoryBHOLD Hold from I/O SystemAOE Address Bus Output EnableDOE Data Bus Output EnableMDS Memory Data Input Strobe during HoldMAO Previous Memory Address Output Select1FT Instruction Cache Flush TrapSIZE Data Bus Transfer SizeRD Read CycleWE Write CycleWRT Advanced Write SignalLDST Load/Store CycleI NULL Null CycleLOCK Bus Lock RequestDXFER Data Fetch CycleVSSO Output Driver GNDVCCO Output Driver PowerVSSI Main GNDVCCI Main PowerVSST Input Circuit GNDVCCT Input Circuit PowerMiscellaneous I/O SignalsIRL(0-3) Interrupt Request LevelINTAK Interrupt AcknowledgeERROR Processor in Error StateRESET Processor Reset InputCLK Input ClockFloating Point/Coprocessor Interface SignalsFP/CP Unit is PresentFCC/CCC(0-1) Condition Codes InputFCCV /CCCV Condition Codes ValidFHOLD/CHOLD Hold InputFEXC/CEXC Exception InputFXACK/CXACK Exception AcknowledgeFINS/CINS(1-2) Floating Point/CoprocessorInstructionINST Instruction Fetch CycleFLUSH Flush Floating Point/Coprocessor InstructionInstruction Set SummaryInstructions fall into five basic categories:1. Load and Store Instructions-Load and store instructionsare the only instructions which access external memory.They use two IU registers or an IU register and asigned immediate value to generate the memory address.The instructions destination field specifies either an IntegerUnit register, a Floating Point Unit register or a coprocessorregister as the destination for a load or the source for astore. Integer load and store instructions support 8, 16, 32,and 64 bit accesses while floating point and coprocessorinstructions support 32- and 64-bit accesses.Load/Store Signed ByteLoad/Store Signed HalfwordLoad/Store Unsigned ByteLoad/Store Unsigned HalfwoodLoad/Store WordLoad/Store Double WordLoad/Store Floating Point/Coprocessor RegistersLoad/Store Double Floating Point/CoprocessorLoad/Store Floating Point/Coprocessor State RegisterStore Double Floating Point/Coprocessor Queue2. Arithmetic/Logical/Shift-These instructions all computea result that is a function of two source operands andwrite the result into a destination register or discard it.They perform arithmetic, tagged arithmetic, logical andshift operations. One instruction, useful in creating a 32-bitconstant in two instructions, writes a 22-bit constant intothe high order bits of a register and zeroes the remainingbits. The contents of any register can be shifted left or righta distance specified either by the instruction itself or byanother register. The tagged arithmetic instructions areuseful in artificial intelligence applications. 6Add (w/wo modifying condition codes)Add with Carry (w/wo modifying condition codes)Tagged Add (w/wo trap on overflow)Subtract (w/wo modifying condition codes)Subtract with Carry (w/wo modifying condition codes)Tagged Subtract (w/wo trap on overflow)Multiply Step and modify condition codesAnd (w/wo modifying condition codes)And Not (w/wo modifying condition codes)Or (w/wo modifying condition codes)Or Not (w/wo modifying condition codes)Exclusive-Or (w/wo modifying condition codes)Exclusive-Nor (w/wo modifying condition codes)Shift Left LogicalShift Right LogicalShift Right ArithmeticSet High 22 Bits of Register3. Control Transfer-Control transfer instructions includejumps, calls, traps and branches. Control transfer is usuallydelayed so that the instruction immediately following thecontrol transfer (called the delay instruction) is executedbefore control is transferred to the target location. The delayinstruction is always fetched, however a bit in the controltransfer instruction can cause the delay instruction to6-7

~ PRODUCT DESCRIPTION CY7C601~~~UcrOR ================================================================~be nullified if the branch is not taken. This flexibility increasesthe likelihood that a useful instruction can beplaced after a control transfer instruction thereby filling anotherwise unused hole in the processor's pipeline. Branchand call instructions use program counter relative displacements.A jump and link instruction uses a register indirectdisplacement: it computes its target address as either thesum of two registers, or the sum ora register and a 13-bitsigned immediate value. The branch instruction provides adisplacement of plus or minus 8 megabytes, and the callinstructions 30-bit displacement allows transfer to any address.Decrement Current Window PointerIncrement Current Window PointerBranch or Integer Condition CodesBranch on Floating Point/Coprocessor ConditionCodesCallJump and LinkReturn from TrapTrap on Integer Condition Codes4. Read/Write Control Registers-The processor providesinstructions to read and write the contents of the variouscontrol registers including:ReadIWrite Multiply Step RegisterReadIWrite Processor State RegisterReadIWrite Window Invalid Mask RegisterReadIWrite Trap Base RegisterFlush Instruction Cache5. Floating Point/Coprocessor Instructions-These instructionsinclude all floating point calculations and futurecoprocessor instructions and involve register to register operationsbetween registers on board the Floating PointController or coprocessor.Convert Integer to Single/Double/Extended PrecisionConvert Single/Double/Extended Precision to Integer(w/wo rounding)Convert Single Precision to Double/ExtendedPrecisionConvert Double Precision to Single/ExtendedPrecisionMove/Negate/Absolute ValueSquare Root Single/Double/ExtendedAdd Single/Double/ExtendedSubtract Single/Double/ExtendedMultiply Single/Double/ExtendedDivide Single/Double/ExtendedCompare Single/Double/Extended(w/wo exception if unordered)Development SupportCompilers for the C, Pascal, and Fortran 77 languages runon both the 68020-based Sun-3 and SPARC-based Sun-4workstations from Sun Microsystems, Inc. Both workstationfamilies include the SunOS operating system withits full complement of Unix® software development utilities.These utilities include well-known programs for textediting, source code checking, source code debugging, performanceanalysis, document formatting, software projectmanagement, and compiler generation. In addition, theSPARC-based Sun-4 systems can serve as a machine-codecompatibleexecution vehicle to verify the correctness andperformance of CY7C601 code.6-8

Pin NamePinNumberPin NamePinNumberPin NamePinNumberAO K2 D23 J17 CINS2 C17Al Kl D24 H17 CXACK C13A2L3D25 H15IRLO AIOA3 LlD26 G17IRLl CllA4 L2D27 H16IRL2 DIOA5 M2D28 G16IRL3 B12A6 N2D29 F16INTACK A13A7 MlD30 F15RESET A9A8 M3D3l G15ERROR B15A9 PIASIO F3 TOE C15AIO P2ASH F2 FPSYN C12All NlASI2 G3 CLK K3A12 N3ASI3 G2A13 R3VSSO B16 F17 R5ASI4 GlA14 R2B17 H4 R14ASI5 H2A15 R4C3 J2 TI6ASI6 HIA16 T4C4 K14 TI7ASI7 J1A17 T5D6 N14 V16SIZEO E2A18 R6D14 P4 V17SIZE 1 D2A19 T6Fl P6A20 V5 MEXC D8 F4 PllA2l V6 MHOLDA C8 F14 P14A22 V7MHOLDB B8VCCO A15 L4A23 T7BHOLD A7A16 M14A24 V8AOE P3A17 N4A25 T8DOE N17Dl P8A26 V9COE C2D12 P12A27 R8MDS B7D17 P16A28 T9MAO E3El P17A29 R91FT C14G4 R16A30 TIO RD A4 K4 R17A3l VllWE B4K15DO RIOLDSTO C5Dl TilI NVLL B5VSSI A3 J3 V2D2 V12LOCK D4A14 Ll4 VIOD3 TI2DXFER D3B2 M4D4 V13WRT E4B3 P5B9 P7D5 TI3 FP C7 Cl RlD6 TI4 FCCO All C16 RllD7 R13 FCCI Bll D13 TID8 V14 FCCV CIO E15 TI5D9 V15 FHOLD A8 H14 VIDIO R15FEXC A5Dll P15CPB6VCCI A2 R7D12 N15CCCO A12Bl R12D13 M15CCCI B13D7 T2D14 M16CCCV BIOE14 T3D15 N16CHOLD C9E16 V3D16 Ll5CEXC A6G14 V4D17 M17H3INST C6D18 Ll6J15FLVSH B14D19 Ll7PIOFINS 1 E17D20 K16FINS2 D16VSST D9 J14D2l K17FXACK DllJ4 P9D22 J16CINSI D15 VCCT D5 P13III6-9

~ PRODUCT DESCRIPTION CY7C601~~~UcrOR==~~~~~~~~~~~~~~~~~~~~====~==~====~ABC D E t G H J K L M N P R T U1 000000000000000020000000000000000030000000000000000040000000000000000050000 000060000 000070000 000080000 000090000 BonOM VIEW 0000100000 0000110000 0000120000 0000130000 000014000000000000000001500000000000000000160000000000000000017000000000000000000129-4Ordering InformationClockPackageOperatingFrequencyOrdering CodeTypeRange(MHz)25 CY7C601-25GC G208 Commercial33 CY7C601-33GC G20825 CY7C601-25GMB G208 Military6-10

PRODUCT DESCRIPTIONCY7C608Floating-Point ControllerFeatures• Interfaces TI74ACT8847 toCY7C601• Provides concurrent coprocessorinterface• Very high performance- 30 ns instruction cycle with 4stage pipeline- Supports 4 megaflops doubleprecision performance(Linpack)• 32 32·bit registers- Organized 16 by 64 bits- Dual port access• All pipeline interlocksimplemented in hardware• Artificial intelligence support• 0.8 micron 2·layer metal CMOStechnology• 280 pin grid array package- Plastic and ceramic• Power less than two wattsProduct CharacteristicsThe CY7C608 Floating-Point Controller(FPC) is a controller designed to interfacethe Texas Instruments (TI)74ACT8847 Floating-Point Processorto the CY7C601 Integer Vnit (IV). Thetwo chips together will provide highperformance single and double precisionfloating-point execution. The TIfloating-point chip performs the followingfloating-point operations: add, subtract,multiply, divide, square root,compare, and convert. In addition tothese operations, the FPC will takecare of register to register move instructions,Floating-Point loads andstores, and Floating-Point State Registerand Floating-Point Queue store instructions.All instructions which areunimplemented by the FPC will causean Vnimplemented FPop trap in whichcase the instruction should be emulatedin software. The FPC design is brokendown into two distinct areas: the IntegerUnit (IV) and memory system interface,and the FPU chip interface.FPC Internal StructureThe CY7C608 FPC consists of an instructionprocessing control unit, anFPV instruction control unit, a registerfile, the Floating-Point Queue, theFloating-Point Status Register, andmiscellaneous data registers. The instructionprocessing control unit takescommands from the IV and dispatchesinstructions to the FPV instructioncontrol unit. The FPV control unithandles all instructions which requirethe use of the FPU datapath chip. Theregister file on the FPC is a dual-ported(one read port, one write port) 16 w?rddeep by 64-bit wide register file. A Slllgleor double precision operand can befetched in one cycle. Thus, two cyclesare required for instructions that usetwo operands. The Floating-PointCY7C601IUINTERFACESYSTEMCONTROLFPFCCVFCC 0-1FHOLDFEXCFXACKFINS1FINS2INSTFLUSHCCCVCHOLDTOEMHOLD A-CMDSDOEFPRESCHAINRESETCLKTEST 0-1TEST 0-1->0................-".... CY7C608..... FLOATING POINTCONTROLLER.....-"".....-".....-"DATA BUS A ..DATA BUS B-=:... RESULT BUS r....INSTR BUS --..... ADDRESS~ DATA ...... ..0-310-310-31 TI8847FPU0-7 INTERFACERESET ENAOPERAND 0-1RND-MD 0-1SELECT 0-2CCLKSTATUS 0-11STALL2-31 SYSTEMBUS0-310131-1Selection GuideGeneric PartNumberComIccMilComfcMilCY7C608-33CY7C608-25TBDTBDTBD3325 256-11

tz PRODUCT DESCRIPTION CY7C608~~~NDUcrOR ~~~~~~~~~~~===============================================FPC Internal Structure (Continued)Queue is 3 instructions deep, with each instruction havinga corresponding address entry. As instructions completetheir execution, they are removed from the queue, withsubsequent queue entries moving toward the front of thequeue. The same actions occur as instructions are read outof the queue in store queue instructions during floatingpointexception handling. The LD_H and LD_L registershold the data coming into the F}>C from memorywhile the register file is being written to. The RSLT_Hand RSL T _L registers hold data coming in from the TIchip until the results can be written to the register file. TheOP _A and OP _B registers hold operands to be sent tothe 8847. The ST_H and ST_L registers hold the datawhich is going out to memory. Please refer to the attachedblock diagram for an overview of the FPC datapath.Processing of InstructionsCY7C608 FPop instructions are single cycle instructions.Each time the IV does an instruction fetch, the FPC takesthat same instruction from the data bus and stores it in itsDecode buffers (D-buffers). The FPC also captures the addressof the instruction off of the address bus and stores theaddress with the instruction in the Floating-Point Queue.When the IV has determined that the current instruction isan FP instruction (D-stage), it signals the FPC to startexecution of the instruction in the FPC's D-buffers. The IVsends the proper signal (FINS 1/FINS2) so that the FPCknows which instruction to execute (D1/D2). There aretwo classes of instructions that the FPC must process,Floating-Point operation (FPop) and Floating-Point Load/Store (FPLdSt) instructions. The FPLdSt instructionsmust be executed in the FPC at the same time the IVexecutes them. They never enter the Floating-Point Queue.The FPops are dispatched to the FPC by the IV and fromthen on, it is up to the FPC to see that they are executed.Once they have gone through the IV's pipeline, they enterthe FP queue and cannot be flushed by the FLVSH signalfrom the IV.Decoding InstructionsSince the FP instruction is available in the FPC in the D­stage, it can be decoded to determine the type of FP operation,and dependency checking that can be done. Most informationcan be decoded when the instruction is in Dland latched when the instruction enters D2. However, dependencychecking depends on dynamic information so D 1and D2 have parallel dependency checking with the properinformation selected by FINS 1 or FINS2. There are twobasic types of instructions that the FPC executes: FPops,which include add, subtract, multiply, divide, square root,convert, compare, register-to-register move, negate, andFPC Datapath6-12DATA BUS B0-31DATA BUS A0-310131-2

~RRSSPRODUCT DESCRIPTION CY7C608~~IOOOOUcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~absolute value instructions; and FP load/store instructions,which include loads, stores and FSR and queue instructions.Register File AccessWhen FP instructions reach the E-stage, the addresses ofthe FP registers that the instruction needs to read fromgoes into the read address unit. For FPops, the read addressspecified by the rs2 or rd field of the instruction wordis latched into a separate register. Floating-Point load andstore instructions have priority in accessing the register filefor both reads and writes, unless a dependency exists.When an FPop is finished and is ready to write its resultinto the register file, the register file write address is takenfrom the front instruction word (rd field) in the FP Queue.For FPLdSt instruction writes, the destination register addressis taken from the instruction word (rd field) andlatched into a register.FPUTI8847by the IV, the FPC will hold until all instructions havecompleted execution and the instruction/address pair isundefined. This does not happen if the FPC is in FP exceptionmode.In the resource dependency case, if it appears that the FPCwill not have any more queue entries available to accommodateany more FPops, then the FPC will assertFHOLD. This condition could occur if the queue is full, orif an FPop is waiting for register file access, waiting tochain, or a divide or square root instruction is executing.If the FPC goes into exception mode, FHOLD is deasserted.If there is a Floating-Point sequence error, FHOLD isasserted for one cycle. This is the only case where FHOLDis asserted in exception mode.PerformanceThe Linpack inner loop has been used as a preliminaryestimate of the performance of the Sunray FPC. The IV/FPC system can execute the 10 instructions of the innerloop without any FHOLDs; thus, it takes 26 cycles to executethe inner loop. Therefore, running with a 30 ns cycletime, we spend 780 ns executing four FPOPs, giving a Linpackinner-loop performance of 5.13 MFLOPS, not countingloop overhead operations. If 5 cycles are allowed forloop overhead, then the performance is 4.30 MFLOPS.Fhold Conditions0131-3In some situations it is necessary to stop the Integer Vnit'spipeline, either because a FPLdSt instruction must be suspended-meaningthat there is an operand dependency, orbecause the FPC cannot accept any more instructionsmeaningthat there is a resource dependency. Fhold is usedto stop the IV from going on in these cases. The followingsituations describe the conditions for Fhold in the operanddependency case:LDF, LDDF-Ioad data from memory into f-register (rd).rd must not be the same as any rs1, rs2, or rd register inprevious FPops that are still executing. This is becausesource registers of FPops (rs1, rs2) may not be altered incase of an FP exception.STF, STDF-store data in f-register (rd) to memory.rd must not be the same as any rd, register in previousFPops that are still executing. (operand dependency)LDFSR, STFSR-Ioad/store data from/to memory intoFloating-Point Status Register.[f any instructions are currently executing in the FPCwhen a LDFSR/STFSR instruction is issued by the IV, theFPC will hold until all instructions have completed executionand are no longer in the queue.STDFQ-store front entry of Floating-Point Queue.[f any instructions are currently executing in the FPC (inFP execution mode) when a STDFQ instruction is issuedFloating-Point Instruction Cycle CountInstructionCyclesFAAD FSUB FCMP FCMPE FMULs 8FMOV FNEG FABS 8FiTOy FyTOi FyTOy 8FMULd 9FDIVs 13FDIVd 18FSQRTs 15FSQRTd 22The table above gives the instruction cycle count for eachof the types off floating-point operations. The cycle countis the number of cycles it takes the operation to execute,starting from the first operand read from the register file tothe result write to the register file.Because of pipelining and chaining, the observed cyclecount for floating-point operations from a performancestandpoint will be much less.IEEE 754 Floating-Point Compatibility andImplementationThis section describes how the CY7C608 Floating-PointController implements the IEEE 75-+ floating-point arithmeticspecification. The issue of which exceptions to implementis dependent on how the Texas InstrumentsSN74ACT8847 Floating-Point Processor handles IEEE exceptions.An exception is implemented if the TI 8847 returns theproper, non-trapping result. Thus, if the exception is enabled,the FPC traps and prevents the writing of the resultinto the register file. If the exception is not enabled, thenthe FPC should write back the correct, non-trapping resultas described by the IEEE specification.6-13

PRODUCT~~~~~~~~~~~~INFORMATIONSTATIC RAMS ~~~~~~~~~~~QUALITY AND §§~§§~~~~~~~gRELIABILITYAPPLICATION BRIEFS ~~~~~~~~.

~~Section Contents~~~O~UcrOR==~~~~~~~~~~~~==~~~====~~====~~~==~~======BridgeMOSPage NumberBridgeMOS Overview ................................................................................... 7-1Device NumberCY8C150CY8C245CY8C291CY8C901CY8C909CY8C911DescriptionBridgeMOS 1024 x 4 Static RAM Separate I/O ................................... 7-1BridgeMOS 2048 x 8 Reprogrammable Registered PROM .......................... 7-1BridgeMOS Reprogrammable 2048 x 8 PROM ................................... 7-1BridgeMOS 4-Bit Slice ........................................................ 7-1BridgeMOS Microprogram Sequencer ........................................... 7-1BridgeMOS Microprogram Sequencer ........................................... 7-1

CYPRESSSEMICONDUCTORBridgeMOSFeatures• May be driven by CMOS orTTL• Drives fully loaded TTL- Inputs switch at 1.SV• Can drive CMOS to full inputlevels- VOL = 0.2V @ IOL = 20IJ-A- VOH = 0.9 V cc @ IOH =-20 IJ-A• SRAM, PROM, LOGIC• 2.0V (V cd Data Retention onall devicesOverviewThe BridgeMOSTM product line fromCypress Semiconductor provides anelectrical bridge between CMOS andTTL or TTL and CMOS devices.BridgeMOS devices may be driven byeither TTL or CMOS devices and intum can drive either fully loaded TTLor CMOS to full input levels. As a result,any combination of TTL and/orCMOS may be interfaced to CypressBridgeMOS products.All devices in the BridgeMOS productline are specified at a 2.0V (V cdstandby mode of operation. This allowsthe device to be powered at 2.0 voltsand maintain the integrity of the datain any volatile storage element.The output drivers in the 7CXXX Cypressproducts are designed for TTLsignals and pull up to 2.4 volts. ForBridgeMOS, Cypress has designed anoutput driver which boosts the outputvoltage sufficiently to drive the inputsof a device to greater than 3.85 volts,thus guaranteeing that the input converterwill draw minimum power. Theoutput drivers source 20 microamps attheir rated BridgeMOS levels. Theywill also source and drive normal TTLloads. Therefore, they are capable ofdriving other non-BridgeMOS loadsand normal TTL loads at the sametime.Although the TTL to CMOS inputconverters power down as describedabove, they switch at TTL levels andall timing is referenced to 1.5 volts. Thedevice will operate at normal TTL levelswith no AC performance degradation.CV8C150 Selection GuideMaximum AccessTime (ns)Maximum OperatingCurrent (rnA)8C150-15Commercial 15MilitaryCommercial 100Military8C150-25 8C150-3525 3525 35100 100125 125:V8C245 Selection Guide8C245-35 8C245-45Maximum Access Time (ns) 35 50Maximum Operating l Commercial 45 45Current (rnA)I Military 80 80•:V8C291 Selection Guide8C291-35 8C291-50Maximum Access Time (ns) 35 50Maximum Operating I Commercial 45 45Current (rnA)I Military 80 807-1

~ BridgeMOS~ ~~~UcrOR=====================================================================CY8C901 Selection GuideRead Modify.Write Cycle (min.) in ns Operating Icc (max.) in mA Operating Range Part Number31 26.5 Commercial 8C901-3132 31.0 Military 8C901-32CY8C909/8C911 Selection Guide8C909·30 8C909·408C911·30 8C911·40Minimum Clock to Output Cycle Time (ns) 30 40Maximum Operating Current (rnA) 15 157-2

k j ilZ QUICKPROPRODUCTINFORMATIONSTATIC RAMSPROMS•EPLDS ,~.LOGICRISCBRIDGEMOSQUALITY ANDRELIABILITYAPPLICATION BRIEFS'I'·1•EllDIPACKAGES

~ Section Contents~~~ucr~========================================================QuickProDevice NumberCY3000DescriptionPage NumberCombined PROM, PLD, and EPROM Programmer ............................... 8-1

CYPRESSSEMICONDUCTORCY3000QuickProFeatures• Combined PROM, PLD, andEPROM programmer• Programs all Cypress CMOSPLDs and PROMs. (All futuredevices will also be supported)• Reads bipolar PLDs andPROMs• Easy to use, menu-drivensoftware• New device updates via floppydisk• IBM-PC® plug-in card format,external ZIF -DIP socket• Compatible with the IBM PCfamily of computers and plugcompatibles• Programs 24- and 28-pin NMOSand CMOS EPROMs• One long slot and 256K bytes ofmemory required• Designed for present and futureNMOS and CMOS devices• Optional LCC, PLCC, SOICsocket adaptersDescriptionQuickPro is a development tool forpresent and future CMOS PROM andPLD devices, and is used within theIBM PC and compatible environment.Older generation bipolar PLDs andPROMs required special programmingvoltages and current difficult to generatewithin the IBM PC.QuickPro is designed for new generationof CMOS PLDs and PROMswhich obsolete the older technology,and use a programming techniqueQuickPro is a trademark of Cypress Semiconductor Corporation.IBM and IBM PC are registered trademarks of International Business Machines Corporation.ABEL TM is a registered trademark of Data I/O Corporation.CUPLTM is a registered trademark of Assisted Technology.P ALASMTM is a registered trademark of Monolithic Memories Inc.0095-18-1

~ CY3000~~~UcrOR ~~~~~~~~~~~~~~~~=====================================Description (Continued)which is more compatible with low cost programmingmethods.QuickPro can also program standard NMOS and CMOSEPROMs in packages up to 28 pins. And QuickPro is fast;intelligent programming is used to reduce programmingtime to a minimum.QuickPro is future oriented. Each I/O pin is fully programmable,allowing the parameters and timing of eachdevice to be handled via software. As new devices becomeavailable, they will be supported by QuickPro. Updates aremanaged by a simple exchange of floppy disks.QuickPro includes a comprehensive set of commands tomake programming PLDs and PROMs as easy as possible.For PLDs, QuickPro uses the JEDEC standard data format,so present and future logic design tools such asABELTM, CUPLTM, and PALASMTM can be used.QuickPro avoids serial download problems from a PC to astand-alone programmer. For PROMs, QuickPro readsPCDOS binary files for use with assemblers and compilers.And QuickPro is low cost, each workstation can have one,eliminating the inconvenience of sharing one expensiveprogrammer. All actions are menu-driven, with completeexplanations provided on-screen, in clear text. There is noneed to look up manufacturer's codes in a table.QuickPro CommandsProgram deviceSelect device typeEdit memoryDisplay memoryRead deviceTest PLD deviceRead disk fileTechnical InformationSizeWrite disk fileVerify deviceBlank check deviceProgram security fuseFill memoryConvertPLD typeIBM PC standard full length card. Uses port addresses300-31F hex.Power+5V 1.0 amp+ 12V 1.0 amp (peak) 0.4 amp average-12V 0.05 ampSocket PodThis is the external socket for connection to the device tobe programmed or read. It provides a 28-pin 300/600 milsocket for compatibility with a wide range of devices. Otheradapters for leadless packages are also available. Fivefilter switches are located on the pod for bypass capacitorsaccording to manufacturers' published programming specifications.Memory256K bytes of total memory is sufficient to operate Quick­Pro.Devices SupportedCypress CMOS PROMs:CY7C225, CY7C235, CY7C245, CY7C245A,CY7C251, CY7C254, CY7C261, CY7C263,CY7C264, CY7C268, CY7C269, CY7C271,CY7C281, CY7C282, CY7C291, CY7C291A,CY7C292, CY7C292A, CY7C293ACypress CMOS PLDs:PAL16L8, PAL16R4, PAL16R6, PAL16R8,PAL22VlO, PLD20GlOQuickPro can read 20 and 24 pin Bipolar PLDs, for conversionto Cypress PLDs.EPROMs: (NMOS and CMOS)2716,2732,2732A,2764,2764A,27128,27256Ordering InformationCY3000 QuickPro System ($995.00) contains:CY300 1 QuickPro BoardCY3OO2CY3OO3QuickPro PodQuickPro System DiscQuick Pro ManualOptional QuickPro Package Adaptors Include:CY3004 (CY3OO6) 28 Lead Square (P)LCC:*7C225, 7C235, 7C245, 7C261, 7C263, 7C264, 7C281,7C282, 7C291, 7C292, PALC22VI0CY3OO5 (CY3OO7) 20 Lead Square (P)LCC:16L8, 16R4, 16R6, 16R8CY3OO8 (CY3009) 28 Lead Square (P)LCC:7C269, 7C271, 7C330, 7C331, 7C332CY3010 (CY3011) 28 Lead Square (P)LCC:PLDC20GI0CY3012 (CY3013) 32 Lead Rectangular (P)LCC:7C268CY3014 28 Pin SOIC:7C225, 7C235, 7C245, 7C251, 7C254, 7C261, 7C263,7C264, 7C269, 7C271, 7C281, 7C282, 7C291, 7C292CY3015 32 Pin SOIC:7C268CY3016 32 Pin DIP:7C268CY3017 (CY3018) 28 Lead Square (P)LCC:7C251,7C254*Switch SettingsA = PALC22VlO, B = PROMs8-2

PRODUCT,.INFORMATIONSTATIC RAMSPROMS••EPLDS ,~.LOGICRISCBRIDGEMOSQUICKPRO'IIII•~ QUALITY AND¥ ~ - RELIABILITYAPPLICATION BRIEFSDPACKAGES

~ Section Contents~~~~UaDR========================================================Quality and ReliabilityPage NumberQuality, Reliability and Process Flows ...................................................................... 9-1

CYPRESSSEMICONDUCTORQuality, Reliability and Process FlowsCorporate Views on Quality andReliabilityCypress believes in product excellence. Excellence can onlybe defined by how the users perceive both our productquality and reliability. If you, the user, are not satisfiedwith every device that is shipped, then product excellencehas not been achieved.Product excellence does not occur by following the industrynorms. It begins by being better than one's competitors,with better designs, processes, controls and materials.Therefore, product quality and reliability are built into everyCypress product from the start.Some of the techniques used to insure product excellenceare the following:• Product Reliability starts at the initial design inception.It is built into every product design from the very start.• Product Quality is built into every step of the manufacturingprocess through stringent inspections of incomingmaterials and conformance checks after critical processsteps.• Stringent inspections and reliability conformancechecks are done on finished product to insure the finishedproduct quality requirements are met.• Field data test results are encouraged and tracked sothat accelerated testing can be correlated to actual useexperiences.Product Assurance DocumentsCypress Semiconductor uses MIL-STD-883C and MIL-M-38510F as baseline documents to determine our Test Methods,Procedures and General Specifications for semiconductors.Customers using our Commercial grade product receivethe benefit of a military patterned process flow at no additionalcharge.Product Testing CategoriesFour different testing categories are offered by Cypress:1) Commercial operating range product: O°C to + 70°C.2) Military Grade product processed to MIL-STD-883C;Military operating range: - 55°C to + 125°C.3) SMD (Standard Military Drawing) certified product;Military operating range: - 55°C to + 125°C, electricallytested per the applicable Military Drawing.4) JAN qualified product; Military operating range:- 55°C to + 125°C, electrically tested per MIL-M-38510 slash sheet requirements.Category 1 and 2 are available on all products offered byCypress Semiconductor. Category 3 and 4 are offered on amore limited basis, dependent upon the specific part typein question.Commercial Product Assurance CategoriesCommercial grade devices are offered with two differentclasses of product assurance. Every device shipped, as aminimum, meets the processing and screening requirementsof level 1.Levell: For commercial or industrial systems where thedemand for quality and reliability is high, butwhere field service and device replacement can bereasonably accomplished.Level 2: For enhanced reliability applications and commercialor industrial systems where maintenance isdifficult and/or expensive and reliability is paramount.Devices are upgraded from Level 1 to Level 2 byadditional testing and a burn-in to MIL-STD-883,Method 1015.Table 1 lists the 100% screening and quality conformancetesting performed by Cypress Semiconductor in order tomeet the requirements of these programs.Military Product Assurance CategoriesOnly one standard product assurance category exists forJAN, SMD and Military grade products. Cypress' militarygrade devices are processed per MIL-STD-883C usingmethods 5004 and 5005 to define our screening and qualityconformance procedures. The processing performed byCypress results in a product that meets the class B screeningrequirements as called out by these methods. Everydevice shipped, as a minimum, meets these requirements.JAN, SMD and Military grade devices supplied by Cypressare processed for applications where maintainance is difficultor expensive and reliability is paramount. Tables 2through 6 list the screening and quality conformance testingthat is performed in order to meet the processing requirementsrequired by MIL-STD-883C and MIL-M-38510.9-1

~ Quality, Reliability and Process Flows~~~~UcrOR=======================================================================Table 1. Cypress Commercial Product Screening FlowsScreenMIL-STD-883 MethodVisuallMechanical• Internal Visual 2010• High Temperature Storage 1008, Cond C• Temperature Cycle 1010, CondC• Constant Acceleration 2001, Cond E,YlOrientation• Hermeticity Check: 1014, Cond A & B; Fine LeakFine/Gross Leak Cond C; Gross LeakBurn-in• Pre-Burn-in Electrical Per Device Specification• Bum-in 1015• Post-Burn-In Electrical Per Device Specification• Percent DefectiveAllowable (PDA)Final Electrical• Functional, Switching,Dynamic (AC) andStatic (DC) TestsPer Device Specification1) At 25°C and PowerSupply Extremes2) At Hot Temperature andPower Supply ExtremesCypress QualityLot Acceptance• External Visual 2009• Final Electrical Cypress Method 17-00064Conformance• Fine & Gross Leak 1014, Cond A & B; Fine LeakConformanceCond C; Gross LeakNotes:1) Electrical Test is performed after burn-in. Results of this are used todetermine PDA percentage.2) Burn-in is performed as a standard for 12 hours at 150°C.Product Temperature RangesCommercial O°C to + 70°CLevell Level 2Plastic Hermetic Plastic Hermetic0.4%AQL 100% 0.4%AQL 100%Not Performed 100% Not Performed 100%Not Performed Not Performed Not Performed Not PerformedDoes Not Apply Not Performed Does Not Apply Not PerformedDoes Not ApplyLTPD = 5;LTPD = 5;Does Not Apply77(1,2) 77(1,2)Does Not Apply Does Not Apply 100% 100%Does Not Apply Does Not Apply 100%[2] 100%[2]Does Not Apply Does Not Apply 100% 100%Does Not Apply Does Not Apply 5% (max)[l] 5% (max)[1]Not Performed Not Performed 100%[11 100%[1]100% 100% 100% 100%[3] [3] [3] [3][3] [3] [3] [3]Does Not ApplyLTPD = 5;LTPD = 5;Does Not Apply77(1,2) 77(1,2)3) Lot acceptance testing is performed on every lot to guarantee 200PPM average outgoing quality.9-2

~ Quality, Reliability and Process Flows~~~NDU~~~~~~~~~~~~~~~~~~~~~~~~~~==~~~~~~~==~~Table 2. Cypress JAN/SMD/Military Product Screening FlowsScreening PerProduct Temperature Range: - SSOC to + 12S0CScreen Method 5004 of SMDlMilitaryMIL-STD-883CJANProductVisuallMechanical• Internal Visual Method 2010, Cond B 100% 100%• Stabilization BakeMethod 1008, 24 Hrs(No End Pt. Electricals) Cond C, Minimum100% 100%• Temperature Cycling Method 1010, Cond C 100% 100%• Constant Acceleration Method 2001, Cond E (Min),Y 1 Orientation Only100% 100%• Hermeticity-Fine Leak Method 1014, Cond A & B 100% 100%-Gross Leak Method 1014, Cond C 100% 100%Bum-in• Initial (Pre-Bum-in)Per Applicable DeviceElectrical ParametersSpecification100% 100%• Burn-in TestMethod 1015, 160 Hrsat 125°C Min or 100% 100%80 hours at 150°C• Interim (Post-Bum-in) Per Applicable DeviceElectrical Parameters,SpecificationPercent DefectiveMaximum PDA, for100% 100%Allowable (PDA) All Lots, 5%Final Electrical Tests• Static Tests Method 5005, Table 1, 100% Test to 100% Test toSubgroups 1, 2 and 3 Slash Sheet Applicable DeviceSpecification• Dynamic and Switching Method 5005, Table 1, 100% Test to 100% Test toTests Subgroups 4, 5, 6, 9, Slash Sheet Applicable Device10 and 11 Specification• Functional Tests Method 5005, Table 1, 100% Test to 100% Test toSubgroups 7 and 8 Slash Sheet Applicable DeviceSpecificationQuality Conformance Tests• Group A Method 5005, See Sample Sample• GroupB Table 3-6 for Sample Sample• GroupC Details Sample Sample• GroupD Sample Sample9-3

~ Quality, Reliability and Process Flows~~~U~==========================~~~~~~~~~~~~~====~~~~==Table 3. Group A Test DescriptionsCypress uses an LTPD sampling plan that was developedby the Military to assure product quality. Testing is performedto the subgroups found to be appropriate for theparticular device type. All Military products have a GroupA sample test performed as outlined by the particularscreen flow.Subgroup Description LTPDSample Size/Accept No.1 Static Tests at 25°C 2 195/12 Static Tests at Maximum 3 129/1Rated Operating Temperature3 Static Tests at Minimum 5 77/1Rated Operating Temperature4 Dynamic Tests at 25°C 2 195/15 Dynamic Tests at Maximum 3 129/1Rated Operating Temperature6 Dynamic Tests at Minimum 5 77/1Rated Operating Temperature7 Functional Tests at 25°C 2 195/18 Functional Tests at Minimum 5 77/1and Maximum Temperatures9 Switching Tests at 25°C 2 195/110 Switching Tests at 3 129/1Maximum Temperature11 Switching Tests at 5 77/1Minimum TemperatureSubgroupTable 4. Group B Quality TestsDescriptionQuantity/Accept #orLTPD1 Physical Dimensions, 2/0Method 20162 Resistance to Solvents, 4/0Method 20153 Solderability, Method 2003 104 Internal VisuallMechanical, 1/0Method 20145 Bond Strength, Method 2011 156 Internal Water Vapor,[2] 3/0 or 5/1Method 10187 Seal: Fine & Gross Leak,[l] 5Method 10148 ESD Characteristics, [3] 15/0Method 3015Notes:1) Fine and Gross Leak is not performed because a 100% screen isemployed.2) Test is only performed if a package contains a dessicant.3) Test is performed only at qualification and upon redesign.Group B testing is performed for each inspection lot. Aninspection lot is defined as a group of material of the samedevice type, package type and lead finish built within a sixweek seal period and submitted to Group B testing at thesame time.9-4Table 5. Group C Quality TestsSubgroup Description LTPD1 Steady State Life Test, End 5Point Electricals, Method 10052 Temp Cycle, Constant 15Acceleration Seal: Fine & GrossLeaks, Visual Examination, EndPoint Electricals Methods 1010,2001, 1014Group C tests for JAN product are performed on one devicetype from one inspection lot representing each technology.Sample tests are performed per MIL-M-38510from each three months production of devices, which isbased upon the lot inspection identification (or date) codes.Group C tests for SMD and Military products are performedon one device type from one inspection lot representingeach technology. Sample tests are performed perMIL-STD-883 from each twelve months production of devices,which is based upon the lot inspection identification(or date) codes.End-point electrical tests and parameters are performedper detailed device specification.Table 6. Group D Quality Tests (Package Related)SubgroupDescriptionQuantity/Accept #orLTPD1 Physical Dimensions, Method 1520162 Lead Integrity, Seal: Fine & 15Gross Leak, Methods 2004 &10143 Thermal Shock, Temp 15Cycling, Moisture Resistance,Seal: Fine & Gross Leak,Visual Examination, End-Point Electricals, Methods1011, 1010, 1004 & 10144 Mechanical Shock, Vibration - 15Variable Frequency, ConstantAcceleration, Seal: Fine &Gross Leak, VisualExamination, End-PointElectricals, Methods 2002,2007, 2001 & 10145 Salt Atmosphere, Seal: Fine & 15Gross Leak, Visual Examination,Methods 1009 & 10146 Internal Water-Vapor 3/0 or 5/1Content; 500 ppm maximum@ 100°C. Method 10187 Adhesion of Lead Finish,[4] 15Method 20258 Lid Torque, Method 2024[5] 5/0Notes:4) Does not apply to leadless chip carriers.5) Applies only to packages with glass seals.

~ Quality, Reliability and Process Flows~~~UCTOR ==~~~~~~~~~~~~~~~~~==~======~====~===============Military Product• Product processed per MIL-STD-883C, method 5004product test flowsGroup D tests for JAN product are performed per MIL­M-38510 on each package type from each six months ofproduction, based on the lot inspection identification (ordate) codes.Group D tests for SMD and Military product are performedper MIL-STD-883 on each package type from eachtwelve months of production, based on the lot inspectionidentification (or date) codes.End-point electrical tests and parameters are performedper detailed device specification.Product Screening SummaryCommercial Product• Screened to either Level 1 or Level 2 product assuranceflows• Hermetic and Molded packages available• Incoming Mechanical and Electrical performance guaranteed:- 0.1 % AQL Electrical Sample test performed on everylot prior to shipment- 0.65% AQL External Visual Sample inspection• Electrically tested to Cypress datasheetOrdering InformationProduct Assurance Grade: Level 1• Order Standard Cypress part number• Parts marked the same as ordered part numberEx: CY7C122-15PCProduct Assurance Grade: Level 2• Burn-in performed on all devices to Cypress detailed circuitspecification• Add "B" Suffix to Cypress standard part number whenordering to designate Burn-in option• Parts marked the same as ordered part numberEx: CY7C122-15PCB• Military grade devices electrically tested to Cypress datasheetspecifications• SMD (Standard Military Drawing) devices electricallytested to military drawing specificationsOR• JAN devices electrically tested to slash sheet specifications• All devices supplied in Hermetic packages• Quality conformance assured: Method 5005, Groups A,B, C and D performed as part of the standard processflow• Burn-in performed on all devices- Cypress detailed circuit specification for non-JAN devicesOR- Slash sheet requirements for JAN products• AC, DC, Functionally and Dynamically tested at 25°Cas well as temperature and power supply extremes on100% of the product in every lot• JAN product manufactured in a DESC certified facilityOrdering InformationJAN Product:• Order per Military document• Marked per Military documentEx: JM38510/28901BVASMD Product:• Order per Military document• Marked per Military documentEx: 5962-868460lEAMilitary Grade Product:• Order per Cypress standard Military part number• Marked the same as ordered part numberl!x: CY7C122-25DMB9-5

~ . Quality, Reliability and Process Flows~~~~~================================~==============~==============~AREA PROCESS... PROCESS DETAILSProduct Quality Assurance FlowQCINCOMING MATERIALSINSPECTIONALL INCOMING MATERIALS ARE INSPECTED TO DOCUMENTED PROCEDURES COVERINGTHE HANDLING, INSPECTION, STORAGE, AND RELEASE OF RAW MATERIALS USED INTHE MANUFACTURE OF CYPRESS PRODUCTS. MATERIALS INSPECTED ARE: WAFERS,MASKS, LEADFRAMES, CERAMIC PACKAGES AND/OR PIECE PARTS, MOLDINGCOMPOUNDS, GASES, CHEMICALS, ETC.FABDIFFUSION / IONIMPLANTATIONSHEET RESISTANCE, IMPLANT DOSE, SPECIES AND CV CHARACTERISTICS AREMEASURED FOR ALL CRITICAL IMPLANTS AND ON EVERY PRODUCT RUN. TESTWAFERS MAY BE USED TO COLLECT THIS DATA INSTEAD OF ACTUAL PRODUCTIONWAFERS. IF THIS IS DONE, THEY ARE PROCESSED WITH THE STANDARD PRODUCTPRIOR TO COLLECTING SPECIFIC DATA. THIS ASSURES ACCURATE CORRELATIONBETWEEN THE ACTUAL PRODUCT AND THE WAFERS USED TO MONITOR IMPLANTATION.FABOXIDATIONSAMPLE WAFERS AND SAMPLE SITES ARE INSPECTED ON EACH RUN FROM VARIOUSPOSITIONS OF THE FURNACE LOAD TO INSPECT FOR OXIDE THICKNESS. AUTOMATEDEQUIPMENT IS USED TO MONITOR PIN HOLE COUNTS FOR VARIOUS OXIDATIONS INTHE PROCESS. IN ADDITION, AN APPEARANCE INSPECTION IS PERFORMED BY THEOPERATOR TO FURTHER MONITOR THE OXIDATION PROCESS.FAB PHOTOLITHOGRAPHY /ETCHINGAPPEARANCE OF RESIST IS CHECKED BY THE OPERATOR AFTER THE SPIN OPERATION.ALSO, AFTER THE FILM IS DEVELOPED, BOTH DIMENSIONS AND APPEARANCE ARECHECKED BY THE OPERATOR ON A SAMPLE OF WAFERS AND LOCATIONS UPON EACHWAFER. FINAL CD'S AND ALIGNMENT ARE ALSO SAMPLE INSPECTED ON SEVERALWAFERS AND SITES ON EACH WAFER ON EVERY PRODUCT RUN.FABMETALIZATIONFILM THICKNESS IS MONITORED ON EVERY RUN. STEP COVERAGE CROSS-SECTIONSARE PERFORMED ON A PERIODIC BASIS TO INSURE COVERAGE.FABFABPASSIVATIONQC VISUAL OFWAFERSAN OUTGOING VISUAL INSPECTION IS PERFORMED ON 100% OF THE WAFERS IN ALOT TO INSPECT FOR SCRATCHES, PARTICLES, BUBBLES, ETC. FILM THICKNESS ISVERIFIED ON A SAMPLE OF WAFERS AND LOCATIONS WITHIN EACH GIVEN WAFER ONEACH RUN. PINHOLES ARE MONITORED ON A SAMPLE BASIS WEEKLY.FABE-TESTSAMPLE ELECTRICAL TEST IS PERFORMED FOR FINAL PROCESS ELECTRICALCHARACTERISITICS ON EVERY RUN.FABQC MONITOR OFE-TEST DATAWEEKLY REVIEW OF ALL DATA TRENDS; RUNNING AVERAGES, MINIMUMS,MAXIMUMS, ETC. ARE REVIEWED WITH PROCESS CONTROL MANAGERTESTWAFER PROBE/SORTVERIFY FUNCTIONALITY, ELECTRICALCHARACTERISTICS, STRESS TEST DEVICESTEST QC CHECK PASS / FAIL LOT BASED ON YIELD,PROBING ANDCORRECT PROBE PLACEMENTELECTRICAL TESTRESULTSTO ASSEMBLYAND TEST(Continued)0032-19-6

~ Quality, Reliability and Process Flows~~~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=========Product Quality Assurance Flow (Continued)PLASTICASSEMBLYFLOWHERMETICASSEMBLYFLOWWAFER PREP / MOUNT / SAWINSPECT FOR ACCURATE SAWING OFSCRIBELINE AND 100% SAW THRUPERIODIC QC MONITOR - WAFER SAWPERFORM MONITOR OF MOUNTING, SAWINGAND POST SAW CLEAN OPERATIONSDIE VISUAL INSPECTIONINSPECT DIE PER CYPRESS EQUIVALENT TOMIL-STD-883, METHOD 2010QC VISUAL LOT ACCEPTANCESAMPLE INSPECT DIE; 1.0% AQLDIE ATIACHATIACH PER CYPRESS DETAILED SPECIFICATIONQC PROCESS MONITORINSPECT FOR DIE POSITION, QUALITY ANDUNIFORMITY OF DIE ATIACH AND ATIACHMENTSTRENGTH, MIL-STD-883, METHOD 2010, CRITERIAWIRE BONDBOND PER CYPRESS DETAILED SPECIFICATIONQC PROCESS MONITOR -MONITOR BOND STRENGTH ANDFAILURE MODEINTERNAL VISUAL INSPECTIONWIRE BONDINGLOW POWER (30X) INSPECTION OF WORKMANSHIPMIL-STD-883, METHOD 2010, CRITERIAQC LOT ACCEPTANCESAMPLE INSPECT LOT TO VERIFY WORKMANSHIP,MIL-STD-883, METHOD 2010, CRITERIA; 0.4% AQLDIE COATCOATING APPLIED TO SELECTED PRODUCTSMOLD / ENCAPSULATE PLASTIC DEVICESSEAL HERMETIC DEVICESPERIODIC QC MONITOR, LID-TORQUESHEAR STRENGTH OF GLASS-FRITSEAL TESTED TO MIL-STD-883, METHOD 2024(Continued)0032-29-7

~ Quality, Reliability and Process Flows~~~U~ ==============================================================Product Quality Assurance Flow (Continued)POST ... OLD CUREPER CYPRESS ... ETHODFOR ... OLDING CO ... POUNDSTABILIZATION BAKE... ETHOD 1008, COND CTE ... PERATURE CYCLE(1)... ETHOD 1010, COND CCENTRIFUGE( 1 )... ETHOD 2001, COND E, Y1 ORIENTATIONLEAD TRI ... / FOR ...FINE AND GROSS LEAK TESr

~ Quality, Reliability and Process Flows~~~NDUcroR ==============================~====~==========================~Product Quality Assurance Flow (Continued)OPTIONAL BURNIN PROCESSING FOR LEVEL 2(STANDARD FOR JAN/MILITARY DEVICES)o PRE - BURNIN ELECTRICAL TESTooIIIBURNIN: METHOD 1015oIIIoIIIIQC MONITOR - BURNIN DOCUMENTS/RESULTSoIIoIIIINTERIM (POST-BURN IN) ELECTRICALSoIIII PER APPLICABLE DEVICE SPECIFICATIONIIIIIIIk>IIQC INSPECTIONPDA VERIFIED WITHIN LIMITS ~IIIFINAL ELECTRICAL TEST100% TEST LOT; DC, AC, FUNCTIONAL AND DYNAMICTESTS PERFORMED PER APPLICABLE DEVICE SPECIFICATIONFINAL DEVICE MARKING:.FINAL VISUAL INSPECTIONINSPECT FOR BENT LEADS, MARKING,SOLDER COVERAGE, ETC.I QC LOT ACCEPTANCE IVIS L SAMPLE INSPECTIONMETHOD 2009 -0.65% AQLELECTRICAL SAMPLE TF'STTO GUARANTEE 200 PPMINSPECTION - PRE-SHIPMENTCONFIRM PART TYPE, COUNT, PACKAGE, CHECKFOR COMPLETENESS OF PROCESSINGREQUIREMENTS, CONFIRM SUPPORTINGDOCUMENTATION IS SENT, IF REQUIREDPACK/SHIP ORDERKey0032-4o PRODUCTION PROCESSo TEST / INSPECTIONIQ) PRODUCTION PROCESS AND TEST INSPECTIONo QC SAMPLE GATE AND INSPECTION0032-5Notes:1. Temp Cycle and Centrifuge performed per Applicable Product Screening Flow.2. JAN/SMD/Military grade products are 100% Fine and Gross Leak tested and sample tested after wafer lot I.D. Commercial grade devicesreceived sample test only. Sample size is per Commercial Product Screening Flow.9-9

~ Quality, Reliability and Process Flows~~~NDU~ ==========================================~==~====~============~Reliability Monitor ProgramThe Reliability Monitor Program is a documented Cypressprocedure that is described in Cypress specification# 25-00008 which is available to Cypress customers uponrequest. This specification describes a procedure that providesfor periodic reliability monitors to insure that allCypress products comply with established goals for reliabilityimprovement and to minimize reliability risks forReliability Monitor Program Sampling PlanTest DescriptionEarly Failure Rate (EFR)150°CHTOLHigh Temp Steady State Life (HTSSL)150°C HTOL with DeltasLatent Failure Rate (LFR)150°CHTOLHigh Temp Storage (HTS)200°CHTSEpoxy Packaged Data Retention165°C BakeHermetic Packaged Data Retention250°C BakePressure Cooker (PCT)121°C/l00% R.H.DurationCypress customers. The Reliability Monitor Program is designedto monitor key products within each generic processfamily. This procedure requires that detailed failure analysisbe performed on all test rejects and the corrective actionsbe taken as indicated by the analysis. A summary ofthe Reliability Monitor Program test and sampling plan isshown below.SampleSizeFrequency [1]12 Hours 125 Weekly1000 Hours 10 Monthly1000 Hours 125 Quarterly1000 Hours 10 Monthly168 Hours 55 Weekly500 Hours 55 Monthly288 Hours 55 WeeklyPreconditioned Temperature Humidity Life (PCTH) 1000 Hours 55 Every 6 Weeks96 Hrs. PCT + Biased 85/85Extended Temperature Cycle (TIC)-65°C to + 150°C1000 Cycles 55 QuarterlyNote:1) Maximum period between samples is listed. More frequent sampling may occur.9-10

PRODUCTINFORMATIONSTATIC RAMS ,.PROMSLOGICRISCBRIDGEMOSQUICKPRO•EPLDS ,~.•QUALITY AND,.RELIABILITY~ ,~ APPLICATION BRIEFS BPACKAGES

~ Section Contents~~~ucr~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Application BriefsPage NumberRAM Input and Output Characteristics .................................................................... 10-174F189 Application Brief ................................................................................ 10-8Programmable Logic Device Application Brief ............................................................. 10-10PAL C 16R6 GCR Encoder/Decoder .................................................................... 10-22Understanding FIFOs ................................................................................. 10-39Interfacing to the FIFOs ............................................................................... 10-51Power Characteristics of Cypress Products ................................................................ 10-53System Design Considerations when Using Cypress CMOS Circuits ............................................ 10-60Microcoded Systems Application Brief .................................................................... 10-78Introduction to Diagnostic PROMs ...................................................................... 10-81CY7C330 Asynchronous SCSI Controller ................................................................. 10-87

Application BriefsRAM Input Output CharacteristicsIntroduction to Cypress RAMsCypress Semiconductor Corporation uses a speed optimizedCMOS technology to manufacture high speed staticRAMs which meet and exceed the performance of competitivebipolar devices while consuming significantly lesspower and providing superior reliability characteristics.While providing identical functionality, these devices exhibitslightly differing input and output characteristicswhich provide the designer opportunities to improve overallsystem performance. The balance of this applicationnote describes the devices, their functionality and specificallytheir I/O characteristics .PRODUCT DESCRIPTIONThe five parts in Figure 1 constitute three basic devices of64, 1024 and 4096 bits respectively. The 7C189 and 7C190feature inverting and non-inverting outputs respectively ina 16 x 4 bit organization. Four address lines address the 16words, which are written to and read from over separateinput and output lines. Both of these 64 bit devices haveseparate active LOW select and write enable signals. The256 x 4 7C122 is packaged in a 22 pin DIP, and featuresseparate input and output lines, both active LOW and activeHIGH select lines, eight address lines, an active LOWoutput enable, and an active LOW write enable. Both the.---------

~ RAM Input/OutputCharacteristics~~~NDUcroR =====================================================================Ag' 1/00AaA7I/O,A6AS1/02A41/03es0027-37C122 7C148/97C148 and 7C149 are organized 1024 x 4 bits and featurecommon pins for the input and output of data. Both partshave 10 address lines, a single active LOW chip select andan active LOW write enable. The 7C148 features automaticpower down whenever the device is not selected, while the7C149 has a high speed, 15 ns, chip select for applicationswhich do not require power control. This family of highspeed static RAMs is available with access times of 15 to45 ns with power in the 300 to 500 m W range. They aredesigned from a common core approach, and share thesame memory cell, input structures and many other characteristics.The outputs are similar, with the exception ofoutput drive, and the common I/O optimization for the7C148 and 7C149. For more detailed information on theseproducts, refer to the available data sheets.GENERIC I/O CHARACTERISTICSInput and output characteristics fall generally into two categories,when the area of operation falls within the normallimits of' Vee and V ss plus or minus approximately600 mY, and abnornial circumstances, when these limitsare exceeded. Inputs under normal operating conditionsare voltages that switch between logic "0" and logic "1".We will consider operation in a positive true environmentand therefore a logic" 1" is more positive than a logic "0".The I/O characteristics of the devices we are concernedwith are what is considered to be TTL compatible. Thereforea logic "I" is 2.0V, while a logic "0" is 0.8V. Theinput of a device must be driven greater than 2.0V, not toexceed Vee + 0.6V to be considered a logic "I" and, toless than 0.8V, but not less than Vss - 0.6V, to be considereda logic "0".Output characteristics represent a signal that will drive theinput of the next device in the system. Since the levels weare dealing with are TTL, we may assume that the VIL andFigure 1. RAM Block Diagrams (Continued)WE0027-4VIH values of 0.8 and 2.0V referenced above are valid. Inconsideration of noise margin however, driving the input ofthe next stage to the required VIL or VIH is not sufficient.Noise margins of 200 to 400 m V are considered more thanadequate, and therefore the VOH we deal with is 2.4V whilethe VOL is O.4V, providing a noise margin of 400 mY.Since the driven node consists of both a resistive and acapacitive component, output characteristics are specifiedsuch that the output driver is capable of sinking 10L at thespecified VOL, and capable of sourcing 10H at VOH. Sincethe values of 10L and 10H differ depending on the device,these values are shown in Table 1. Outputs have one othercharacteristic that we need to be concerned with, OutputShort Circuit Current or los. This is the maximum currentthat the output will source when driving a logic "I" intoV ss. We need to be concerned for two reasons. First, theoutput should be capable of supplying this current for somereasonable period of time without damage, and second, thisis the current that charges the capacitive load when switchingthe output from a "0" to a "1" and will control theoutput rise time.Since memories such as these are often tied together, weare also concerned about the output characteristics of thedevices when they are deselected. All of the devices in thisfamily feature three state outputs such that in addition totheir active conditions when selected, when deselected, theoutputs are in a high impedance condition which does notsource or sink any current. In this condition, as long as theinput is driven in its normal operating mode, it appears asan open, with less than 10 J-LA of leakage. Thus to anyother device driving this node, it is non-existent.10-2

~ RAM Input/Output Characteristics~~~UcrOR==================================================================TECHNOLOGY DEPENDENCIES ANDBENEFITSSome of the products in this application note were originallyproduced in a BIPOLAR technology, some have sincebeen re-engineered in NMOS technology and Cypress hasnow produced them in a speed optimized CMOS technology.There are both technology dependencies and benefitsrelative to the design of input and output structures thatare associated with each technology. The designer whouses these products should be knowledgeable of these characteristicsand how they can benefit or impede a designeffort. One of the most obvious is that both NMOS andCMOS device inputs are high impedance, with less than 10/-LA of input leakage. Bipolar devices, however, require thatthe driver of an input sink current when driving to VIL, butappear as high impedance at VIH levels. This is due to thefact that the input of a bipolar device is the emitter of abipolar NPN type device with its base biased positive. Thebias is what establishes the point at which the input changesfrom requiring current to be sourced to high impedanceand is 1.5V. This switching level is the reason that ACmeasurements are done at the 1.5V level. Although NMOSand CMOS device inputs do not change from low to highimpedance, great care is taken to balance their switchingthreshold at 1.5V. To a system designer this allows fanoutto consider only capacitive loading with MOS deviceswhile bipolar has both a capacitive and DC component.The other input characteristic which differs from bipolar toMOS is the clamp diode structure. This structure exists inboth MOS and bipolar, however in MOS that uses BIASGENERATOR techniques, all high speed MOS devices,the diode does not become forward biased until the inputgoes more negative than the substrate bias generator plusone diode drop. Since the bias generator is usually about- 3V this has the effect of removing the clamping effect.I/O ParametersCMOS/NMOS/BIPOLAR INPUTCHARACTERISTICSAlthough NMOS, CMOS and BIPOLAR technologies differwidely, the I/O characteristics tend to fall into twoareas. The traditional characteristics are the TTL derivativesthat have been covered above, and are documented inTable 1. With the exception of the differences in input impedancebetween MOS and BIPOLAR devices all threetechnologies are used to produce TTL compatible products.The second camp is the true CMOS interface wheresignals swing from V ss to Vee. These interface specificationsdefine a "1" as greater than Vee - 1.5V and a "0" asless than Vss + 1.5V. In addition, loads are primarilycapacitive. Only devices produced in a CMOS technologyare capable of behaving in this manner. CMOS devices can,however, handle both TTL and CMOS inputs. Devicessuch as the ones described in this application note haveinput characteristics depicted in Figure 2.«EI(.)~3.53.02.52.01.51.00.5o0.0Table 1. DC ParametersParameters Description Test Conditions/r ----- -~/ \/ _\I{~\."1.0 2.0 3.0 4.0 5.0 6.0INPUT VOLTAGE-VFigure 2. Input Voltage vs. Current7C122 7C148/9 7C189/90Min. Max. Min. Max. Min. Max.VOH Output High Voltage Vee = Min., IOH = - 5.2 rnA 2.4 2.4 2.4 VVOL Output Low Voltage Vee = Min., IOL = 8.0 rnA 0.4 0.4 0.4 VVIH Input High Voltage 2.1 Vee 2.0 Vee 2.0 Vee VVIL Input Low Voltage -3.0 0.8 -3.0 0.8 -3.0 0.8 VIlL Input Low Current Vee = Max., VIN = Vss 10 10 10 p,A,IIH Input High Current Vee = Max., VIN = Vee 10 10 10 /-LAIOFF Output Current (High Z) VOL < VOUT < VOH, TA = Max. -10 +10 -10 + 10 -10 +10 p,AlosOutput Short Vee = Max.,O°C < TA < 70°C -70 -90 -275 rnACircuit Current VOUT = Vss, -55°C < TA < 125°C -80 -90 -350 rnA0027-5Units10-3

~ RAM Input/Output Characteristics~~~~UcrOR ==================================================================~When operated in the TTL range, they perform normally.Operated in full CMOS mode, an additional benefit ofpower savings is realized as the current consumed in theinput converter decreases as the input voltage rises above3.0V, or falls below 1.5V. Since the input signal is in the 1.5to 3.0V range only when transitioning between logic states,the power savings in a large array with true CMOS inputscan be significant. With input signals on over half of thepins of a device, significant savings in a large system can berealized by using CMOS input voltage swings even in TTLsystems.Switching CharacteristicsAlthough this application note does not directly deal withthe AC characteristics of high speed RAMs, the input andoutput characteristics of these devices have a great deal todo with the actual AC specifications. Conventionally, allAC measurements associated with high speed devices aredone at 1.5V and assume a maximum rise and fall time.This eliminates the variations associated with the variousconfigurations that the device will be used in (as a figure ofmerit when testing the device) but, does not mean that thedesigner can ignore these influences when designing a system.Maximum rise and fall time is usually found in thenotes included on every data sheet. For the products referredto in this application note, a 10 ns maximum riseand fall time is specified for all devices with access timesequal to or greater than 25 ns and a 5 ns maximum rise andfall time for all devices with access times less than 25 ns.The AC load and its Thevenin equivalent in Figure 3 representthe resistive and capacitive components of load whichthe devices are specified to drive. With either of theseloads, the device will be required to source or sink its ratedoutput current at its specified output voltage. The capacitancestresses the ability of the device output to source orsink sufficient current to slew the outputs at a high enoughrate to meet the AC specifications. The high impedanceload is a convenience to testing when trying to determinehow rapidly the output enters a high impedance condition.Once the output enters a high impedance mode, the resistivedivider will charge the capacitance until equilibrium isreached. Allowing for noise margin, testing for a 500 m Vchange is normal. By using a smaller capacitancethan normal, the change will occur more quickly, allowinga more accurate determination of entry into the high impedancestate.SWITCHING THRESHOLD VARIATIONSSwitching threshold variations along with input rise andfall times can have an effect on the performance of anydevice. Input rise and fall times are under the control of thedesigner, and are primarily affected by capacitive loading,the driver and bus termination techniques. Switchingthreshold is affected by process variations, changes in Veeand temperature. Compensation of these variables is theterritory of the manufacturer, both at the design stage andthe manufacturing of the device. Combined threshold shiftsover full military temperature ranges and process variationsaverage less than 100 mY. This translates directly toVIL and VIH variations which track well within the noisemargins of normal system design particularly since theVOL and VOH changes track to the same 100 mY.Input Protection MechanismsTHE ELECTROSTATIC DISCHARGEPHENOMENONBecause of their extremely high input impedance and relativelylow (approximately 30V) breakdown voltage, MOSdevices have always suffered from destruction caused byESD (Electro Static Discharge). This has caused two actions.First, major efforts to design input protection circuitswithout impeding performance has resulted in MOS devicesthat are now superior to bipolar devices. Second, carein handling semiconductors is now common practice. Interestinglyenough, bipolar products that once did not sufferfrom ESD have now suddenly become sensitive to thephenomenon, primarily because new processing technologyinvolving shallow junctions is in itself sensitive. MOS devicesare in many cases now superior to bipolar products.A sampling of competitive BIPOLAR and NMOS 64 bit,1K bit and 4K bit products reveals breakdown voltages aslow as ± 150V to greater than ±2oo1V magnitudes. Thecircuit in Figure 4 is used to protect Cypress productsagainst ESD. It consists of two thick oxide field transistorswrapped around an input resistor and a thin oxide deviceACLoadHigh Impedance LoadR1470nOUTPUT 0-----..--------...I~P'R2224nThevenin Equivalent152 nOUTPUT ~1.62V0027-7R1470n5V~-------JVV~~OUTPUT 0-----...... -----'1t"R2224n0027-6 0027-8Figure 3. Test Loads10-4

~RFSSRAM Input/Output Characteristics~~~ONDUcrOR =====================================================================RpTTL TO~--+-------+-------~--~VV~---'-----------'--------------~~--~CMOSCONVERTERTHIN OXIDETRANSISTOR'Thick Oxide Field Transistor'·Substrate DiodeVSUBFigure 4. Input Protection Circuit0027-9with a relatively low breakdown voltage of approximately12V. Large input voltages cause the field transistors to turn)n discharging the ESD current harmlessly to ground. The:hin oxide transistor breaks down when the voltage acrosst exceeds the 12V level and it is protected from destruction'y the current limiting of Rp. The combination of these:wo structures provides ESD protection greater than~250V, the limit of the testing equipment available. In adiition,repeated applications of this stress do not cause aiegradation that could lead to eventual device failure as)bserved in functionally equivalent devices.CMOS Latchuprhe parasitic bipolar transistors shown in Figure 5 result inl built-in silicon controlled rectifier illustrated in Figure 6.Jnder normal circumstances the substrate resistor RSUB is:onnected to ground. Therefore, whenever the signal onhe pin goes below ground by one diode drop, current flowsfrom ground through RSUB forward biasing the lower transistorin the effective SCR. If this current is suffi~ient toturn on the transistor, the upper PNP transistor is forwardbiased, the SCR turns on and normally destroys the device.Several solutions are obvious, decreasing the substrate resistance,or adding a substrate bias generator are two. Thebias generator technique has several additional benefits,however, such as threshold voltage control which increasesdevice performance and is employed in all Cypress products,along with guard rings which effectively isolate inputand output structures from the core of the device and thuseffectively decrease the substrate resistance by short circuitingthe current paths. Latchup can potentially be inducedat either the inputs or outputs. In true CMOS outputstructures as discussed above, the output driver has aPMOS pullup which creates additional vertical bipolarPNP transistors compounding the latchup problem. Additonalisolation using the guard ring technique can be usedto solve this problem, at the expense of additional siliconOutput DriverCMOS Invertern-MOSPULL-DOWNn-MOSDEVICE / PULL-UP"n OUTPUT l..J DEVICEVeeOUTPUTINPUTn+ DIFFUSION AND p+ DIFFUSIONn- WELL GUARD RING GUARD RINGLATERAL npn BIPOLARTRANSISTORPARASITICRESISTANCE0027-10Figure 5. CMOS Cross Section and Parasitic Circuits10-5

~ RAM Input/Output Characteristics~~~~u~==================================================================VeeSubstrate Bias Generatorc~Figure 6. Parasitic SCR and Bias Generator0027-11area. Since all of the devices of concern here require TTLoutputs, the problem is totally eliminated through the useof an NMOS pullup.LATCHUP CHARACTERISTICSInducing Latchup for Testing PurposesCare needs to be exercised in testing for latchup since it isnormally a destructive phenomena. The normal method isto power the device under test with a supply that can becurrent limited, such that when latchup is induced, insufficientcurrent exists to destroy the device. Once this setupexists, driving the inputs or outputs with a current, andmeasuring the point at which the power supply collapseswill allow non-destructive measurement of the latchupcharacteristics of the devices under question. In actual testing,with the device under power, individual inputs andoutputs are driven positive and negative with a voltage andthe current measured at which the device latches up. Thisprovides the DC latchup data for each pin on the device asa function of trigger current.Measurement of Latchup SusceptibilityActually measuring the latchup characteristics of devicesshould encompass ranges of reasonable positive and negativecurrents for trigger sources. Depending on the device,latchup can occur as low as a few rnA to as high as severalhundred rnA of sink or source current. Devices which latchat trigger currents of less than 20 to 30 rnA are in danger ofencountering system conditions that will cause latchup failure.Competitive DevicesAlthough there are few devices directly competitive withthe Cypress devices covered in this application note, thelatchup characteristics of the closest functionally similardevices were measured. The results show devices thatlatchup at as low as 10 rnA all the way to devices that cansustain greater than 100 rnA of trigger current withoutlatchup. The Cypress devices covered in this document cansustain greater than 200 rnA without incurring latchup, farmore than is possible to encounter in any reasonable systemenvironment.Elimination of Latchup in CypressRAMsSince the latchup characteristic is one that inherently existsin any CMOS device, rather than change the laws of physics,we design to minimize its effects over the operatingenvironment that the device must endure. These includetemperature, power supply and signal levels as well as processvariations. There are several techniques employed toeliminate the latchup phenomenon. Two of them involvemoving the trigger threshold outside the operating range asto make it impossible to ever encounter it. These are eitherusing low impedance, epitaxial, substrates and/or a substratebias generator. The use of a low impedance substratehas the effect of increasing the undershoot voltage requiredto generate the required trigger current that causes latchup.A substrate bias generator has two effects which help toeliminate latchup. First, by biasing the substrate at a negative,- 3.0V, voltage, the parasitic diodes can not be forwardbiased unless the undershoot exceeds the - 3V by atleast one diode drop. Second, if undershoot is this severe,the impedance of the bias generator· itself is sufficient todeter sufficent trigger from being generated. The bias generatorhas one additional noticeable characteristic, it effectivelyremoves the input clamp diode. This is due to theanode of the diode connecting to the substrate which is at- 3.0V. Therefore, even though the diode exists as shownin Figure 4, DC signals of - 3.0V do not forward bias thediode and exhibit the clamp condition. The benefits of thisare apparent in higher noise tolerance as substrate currentsdue to input undershoot do not occur.101.00.1~I 0.01III.Ie0.00 10.000 10.00001-5.0 -4.0I ,IL~ ~ r----3.0 -2.0 -1.0VBB -vFigure 7. Bias Generator Characteristics0027-1210-6

~ RAM Input/Output Characteristics~~~U~==================================================================0.0-1.0~!-2.0~-3.0-4.0/IVeeIIII ,=S.OV-6.0 0.0 6.0 12.00.0-1.0iiiI- 0Z -2.0w!!!~! -3.0~-4.0-5.0Vee = S.OV-6.0 0.0 6.0 12.0VINPUT (VOLTS) 0027-13Figure 8. Input VII CharacteristicsFigures 8 and 9 represent the voltage and current characteristicsof the devices discussed in this application brief.Figure 8 is characteristic of an input pin, and Figure 9 anoutput pin in a high impedance state. In Figure 8, the inputcovers + 12V to - 6V, well outside the + 7V to - 3V specification.Referring to Figure 4 to understand these characteristics,when the input voltage goes negative, the thinoxide transistor acts as a forward biased diode and theVINPUT (VOLTS) 0027-14Note: Output is in a High Impedance Condition.Figure 9. Output V II Characteristicsslope of the curve is set by the value of Rp. As the inputvoltage goes positive, only leakage current flows. The outputcharacteristics in Figure 9 show the same phenomenon,with the exception that, since this is not an input, no protectioncircuit exists, and therefore no Rp exists. An equivalentthin film device acts as a clamp diode which limitsthe output voltage to approximately - 1 V at - 5 rnA.10-7

CYPRESSSEMICONDUCTOR74F189 Application BriefIntroductionThere are available in the market a number of high speed64 bit static RAMs organized 16 by 4 bits. Because of thevarious different manUfacturers specifications, there is noapparent true second source for these products as each operateswith some unique characteristics. The compositespecifications contained in this applications brief will allowthe interchangeable use of the Cypress CY7C189 with the74F189 and the Cypress CY7C190 with the 74F219 withoptimization for either power or performance.Electrical Characteristics Over the Operating RangeSpecificationsDepending on system requirements, the SPEED OPTI­MIZED specification will allow the designer to select performanceat the expense of power, and use either Cypress'sCY7C189-15 or the 74F189 interchangeably. If, however,the major criteria is power the designer can achieve a 55rnA max power specification using the Cypress CY7C189-25 interchangeably with the 74F189 by designing with thePOWER OPTIMIZED specification.SpeedPowerParameters Description Test Conditions Optimized Optimized UnitsMin. Max. Min. Max.VOH Output HIGH Voltage Vee = Min., IOH = - 3.0 mA 2.4 2.4 VVOL Output LOW Voltage Vee = Min.,IOL = 16.0mA 0.5 0.5 VVIR Input HIGH Voltage 2.0 Vee 2.0 Vee VVIL Input LOW Voltage -3.0 0.8 -3.0 0.8 VIIX Input Leakage Current GND~ VI ~ Vee -600 +20 -600 +20 p,Aloz Output Leakage Current GND ~ Vo ~ Vee -50 +50 -50 +50 p,AlosOutput ShortCircuit CurrentVee = Max., VOUT = GND -150 -150 mAIcePower Supply CurrentVee = Max., I Commercial 90 55 rnAlOUT = OmAI Military 70 mA10-8

~ 74F189 Application Brief~~~~u~ ==================================================================Switching Characteristics Over the Operating RangeParametersREAD CYCLEDescriptionSpeed OptimizedPower OptimizedMin. Max. Min. Max.tRC Read Cycle Time 27 27 nstACS Chip Select to Output Valid 14 15 nstHZCS Chip Select Inactive to High Z 12 15 nstLZCS Chip Select Active to Low Z 12 15 nstOHA Output Hold from Address Change 5 5 nstAA Address Access Time 27 27 nsWRITE CYCLEtwc Write Cycle Time 15 20 nstHZWE Write Enable Active to High Z 14 20 nstLZWE Write Enable Inactive to Low Z 12 20tAWE Write Enable to Output Valid 29 29 nstpwE Write Enable Pulse Width 15 20 nstSD Data Setup to Write End 15 20 nstHD Data Hold from Write End 0 0 nstSA Address Setup to Write Start 0 0 nstHA Address Hold from Write End 0 0 nstHCS Chip Select Hold from Write End 6 6 nsRead Cycle~Ioo---- tRC------+lj,ADt~E~---~~------f-tOH-A--------x:::e!CHIP SELECTUnitsWrite Cycle0043-1WCAo-A3ADDRESS~CHIP SELECT!sAt--t-}f-tHAII-- 'HcS 7tsotHOj00-0 3DATA IN~ftPWE~~WRITE ENABLE-' ~.,~00-03DATA OUTPUTSLOADIHZWE10-9I""!---tAWE--,IITT7fIJ. l\:~!.--tLZWE0043-2

CYPRESSSEMICONDUCTORProgrammable Logic DeviceApplication BriefScope and PurposeThe purpose of this application brief is to provide thereader with a basic understanding of Cypress CMOSProgrammable Logic Devices. This includes a descriptionof their architecture and design, the technology used intheir fabrication, how they are programmed and adiscussion of their reliability.This document will tell the reader how state-of-the-artCMOS technology and a unique architecture have beenincorporated in a family of PLD integrated circuits that arefunctionally equivalent, pin compatible, and superior inperformance to their bipolar counterparts.The appendix discusses and illustrates the designtechniques that Cypress uses on all products to eliminatelatchup and improve ESD (Electro-Static-Discharge)protection.IntroductionThe PLD is a Programmable Logic Device. The basic(functional) logic structure of a PLD is programmableAND array whose outputs feed into a fixed OR array. Thepertinent parameters are the number of inputs, the numberof outputs, the width (number of factors) in the ANDarray and the width (number of terms) in the OR array.The Boolean equation implemented is the sum-of-productsor minterm form.The first PLDs were strictly combinatorial logic. Theywere followed by devices that added latches (D flip-flops) aclock input, and internal feedback. For the first time aprogrammable, sequential, state machine could beimplemented in a single package. Three-state outputs, the"security fuse", flip-flop initialization, and in general terms"testability" are features that have been added forincreased flexibility.ApplicationsPLDs are used to replace SSI/MSI logic· and "glue chips"primarily to increase. packaging density. A single PLD isthe functional equivalent of many SSI ICs (in the 200-500equivalent gate range). When PLDs are used to replacestandard logic gates, the resulting reduction in PC cardarea, although application dependent, has been found tovary between 4 to 1 and 10 to 1. i.e., One PLD will replacebetween four and ten 14 pin ICs. Secondary benefits to theuser are reduced parts inventory, reduced power, higherreliability, faster design and turnaround time, productsecrecy and equal (matched) propagation delays throughthe AND OR array.ReliabilityReliability studies have shown that system reliability isinversely proportional to the number of interconnectionsbetween system elements. However, the failure rate formature ICs is about 0.1 % per thousand hours and hasremained constant during the last twenty years in spite ofthe fact that circuit complexity (density) has increased bymore than two orders of magnitude.The conclusion is that higher levels of IC integrationprovide increased system reliability. Thus the user isincreasing system reliability when Cypress CMOS PLDsreplace glue chips.ProgrammingPLDs must be programmed. This can be accomplished byeither designing and building a programmer or purchasingone for $1,000 to $to,OOO.Programming Bipolar PLDsBipolar PLDs use a fuse as the programmable element. Inan unprogrammed device all of the connections are"made" during the manufacturing process and theunwanted connections are later "unmade" by blowing fusesduring the programming process.Bipolar products are programmed using 20 Volt pulses ofdurations from 50 microseconds to 10 milliseconds duringwhich 100 to 300 milliamperes (mA) of current exist. Inorder to limit the heat generated during programming, theduty cycle for the programming pulses is limited to 20 to30 percent. One fuse is blown at a time so that the heatgenerated will neither permanently damage the IC norstress it to the point that it could fail later. Someprogramming algorithms take into account the physicallocations of the fuses and avoid sequentially blowing fusesthat are physically close to each other in order to preventexcessive localized heating of the chip. Because of the highcurrents required, bipolar products are not "gang"programmed, as are EPROMs.to-to

m~ Programmable Logic Device Application Brief~~~~UcrOR==================================================================Programming Cypress CMOS PLDsCypress PLDs are programmed by storing charge on thefloating gate of an EPROM transistor. Charge storage isaccomplished by hot carrier injection; a process that doesnot physically destroy material or heat the device. Duringprogramming, EPROM cells are stressed significantly lessthan fuses. In addition, every cell is programmed, testedand erased as part of the manufacturing process. This100% testing guarantees a very high programming yield tothe customer, which is impossible to guarantee with anyfuse programmable device.The storage mechanism is well understood. Products usingit have been in volume production for more than ten years.Reliability studies have been performed by manyindependent organizations and all have concluded that thetechnology is reliable.Cypress PLDs are programmed using high voltage pulsesof durations from 100 microseconds to 10 ms, duringwhich 50 milliamperes of programming current exist. Eightbits are programmed at the same time and, because of thelower currents required, gang programmers that canhandle 10 to 20 devices in parallel are possible.Before programming, AND gates or PRODUCT TERMSare connected via EPROM cells to both true andcomplement inputs. Programming an EPROM celldisconnects an input from a PRODUCT TERM. Selectiveprogramming of these cells enables a specific logic functionto be implemented. PLDs are supplied in a number offunctional configurations. These functional variations offerthe user the choice of combinatorial as well as registeredpaths to implement logic functions.CMOS TechnologyCypress PLDs are fabricated using an advanced "N-well"CMOS technology. The use of proven EPROM technologyto achieve memory non-volatility, combined with novelcircuit design and a unique architecture, provides the userwith a superior product in terms of performance,reliability, testability and programmability.PAL@ is a registered trademark of Monolithic Memories, Inc.Functional DescriptionGeneralThe variations of PLD functions available are listed inTable 1. The 16L8, which is used as an example (see Figure2), is purely combinatorial and consists of eight groups of7-input AND gates, each of which can have up to 32inputs. One of the AND gates of each group (of 8) is usedto enable the (inverting) output driver, so that 7 ANDgates (each of which may have 32 inputs) each feed one ORgate, whose output is inverted.The 16R8 is similar to the 16L8, except that the outputsare latched using D flip-flops (with a common clock), theinputs to the 8 OR gates are the outputs of 8 AND gates;the three-state output drivers are enabled by a commonenable input.The reader should refer to the PLD data sheets for a moredetailed description of the other members of the family.The 16R4, 16R6 and 16R8 have 4, 6, or 8 registeredoutputs with feedback.The 22VlO offers a unique macro-cell flexibility to allowany combination of up to 10 combinatorial or registeredoutputs. In a similar manner the 20G lOuses macro-cells toallow the user to program the functionality of the 10 mostpopular PAL ® 24 devices.Register PreloadThe preload function is used to load data into the internalregister (of registered devices) for testing purposes. Thissignificantly simplifies and shortens the testing procedure.Loading is accomplished by applying a supervoltage pulseof at least 100 microseconds duration to pin 5 as a writepulse while pin 11 is held at VIR and data is applied topins 12 through 19.Security FunctionThe security function prevents the contents of the regulararray from being electrically verified. This enables the userto safeguard proprietary logic. The EPROM technologyprevents the state of the cell from being visuallyascertained. The security function is implemented byprogramming an EPROM cell that disconnects the linesthat are used to verify the array. This cell has beendesigned to retain its charge longer than any of the othercells in the array.10-11

~ Programmable Logic Device Application Brief~~~UcrOR=====================================================================Commercial Selection GuideGenericOutput leemA tpDns tsns tconsPart Logic OutputsEnableNumberL STD ·25 ·35 ·25 ·35 ·25 ·3516L8(8) 7-wideAND-OR-InvertProgrammable(6) Bidirectional(2) Dedicated45 70 25 35 - - - -16R8 (8) 8-wide AND-OR Dedicated Registered Inverting 45 70 - - 20 30 15 2516R616R42001022V1O(6) 8-wide AND-OR Dedicated Registered Inverting(2) 7-wideAND-OR-InvertProgrammableBidirectional(4) 8-wide AND-OR Dedicated Registered Inverting(4) 7-wideAND-OR-InvertProgrammableBidirectional(10) 8-wide AND-OR- Programmable Programmable BidirectionalInvert with MACRO or Dedicated or Registered(10) variable AND-OR-Invert with MACROMilitary Selection GuideProgrammableProgrammable Bidirectionalor Registered45 70 25 35 20 30 15 2545 70 25 35 20 30 15 25- 55 25 35 15 30 15 2555 90 25 35 15 30 15 25GenericOutput Vee tpDns ts ns tconsPart LogicOutputsEnablemANumber ·20 ·25 ·30 -40 ·20 ·25 ·30 ·40 ·20 ·25 ·30 ·4016L816R8(8) 7-wide(6) BidirectionalProgrammableAND-DR-Invert(2) Dedicated(8) 8-wideAND-OR70 20 NA 30 40 - NA - - - NA - -Dedicated Registered Inverting 70 - NA - - 20 NA 25 35 15 NA 20 25(6) 8-wideDedicated Registered InvertingAND-OR16R6 70 20 NA 30 40 20 NA 25 35 15 NA 20 25(2) 7-wideProgrammable BidirectionalAND-DR-Invert(4) 8-wideDedicated Registered InvertingAND-OR16R4 70 20 NA 30 40 20 NA 25 35 15 NA 20 25(4) 7-wideProgrammable BidirectionalAND-DR-Invert(10) 8-wide Programmable20010 AND-DR-Invert Programmable Bidirectional 80 NA - 30 40 NA - 25 35 NA - 20 25with MACROor Registered(10) variable Programmable22V1O AND-DR-Invert Programmable Bidirectional 100 NA 25 30 40 NA 20 25 35 NA 20 20 25with MACROor RegisteredTable 1. PLD Selection Guide10-12

~ Programmable Logic Device Application Brief~~~NDUCTOR ==~~~~~~~~~~~~~==~~~~~~==~~~~~==~~~~~===INPUTS (0 - 31)POP1 P2P3 0 1 2 3 4 II • 7 •• 1011 121314111 1.171.1. 20212223 2421121127 212130317 _.......1-----..4-1 >......-....""1~....~~r+~----------~ .. ~POP1P2P3 0 1 23 45 6 7 891011 12131415 18171819 20212223 24252827 28283031Figure 2. Functional Logic Diagram PAL C 16L8A0049-210-13

~ Programmable Logic Device Application Brief_r.~UcroR =================================There are 2048 EPROM cells in the PAL C 20 array thatare used to specify up to 32 inputs for 8 groups of 7-inputAND OR gates and 8 32-input AND output enable gates.In normal usage, a maximum of 16 inputs would beconnected to any AND gate, because connecting both atrue and a complement input of the same signal to theinput of an AND'· gate will result in a constant LOWoutput.Phantom ArrayThere are an additional 256 bits in a phantom array thatare used to test the PAL C 20 device functionally and toverify dynamic (AC) operation without using the regulararray after the device is packaged. The phantom array isprogrammed and verified as part of the final electrical testprocedure during the manufacturing process. It may beused by the customer as part of an incoming inspection andcould be used to verify programmability as well asfunctionality. Three input pins are used to verify operationof the phantom array. One (pin 2) has a worst case. (longestphysical length) propagation delay path through theregular array.Programming the ArraysThe phantom array is programmed in the same manner asthe regular array. Both are addressed as byte arrays forprogramming. The normal array has 256 bytes to programand the phantom array has 32 bytes. The customer maytest the programmed phantom. array functionally anddynamically as part of an incoming inspection.Programming the EPROM CellA schematic of the two-transistor EPROM cell used in allPLDs is illustrated in Figure 1. Conventional EPROMSuse one transistor per cell and its design is a compromisebetween being able to program (write) rapidly and read.Cypress uses a two-transistor cell that enables the PLDs toachieve superior performance by optimizing the readtransistor, R, and program transistor, P, for theirrespective functions. The cell size is 20.4 microns by 6.7microns. Note that the selection gates, the floating gatesand the sources of both transistors are (respectively)connected together.OperationIn the unprogrammed state, the threshold voltage of the Rtransistor is less than that of theP transistor.A (INPUT TERt.4)-+--.-+ PROGRAt.4-+-1-.-+ ~e::gDUCT TERt.4)V5/15 0049-1Figure 1. PLD EPROM Cell SchematicTo program the cell, the input line (A) is raised to 15 volts,which causes charge to be stored on the floating gate of theP transistor, which causes its threshold to increase byapproximately 7 volts. Because the floating gates of bothtransistors are connected together, the threshold of the Rtransistor increases by the same amount.To read from the cell, the input line (A) is raised to 5 volts.If the cell had been programmed, this voltage would not besufficient to tum-on the read transistor. However, if thecell had not been programmed, the read transistor wouldtum-on. Under this condition the current through the readtransistor is 150 microamperes; approximately an order ofmagnitude greater than that used in a conventionalEPROM cell. The larger current is required in order toachieve the specified performance.Operational OverviewThe device operates in two basic modes; normal andPROGRAM. In the normal mode either the Regular arrayor the Phamtom array may be used, together with the datainputs, to determine the state of the outputs. In thePROGRAM mode either the Regular array or thePhantom array may be programmed using the 8 outputs(pins 12-19) as data inputs and pins 2 through 9 as addressinputs.Table 2 illustrates the various modes of operation for thePAL C 20 device. They are decoded by high-voltagesensitiveon-chip circuits. It is permitted to go from anymode to any other mode. Note that the normal data outputpins (12-19) are used as data input pins for programming.ProgrammingTables 3 and 4 indicate how the regular and the phantomarrays in the PAL C 20 device are addressed. The 20G 10and 22V1Oare similar. The regular array is addressed as a10-14

~ Programmable Logic Device Application Brief~~~~================================================================256 word (8 X 32) by 8-bits per word memory. Thephantom array is selected using the same addresses ascolumns 0, 1,2 and 3, but with pin 7 at Vpp (per Tables 2and 4).In either case (normal or phantom array), the productterms are addressed in groups of 8 as shown in Table 3.There is a one-to-one correspondence between the data tobe programmed and the DO-D7 inputs and the productterms, as modified modulo 8, by the address on pins 2, 3, 4(Refer to Figure 2). In other words, a one on DOcorresponds to de-selecting the "product term input" atinput line 0 and product term O. A one on D 1 correspondsto de-selecting the product term input at input line 0 andproduct term 8, etc. One method of programming the arraywould be to program and verify the bits corresponding tothe first product term address and then increment acounter that generates the "OR" gate addresses (pins 2, 3,4) and then program and verify the second row of Table 3,and continue this process 8 times until all 64 product termsassociated with input line 0 have been programmed andverified. To select the second (1) input term, address pins 6,7, 8 and 9 are held LOW (as before) and pin 5 = HIGH.The preceding sequence is then repeated 31 more times,incrementing pins 5 through 9 in a binary sequence, toprogram and verify the entire array. The other members ofthe family are programmed in an identical manner.Table 2. PAL C 20 Series Operating ModesPin Name Vpp PGM/OE At A2 A3 A4 AS D7-ooPin Number (1) (11) (3) (4) (5) (6) (7) (12-19) NotesOperating ModesPAL X X XProgram PAL Vpp Vpp XProgram Inhibit Vpp VIHP Xprogram Verify Vpp VILP XPhantom PAL X X XProgram Phantom PAL Vpp Vpp XPhantom Program Inhibit Vpp VIHP XPhantom Program Verify Vpp VILP XProgram Security Bit Vpp Vpp VppVerify Security Bit X X (Note 8)Register Preload X X XNotes:1. Vpp = 13.S ±O.SV, Ipp = SOmA; Veep = S ±0.2SV; VIHP = 3V;VILP = O.4V.2. Measured at 10% and 90% points.3. Vss < X < Veep.4. All "X" inputs operational per normal PAL function.S. Address inputs occupy Pins 2 thru 9 inclusive, for both programmingand verification see programming address Tables 3 and 4.6. All "X" inputs operational per normal PAL function except that theyoperate on the function that occupies the phantom array.XXXXXXXXXVppXX X X Programmed Function 3,4X X X Data In 3,5X X X HighZ 3,5X X X Data Out 3,5X Vpp X Programmed Function 3,6X X Vpp Data In 3,7X X Vpp HighZ 3,7X X Vpp Data Out 3,7X X X HighZ 3X X X HighZ 3Vpp X X Data In 3,97. Address inputs occupy Pins 2 thru 9 inclusive, for both programmingand verification see programming address Tables 3 and 4. Pin 7 isused to select the phantom mode of operation and must be taken toVpp before selecting phantom program operation with Vpp on Pin 1.S. The state of Pin 3 indicates ifthe security function has been invokedor not. If Pin 3 = VOL security is in effect, if Pin 3 = V OH, the datais unsecured and may be directly accessed.9. For testing purposes, the output latch on the 16RS, 16R6 and 16R4may be preloaded with data from the appropriate associated outputline.Table 3. PAL C 20 Series Product Term AddressesProduct Term AddressesBinary AddressPin NumbersLine Number(4) (3) (2)VILP VILP VILP 0 8 16 24 32 40 48 56VILP VILP VIHP 1 9 17 25 33 41 49 57VILP VIHP VILP 2 10 18 26 34 42 50 58VILP VIHP VIHP 3 11 19 27 35 43 51 59VIHP VILP VILP 4 12 20 28 36 44 52 60VIHP VILP VIHP 5 13 21 29 37 45 53 61VIHP VIHP VILP 6 14 22 30 38 46 54 62VIHP VIHP VIHP 7 15 23 31 39 47 55 63DO Dl D2 D3 D4 D5 D6 D7Programmed Data Inputto-15

~ Programmable Logic Device Application Brief~~~NDucrOR ~~~~~~~~~~~==~~========~~====~~========~===========Table 4. PAL C 20 Series Input Term AddressesInputTermsNumbersInput Term AddressesBinary AddressesPin Numbers(9) (8) (7) (6) (5)0 VILP VILP VILP VILP VILP1 VILP VILP VILP VILP VIHP2 VILP VILP VILP VIHP VILP3 VILP VILP VILP VIHP VIHP4 VILP VILP VIHP VILP VILP5 VILP VILP VIHP VILP VIHP6 VILP VILP VIHP VIHP VILP7 VILP VILP VIHP VIHP VIHP8 VILP VIHP VILP VILP VILP9 VILP VIHP VILP VILP VIHP10 VILP VIHP VILP VIHP VILP11 VILP VIHP VILP VIHP VIHP12 VILP VIHP VIHP VILP VILP13 VILP VIHP VIHP VILP VIHP14 VILP VIHP VIHP VIHP VILP15 VILP VIHP VIHP VIHP VIHP16 VIHP VILP VILP VILP VILP17 VIHP VILP VILP VILP VIHP18 VIHP VILP VILP VIHP VILP19 VIHP VILP VILP VIHP VIHP20 VIHP VILP VIHP VILP VILP21 VIHP VILP VIHP VILP VIHP22 VIHP VILP VIHP VIHP VILP23 VIHP VILP VIHP VIHP VIHP24 VIHP VIHP VILP VILP VILP25 VIHP VIHP VILP VILP VIHP26 VIHP VIHP VILP VIHP VILP27 VIHP VIHP VILP VIHP VIHP28 VIHP VIHP VIHP VILP VILP29 VIHP VIHP VIHP VILP VIHP30 VIHP VIHP VIHP VIHP VILP31 VIHP VIHP VIHP VIHP VIHPPO VILP VILP Vpp X XPI VILP VIHP Vpp X XP2 VIHP VILP Vpp X XP3 VIHP VIHP Vpp X XImplementationA simplified block diagram of a 16L8 is presented in Figure3. The method of programming and sensing is illustrated inFigure 4.Programming OperationPins 5-9 are decoded (according to Table 4) in a one of 32decoder, whose outputs correspond to the inputs labeled0-31 of Figure 2. For programming, 15 volts is applied tothe bottom of the input term line through a weak depletionmode device (Figure 4). The EN (enable) signal to all of thethree-state drivers is LOW, which prevents the normalinput signals from driving the input term lines duringprogramming. The 00-07 inputs (pins 19 through 12)drive the program transistors (0, 8, 16, 24 etc.) as selectedby pins 2, 3, 4 and as listed in Table 3. To disconnect aninput term line from a product term line, the P transistor isforward biased, which increases the threshold of the Rtransistor.Verify OperationTo verify the programmed cells, the device must go fromthe PROGRAM mode to the PROGRAM INHIBITmode to the PROGRAM VERIFY mode. This isaccomplished by reducing the voltage on pin 11 to VIHP(3V) and then to VILP (0.4V). Internal to the device (seeFigure 4) the 1 of 32 decoder is disabled, the EN signal isLOW, and 31 of the 32 input term lines are at zero volts.The line being verified is at 5 volts. The input address lines(pins 2 through 9) do not need to change when going fromprogram to verify.The "ones" that were programmed cause the thresholds ofthe R transistors to increase, so they do not tum on duringverify. Conversely, the unprogrammed transistors do tumon, so the complement (inverse) of the data programmed isread during verify.Normal OperationThe PAL device will implement the programmed functionwhen there are no su'pervoltages applied to any of the pins.Ouring regular PAL operation the 1 of 32 decoder and the00-07 decoder are disabled, the EN signal is HIGH andall 32 input term lines are at 5 volts. Under theseconditions, the data at the input pins is applied to all 64 ofthe product term lines. If any of the P transistors (16 perproduct term line) had not been programmed, they willtum on and pull the lower input to the corresponding senseamplifier (SA) to 2 volts or less. This voltage will be lessthan the reference (Vref) so that the output of the senseamplifier will be LOW.The reference is an unprogrammed EPROM cell thattracks the same process, voltage and temperaturevariations that affect all of the cells in the array. It isapproximately three volts at room temperature andnominal ( 5 volts) Vee.10-16

~ Programmable Logic Device Application Brief~~~~UcrOR =====================================================================PIN1VppPINS5-95PINS12-198PINS2-43~~ 1 OF 32 DECODE IPROGRAMLOGIC t- (PROGRAM ONLY)&: H.V.32 FEEDBACK L~ 14 I BUFFERS I!INPUTBUFFERAND&: H.V.EPROM8SENSE 7-INPUT 8CELLARRAY 1--+ AMPLIFIERS 1--+ I---t OUTPUTINPUT NOR DRIVERS7X8=56BUFFER 2048 REG. GATES&: H.V. r--+ 256 PHANTOM1 OF 81DECODE321 1INPUT t-f- PROGRAMBUFFER PAL/PROGRAM REFERENCE&: H.V. l.....-..+ VOLTAGE FOR SENSESELECTAMPLIFIER1-7"-'PINS12-19ŌEFigure 3. 16L8 Device Simplified Block Diagram0049-3PINS 5 - 91 OF 32 DECODER(INPUT TERMS)o1 CORRESPONDS TOINPUTS 0,1 OF FIG. 2INPUTSPINS 2 - 9 FOR NORMAL OPERATION ONLYDO-D7DECODEFOR PROGRAMONLY5V FOR NORMAL AND VERIFY OPERATIONS15V FOR PROGRAMMINGFigure 4. Programming Method0049-410-17

~~ ==========P;;;;;r;;;;;ogr=8;;;;;m;;;;;m;;;;;8;;;;;b;;;;;l;;;;;e;;;;;Lo=gI;;;;;"c;;;;;D;;;;;;;;;;ev;;;;;i;;;;;c;;;;;e;;;;;A;;;;;p;;;;;p;;;;;li;;;;;C;;;;;8t;;;;;i;;;;;oD;;;;;;;;;;B;;;;;r;;;;;ie;;;;;fPhantom OperationThe PAL C 20 device is in the PHANTOM mode ofoperation when a supervoltage (Vpp = 13.5V) is applied topin 6. The phantom array is programmed as shown inFigure 2. The user may measure the worst case propagationdelay from the pin 2 input to the outputs (pins 12 through17). The truth table for the phantom array is shown inTable 5.Table 5. Phantom Array Truth TableInputsOutputsPin 2 3 4 19 18 17 16 15 14 13 120 0 1 X X 1 1 1 1 1 11 0 1 X X 0 0 0 0 0 00 1 X 1 0 X X X X X X0 1 X 0 1 X X X X X XReliabilityReliability is designed into all Cypress products from thebeginning by using design techniques to eliminate latchup,improve ESD and by paying careful attention to layout. Inaddition, all products are tested for all known types ofCMOS failure mechanisms.Failure mechanisms can be either classified as thosegeneric to CMOS technology or those specific to EPROMdevices.Table 6. Generic CMOS Failure MechanismsTable 6 lists both categories of failures, their relevantactivation energies, Ea in e V ( electron volts), and thedetection method used by Cypress. In both cases, themechanisms are aggravated by HTOL (High TemperatureOperating Life) tests and HTS (High Temperature Storage)tests.Specific EPROM failure mechanisms include charge loss,charge gain and electron trapping. Charge loss isaccelerated by thermal energy and field emission effects.Thermal charge loss failures usually occur on random bitsand are often related to latent manufacturing defects.Field emission effects are generally detected as weaklyprogrammed cells. The high voltages used to program a"selected bit" may disturb (as a result of a defect) an"unselected bit".Charge gain is due to electrons accumulating on a floatinggate as a result of bias or voltage on the gate. This results ina reduced read margin. This mechanism is generallynegligible.Charge gain and charge loss are monitored on everyCypress die in wafer form by programming, performing aHTS test and verifying that the programmed data isretained in the device.MechanismActivationEnergy (eV)Surface Charge 0.5 to 1.0Contamination 1.0 to 1.4Electromigration 1.0Micro-cracks -Silicon Defects 0.3Oxide Breakdown 0.3Hot Electron Injection -Fabrication Defects -Latchup -ESD -Charge Loss 0.8 to 1.4Charge Gain(Oxide Hopping)Electron Trappingin Gate Oxide0.3 to 0.6Notes:Table 6 has been adapted from, "An Evaluation of2708, 2716, 2532, and2732 Types of U-V EPROMS, Including Reliability and Long Term-Detection MethodHTOL, Fabrication MonitorsHTOL, Fabrication MonitorsHTOLTemperature CyclingHTOLHigh Voltage Stress, HTOLLTOL (Low Temp. Operating Life)Burn InHigh Voltage Stress, Burn In,CharacterizationCharacterizationHTS (High Temperature Storage)HTOLProgram/Erase CycleStability." Danish Research Center for Applied Electronics, Nov. 1980.10-18

~ CYPRESSProgrammable Logic Device Application Brief~~~IOO~UaoR==================================================================HTOL TestingHigh Temperature Operating Life test (or bum-in) is usedto detect most generic CMOS failure mechanisms. Unitsare placed in sockets under bias conditions with powerapplied and at elevated temperatures for a specific numberof hours. This test is used to weed out the "weak sisters"that would fail during the first 100 to 500 hours ofoperation under normal operating temperatures. HTOLtests are also used to measure parameter shifts in order topredict (and screen for) failures that would occur muchlater.HTS TestingHigh Temperature Storage tests are used to thermallyaccelerate charge loss. These tests are performed at thewafer level and under unbiased conditions. Both pass/faildata as well as shifts in thresholds may be measured. For amore detailed discussion of charge loss screening the readeris referred to the article on EPROM reliability beginningon page 132 of the August 14, 1980, issue of Electronicsmagazine.The generally accepted screening method for identifyingcharge loss is a 168 hour bake at 250°C. This correlateswith more than 220,000 years of normal operation at 70°Cusing a failure activation energy of 1.4 eV.Initial QualificationThe process in general and the EPROM cell design inparticular was qualified using HTS (bake) at 250°C for 256hours, in conjunction with an HTOL test at 125°C for 1000hours.ProcedureFour wafers were erased using ultraviolet light and thelinear thresholds of the cell read transistors measured attwenty-five "sites" on each wafer.The wafers were then programmed and the linearthresholds then measured and recorded.The wafers were alternately baked at 250°C and the linearthresholds measured and recorded at 0.25, 0.5, 1, 2, 4, 8,16,32,64, 128, and 256 hours. The number of device hoursis then 100 X 256 = 25,600.ResultsThe average threshold reduction due to charge loss was0.66 volts. The range was eight to ten percent of theaverage initial threshold of 7.7 volts. This reducedthreshold is greater than four volts above the senseamplifier voltage reference. There were no failures.If the charge loss failure activation energy is assumed to be1.4 eV, the HTS time of 256 hours at 250°C translates to438,356 years of operation at 70°C.The time translations were computed using the industrystandard Arrhenius equation, which converts the time tofailure (operating lifetime) at one temperature and time toanother temperature and time.SummarySample size: 100Device hours: 25,600 hoursHTS conditions: 256 hours at 250"CAverage initial threshold: 7.7 voltsAverage threshold decrease: 0.66 voltsStandard deviation: 0.12Lifetime (1.4 ev): 438,356 years at 70°CConclusionAn HTS experiment, performed according to industrystandard conditions, and using representative Cypressproduct confirms that the data retention characteristics ofthe EPROM cell used in all Cypress PLDs and PROMsguarantees a minimum operating lifetime of 438,356 yearsfor activation energies of 1.4 eV.Production ScreenUnits from the same population were assembled withoutbeing subjected to HTS and were subjected to an HTOL of150 degrees C for 1000 hours. The units were tested at 12,24,48,96, 168,336, and 1008 hours and the measurementsrecorded. Variations in the thresholds of the EPROM cellswere measured and correlated to· the units tested in theHTS test in order to determine a maximum acceptable rateof charge loss in order to guarantee data retention overtheir normal operating lifetime.Advantages Over BipolarLower power results in several benefits to the user. Theyare:• Lower capacity and, therefore, lower cost powersupplies.• Reduced cooling requirements.• Increased long term reliability due to lower die junctiontemperatures.Power dissipation may be further reduced by driving theinputs between 0.5 volts (or less) and 4 volts (or more).This reduces the power dissipation in the input TTL toCMOS buffers, which dissipate power when their inputsare between 0.8 volt and 3 volts. Each buffer drawsapproximately 0.8 mA of Icc current at VIN = 2 volts.10-19

~ Programmable Logic Device Application Brief~~~~~~~~~~~~~~~~====~~~~~==~~~~====~~==~~Rp~--'-----~~-----+---JVV~--~----------'--------------+-----CMOSTTL TOCONVERTER·Thick Oxide FieldTransistor"Substrate DiodeTHIN OXIDETRANSISTORVSUBAppendixThe Cypress double-layer polysilicon, single-layer metal,N-well, CMOS technology has been optimized forperformance. Careful attention to design details and layouttechniques has resulted in superior performance productswith improved ESD input protection and improvedlatchup protection.Input ESD ProtectionThe circuit shown in Figure 5 is used at every input pin inall Cypress products to provide protection against ESD.This circuitry has been designed to withstand repeatedapplications of high voltages without failure orperformance degradation. This is accomplished bypreventing the high (ESD) voltage from reaching the thingate oxides of the internal transistors.The circuit consists of two thick oxide (field) transistorswrapped around an input resistor (Rp) and a thin oxide(gate) transistor with a relatively low breakdown of 12volts. Large input voltages cause the thick oxide transistorsto tum on, discharging the ESD current to ground. Thethin oxide transistor breaks down when the voltage acrossit (drain to source) exceeds 12 volts. It is protected fromdestruction by the current limiting action of Rp.Experiments have confirmed that this input protectioncircuitry results in ESD protection in excess of 200 1 volts.Definition of LatchupLatchup is a regenerative phenomenon that occurs whenthe voltage at an input pin or an output pin is either raisedabove the power supply voltage potential or lowered belowthe substrate voltage potential (which is usually ground).Current rapidly increases until, in effect, a short circuitfrom V cc to ground exists. If the (V cd current is notlimited it will destroy the device; usually by melting ametal trace.Causes of LatchupThe CMOS processing, which provides both N-channeland P-channel MOS transistors, also inherently providesparasitic bipolar transistors; both NPNs and PNPs.Latchup is caused when these parasitic transistors areinadvertently turned on.Figure 5. Input Protection Circuit0049-5As long as the voltages that are applied to the package pinsof the CMOS IC remain within the limits of the powersupply voltages (usually 0 volts to 5 volts), these parasiticbipolar transistors will remain dormant (i.e., ofl). However,when either negative voltages or positive voltages greaterthan the V cc supply voltage are applied to input or outputpins, these parasitic bipolar transistors may tum on andcause latchup.Conditions For LatchupA cross section of a typical CMOS inverter using aP-channe1 pullup transistor and an N-channe1 pulldowntransistor is shown in Figure 6. Also shown is anN-channe1 output driver that is isolated from the CMOSinverter by a guard ring (channel stopper) that is necessaryto prevent parasitic MOS transistors between devices. P +guard rings surround N-channel devices and N + guardrings surround P-channel devices. The parasitic SCR(PNPN) and bias generator are illustrated in Figure 7. Theoutput driver schematic is not shown.In order for latchup to occur two conditions must besatisfied; (1) the product ofthe betas ofthe NPN and PNPtransistors must be greater than one, and (2) a triggercurrent must exist that turns on the SCR.Since the SCR structure in bulk CMOS cannot beeliminated, preventing latchup is reduced to keeping theSCR from turning on. If either RWELL = 0 or RSUB = 0the SCR cannot tum on because the base emitter junctionof the PNP cannot be forward biased because they are tiedtogether and the base emitter junction of the NPN cannotbe forward biased because the base is connected to ground.Note, however, that the NPN could be turned on by anegative voltage on the output pin (if the right end of RSUBis grounded).Prevention of Latchup; TraditionalApproachesThe traditional cures include increased horizontal spacing,diffused guard rings and metal straps to critical areas.These solutions are obviously opposite to the goal ofgreater density.A brute-force approach that has been successful inreducing latchup has been to increase the conductivity ofthe N-well and the substrate. Changing the well10-20

~ Programmable Logic Device Application Brief~~~~UcrOR ==~~~~~~~~~~~~~~==~~~~~~==~~~~~==~~~~~~=Output DriverCMOS Invertern-MOS:;~t~c~OWN"'--n-MOS/PULL-UPSL. OUTPUT 'l.I DEVICEVeeOUTPUTINPUTn+ DIFFUSION AND p+ DIFFUSIONn- WELL GUARD RING GUARD RINGLATERAL npn BIPOLARTRANSISTORconductivity is unacceptable because it affects thecharacteristics of the P-channel MOS transistors. Using anepitaxial layer to reduce the substrate resistivity (RSUB) isanother possible solution.VeePARASITICRESISTANCEFigure 6. CMOS Cross Section and Parasitic CircuitscrJJSubstrate Bias Generator ~Figure 7. Parasitic SCR and Bias Generator0049-7The Cypress Solution to LatchupCypress uses several design techniques in addition tocareful circuit layout and conservative design rules toeliminate latch up.NMOS Output Pullup TransistorsConventional CMOS technology uses a P-channel MOS asa pullup transistor on the output drivers. This has theadvantage of being able to pull the output voltage HIGHlevel to within 100 millivolts of the positive voltage supply.VERTICAL pnp BIPOLARTRANSISTORPARASITICRESISTANCE0049-6However, this is of marginal value when TTL compatibilityis required. In addition, the P-channel pullup is sensitive toovershoot and introduces another vertical PNP transistorthat further compounds the latchup problem. Cypress usesN-channel pullup transistors that eliminate all of theseproblems and still maintain TTL compatibility.Substrate Bias GeneratorCypress is the first company to use a substrate biasgenerator with CMOS technology. The bias generatorkeeps the substrate at approximately - 3 volts DC, whichserves several purposes.Input PinsThe parasitic diodes shown in Figure 5 cannot be forwardbiased unless the voltage at an input pin is at least onediode drop more negative than - 3 volts. This translatesinto increased device tolerance to (negative voltage)undershoot at the input pins, caused by inductance in theleads. If the undershoot is this large, the output impedanceof the bias generator itself is sufficient to prevent triggercurrent from being generated.Output PinsThe same reasoning applies to negative voltages at theoutput pins as shown in Figure 7. In order to turn on theNPN transistor the voltage at the output pin must be atleast one VBE more negative than - 3 volts.Guard RingTo protect the "core" of the die from free floating holesand stray currents, a diffused collection guard ring that isstrapped with metal and connected to the bias generator isused. This provides an effective wall against transientcurrents that could cause mis-reading of the EPROM cells.1m•1O-2l

CYPRESSSEMICONDUCTORPAL® C 16R6 Design Example:GCR Encoder IDecoderIntroductionDigital encoding and decoding of data is often used to increasethe reliability of data transmission and storage. Onearea where digital techniques are employed is the transformationbetween data stored on one-quarter inch magnetictape and serial digital data.This document describes the procedure used to encode/decodeserial digital data for recording/reading fromone-quarter inch magnetic tape using a Cypress CMOSPAL C 16R6 to implement the logic.HistoryThe recording format and the Group Code Recording(GCR) code have been adopted and incorporated in a seriesof standards by a committee called the QIC (QuarterInch Cartridge) Committee, composed of manufacturersand users of quarter inch tapes and cartridges. The purposeof the committee is to insure compatibility between manufacturersand reliability to end users.Quarter inch tape cartridges are used extensively to backupor archive data from hard disks. Most drives are operatedin a continuous or streaming mode (for reasons that will bediscussed later) and data is recorded at 10,000 FRPS (FluxReversals Per Inch) in a serpentine manner on seven tofourteen channels. The tape moves at 30 to 90 ips (inchesper second) and the error rates achieved are one in 109 or1010. A cartridge holds 2000 to 3000 feet of tape 0.001 inchthick and stores 20 to 80 million bytes (mega-bytes) ofdata.Typical SystemA block diagram of a typical system is shown in Figure 1.The interface between the Host (or Host Adapter) is bi-RPULSEDEl.DATASEP.TAPEF'ORMATIERORCONTROLLERHOST1+---1~ ADAPTERHOSTDRIVEF'ORMATIERQIC-24/36 QIC-02QIC-50 SCSIQIC-59 IPIInterfaceStandardsInterfaceStandardsFigure 1. A Typical Tape Drive SystemHOST0060-1PAL® is a registered trademark of Monolithic Memories Inc.ABELTM is a trademark of Data I/O CorporationPALASMTM is a trademark of Monolithic Memories Inc.V AXTM is a trademark of Digital Equipment Corp.WORDSTARTM is a trademark of MicroPro International10-22

~ PAL® C 16R6 GCR Encoder/Decoder~~~U~================================================================Typical System (Continued)directional, with a byte-wide data path and 10 to 20 controlsignals, depending upon the interface standard. Data ratesare 300 KBs (thousand Bytes per second) to 1 MBs (MillionBytes per second).The Formatter or Tape Controller performs serial/parallelconversion and encoding/decoding of the data as well aserror checking and, in some cases, error correcting. Controlis usually provided by a state machine that handles thehandshaking between the host as well as control of thetape. Data is written in blocks of various lengths (dependingupon the standard) and a "read after write" check isusually performed. Buffer storage of at least two blocks ofdata is usually provided using static RAMs (SRAMs),FIFOs, or some combination of the two.The Drive electronics consist of digital signals that controland sense the tape motion and analog signals in the readand write paths. The interface between the Drive and theFormatter is digital and, once again, there are various standards.Reading and Writing on TapeTo write on the tape a current of 100 rnA or less is used tochange the direction of magnetization. To read from thetape a coil of wire (the read head) is held against the tapeand a voltage (10m V or less) is induced by the change indirection of the magnetic flux on the tape.Recording CodesAll codes used for recording on magnetic mediums areclassified as Franaszek Run Length Limited (RLL) codesof the form:(D, K)where D = the minimum number of zeros between consecutiveones, andK = the maximum number of zeros between consecutiveones.D controls the highest frequency that can be recorded andK controls the lowest frequency.Using the Franaszek notation, the GCRcode is (1,2). Asillustrated in Figure 2, a flux reversal signifies a one and theabsence of a flux reversal signifies a zero. This is true for allcodes.Peak Detection and Data SeparationPeaks are detected (versus zero crossings) because the circuitsused are less sensitive to noise. The output of the peakdetector goes to the most critical analog circuit in thedrive; the data separator.The function of the data separator is to provide ones andzeros that occur at a precise frequency. It does this by firstsynchronizing itself to a crystal controlled reference clockand then attempting to "lock" itself to the maximum datafrequency on the tape by finding the phase difference betweenitself and the data output of the peak detector anddriving a voltage controlled oscillator (VCO) such thatthey are equal. This is calleda Phase Locked Loop (PLL).The frequency of the reference clock must be at least twice(2t) that of the highest frequency that is to be read (t).The PLL is synchronized to the 2f reference frequencywhen it is not in use. A string of ones is recorded, which iscalled the preamble, before the block of data· is recorded.When the command to read is given, the 2f reference frequencyis removed from the data separator and the signalfrom the peak detector is applied to the data separator. ThePLL then attempts to "lock" to the preamble. Just after thepreamble, a code violation is recorded so that the Formattercan recognize where valid data begins. The procedureof locking onto the preamble is called "getting bit sync."The detection of the code violation is called "obtainingbyte sync".PLLs typically exhibit frequency and phase offsets duringacquisition of the preamble. Phase errors also occur afterlock, during the reading of the data field. Differences intape speed during record and playback (as well as fromunit to unit) result in frequency differences between thedata read from the tape and the 2f reference.Random phase errors caused by noise, intersymbol interference(bit crowding), timing errors and other transientsmay also get the PLL out of lock.The data separator's PLL is susceptible to these errors becauseit must satisfy two conflicting conditions: (1) it musto o oo o oo o oREADING FRO ... TAPEFigure 2o o oI ~ '-CUP\=z/LEVEL0060-2m10-23

~ PAL® C 16R6 GCR Encoder/Decoder~~~~==============================================================Reading and Writing on Tape (Continued)lock quickly enough to detect the preamble, but (2) it mustnot overcorrect phase for a single misaligned bit.Strings of zeros cause the phase of the PLL to shift and ifthe shift is larger than the "bit window", an error willoccur. The QIC-24 standard calls for up to 37% bit shifttolerance, which means that the data separator must beable to recognize a "one" (flux transversal) that deviates± 18.5% from its expected time position without causing adata error. In order to achieve this performance a four-bitbinary nibble is encoded into a five-bit "OCR code word"that is written onto the tape.Reasons for the GCR CodeThe 5-bit OCR code format is required to encode the datasuch that no more than two consecutive zeros occur in theserial data. This encoding relaxes the performance requirementsof the PLL and the loop filter so that the desiredsystem performance can be achieved.Static TolerancesAnother reason for OCR encoding is to compensate for thespeed variation of the tape due to:Mechanical TolerancesCartridgeTape thickness (±3%)Tape Elasticity and WearMotor Speed VariationTemperature and HumidityThe preceding static tolerances can result in a ± 10%speed variation of the tape.Dynamic TolerancesIn addition to the static tolerances, there are InstantaneousSpeed Variations (ISV) due to discontinuous tape release atthe unwind spool (10-20%), guide/back stick slip (5%)and shuffle ISV (vibration) due to start/stop (5-30%). Theshuffie ISV can be avoided by operating the tape in a continuous(streaming) mode. If these dynamic tolerances areadded together they can result in a ± 15% speed variation.Electronics CompensateThe electronics in the tape controller and the drive aredesigned to compensate for the tape speed variations due tothe mechanical tolerances.The compensation is performed by:Data Encoding and Error Detection and CorrectionPhase Locked Loop DesignBit Window ToleranceSequence of OperationsDuring a write operation the following sequence occurs:1. Idle (Hold)2. Convert 4-bit parallel input to 5-bit OCR code andload into 5-bit register.3. Shift out 5-bits to write amplifier.During a read operation the following sequence occurs:1. Idle (same as during write)2. Shift in 5-bits.3. Detect sync markSet/Clear invalid flagConvert 5-bit serial input to 4-bit binary value andload into register.Note: that the read clock and the write clock are not thesame.Also, the logic must keep up with the tape data rate.And finally, the read and write operations are mutuallyexclusive so that the storage elements (D flip-flops) can betime-shared and that read and write operations require 5clocks.A total of 5 states are required because the idle state iscommon to both read and write operations. Therefore, 3control lines will be required. It is convenient to designateone control line as an enable line (active LOW) and theother two lines as Mode Control signals.The control of these lines is not described here, nor is therequired clock synchronization. The reason for not doingthis is that at the next level of control, system considerationssuch as what action to take when errors occur mustbe implemented in hardware and these tend to be not onlyapplication dependent but also very subjective.The diagrams of Figure 3 show the flow of data under thecontrol of the ENABLE signal and the MO and Ml modecontrol signals.The GCRCodeThe OCR code is part of the QIC-24 Standard and is alsothe ANSI X3.54 standard (1976). The MSB (leftmost bit)is recorded first. Note that there are a maximum of twoconsecutive zeros in the five-bit code that is recorded onthe tape.4-BitCode5·Bit CodeLine Number D D D D Y Y Y Y S(For Ref.) 3 2 1 0 3 2 1 0 00 0 0 0 0 1 1 0 0 11 0 0 0 1 1 1 0 1 12 0 0 1 0 1 0 0 1 03 0 0 1 1 1 0 0 1 14 0 1 0 0 1 1 1 0 15 0 1 0 1 1 0 1 0 16 0 1 1 0 1 0 1 1 07 0 1 1 1 1 0 1 1 18 1 0 0 0 1 1 0 1 09 1 0 0 1 0 1 0 0 110 1 0 1 0 0 1 0 1 011 1 0 1 1 0 1 0 1 112 1 1 -0 0 1 1 1 1 013 1 1 0 1 0 1 1 0 114 1 1 1 0 0 1 1 1 015 1 1 1 1 0 1 1 1 1A A A A B 13 B B B3 2 1 0 0 '1 2 3 4Figure 4. GCR Code10-24

~ PAL® C 16R6 GCR Encoder/Decoder~~~NDUcroR =====================================================================ENABLE M 1 MOOPERATIONDATA FLOW DIAGRAMx X HOLDY3Y2Y1YOSOaa a SERIALSHIFT INr---- SINY3Y2Y1YOSOCONVERT 5-BIT TO 4-BITA1a 1 0 CONVERT5-BIT TO 4-BITY303!Y202Y101YOSO0 1 1 CONVERT4-BIT TO 5-BITEpY3YY2Y1Y YYOSOaa 1 SERIALSHIFT OUTIliY3Y2Y1Figure 3. Data Flow DiagramsYOSO0060-310-25

~CfPRFSSPAL® C 16R6 GCR Encoder/Decoder~~~~============================================================Design ProcedureThe design procedure will be to map the code conversionsusing Venn diagrams and write the logic equations as the"sum of products" or in minterm form. Six flip-flops arerequired, so the logic will be implemented using a PAL C16R6. Because the PAL device has inverting output buffers,the zeros wiIl be mapped. The D flip-flops require an"extra term" for them to hold their states when the EN­ABLE is HIGH.For example, for a conventional D flip-flop the form of thelogic equations would be:D = ENABLE 1 ( Q )++ENABLE 2 ( F2 )ENABLE 3 ( F3 ); RECIRCULATEPRESENTSTATE; FUNCTION 2; FUNCTION 3Where the ENABLE controls are mutually exclusive.4-Bit to 5-Bit Conversion for Y3 OutputIn Figure 4 (at the bottom) the 5-bit code columns arelabeled BO through B4 to help the reader understand howthe 4-bit code is mapped. In addition, the line numbers arelabeled 0 through 15, which correspond to the values of the4-bit binary code.Figure 5a shows how the 4-bit binary code is mapped onthe Venn diagram. For example, reference line numberzero, which corresponds to binary value zero, is located inthe lower right hand corner of Figure 5a.The Venn diagram of Figure 5b shows the conversion forthe Y3 output. It is labeled the BO input to the D flip-flop.Note that the parallel nibble (see Figure 3) is reversed (endfor end) so that the MSB is written first when it is shiftedout.000100............ ......,1 0 0 11 0 0 11 0 1 11 0 1 103Figure 5b. Y3 Map020060-5In Figure 5b, the ones and zeros in column BO are mapped.For example, reference line zero has the value 1 in columnBO of Figure 4. Therefore, a one is placed in the squarecorresponding to binary value zero in Figure 5b. In a similarmanner, ref. line 15 has a value of zero in column BO, soa zero is placed in the square corresponding to binary valuefifteen.Writing the EquationIf the output of the PAL C 16R6 were positive true logic,we would write the equation to include all of the ones onthe Venn diagram. However, because the PAL device outputis negative logic (active LOW) we will write the equationto include all of the zeros. Then, when the PAL deviceinverts the signals, the zeros will be changed to ones, sothat the final outputs wiIl be positive true logic.By inspection:BO = D3DO + D3Dlor,Y3 = D3DO + D3Dl3 11 10 2017 15 14 6025 3 12 41 9 8 003Figure Sa. Binary Values0060-410-26

~CYPFJSSPAL® C 16R6 GCR Encoder/Decoder~~I~U~~~~~~~~~====================~====~==================~Design Procedure (Continued)4-Bit to 5-Bit Conversions for Y2, YI, YO, SoThese are presented for the sake of completeness.0100~-- r-.-.0 1 1 0/""'. /-- 0 1 1 0'-..../ "--../0 1\...J1 11 1 1 103Y2 = HI = IDOl + ID02DOFigure Sc. Y2 Map020060-601011(0000 01 11 10 003VI = In = 02Figure Sd. YI Mapo~11or\02bJ0060-700001 1 1 11......"".1 0.....,001011 1 1 111 00(0 ~ 1 ~0211 01021 0 1 011 0103YO = ID = mDII50 + D3DIOO + 02DIoOFigure 5e. YO Map0060-85-Bit to 4-Bit Conversion for Y OutputsThis conversion requires two 16 square Venn diagrams becausethere are 25 = 32 possible binary values. However,note that in Figure 4 not all 32 possible combinations areused in the 5-bit code columns. These unused combinationsare "don't cares", which are represented by Xs in the03So=B4=OlDO+D3DOFigure Sf. So Map0060-9Venn diagrams, which can be either ones or zeros, whichfurther reduces or simplifies the logic equations.The procedure is: plot the 1s and Osput Xs in the blank squareswrite the equations for the zeros.IE10-27

~ PAL® C 16R6 GCR Encoder/Decoder~~~~============================================================YOYO( x 0 xX) I----- I'(x0 0 XY1Y11 1 XX 1X 0 1Y2Y21 1 XX 10 0 1X 0 Xx) I'-----'~x0 x xSO=OY3Y3 = AJ = Y2 + Y3 SoFigure 6aY3SO=10060-10YOYOX 1 XXX1 1 XY1Y11 1 XX1X 1 1Y2Y20 0 XX00 0 X1 0 XXX0 0 xSO=OY3Y1=A2=YIFigure 6bY3SO=10060-11Y1YOX 1 X1 0 XLXY1~t-------- V--X 1XYO----------1 0 XX 0 0Y2Y21 0 XX 10 0 0X 1 XXX1 X XSO=OY3Yl = AI = YO + Y3 Y2Figure 6cY3SO=10060-12YOYOY1x 0 x/-....,0 0 XxXY1X 11 1 X/,X 0 1Y2Y20 0 XX 11 0 1X 0 XXX1 1 XSO=OY3YO = AO = Y3 Y2 YO + SoFigure6dY3SO=10060-1310-28

~ PAL® C 16R6 GCR Encoder/Decoder~~~~UcrOR=====================================================================Design Procedure (Continued)Serial Shift InDuring serial shift in (both mode control signals LOW) thedata output of the data separator is applied to the input ofthe formatter. The signal is called SIN and is applied to theD input of the SOUT flip-flop. The output of the SOUTflip-flop is applied to the D input of the YO flip-flop and itsoutput is applied to the input ofthe Yl flip-flop, etc. Afterfive read clocks the MSB of the 5-bit GCR coded data is inY3 and the LSB is in SOUToSerial Shift OutDuring a write operation, after the 4-bit data is convertedto 5-bit data and reversed, it is shifted out using the writeclock and written on tape. The shift direction is opposite tothat in Serial Shift In. Note that it is right shifted "endaround" (see Figure 3) so that after 5 write clocks the samedata appears in the register.Invalid Flag (INV Flip-Flop)The Invalid flip-flop is set to a one when an invalid 5-bitcode is read from the tape. This is used to tell the tapeFormatter that the next data read is the beginning of thedata block. This procedure is called getting "byte sync."INV is a negative true signal, so the logic equations arewritten for ones on the Venn diagram.The 16 binary values that are NOT listed in Figure 4 areplotted as ones in Figure 7. The procedure was to plot zerosin the squares where there were valid 5-bit codes, then fillthe rest with ones and then write the equation for the ones.The Invalid flip-flop is enabled by a signal called CIF(Control Invalid Flag) and reset when CIF is LOW.Synchronization Mark DetectionBit synchronization is achieved when the illegal 5-bit codeof all ones is read from the tape. It is the logical AND of allfive bits, or BS = Y3 • Y2 • Yl • YO. SOUToImplementation ProcedureOnce the conceptual design has been completed, it must bereduced to practice. There are two main steps in the process;1. describe the logic using a high-level language, and2. program the PAL device.Several programs that run on the IBM PC (or equivalent)or the V AXTM computer are available from either semiconductormanufacturers or from third party software vendors.The first such program, called P ALASMTM (PALdevice Assembler) was developed by Monolithic Memories.It enables the designer to describe the logic in terms ofBoolean equations, truth tables, or state diagrams using alanguage whose syntax is comparable to a microcomputerassembly language.PALASM EquationsThe equations were written in the PALASM syntax. The(ASCII) file created using WORDSTAR in the non-document(N) mode is shown in Figure 8.Conversion to ABELTMThe PALASM file (GCREX.PAL) was then translated toABEL syntax using the TOABEL program. The format ofthe command is:TOABEL - IB:GCREX - OB:GCREXTThe TOABEL program converted the GCREX.PAL file toa file named GCREXT.ABL, whose listing is shown inFigure 9.INV = YO SOUT + Y3 Y2 + Y3 Yl YO + Y3 Y2 Yl YO SOUTFigure 70060-1410-29

~ PAL® C 16R6 GCR Encoder/Decoder~~~UcrOR ==~~~~~~~~~~~~~~~~~~~~~~~~===================ABEL Program ProcedureThe ABEL program consists of an executive and severaloverlay programs that are executed by simply typing in;ABEL B:GCREXTfollowed by an enter (CR) from the keyboard of an IBM(or look-alike) PC. The ABEL program was developed bya programmer manufacturer, Data I/O Corporation. Thesource file may be simplified (logic reduction), a logic simulationmay be performed, and test vectors may be generated.ABEL ProgramsThe ABEL programs are:Program NamePARSETRANSFORREDUCEFUSEMAPSIMULATEFunctionRead source file, check syntax, expandmacros, act upon assembler directives.Convert the description to an intermediateform.Perform logic reduction.Create the programmer load (JEDEC) me.Simulate the operation of a programmeddevice.DOCUMENT Create a design documentation me.ABEL OutputsThe output files are:GCREXT.LSTGCREXT.OUTGCREXT.DOCGCREXT.SIMPI6R6.JEDsee Figure 10(This design was not simulated.)see Figure 11The last file is in JEDEC (JC-42.1-81-62) format; suitablefor loading into a PLD programmer. The listing is shownin Figure 11. The DOCUMENT program output is shownin Figure 10.Programming the 16R6The 16R6 was programmed using the Data 110 model 29Bprogrammer operated in the remote mode to the PC. Thedesign was then verified by checking out the device on thebench.SummarySpace Saving AdvantageThis design example illustrates the space saving advantageof Cypress CMOS PAL devices. The FUSEMAP programprinted out that 40 of the 64 available product terms wereused.If the P ALASM input equations of Figure 8 are implementedin two-input gates, approximately thirty gates arerequired for each one of the six D flip-flop inputs, or a totalof 6 X 30 = 180 two-input gates. The logic equationsalone would then require 180 divided by 4 = 45 14 pinDIPs. The six flip-flops would require three 14 pin DIPsfor a total of 48 DIPs. This example demonstrates the powerof the Cypress PAL devices.Power Saving AdvantageThe maximum Icc current, under worst case conditions,for the PAL C 16R6L-25PC is 45 mAoIf the typical Icc per package is assumed to be 10 mA, thetotal Icc for 50 TTL packages would be 500 mAoThe worst case Icc for the TTL system could be as high as20 mA per DIP, which would mean a total of one Amperefor the system.The Cypress CMOS PAL device results in a system powerreduction of between a factor of 10 or 15, depending uponwhether typical or worst case numbers are compared.P ALASM EquationsPAL16R6DESIGN EXAMPLEPATOOl4B-5B ENCODER/DECODERCYPRESS SEMICONDUCTORCK Ml MO D3 D2 Dl DO /EN /CIF GND/E SIN /INV YO Yl Y2 Y3 SOUT /BS VCC/SOUT:= EN*/SOUT/EN*/Ml*/MO*/SIN/EN*/Ml*MO*/YO/EN*/Ml*/MO*/SIN/EN*/Ml* MO* Dl*/DO/EN*/Ml* MO* D3*/DOFigure 8FILENAME; GCREX.PALBRUCE WENNIGER 9/17/85+ HOLD/RECIRCULATE+ SERIAL SHIFT IN+ SERIAL SHIFT OUT+ CONV. SIN Be LOAD+ CONV. PAR. ae LOADDITTO10-30

~ PAL® C 16R6 GCR Encoder/Decoder~~~~====================================================~========P ALASM Equations (Continued)IYO := EN*/YOIEN*/M1*/MO*/SOUTIEN*/M1* MO*/YlIEN* Ml*/MO*/SOUTIEN* Ml * IMO· Y3* Y2*/YOIEN* Ml* MO* D2*/D1*DOIEN* Ml* MO* D3*/D1* DOIEN* Ml* MO*/D3*/D1*/DOIYlIY2IY3INVBS:= EN* IYlIEN*/M1*/MO*/YOIEN*/M1* MO*/Y2IEN* Ml*/MO*/YOIEN* Ml*/MO* Y3* Y2IEN* Ml* MO*/D2:= EN* IY2IEN*/M1*/MO*/YlIEN*/M1* MO*/Y3IEN* Ml*/MO*/YlIEN* Ml* MO*/D3* DlIEN* Ml* MO*/D3* D2* DO:= EN*/Y3IEN*/M1*/MO*/Y2IEN*/M1* MO*/SOUTIEN* Ml*/MO* Y3* SOUTIEN* Ml*/MO*/Y2IEN* Ml* MO* D3* DOIEN* Ml* MO· D3* Dl:=/CIF* INVCIF* Ml*/MO*/Y3*/Y2CIF* Ml*/MO*/Y3/Yl*/YOCIF* Ml*/MO*/YO*/SOUTCIF* Ml*/MO* Y3* Y2* Yl* YO* SOUT= Y3* Y2* Yl* YO* SOUT++++++++++++++++++++++++++++Figure 8 (Continued)HOLDSEJUAL SHIFT INSERIAL SHIFT OUTCONV. SIN & LOADDITTOCONV. PAR. & LOADDITTODITTOHOLDSERIAL SHIFT INSERIAL SHIFT OUTCONV. SIN & LOADDITTOCONV. PAR. & LOADHOLDSERIAL SHIFT INSERIAL SHIFT OUTCONV. SIN & LOADCONV. PAR. & LOADDITTO~OLDSERIAL SHIFT INSERIAL SHIFT OUTCONV. SIN & LOADDITTOCONV. PAR. & LOADDITTOHOLD INV FLAG(ACTIVE LOW)SET IF INVALIDDITTODITTODITTOBIT SYNC.(ACTIVE LOW)10-31

~ PAL® C 16R6 GCR Encoder/Decoder~~~UcrOR==============================================================ABEL Listingmodule --gcrext;titleflag '-rO;'PAL16R6 DESIGN EXAMPLE FILENAME: GCREX.PALPATOOl4B-5B ENCODER/DECODERCYPRESS SEMICONDUCTOR-Translated by TOABEL-' ;P16R6 device 'P16R6';BRUCE WENNIGER 9/17/85"declarationsequationsTRUE,FALSE = 1,0;H,L = 1,0;X,Z,C = .X.,.Z.,.C.;GND,VCCpin 10,20;CK,Ml,MO,D3,D2,Dl,DO,EN,CIF,Epin 1,2,3,4,5,6,7,8,9,11;INV,YO,Yl,Y2,Y3,SOUTpin 13,14,15,16,17,18;SIN,BSpin 12,19;ISOUT := lEN & ISOUT# EN & IMl & IMO & ISIN# EN & IMl & MO & IYO# EN & Ml & IMO & ISIN# EN & Ml & MO & Dl & IDO# EN & Ml & MO & D3 & IDOII HOLD/RECIRCULATEII SERIAL SHIFT INII SERIAL SHIFT OUTII CONY. SIN & LOADII CONY. PAR. & LOADIIIYODITTO.- lEN & IYO# EN & IMl & IMO & ISOUT# EN & IMl & MO & IYl# EN & Ml & IMO & ISOUT# EN & Ml & IMO & Y3 & Y2 & IYO# EN & Ml & MO & D2 & !Dl & DO# EN & Ml & MO & D3 & !Dl & DO# EN & Ml & MO & !D3 & !Dl & !DO;Figure 910-32

~ PAL® C 16R6 GCR Encoder/Decoder~~~~UcrOR================================================================ABEL Listing (Continued)" HOLD" SERIAL SHIFT IN" SERIAL SHIFT OUT" CONV. SIN & LOAD"DITTO"CONV. PAR. & LOAD"DITTO"DITTOlYl.- lEN & lYl# EN & IMl & IMO & lYO# EN & IMl & MO & lY2# EN & Ml & IMO & lYO# EN & Ml & IMO & Y3 & Y2# EN & Ml & MO & !O2 ;"HOLD"SERIAL SHIFT IN"SERIAL SHIFT OUT"CONV. SIN & LOAD"DITTO"CONV. PAR. & LOADlY2 .- lEN & lY2# EN & IMl & IMO & lYl# EN & IMl & MO & lY3# EN & Ml & IMO & lYl# EN & Ml & MO & !O3 & Dl# EN & Ml & MO & !O3 & D2"HOLD"SERIAL SHIFT IN"SERIAL SHIFT OUT"CONV. SIN & LOAD"CONV. PAR. & LOAD"DITTOlY3:= lEN & lY3# EN & IMl & IMO & lY2# EN & IMl & MO & ISOUT# EN & Ml & IMO & Y3 & SOUT# EN & Ml & IMO & lY2# EN & Ml & MO & D3 & DO# EN & Ml & MO & D3 & DlFigure 9 (Continued)& DO10-33

~ PAL® C 16R6 GCR EncoderlDecoder~~~~==============================================================ABEL Listing (Continued)"HOLD"SERIAL SHIFT IN"SERIAL SHIFT OUT"CONV. SIN & LOAD"DITTO"CONV. PAR. & LOAD"DITTOIINV := CIF & IINV# ICIF & Ml & IMO & IY3 & IY2# ICIF & Ml & IMO & IY3 & IYl & IYO# ICIF & Ml & IMO & IYO & ISOUT# ICIF & Ml & IMO & Y3 & Y2 & Yl & YO & SOUT" HOLD INV FLAG" SET IF INVALID" DITTO" DITTO" DITTOIBS = Y3 & Y2 & Yl & YO & SOUT;" BIT SYNC.end --gcrext;Figure 9 (Continued)10-34

~ PAL® C 16R6 GCR Encoder/Decoder~~~~UcrOR==============================================================Document FileABELTM Version 1.10 - Document GeneratorPAL16R6DESIGN EXAMPLEPATOOl BRUCE WENNIGER 9/17/854B-5B ENCODER/DECODERCYPRESS SEMICONDUCTOR-Translated by TOABEL-Equations for Module --gcrextDevice P16R6Reduced Equations:SOUT := l( lEN & lSOUTYO .-Yl.-# EN & lMO & lMl & lSIN# EN & MO & lMl & lYO# EN & lMO & Ml & lSIN# lDO & Dl & EN & MO & Ml# lDO & D3 & EN & MO & Ml) ;l( lEN & lYO# EN & lMO & lMl & lSOUT# EN & MO & lMl & lYl# EN & lMO & Ml & lSOUT# EN & lMO & Ml & lYO & Y2 & Y3# DO & !Dl & D2 & EN & MO & Ml# DO & lDl & D3 & EN & MO & Ml# lDO & lDl & lD3 & EN & MO & Ml) ;1 ( lEN & lYl# EN & lMO & lMl & lYO# EN & MO & lMl & lY2# EN & lMO & Ml & lYO# EN & lMO & Ml & Y2 & Y3# lD2 & EN & MO & Ml) ;Y2.- l( lEN & !Y2Y3 .-INV =# EN & lMO & lMl & lYl# EN & MO & lMl & lY3# EN & lMO & Ml & lYl# Dl & lD3 & EN & MO & Ml# DO & D2 & lD3 & EN & MO & Ml) ;l( lEN & lY3# EN & lMO & lMl & lY2# EN & MO & lMl & lSOUT# EN & lMO & Ml & SOUT & Y3# EN & lMO & Ml & lY2# DO & D3 & EN & MO & Ml# Dl & D3 & EN & MO & Ml) ;1 (CIF & lINVFigure 1010-35Page 117-Sept-85 8:30 AMFILENAME; GCREX.PAL

~ PAL® C 16R6 GCR Encoder/Decoder~~~~u~==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Document File (Continued)Page 1ABELTM VERSION 1.10 - Document Generator17 Sept-85 8:30 AMPAL16R6DESIGN EXAMPLEFILENAME: GCREX.PALPAT001BRUCE WENNIGER 9/17/854B-5B ENCODER/DECODERCYPRESS SEMICONDUCTOR-Translated by TOABEL­Equations for Module --gcrextDevice P16R6# lCIF Be lMO Be M1 Be lY2 Be lY3# lCIF Be lMO Be M1 Be lYO Be lY1 Be lY3# lCIF Be lMO Be M1 Be lSOUT BelYO# lCIF Be lMO Be M1 Be SOUT Be YO Be Y1 Be Y2 Be Y3) ;BS = l(SOUT Be YO Be Y1 Be Y2 Be Y3) ;Chip diagram for Module --gcrextDevice P16R6Figure 10 (Continued)PALC16R6CKM1MO03020100ENCIFGNO1 Vee2 BS3 SOUT4 Y35 Y26 Y17 YO8 INV9 SIN10 11 Eend of module --gcrext0060-1510-36

~ PAL® C 16R6 GCR EncoderlDecoder~~~U~R==========================================================JEDECFileABELTM Version 1.10 JEDEC file for: P16R6Created on: 17-Sept-85 8:30 AMPAL16R6DESIGN EXAMPLEPAT0014B-5B ENCODER/DECODERCYPRESS SEMICONDUCTOR-Translated by TOABEL-*QP20* QF2048*LOOOO11111111111111111111111111111111111111011101110111011101111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111011111111111111111011111110111011111111111111111101111110101101111111111111111110011111110111101111111111111111110111111001110111111111110111101101111111011101110111111111111011011111110000000000000000000000000000000000000000000000000000000000000000111111111110111111111111101111111011101111111110111111110111111110110110111111111111111101111111011110011101111111111111011111110111101111111110111111110111111101110111011111111111011101111111011101110111111101111111011111110000000000000000000000000000000000000000000000000000000000000000111111111110111111111111101111111011101111111110111111110111111110110110111111111111111101111111011110011101111111111111011111110111101111111110111111110111111101111111111111111111011101111111011101110111111101111111011111110000000000000000000000000000000011111111111111101111111110111111FILENAME: GCREX.PALBRUCE WENNIGER 9/17/85Figure 11III10-37

~ PAL@ C 16R6 GCR Encoder/Decoder~~~ucr~==========================================================JEDEC File (Continued)101110111111111111101111011111111011011111101111111111110111111101111011111111111110111101111111011101111011111101111111011111110111011110110111111101110111111100000000000000000000000000000000000000000000000000000000000000001111111111111111111011111011111110111011111111111111111001111111101101111111111011111111011111110111101111111111111111100111111101111011110111011111111101111111011101111111101111111111011111110000000000000000000000000000000000000000000000000000000000000000111111111111111111111110101111111011101011111111111111110111111110110111111111111110111101111111011110111111111111111111011111110111101111011101111111100111111101110111111101111011011101111111011101110111111110110111011111110111011110111111101110110111111111111111111111111111111111100111011110111110111011111111111110110111101111101111111011101111101101111010111111111111111011111011011110011101110111011101111110110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*C8E51*D15AFigure 11 (Continued)10-38

CYPRESSSEMICONDUCTORUnderstanding FIFOsIntroductionFIFO is an acronym for First-In-First-Out.In digital electronics, a FIFO is a buffer memory that isorganized such that the first data entered into the memoryis also the first data removed from the memory.History of FIFOsSoftware FIFOsSoftware FIFOs have been (and are being) used extensivelyin computer programs where tasks are placed in queueswaiting for execution. In the programmers' language theprogram (process) that puts data into the memory is a"producer" and the program that takes data out is a "consumer".Obviously the producer and the consumer cannotaccess the memory simultaneously. It is the responsibilityof the programmer to insure that contention does not occur.Data transfer via a shared memory is a standard programmingtechnique but it is not feasible to have the processorin the data path for data rates greater than 5 Megabytesper second (MB/s). For higher data rates DMA,FIFO, or some combination of the two techniques are usedto transfer information.Hardware FIFOsIn the design of systems, once procedures are standardizedand verified in software, the software can be replaced withhardware. The benefits of doing this are improved performance,reduced software, ease of design and usually reducedcosts.Register ArrayThe first hardware FIFOs were of the "register array" architectureand included the serializer/deserializer(SERDES) within the IC. As they evolved, and due to theubiquitous microprocessor, the parallel input and paralleloutput configuration became the standard. For applicationsthat required SERDES users added external shift registers.The method of transferring data from one register to anotheris called a "bucket brigade". The transfer is controlledby a "valid data" bit (one per word) that designateswhich words have been written into but not yet read fromand combinatorial control logic. The time for this logic topropagate a word of data from the input to the output of aninitially empty FIFO is called "fallthrough time".Dual Port RamThe "second generation" of FIFOs are of the "dual portRAM" architecture. In order to achieve truly independent,asynchronous operation of inputs and outputs, the capabilityto read and write simultaneously must be designed intothe basic memory cell.The fall through time present in the register array organizationis eliminated by the RAM architecture. However, theRAM must be (internally) addressed, which requires twopointers. One points to the location to be written into andthe other points to the location to be read from. In addition,a bit is required for every FIFO word to designatewhich words have been written to but not yet read.ApplicationsFIFOs are used as building blocks in applications whereequipment that are operating at different data rates mustcommunicate with each other, i.e., where data must bestored temporarily or buffered.These include:• Word processing systems• Terminals• Communications systems; including Local Area Networks• EDP, CPU, and peripheral equipment; including diskcontrollers and streaming tape controllersThe Ideal FIFOThe characteristics of an ideal FIFO are:INPUTS• Infinitely variable input frequency (0 to infinity)• Infinitely variable input handshaking signalsOUTPUTS• Infinitely variable output frequency• Infinitely variable output handshaking signals10-39

~ Understanding FIFOs~~~~U~R==================================================================The Ideal FIFO (Continued)BOTH• Inputs and outputs are completely independent andasynchronous to each other, except that over-run orunder-run are not possible.STATUS INDICATORS• Full/empty• One-half full, Y4 full, Y4 emptyLATENCY• The latency should be zero. In other words, the datashould be available at the FIFO outputs as soon as it iswritten. In the empty condition this would be the nextcycle.EXPANSION• Expandable word length and depth without externallogic and without performance degradation.NO FALLTHROUGH OR BUBBLETHROUGH TIMEAnalysis of Present ArchitecturesRegister ArrayThe first Integrated Circuit FIFOs were an extension of thesimplest FIFO of all; a serial shift register.Input StageAs illustrated in Figure 1, the input stage is a one word bym-bit parallel shift register that is under control of the inputhandshaking signals SI (Shift In) and IR (InputReady).Output StageThe output stage is also a one word by m-bit parallel shiftregister that is under control of the output handshakingsignals OR (Output Ready) and SO (Shift Out).Register ArrayThe middle N-2 X m-bit registers are controlled by signalsderived from the preceding control signals.Valid DataA flag bit is associated with each word of the FIFO inorder to tell whether or not the data stored in that word isvalid. The usual convention is to set the bit to a one whenthe data is written and to clear it when the data is read.Fallthrough and BubblethroughThe preceding statements regarding input and outputstages are not precisely correct under two special conditions,which occur when the FIFO is empty and full:EMPTY CONDITION - FALLTHROUGHIn the empty condition the data must enter the inputstage and propagate to the output stage. This is calledFallthrough time and it limits the output data rate.FULL CONDITION - BUBBLETHROUGHWhen the FIFO is full and one word is read, all of theremaining words must move down one word (or theempty word must propagate to the input). This iscalled Bubblethrough time and it limits the input datarate.As we shall see, Bubblethrough time and Fallthrough timeare usually equal because the same logic is used.Dual Port RAM ArchitectureThe dual port RAM architecture refers to the basic memorycell used in the RAM. By adding read and write transistorsto the conventional two transistor RAM cell, the readand write functions can be made independent of each other.Obviously this increases the size of the RAM cell, butdoing this is more than compensated for by simpler controllogic and improved performance.The RAM requires two address pointers; one to addressthe location where data is to be written and the other toaddress where data is to be read. Comparators are used tosense the empty and full conditions and control logic isrequired to prevent over-run and under-run.1 WORDN-2WORDS1 WORDOUTPUT DATAFigure 1. Register Array Architecture0044-110-40

~ Understanding FIFOs~~~U~ =====================================================================Analysis of FIFOsThe procedure will be to first analyze the FIFO as a "blackbox" and then to compare the most important characteristicsof a class of representative FIFOs with the characteristicsof the CY7C401 FIFO.The class of FIFOs chosen is the industry standardXXX401A and XXX402A that are available from severalsources. The 401 is 64 x 4 and the 402 is 64 x 5 with thesame performance. Both are of the register array architecture.Both are expandable in depth (number of words),which is called cascadeable, without additional logic aswell as expandable in word width (number of bits perword) with additional logic. The operation will first be analyzedin the standalone configuration.Functional DescriptionData Input - Refer to Figures 2, 3After power-on the Master Reset (MR) input is pulsedLOW to initialize the FIFO. When the IR output goes highit signifies that the FIFO is able to accept data from theproducer at the DI inputs. Data is entered into the inputstage when the SI input is brought high (if IR is also high).SI going high causes IR to go low, acknowledging receiptof the data, which is now in the input stage.When SI goes low (in response to IR going low) and if theFIFO is not full, IR will go back high, indicating that moreroom is available in the FIFO. At the same time SI goeslow data is propagated to the next empty location, whichfFl0SHIFT IN + ED ,.......'~~'------.'may be the second location, but could be any location up tobut not including the output stage.Data Output - Refer to Figures 4, 5Data is read from the DO outputs of the output stage undercontrol of the SO and OR handshaking signals. Thehigh state of OR indicates to the consumer that valid datais available at the outputs. When OR is high, data may beshifted out by bringing the SO line high (request), whichcauses the OR line to go low (acknowledge). Valid data ismaintained on the outputs as long as SO is high. When SOgoes low (in response to OR going low) and if the FIFO isnot empty, OR will go back high, indicating that there isnew valid data at the outputs. If the FIFO is empty ORwill remain low and the data on the outputs will notchange.Empty/FullIf the FIFO is empty, OR will not go high within a fallthroughtime after SO goes low, so this condition may besensed and used to indicate EMPTY.Similarly, if the FIFO is full, IR will not go high within abubblethrough time after SI goes low, so this conditionmay be sensed and used to indicate FULL.Standalone OperationInput Data Setup and HoldThe input data must be stable for an amount of time equalto the setup time (tms) before the rising edge of SI andtD - - __ .ill..INPUT READY ~~ Lgy""--~~INPUT DATA 2QDf-STABLE DATAY

~ Understanding FIFOs~~~NDUcroR ~~~~~~~~~~~~~~~====~~~~~~~~~~~~~==~~===Analysis of FIFOs (Continued)~ ,¥e~----+I..'--------:¥P~"''-- _-3:::::~____ ~ ___ 5...LSHIFT OUT -----j-' 1 + -OUTPUT READY ~~"""'1_ _ _ _ __OUTPUT DATA ------A---D-AT-A------..,*tiUi,~I-A OR B-10044-4Figure 4. The Method of Shifting Data Out of the FIFONotes:EEl External "consumer" response time.® Output Ready goes LOW.+ SO pulse could be of fixed positive duration and would then not@ Contents of word 52 (B-DATA) is released to propagate to word 53.depend upon response time of consumer.® Output Ready goes high indicating that new data (B) is now available(i) Output Ready high indicates that data is available and a Shift Outat the FIFO outputs.pulse may be applied.@ Ifthe FIFO has only one word loaded (A-DATA) then Output® Shift Out goes high causing the next step.Ready stays LOW and the A-DATA remains unchanged at the outputs.SHIFT OUTOUTPUT READY ----I.......-+~~"'"Figure S. Output Timing for Register Array FIFO0044-5Notes:(i) The diagram assumes that, at this time, words 63,62,61 are loadedwith A, B, C Data respectively.remain stable for an amount of time equal to the hold time(tIDH) after the rising edge of SI.tIDS = 0 nstIDH = 40nsInput TimingFigure 3 shows the timing relationships between the inputdata and the handshaking signals when operating at themaximum input data rate of 15 MHz. The Input Readysignal lags (follows) the rising edge of the Shift In signal by40 ns (max.) for this two edge handshake.Fallthrough TimeFigure 2 shows the method of entering data into the FIFO.The fallthrough time (Figure 6) is measured from the fallingedge of the SI signal to the rising edge of the IR signal.For a 15 MHz Register Array FIFO, this time is specifiedas tpT = 1.6 p,s (microseconds).® Data in the crosshatched region may be A or B Data.Register Array Propagation Delay TimeThe register array propagation delay time may be approximatedby using the delay from the falling edge of the SOsignal to the rising edge of the OR signal as being representativeof the. data propagation delay through the outputstage and subtracting this from the fallthrough time.Reg. Prop. Delay =Fallthrough time -Output Prop. Delay TimeThe delay per stage is then calculated by dividing the registerarray propagation delay time by the number of stagesthe data propagates through.Reg. Prop. Delay = 1.6 p,s -Delay per stage= 1.55 p,s= 1.55 p,s64 - 2= 25 ns50 ns10-42

Understanding FIFOsAnalysis of FIFOs (Continued)Output TimingFigure 5 shows the timing relationships between the outputdata and handshaking signals when operating at the maximumoutput data rate of 15 MHz. The Output Ready signallagsthe Shift Out signal by 45 ns (max.) for this twoedge handshake. Data is shifted to the output stage on thefalling edge of SO, but does not stabilize until 45 ns later.OR goes low in response to SO going high (45 ns later) andthen goes back high 50 ns (max) after the high to lowtransition of SO.The reader may assume that the (new) output data is valid50 - 45 = 5 ns before the rising edge of the OR signal, butthis is incorrect. The data sheet specifies these two numbersonly as maximums and not also as minimums. Evaluationof these FIFOs has revealed that the data may changeseveral nanoseconds AFTER the rising edge of the ORsignal.The consumer is responsible for delaying the rising edge ofthe SO signal in order to satisfy his data setup time requirements,which may further reduce the throughput.Full ConditionThe maximum propagation delay from SI going low untilIR goes high is 40 ns (Figure 3). The bubblethrough timefor the full condition is illustrated in Figure 7. This time,tpT, is specified as 1.6 p.s on the data sheet. The delay perstage is calculated by subtracting 40 ns from 1.6 p.s anddividing by the number of stages (64 - 2).Delay per stage =Bubblethrough time -Number of stages25.16 nsBubblethrough TimeOutput Delay time1.6 p.s - 0.04 }J-s64 - 2The bubblethrough timing is illustrated in Figure 7. It isseen to be equal to the fallthrough time.SHIFT ININPUT READY -----1--+--""SHIFT OUTtpT (5)-1.6J1.S--+--'I r If!? ptoPH_I-----­\OUTPUT READY "'"""---------------..1- 1 _~30nsFigure 6. Falltbrough TimingNotes:

~ Understanding FIFOs~~~U~==================================================================Analysis of FIFOs (Continued)Maximum Throughput CalculationsThe maximum throughput of the FIFO is seen to be limitedby the fallthrough time when it is empty and the bubblethroughtime when it is full.The "throughput period" corresponding to the "standaloneperiod" (tA) and the fallthrough time (tF) is:Tmax. = tA + tFConverting to frequency yields1 1--=-+tFFmax. FARearranging and solving for Fmax yields1Fmax= ---EQ.lI-+tFFAThe expressions for the throughput frequencies for theFIFO under the full and empty conditions are then;EMPTY FIFOFULL FIFOFin = Fin (max.)1Fout = -1----+tFFAF out = Fout (max.)11-+tFFAThe maximum throughput that can be handled by a "nearlyempty" or a "nearly full" FIFO operating in the standalonemode is then:1F (max.) = -1----+tFFA1F (max.) = 1 = 1.667 fJ-s--- + 1.6fJ-s15 MHzF (max.) = 599.88 kHzNote that this is considerably less than the 15 MHz specifiedon the data sheet.FULLNESS SENSITIVITY (STANDALONE)The number of words written into the FIFO correspondingto the fall through time if the input data rate is at the maximum(15 MHz) is:Fin 15 MHz--...:::.::..-- = --- = 24 words. EQ. 2F fallthrough 11.6 fJ-sSince the bubblethrough time is the same as the fallthroughtime (in this case) the same number of words can be outputat the maximum data rate from a full FIFO.What this means is that the FIFO can operate at its maximumdata rate (15 MHz) only when it is between 24 wordsand 64 - 24 = 40 words full. In order to NOT be sensitiveto its fullness, the FIFO must be operated at a maximumfrequency less than or equal to the frequency correspondingto the fallthroughlbubblethrough time (625 KHz).Cypress proposes defining a Fullness Sensitivity (FS) figureof merit for FIFOs that is a measurement of the capacityrange (or fullness) over which the FIFO can be operated atits maximum input rate AND its maximum output rate.The FS is normalized; one (1) is ideal and 1 > FS > O.FS =N - FIA tF - FOA tBNWhere: FS = Fullness SensitivityN = The number of words in the FIFOEQ.3FIA = Standalone maximum input frequencytF= Fallthrough timeFOA = Standalone maximum output frequencytB= Bubblethrough timeAs an example we will calculate FS for a typical registerarray FIFO.FIA = FOA = 15 MHztF = tB = 1.6 fJ-sN = 64 words64-15X 106 X 1.6X 1O-9 -15X 106 X 1.6X 10-9FS = ----------------6464-24-24FS=-----64FS = 0.25If the partial products would have had fractional parts wewould have rounded them up to the next highest integers.FIFO ExpansionThe interconnection of two 64 word FIFOs to form a 128 x4 FIFO is shown in Figure 8. Observe that the OR outputof the first FIFO becomes the SI input of the second FIFOand that the IR of the second becomes the SO input to thefirst.What this means is that the bubblethrough/fallthroughtimes serially add when the FIFOs are cascaded.The maximum throughput that can be handled by twoFIFOs cascaded together is:F(max.) = 1- + 2tFFAF(max.) = 306 KHzWhere, as before, FA = 15 MHz, tF = 1. 6 fJ-s.10-44

~ Understanding FIFOs~~~~u~==================================================================Analysis of FIFOs (Continued)In general, when N FIFOs are cascaded together, the maximumthroughput of the combination is:1F(max.) = 1 EQ.4-+ NtFFAThe FS is also affected by the cascading of FIFOs. If NFIFOs are cascaded together the number of words that canbe output or input is N times that of the standalone condition.Fin = FAF fallthrough 1EQ.5NtFIf this number is greater than the actual (physical) FIFOdepth it means that the FIFO cannot be operated at itsmaximum frequency.To make a wider word, as well as a deeper FIFO, connectthe FIFOs as illustrated in Figure 9. Composite IR and ORsignals must be generated using two external AND gates(e.g., 74LS08) to compensate for variations in the propagationdelay of these signals from device to device. The max-imum throughput for this configuration is 205 KHz(N = 3 in preceding formula).Cascadability ConsiderationsIn order to guarantee the ability of multiple FIFOs to reliablycascade with each other using the handshaking methodpreviously described, certain conditions must be met.These are now considered.SI or OR Signal CompatabilityIn the cascaded configuration, the OR signal of the NthFIFO must be specified such that it can be detected when itis applied to the SI input of the N + lth FIFO. See Figure8. This means that the minimum high time (positive pulsewidth) of the OR output signal of the input FIFO must beable to be recognized at the SI input of the output FIFO.IR and SO Signal CompatabilityIn the cascaded configuration, the IR output of the N + I thFIFO must be specified such that it can be detected when itis applied to the SO input of the Nth FIFO.Minimum Delay Between SI and IRThe minimum delay between SI going HIGH and IR goingLOW is an unspecified parameter in the industry standardSHIFT ININPUT READYt.lR----+~SIORIRSO01 0 0°0011 00101 2 0°201 3 - 00t.lR 3YSIIR01 001101 201 3.!..t.lRYORSO0°00°10°20°3OUTPUT READYSHIFT OUT] DATA OUT0044-8Figure 8. 128 x 4 FIFOFigure 9.192 x 8 FIFO0044-910-45

~ Understanding FIFOs~~~~UaoR~~~~~~~~~~==============================================Analysis of FIFOs (Continued)data sheets. The Cypress FIFO exhibits a 6 to 10 ns minimumdelay. Care must be taken when mixing Cypress FI­FOs and competitive FIFOs to insure that the parts willcascade with one another. In general, delaying the IR outputof the Cypress FIFOs enables competitive parts to cascadewith Cypress parts. The Cypress FIFO can alwaysrecognize the output of the competitive product.Minimum Delay Between OR and SOAnother unspecified industry parameter is the delay betweenOR and SO. The minimum delay for Cypress FIFOsis 6 ns. A 500 pF capacitor added between the OR pin andground and the IR pin and ground of all Cypress FIFOswill permit cascading with competitive FIFOs. These capacitorsdelay the signals the appropriate amount of time.Product Configuration tFCY7C401 64x4 65 nsCY7C403 64x4 65 nsCY7C402 64x 5 65 nsCY7C404 64x 5 65 nsCascading at the Operating FrequencyIn order to operate at a given frequency, Fa, in the cascadedconfiguration the following relationship must be satisfied;1tSIH + tIRH < - FaThis condition is met by both the MMI and CypressFIFOs.Description of the CY7C401A block diagram of the CY7C401 is shown in Figure 10. Itis a direct, pin for pin, functional equivalent, improved performance,replacement for the register array FIFOs. Thesimilarities and differences between the 401,402,403, and404 are summarized in the table.PackageDescription16 pin DIP Industry Standard16 pin DIP Pin 1 is three-stateoutput enable18 pin DIP Industry Standard18 pin DIP Pin 1 is three-stateoutput enableIRWRITE PTR.DATA01-. INCONTROLMUX INDOORFigure 10. CY7C401 Block Diagram0044-1010-46

Understanding FIFOsDescription of the CY7C401 (Continued)Architecture Refer to Figure 10The architecture is that of a dual port RAM, which isaccessed by two pointers; a read pointer and a write pointer.The input data and output data do not reside in input oroutput registers as in the register array architecture. Instead,the pointers address the memory locations of theinput and output data. Comparators are used to control theIR and OR lines to prevent overflow and underflow. Thekey to this architecture is the dual port RAM cell, which isillustrated in Figure 11. It is only 1.2 square mils in area.Separating the read and write functions enables the memorycell to be read from and written to simultaneously andindependently. This increases the basic cell size, but simplifiesthe overall architecture and improves the performance.The bubblethrough time is greatly reduced (65 ns versus1.6 p,s) because it now represents the time required to updatethe pointers, not the time required for data to propagatethrough the memory array.Figure 11A. CY7C401 Ram Cell Layout0044-1101 DO R R DO Di.1 .1Figure 11B. Cell Schematic0044-1210-47

~ CYPf?FSSUnderstanding FIFOs~~I~~============================================~==~~~~~~~Description of The CY7C401 (Continued)Functional DescriptionTo the "outside world" the CY7C401 appears functionallye

~ Understanding FIFOs~~~~UcrOR=====================================================================Comparison of Register Array FIFO's and the CY7C401 (Continued)101.0CY7C401-15~ CY7C401-250.8~:>i=~ 0.6LLIIf)If)If)~ 0.4....I....I:;)Lo..0.2\.. 0.96875o 500 1000 1 500 2000FIFO DEPTH IN WORDS0044-13Figure 12. Maximum FIFO Throughput vs. Depthoo 10 20 30 40 50 60FIFO DATA IN WORDS0044-14Figure 13. Fullness Sensitivity in the Standalone ModeNI-161412a::LLI:I: 10

~ Understanding FIFOs~~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===Summary and ConclusionsIn most systems where FIFOs are used they are neither fullnor empty, except at the beginning or end of an operation.After analyzing the preceding two FIFOs the reader canunderstand why. Serious performance degradation occursunder these conditions, especially if the FIFO uses the registerarray architecture. To compensate for this, manufac-turers have added one-half empty/full indicators (etc.),which has helped by alerting the system controller beforethe performance suffers.A better solution to the performance problem is to use aFIFO that has the dual port RAM architecture, which hasbeen shown to result in a superior performance FIFO.10-50

CYPRESSSEMICONDUCTORInterfacing to the FIFOApplication BriefIntroductionThis application brief is intended to be a guide to the FIFOuser and to make him aware of certain conditions thatshould be considered when interfacing to the FIFO. Thetwo areas of concern are (1) voltage sensitivity on theSI and SO inputs and, (2) metastability when the SI or theSO signals are derived from independent clocks. Thesetwo issues are independent of each other. All commentsapply to the following Cypress CMOS FIFOs:CY7C4011402/403/404, CY7C3341, CY7C40S/409.High Gain InputsThe minimum positive SI and SO pulse widths are specifiedon the FIFO data sheet as 11 ns (25 MHz SI/SO) and20 ns (other speed grades). At room temperature and nominal(5V) Vee the FIFO will operate reliably with SI/SOpulses as short as 5 ns. The reason these FIFOs respond tosuch short pulses is that the Cypress high performanceCMOS process yields circuits that have very high gainsand, consequently, require very little energy to changestate.Termination networks are recommended on the SI and SOlines (traces) on Printed Circuit Boards (PCBs) when thelines exceed seven inches in length (from source to load).The termination matches the load impedance to the characteristicimpedance of the PCB trace, which is typically50n or less for microstrip or stripline construction on G-lOglass epoxy material. For minimum voltage reflections aslightly overdamped termination is preferred. Cypress recommendsa series capacitor of lO pF and resistor of 47n beconnected from the input pin (SI/SO) to ground as shownin Figure 1. This termination network acts as a low passfilter for short, high frequency pulses and dissipates no DCpower. If more than one FIFO is connected in parallel tomake a wider word only one termination network is required.It should be located at the input that is electricallythe farthest away from the source.Synchronous And AsynchronousOperationWhen the SI and SO signals are derived from a commonfrequency source (or clock) the FIFO is, by definition, operatingin the synchronous mode. There is a precise, knownrelationship between the SI and SO signals.Conversely, when the SI and SO signals are d~rived fr?mtwo independent frequency sources, the FIFO IS operatmgin an asynchronous mode.In the synchronous mode the designer can assure that theOR signal not occur within the setup and hold time windowthat normally "surrounds" the output system clockedge (or sampling signal). The same reasoning applies tothe occurance of the IR signal with respect to the inputsystem clock.In the asynchronous mode, the designer cannot assure aknown relationship between the OR signal and the outputsystem clock either with respect to frequency or with respectto phase. It is the responsibility of the designer toinsure that, even though the output system clock edge mayoccur at the same time that the OR signal occurs, theFIFO still receives a SO clock that is wide enough to bereliably recognized as such by the FIFO. The same reasoningapplies to the SI signal that is generated in response tothe IR signal under control of the input system clock.AB10pF I470Ht.lS ~CYPRESSFIFOORCLK"'---+-!SOFigure 1. Recommended Termination Network0097-1Figure 2. Pulse Synchronizer0097-2lO-51

~ Interfacing to the FIFO Application Brief~~~U~================================================================Pulse SynchronizerThe circuit of Figure 2 is recommended to generate the SOpulse as a function of OR under control of the output systemclock. An identical circuit should be used to generatethe SI pulse as a function of IR under control of the inputsystem clock. If it is required to perform control functionson the OR or the IR signals, it should be done before theyare clocked by the first D flip-flop.State DiagramThe two stage shift register is analyzed as a state machinein Figure 3. Other, more complex state machines can bedesigned, but the idea is the same; reliably generate a singlepulse of a known minimum width for every OR or IRLOW to HIGH transition.Figure 3. Pulse Synchronizer State DiagramTransition TableA B STATE DESCRIPTIONr-+ 0 0 0 IDLE AT STATE 01 0 1 GENERATE SO = 11 1 3 GENERATE SO = 0........ 0 1 2 TRANSITION STATE0097-30097-4Design ConsiderationsThe frequency of the clock to the pulse synchronizershould be at least twice that of the maximum rate data isshifted into or out of the FIFO.For example, if it is required to shift data into the FIFO ata 10 MHz (SI) rate, the clock to the input pulse synchronizershould be 20 MHz. If it is required to shift data out ofthe FIFO at a 15 MHz (SO) rate the clock to the outputpulse synchronizer should be 30 MHz.Minimum SI/SO Pulse WidthThe minimum pulse width of the SO signal of Figure 2under normal operating conditions will be one cycle of theoutput clock (CLK). However, when the OR or the IRsignal changes within the "unallowed window" around theclock edge, defined by the flip-flop setup time and holdtime, the flip-flop may go into a metastable state. i.e., itsoutputs may be between the logic ONE and the logicZERO voltage levels. The amount of time the flip-flop willstay in the metastable region will be approximately 4 X,where X = clock to output propagation delay time.The minimum pulse width of the SO signal is determinedby the delay, d, through the NOR gate, plus any delay thedesigner may add (D, shown as a box) in the path from the/Q output of the A flip-flop to the input of the NOR gate.The NOR gate acts as a low pass filter and will not pass apulse if its width is less than d. Adding an external delay,D, increases the minimum pulse width to d + D. Themaximum frequency that the circuit can operate at, assumingequal gate tum-on and tum-off times, is then1f(max.) = 2 (d + D)·The total delay should be chosen such that the minimumpulse width is sufficient to reliably be detected by theFIFO. The preceding comments apply to lumped delays,not to analog or distributed delay lines.Implementation Of The DelayIf only the NOR gate provides the delay, the followingtable lists typical and maximum propagation delays undernominal Vee and loading (20 pF) conditions.Table 1. Propagation Delay in nsFamily Typical MaximumLS 10 15ALS 5 11HCMOS 8 23FACT 5 9.5A 74LS02 NOR gate will result in a minimum pulse widthof 10 ns, which will reliably operate a 25 MHz CY7C403or a CY7C404 FIFO.If it is required to operate a 10 MHz CY7C401!402, the Qoutput of the A flip-flop may be inverted through a 74LS04and applied to the lower input of the NOR gate. The minimumpulse width is then 10 + 10 = 20 ns.A delay line or a RC network could also be used to delaythe signal to the lower input of the NOR gate.The circuit of Figure 2 can also be used to synchronize theSI and SO inputs of the CY7C334l.The rising edge of the SO signal should be used to samplethe FIFO data.10-52

IntroductionPower Characteristics ofCypress ProductsSCOPE AND PURPOSEThis document presents and analyzes the power dissipationcharacteristics of Cypress products. The purpose of thisdocument is to provide the user with the knowledge andthe tools to manage power when using Cypress CMOSproducts.DESIGN PHILOSOPHYThe design philosophy for all Cypress products is toachieve superior performance at reasonable power dissipationlevels. The CMOS technology, the circuit design techniques,architecture and the topology have been carefullycombined in order to optimize the speed/power ratio.SOURCES OF POWER DISSIPATIONPower is dissipated within the integrated circuit as well asexternal to it. Both internal and external power have aquiescent (or DC) component and a frequency dependentcomponent. The relative magnitudes of each depend uponthe circuit design objectives. In circuits designed to minimizepower dissipation at low to moderate performance,the internal frequency dependent component is significantlygreater than the DC component. In the high performancecircuits designed and manufactured by Cypress, theinternal frequency dependent power component is muchless than the DC component. The reason for this is that alarge percentage of the internal power is dissipated in linearcircuits such as sense amplifiers, bias generators and voltage/currentreferences that are required for high performance.External Power DissipationThe input impedance of CMOS circuits is extremely high.As a result, the DC input current is essentially zero (10 J-LAor less). When CMOS circuits drive other CMOS circuitsthere is practically no DC output current. However,when CMOS circuits drive either bipolar circuits or DCloads, external DC power is dissipated. It is standard practicein the semiconductor industry to NOT include the currentfrom a DC load in the device Icc specification.Cypress supports this practice. It is also standard practiceto NOT include the current required to charge and dischargecapacitive loads in the data sheet Icc specification.Cypress also supports this standard practice.Frequency Dependent PowerCMOS integrated circuits inherently dissipate significantlyless power than either bipolar or NMOS circuits. In theideal digital CMOS circuit there is no direct current pathbetween V cc and V ss; in circuits using other technologiessuch paths exist and DC power is dissipated while the deviceis in a static state.The principal component of power dissipation in a poweroptimizedCMOS circuit is the transient power required tocharge and discharge the capacitances associated with theinputs, outputs, and internal nodes. This component iscommonly called CV2f power and is directly proportionalto the operating frequency, f. The corresponding current isgiven by the formulaIcdt) = CVf.The primary sources of frequency dependent power are dueto the capacitances associated with the internal nodes andthe output pins. For "regular" logic structures, such asRAMs, PROMs and FIFOs the internal capacitances are"balanced" so that the same delay and, therefore, the samefrequency dependent power is dissipated independent ofthe location that is addressed. This is not true for programmabledevices such as PALs because the capacitive loadingof the internal nodes is a function of the logic implementedby the device. In addition, PALs and other types of logicdevices may contain sequential circuits so the input frequencyand the output frequency may be different.The capacitance of each input pin is typically 5 pF, so itscontribution to the total power is usually insignificant.Note:The Cypress Power/Speed Program, which implements the equations in this application note, is available from Cypress for your use on personalcomputers.III•PAL® is a registered trademark of Monolithic Memories.10-53

~ Power Characteristics~~~UcroR =====================================================================Introduction (Continued)Derivation of Applicable EquationsThe charge, Q, stored on a capacitor, C, that is charged toa voltage, V, is given by the equation;Q = CV.EQ.lDividing both sides of equation 1 by the time required tocharge and discharge the capacitor (one period or T)yields;EQ.2By definition, current (I) is the charge per unit time and1f= -.TTherefore,1= CVf. EQ.3The power (P = VI) required to charge and discharge thecapacitor is obtained by multiplying both sides of equation3 byV.P = VI = CV2fEQ.4It is standard practice to make the assumption that thecapacitor is charged to the supply voltage (V cd so thatP = VeeI = C [Vec1 2 f EQ.5The total power consumption for a CMOS integrated circuitis dependent upon:• the static (quiescent or DC) power consumption.• the internal frequency of operation• the internal equivalent (device) capacitance• the number of inputs, their associated capacitance, andthe frequency at which they are changing• the number of outputs, their associated capacitance,and the frequency at which they are changingIn equation form:PD = [(CIN) (FIN) + (CINT) (FINT) + (CLOAD) (FLOAD)][Vee]2+ IcC (quiescent) Vee.EQ.6The first three terms are frequency dependent and the lastis not. This equation can be used to describe the powerdissipation of every IC in the system. The total systempower dissipation is then the algebraic sum of the individualcomponents.The relative magnitudes of the various terms in the equationare device dependent. Note that equation 6 must bemodified if all of the inputs, internal nodes or all of theoutputs are not switching at the same frequency. In thegeneral case, each of the terms is of the form C 1 F 1 +C2 F2 + C3 F3 + ... Cn Fn. In practical reality theterms are estimated using an equivalent capacitance andfrequency.Transient Power: Input Buffers and InternalIn the N-well CMOS inverter, the P-channel pullup transistorand the N-channel pulldown transistor (which are inseries with each other between Vee and V ss) are never onat the same time. This means that there is no direct currentpath between Vee and ground, so that the quiescent poweris very nearly zero. In the real world, when the input signalmakes the transition through the linear region (i.e., betweenlogic levels) both the N-channel and the P-channeltransistors are partially turned ON. This creates a low impedancepath between Vee and V ss, whose resistance isthe sum of the N-channel and P-channel resistances. Thesegates are used internally in Cypress products.DC or Static PowerIn addition to the conventional gates there are sense amplifiers,input buffers and output buffers, bias generators andreference generators that all dissipate power. The RAMsand FIFOs also have memory cells that dissipate standbypower whether the IC is selected or not. The PROM andPAL® products have EPROM memory cells that do notdissipate as much standby power as a RAM cell.Power Down OptionsMany of the Cypress static RAMs have power down optionsthat enable the user to reduce the power dissipation ofthese devices by approximately an order of magnitudewhen they are not accessed. The technique used is to disableor tum-off the input buffers and the sense amplifiers.Worst Case Device Power SpecificationsAll Cypress products are specified with Icc under worst,worst, worst case conditions. This means that the Veevoltage is at its maximum (5.5V), the operating temperatureis at its minimum, which is O°C for commercial productand - 55°C for military product and all inputs are atVIN = 2V.Icc TEMPERATURE DEPENDENCEFor all Cypress products operating under all conditions,the Icc current increases as the temperature decreases. TheIcc temperature coefficient is -0.12% per DC. To calculatethe percentage change in Icc from one temperature toanother, this temperature coefficient is multiplied by thetemperature difference.If, for example, it is required to calculate the expected reductionin Icc if either a commercial or a military gradeCypress IC is operated at room temperature (25°C), thecalculations are:For commercial products[0 - 25] X [-0.12%] = 3% less Icc at room temperaturethan at O°C.For military products[-55 - (25)] X [-0.12%] 9.6% less Icc at roomtemperature than at - 55°C.ProcedureThe procedure will be to develop a general purpose powerdissipation model that applies to all of the Cypress CMOSproducts and to then present tables so that users can estimatetypical and worst case power dissipations for eachproduct. The data will be presented in chart form as functionsof product type and capacitance, that is: SRAM,PROM, PAL or Logic; including FIFOs.to-54

~ Power Characteristics~~~NDUcroR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=INPUTSn;'::t~INPUT ..COREmOUTPUT I ..BUFFERS .,L BUFFERS '.,L~CIN ~CINT ~CLOUTPUTSPower Dissipation ModelA general purpose power dissipation model for all Cypressintegrated circuits is shown in Figure 1.The procedure will be to isolate the four components ofpower dissipation described by equation 6 by controllingthe inputs to the IC. The quiescent (Icd current is measuredwith the inputs to the IC at O.4V or less. Under thiscondition the input buffers and output buffers (unloadedDC wise) draw only leakage currents. All other direct currentsare due to the substrate bias generator, sense amplifiers,other internal voltage or current references and NMOSmemory circuits.At VIN = 1.5V the input buffers draw maximum Icc current.The total current is measured and the quiescent currentsubtracted to find the total input buffer Icc current.The current per input buffer is then calculated by dividingthe total input buffer current by the number of input buffers.INPUT BUFFERSThree different types of input buffers are used in Cypressproducts. For purposes of illustration they are referred toas types A, Band C. Table 1 lists the maximum ICCs.BufferTypeTable 1. Types of Input BuffersICC(max. iR mA)A 1.3B 0.8C 0.6The schematics and input characteristics for the threetypes of buffers are illustrated in Figure 2. A circle on thegate of a transistor means that it is a P-channel device.As can be seen from the figure, the input buffers drawessentially zero Icc current when VIN is 0.4V or less orFigure 1. Power Dissipation Model0059-1(except for type A) when VIN is 4V or more. In otherwords, if the inputs are driven "rail to rail" the Band Cinput buffers will dissipate power only during the inputsignal transitions.To reach these levels the input pins should be either drivenby a CMOS driver or by a TTL driver whose output doesnot drive any other TTL inputs.When the inputs are driven by the minimum TTL levels(VIR = 2V, VIL = 0.8V) each input buffer draws 20%more ICC current than if it were driven rail to rail.1.3o '-_~..L.Figure 2AVOUT__-L___o 0.6 2.0VIN (V)Figure 2BType A0059-30059-410-55

~ Power Characteristics~~~~~~~~~~~~~~~============================================Power Dissipation Model (Continued)DUTY CYCLE CONSIDERATIONSThe input characteristics of the type B (Figure 2D) and thetype C (Figure 2F) buffers may be approximated by trianglessymmetric about the VIN = 1.5V points, whose amplitudesare 0.8 rnA and 0.6 rnA, respectively. Therefore, betweenthe VIN = 0.5V and VIN = 3.5V points the averagecurrent is one-half the peak current, or 0.4 rnA and0.3 rnA, respectively. In most systems the input signal slewrates are one-half volt per nanosecond or greater so theinput transitions occur quickly. Under these conditions theduty cycle of the input buffers must be considered.0.8veeFigure 2Co--~~--~----~--~o 0.5 1.5 3.5 4.0v,. 1VIN (V)Figure2DTypeDveeFigure2E0059-70059-50059-60.6O __-=:;..L--__---JL--__---J~__o 0.5 1.5 3.5VIN (V)Figure 2FTypeC0059-8For example, if the CY7C167-35 RAM were used withinput signals having a slew rate of one-half volt per nanosecondit would take1[3.5V - 0.5V] X -- = 6 ns0.5V/nsfor the input signals to go through the 3V transition. Duringthe transition each input buffer would be drawing0.3 rnA of current from the Icc supply. However, this timeis only 6 ns/35 ns = 0.17 or 17% of the access cycle.Therefore, the actual input buffer transient current is only0.17 X 0.3 rnA = 0.051 rnA. It will be shown that this isinsignificant in most power calculations.INPUT BUFFER FREQUENCYDEPENDENT CURRENTThis is the current required to charge and discharge thecapacitance associated with each input buffer. The capacitanceis typically 5 pF and the voltage swing is typically4V.Using equation 3;1= CVflec(t) = 5 X 10-12 X 4 X f.Iec(t) = 20 X 1O- 12f.CORE AND OUTPUT BUFFERSThe memory core will have a standby power dissipationdue to the substrate bias generator, reference generators,sense amplifiers, and polyload RAM cells or EPROMcells. This current is measured with VIN = OV, so that theinput buffers draw no current. Under these conditions theoutput buffers will draw only leakage current and dissipateessentially no power.The output buffers have N-channel pullup devices thatcause the output voltage level to reach VOH = Vee - IV.The capacitance of the output buffers, including stray capacitance,is typically 10 pF.IfCL = 10 pF, VOH ~ 4V.Again, using equation 3, Iec(t) = 40 X 1O- 12 f for theoutput buffers.10-56

~ Power Characteristics~~~~UcrOR ==================================================================~Current MeasurementINSTANTANEOUS CURRENTFigure 3 illustrates the instantaneous current drawn by aCypress RAM. The instantaneous power is calculated bymultiplying this current times the constant supply voltage,V cc. Most of the power is dissipated in the time correspondingto the access time. This is also true for PROMsand PALs.ICCADDRESS/DATA~-------tA--------~1-----------T Cy ---------1I, = Quiescent Icc12 = Average Icci(t) = Instantaneous IccFigure 3. RAM IccAVERAGE CURRENT0059-2The current measurement unit in an automatic tester integratesthe instantaneous current over the measurement cycleand arrives at an equivalent average current. In otherwords, the average current, 12, during time TCY is equal tothe area between the instantaneous current, i (t), and the Xaxis during TCY. Therefore, when the frequency is decreased,the "current pulse" is (figuratively) spread over alonger time, so the average current is proportionately less.DC Load CurrentNote that the preceding calculations have not accountedfor any DC loads. The user must calculate these separately.Product Characteristic TablesThe following tables are listed to enable the user to calculatethe current requirements for Cypress products. CINT isthe equivalent device internal capacitance, Icc (Q) is thequiescent or DC current and leC(MAX) is the maximumIcc current (as specified on the data sheet) for the commercialoperating temperature range.STATIC RAMsPart No.Table 2Buffer No. No. CINT Icc (Q) Icc (Max.)Type Inputs Outputs (pF) (mA) (mA)CY7C122/123 A 16 4 24 50 90CY7C128 B 14 8 27 59 120CY7C147 B 15 1 34 28 90CY7C148/149 B 12 1 32 45 90CY7C150 B 18 4 20 44 90CY7C161/162 B 22 4 300 13 70CY7C164 B 20 4 300 13 70CY7C166 B 21 4 300 13 7010-57Part No.Table 2 (Continued)Buffer No. No. CINT Icc (Q) ICC (Max.)Type Inputs Outputs (pF) (mA) (mA)CY7C167 C 17 1 75 25 70CY7C168/169 C 18 4 75 50 70CY7C170 B 18 4 50 33 90CY7C171/172 B 18 4 100 27 70CY7C185/186 B 25 8 330 13 100CY7C187 B 19 1 150 7 100CY7C189/190 B 10 4 21 32 90PROMsPart No.Table 3Buffer No. No. CINT ICC(Q) ICC(Max.)Type Inputs Outputs (pF) (mA) (mA)CY7C225 B 12 8 32 35 90CY7C235 B 13 8 35 35 90CY7C245 B 13 8 35 50 90CY7C261/3/4 C 14 8 60 45 100CY7C268/269 C 19/17 9 60 60 100CY7C281/282 B 14 8 35 35 100CY7C291/292 B 14 8 35 50 100PALsFor the 16L8, 16R8, 16R6 and 16R4 the number of inputsand outputs is, within limits, user configurable. All usetype B buffers.Table 4Part No.CINT(pF)PALC16L8/R8/R6/R4 40PLDC20G10 50PALC22VlO 50PLDCY7C330 300LOGIC PRODUCTSTable 5Part No.Buffer No. No.Type Inputs OutputsCY7C401 B 6 6CY7C402 B 7 7CY7C403 B 7 6CY7C404 B 8 7CY7C408 B 11 12CY7C409 B 11 13CY7C51O C - -CY7C516/517 C - -CY3341 B 6 6CY7C901 C 28/24 10/14CY7C909 C 21 5CY7C911 C 13 5CY7C9101 C - -Icc (Q)(mA)ICC(Max.)(mA)25 4530 5540 8042 120CINT ICC(Q) ICC(Max.)(pF) (mA) (mA)53 30 7553 30 7553 30 7553 30 75100 42 135100 42 13560 30 10060 30 10053 30 45160 25 7080 25 5580 25 5570 30 85The CY7C901 has four bi-directlonal I/O pms.Static RAM ExampleTo illustrate how to use the preceding tables and performthe required calculations the following example is provided.Estimate the typical Icc current for the CY7C169-35RAM at room temperature (TA = 25°C) and Vee = 5V.Assume the duty cycle is 100% at the specified access time.

~ Power Characteristics~~~U~==================================================================Static RAM Example (Continued)Calculate typical and worst case Icc (all inputs and outputschanging) with output loading of 10 pF.From the RAM product characteristiC table;I/: inputs = 18I/: outputs = 4CINT = 75 pFIcc (Q) = 50 rnATRANSIENT INPUT BUFFER CURRENTThe input buffers on the CY7C169 are type C, so the averagecurrent is 0.3 rnA. If the input signal level transitionsare 4V and the transition times are 0.5 V Ins, the transitiontime is:The duty cycle is then;4VTt = -_._- = 8 ns.0.5 V/ns8 ns/35 ns = 0.23.Therefore, each input buffer draws0.3 rnA X 0.23 = 0.069 rnA.If all inputs change, the total transient input buffer currentis18 X 0.069 = 1.24 rnA.CVf Input Buffer CurrentI = CVfI = 0.57 rnACIN = 5 pFV = 4Vf = 1/35 nsTotal = 18 X 0.57 = 10.28 rnAInternal CVf CurrentI = CVf CINT = 75 pFI = 10.71 rnA V = 5Vf = 1135 nsOutput CVf Current1= CVf COUT = IOpFI = 1.15 rnA V = 4Vf = 1135 nsTotal = 4 X 1.15 = 4.6 rnAThe Quiescent Current is 50 rnAThe Total Current At TCY = 35 ns is;Input Transient 1.24 rnAInput CVf10.28 rnAInternal CVf 10.71 rnAOutput CVf 4.6 rnAQuiescent 50 rnATotal Icc76.83 rnA (all inputs/outputs changing)Note that the worst case transient current is 26.83 rnA.If one-half of the inputs and outputs change this is reducedto 13.4 rnA, which gives a total current of 63.4 rnA (typicalled·10-58If the duty cycle is 10% the transient current is reduced to1.34 rnA, which results in a total current of 51.34 rnA.Note also that the Input CVf current and the output CVfcurrent would have the same values for a bipolar device.WORST, WORST, WORST CASE IcCNext, let's estimate the Icc for worst case Vee and lowtemperature, in addition to all inputs and outputs changingand compare it with the Icc. specified on the data sheet.The Icc current will be greater at high Vee, which is 5.5Vor 1.1 X the nominal 5V Vee. The increase in Icc due tothe lower temperature is 3%, so the total increase is 13%.These factors apply to the· Internal CVf current (10.71rnA), the output CVf current (4.6 rnA), and the quiescentcurrent (50 rnA), (total 65.31 rnA).Total Icc = Input Transient Icc + Input CVf Icc +[Internal CVf+ OutputCVf+ Icc (Q)] X 1.13Icc = 1.24 + 10.28 + [65.31] X 1.13 = 85.32 rnA.This is approximately 95% of the 90 rnA specified on thedata sheet.Note, however, that the data sheet Icc maximum doesNOT include the output CVf current.Typical ICC Versus FrequencyCharacteristicThe Icc versus frequency curves for all Cypress productshave the same basic shape, which is illustrated by thePAL 16R8 curve of Figure 4. The current remains essentiallyconstant at the quiescent Icc value until the frequencyincreases to the point where the capacitances begin tocause appreciable currents. This point depends upon thecapacitances (input, internal, and output), the number ofinputs and outputs, the rate at which they change, and thevoltage levels that they are switched between. For Cypressproducts this point is in the 1-10 MHz range.The PAL 16R8 devices that were tested to obtain the datafor the curve were exercised such that all inputs and alloutputs changed every cycle. Curve A shows the total Icccurrent for a 50 pF load on each of the eight outputs.Curve B shows the total Icc current when the outputs aredisabled. The B curve results from the input and the internalcapacitances. In most applications the actual operationof the device will be somewhere between the A and Bcurves.The A and B curves may be extrapolated backwards untilthey intersect the quiescent current (point C in Figure 4).Point C is approximately 5.6 MHz. This gives the user aneasy to use approximate formula to calculate the ICC current.For frequencies less than 5.6 MHzIcc = Icc (Q) = 25 rnAFor frequencies greater than 5.6 MHzIcc = Icc (Q) + 3.5 rnA per MHz (all outputs changing)or,Icc = Icc (Q)+0.5 rnA per MHz (no outputs changing)

~ Power Characteristics~~~~ucrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==TRANSIENT INPUT BUFFER CURRENT (Continued)120100< SOE~(.).Y 60II TYPICAL IIcc VS fFrequency in HertzIcd VS FREQUENCY FOR PAL 16R8ALL INPUTS / OUTPUTS CHANGEVcc=5V. T A =25 0 C. V IL =O.SV. V IH =2V(OUTPUTSEN~BL7D)Ai*J+iIICf>~j).40o·II(Q) ~~ ~cJ=O~F25--- / flo 10"1'ct:;( B (OUTPUTS20Trrl010KHz 100 KHz 1 MHz 10MHz 100MHzJ;/!",'V'd el =50P'FREQUENCY IN HERTZFigure 4. Typical Icc vs f0059-910-59

CYPRESSSEMICONDUCTORSystems Design Considerations WhenUsing Cypress CMOS CircuitsIntroductionThis document is intended to be a guide for the systemsdesigner. Its purpose is to make him aware of the things toconsider either when designing new systems using Cypresshigh performance CMOS integrated circuits or when Cypressproducts replace either bipolar or NMOS circuits inexisting systems. The two major areas of concern are transmissionline effects due to impedance mismatching betweenthe source and load, and device input sensitivity.Design for PerformanceIn order to achieve maximum performance when using CypressCMOS integrated circuits, the systems designer mustpay attention to the placement of the components on thePrinted Circuit Board (PCB), the routing of the metaltraces that interconnect the components, the layout anddecoupling of the power distribution system on the PCBand, perhaps most important of all, the impedance matchingof (some ot) the traces (which, under certain conditions,must be analyzed as transmission lines) between thesource and the loads. The most critical traces are those ofclocks, write strobes (on SRAMS), and chip enables.Issues of Concern When Cypress ICs ReplaceEither Bipolar or NMOS ICsCypress CMOS ICs have been designed to replace bothbipolar ICs and NMOS products, and to achieve equal orbetter performance at one-third (or less) the power of thecomponents they replace.When high performance Cypress CMOS circuits replaceeither bipolar or NMOS circuits in existing sockets, theuser must be aware of certain conditions, which may bepresent in the existing system, that could cause the CypressICs to behave in a manner different than expected. Theseconditions fall into two general categories; (1) device inputsensitivity and, (2) sensitivity to reflected voltages.Input SensitivityHigh performance products, by definition, require less energyat their inputs in order to change state than low ormedium performance products.Unlike a bipolar transistor, which is a current sensing device,a MOS transistor is a voltage sensing device. In fact, aMOS circuit design parameter called K' is analogous to thegm of a vacuum tube, and is inversely proportional to thegate oxide thickness.The thin gate oxides, which are required to achieve thedesired performance, result in highly sensitive inputs thatrequire very little energy. High frequency signals that bipolardevices would not respond to may be detected byCMOS products.MOS transistors also have extremely high (5 to 10 millionohm) input impedances, which make their gate inputs analogousto the input of a high gain amplifier (or an RF antenna).In contrast, bipolar ICs have input impedances of10000 or less, so they require much more energy to changestate than MOS ICs. In fact, a Cypress IC requires lessthan 10 picojoules of energy to change state.Therefore, when Cypress CMOS ICs replace either bipolaror NMOS ICs in existing systems, they may respond topulses of energy that are present in the system that are notdetected by the bipolar or NMOS products.Reflected VoltagesCypress CMOS ICs have very high input impedances and,to achieve TTL compatibility and to drive capacitive loads,low output impedances. The impedance mismatch, due tolow impedance outputs driving high impedance inputsmay, under certain conditions, cause unwanted voltage reflectionsand ringing, which could result in less than optimumsystem operation.When the impedance mismatch is very large, a nearly equaland opposite negative pulse is reflected back from the loadto the source when the (electrical) length of the line (PCBtrace) is greater thant = TR (ns)2 Tpd (ns/ft.)where TR is the rise time of the signal at the source andTpD is the one-way propagation delay of the line per unitlength.The input clamping diodes that bipolar logic "IC families"(e.g., TTL, LS, ALS, FAST) all have are inherent in thefabrication process. The p-substrate is usually groundedand n wells are used for the NPN transistors and p typeresistors. The wells are reverse biased by connecting themto the Vee supply. As a result, a PN junction diode isformed between every input pin (cathode or n material)10-60

~~Introduction (Continued)and the substrate (anode or p-material). When a negativevoltage occurs at an input pin, either due to lead inductanceor to a voltage reflection, the diode is forward biased,turns on, and clamps the input pin to a Vf below ground(approximately -O.SV).As circuit performance improved, the output rise and falltimes of the bipolar circuits decreased to the point wherevoltage reflections began to occur (even for short traces)when there was an impedance mismatch between the lineand the load. Most users, however, were unaware of thesereflections because they were suppressed by the clampingaction of the diodes.Conventional CMOS processing results in PN junction diodes.However, they adversely affect the ESD (ElectrostaticDischarge) protection circuitry at each input pin andcause an increased susceptibility to latchup. To eliminatethis, a substrate bias generator is used.Voltage reflections should be eliminated by using impedancematching techniques and crosstalk should be reducedby careful PCB layout.CrosstalkThe rise and fall times of the waveforms generated by theoutput circuits are 2 to 4 ns between levels of O.4V and 4V.The fast transition times and the large voltage swings couldcause capacitive and inductive coupling (crosstalk) betweensignals if insufficient attention is paid to PCB layout.Crosstalk is reduced by avoiding running PCB traces parallelto each other. If this is not possible, ground tracesshould be run between signal traces. In synchronous systems,the worst time for the crosstalk to occur is during theclock edge with which the data is sampled. In most systemsit is sufficient to isolate the clock and other data strobelines so that they do not cause coupling to the data lines.The Theory of Transmission LinesA connection ( trace) on a PCB should be considered as atransmission line if the wavelength of the applied frequencyis short compared to the line length. If the wavelength ofthe applied frequency is long compared to the length of theline, conventional circuit analysis can be used.In practice, transmission lines on PCBs are designed to beas nearly lossless as possible. As a result, the mathematicsrequired for their analysis, compared to a lossy (resistive)line can be simplified.Systems Design Considerations When Using Cypress CMOS CircuitsIdeally, all signals between ICs travel over constant-impedancetransmission lines that are terminated in their characteristicimpedances at the load. In practice this ideal situationis seldom achieved for a variety of reasons.Perhaps the most basic reason is that the characteristicimpedances of all real transmission lines are not constants,but present different impedances depending upon the frequencyof the applied signal. For "classical" transmissionlines driven by a single frequency signal source the characteristicimpedance is "more constant" than when the transmissionline is driven by a square wave or a pulse.A square wave is composed of an infinite set (Fourier seriesexpansion) of discrete frequency components, i.e., fundamentalplus odd harmonics of decreasing amplitUdes.When the square wave is propagated down a transmissionline the higher frequencies are attenuated more than thelower frequencies and, due to dispersion, all of the frequenciesdo not travel at the same speed.Dispersion indicates the dependance of phase velocity uponthe applied frequency. (Ref. 1, pg. 192). The result is thatthe square wave is distorted when all of the frequency componentsare added together at the load.A secondary reason why practical transmission lines arenot ideal is that they frequently (of necessity) have multipleloads. The loads may be distributed along the line at regular(or irregular) intervals or they may be lumped together(as close as practical) at the end of the line. The signal-linereflections and ringing caused by impedance mismatches,nonuniform transmission line impedances, inductive leads,and non-ideal resistors could compromise the dynamic systemnoise margins and cause inadvertent switching.One of the system design objectives is to analyze the criticalsignal paths and design the interconnections such thatadequate system noise margins are maintained. There willalways be signal overshoot and undershoot. The objectiveis to accurately predict them and to keep them within acceptablelimits.The Ideal (Lossless) Transmission LineAn equivalent circuit for a transmission line is presented inFigure 2.1. It consists of subsections of series resistance (R)and inductance (L) and parallel capacitance (C) and shuntadmittance (G) (or parallel resistance, Rp). For clarity andconsistency these parameters will be defined per unitlength. The value of the parameter (R, L, C, Rp) must bemultiplied by the length of the subsection, t, to find thetotal value. The line is assumed to be infinitely long.If the line of Figure 2.1 is assumed to lossless (R = 0, Rp= infinity) Figure 2.1 is reduced to Figure 2.2.1------- t -----+------- t -----ItL tR tLTOINFINITYIFigure 2.1. Transmission Line Model0099-110-61

~R£SSSystems Design Considerations When Using Cypress CMOS Circuits.~ICONDUcrORThe Theory of Transmission Lines (Continued)TOINFINITYInput or Characteristic ImpedanceWe shall now calculate the characteristic impedance (ACimpedance or surge impedance) looking into terminals a-bof Figure 2.2.Let the input impedance looking into terminals a-b be ZI,that looking into terminals c-d be Z2, that looking intoterminals e-f be Z3, etc. The input impedance, ZI, lookinginto terminals a-b is the series impedance of the first inductor(f L) in series with the parallel combination of Z2 andthe impedance of the capacitor (t C).From AC theory:XL = jwt LWhere XL is the inductive reactance.1XC=-­jwtcWhere XC is the capacitive reactance.ThenZ2XCZI = XL + --­Z2 + XCFigure 2.2. Ideal Transmission Line Model(2-1)If the line is "reasonably" long ZI = Z2 = Z3. SubstitutingZI = Z2 into equation 2-1 yields;ZIXCZI =XL+---ZI + XCOr, z}2 - ZI XL - XC XL = 0 (2-2)Substituting the expressions for XC and XL yields;Lz}2 - jwt L = - (2-3)CEquation 2-3 contains a complex component that is frequencydependent. It can be eliminated by allowing t tobecome very small and by recognizing that the ratio L/C isconstant and independent of t or w.ZI = # (2-4)The AC input impedance of a purely reactive, uniform,lossless line is a resistance. This is true for AC or DCexcitation.Propagation Velocity and Propagation DelayThe propagation velocity (or phase velocity) of a sinusoidtraveling on an ideal line (Ref. 1, pg. 33) is:1a = M'0099-2The propagation delay for a lossless line is the reciprocal ofthe propagation velocity.T pd = JLC (2-5)= ZICwhere Land C are the intrinsic line inductance and capacitanceper unit length.If additional stubs or loads are added to the line the propagationdelay will increase by the factor (Ref. 2, pg. 129).~1+~.Where CD = load capacitance.Therefore, the propagation delay, TpD', of a loaded line is:r.cnTpD' = TPD\jl + C· (2-6)The characteristic impedance of a capacitively loaded lineis decreased by the same factor that the propagation delayis increased.Reflection CoefficientsZIZI' = ----:===-~1+~(2-7)The third attribute of the ideal transmission line; reflectioncoefficients, are not actually a line characteristic. The lineis treated as a circuit component (which it is) and reflectioncoefficients are defined that measure the impedance mismatchesbetween the line and its source and the line and itsload. The reason for defining the reflection coefficients willbecome apparent later when it will be shown that if theimpedance mismatch is sufficiently large, either a negativevoltage or a positive voltage may be reflected back from theload to the source, where it may either add to or subtractfrom the original signal. If the impedance of the source ismismatched to the line impedance it may also cause a voltagereflection, which in turn will be reflected back to theload. Therefore, two reflection coefficients will be defined.For classical transmission lines driven by a single frequencysource the impedance mismatches cause standing waves.When pulses are transmitted and the output impedance ofthe source changes depending upon whether a LOW toHIGH or a HIGH to LOW transition occurs, the analysisis further complicated. Classical transmission analysis,10-62

~PRKSS.nEMICONDUcrORSystems Design Considerations When Using Cypress CMOS CircuitsThe Theory of Transmission Lines (Continued)where pulses are represented by complex variables withexponentials, could be used to calculate the voltages at thesource and the load after several back and forth reflections.However, these complex equations tend to obscure what isphysically happening.Energy ConsiderationsConsider next, driving the ideal transmission line from asource capable of generating digital pulses and analyze thebehavior of the line under various driving and loading conditions.The circuit to be analyzed is illustrated in Figure 2.3. Theideal transmission line of length f is being driven by adigital source of internal resistance Rs and loaded with aresistive load of RL. The characteristic J!N?edance of theline appears as a pure resistance, Zo = ~L/C to any excitation.The ideal case is when RS = Zo = RL. The maximumenergy transfer from source to load occurs under this condition,and there are no reflections. One half the energy isdissipated in the source resistance, Rs, and the other half isdissipated in the load resistance, RL, (the line is lossless).If the load resistor is greater (larger) than the characteristicimpedance of the line there will be extra energy available atthe load, which will be reflected back to the source. This iscalled the underdamped condition, because the load underusesthe energy available. If the load resistor is smaller thanthe line impedance the load will attempt to dissipate moreenergy than is available. Since this is not possible, a reflectionwill occur that is a signal to the source to send moreenergy. This is called the overdamped condition. Both ofthese cases will cause negative traveling waves, whichwould cause standing waves if the excitation were sinusoidal.The condition Zo = RL is called critically damped.It should be intuitively obvious to the reader that the "safest"termination condition, from a systems design viewpoint,is the slightly overdamped condition. No energy isreflected back to the source.Derivation of the Line Voltage for StepFunction ExcitationThe procedure is to apply a step function to the ideal lineand to analyze the behavior of the line under various loadingconditions. The following section will analyze pulses,reflections from various terminations, and the effects of risetimes on the waveforms.The step function response is important because any pulsecan be represented by the superposition of a positive stepfunction and a negative step function, delayed in time withrespect to each other. By proper superposition the responseof any line and load to any width pulse can be predicted.The principle of superposition applies to all linear systems.According to theory, the risetime of the signal driven bythe source is not affected by the characteristics of the line.This has been substantiated in practice by using a specialcoaxially constructed reed delay that delivered a pulse of18 amperes into 50.0 with a risetime of 0.070 ns (70 ps).(Ref. 1, pg. 162).The equation representing the voltage waveform goingdown the line (Figure 2.3) as a function of distance andtime is:VL(X, t) = VA(t) U(t - X tpd) for t < To (2-8)Where: VA(t) = Vs(t) ( zo) (2-9)Zo + RSV A = the voltage at point AX = the voltage at a point X on the linef = the total line lengthtpd = the propagation delay of the line in ns/ft.TO = f tpd, or the one-way line propagation delayU(t) = a unit step function occurring at X = 0, andVs(t) = the source voltageWhen the incident voltage reaches the end of the line areflected voltage, VL', will occur if RL is not equal to ZOoThe reflection coefficient at the load, pL, can be obtainedby applying Ohm's Law.The voltage at the load is VL + VL', which must be equalto (IL + IL')RL. But IL = VL/Zo and IL' = - VL' /ZO(the minus sign is due to IL being negative. i.e., it is oppositeto the current due to VL.)Therefore,VB = VL + VL' = (VL _ VL') RL (2-10)Zo ZoBy definition:reflected voltage VL'pL =incident voltage VLSolving for VL' /VL in equation 2-10 and substituting inthe equation for pL yields:RL - ZopL - (2-11)RL + ZoThe reflection coefficient at the source is:Rs - ZopS -(2-12)RL + ZoRe-arranging equation 2-10 yields:VBVL')= VL + VL' = ( 1 + VL VL = (1 + pL)VL (2-13)Equation 2-13 describes the voltage at the load (VB) as thesum of an incident voltage (VL) and a reflected voltage (pLVL) at time t = To. When RL = Zo no voltage is reflected.When RL < Zo the reflection coefficient at the load isnegative, so the reflected voltage subtracts from the incidentvoltage, giving the load voltage. When RL > Zo thereflection coefficient is positive, so the reflected voltageadds to the incident voltage, again giving the load voltage.Note that the reflected voltage at the load has been definedas positive when traveling toward the source. This meansthat the corresponding current must be negative, subtractingfrom the current driven by the source, which it does.This "piecewise" analysis is cumbersome and can be tedious.However, it does provide an insight into what is physi-IE10-63

~~Systems Design Considerations When Using Cypress CMOS CircuitsThe Theory of Transmission Lines (Continued)cally happening and demonstrates that a complex problemcan be solved by dividing it into a series of simpler problems.Also, the mathematics are simple if the exponentials,which provide phase information in the classical transmissionline equations, are eliminated. One must provide the"bookkeeping" to combine the reflections at the propertime. This is quite straightforward, since a pulse travelswith a constant velocity along an ideal or low loss line andthe time delay between reflected pulses can be predicted.The rules to keep in mind are that at any point and instantof time the voltage or the current is the algebraic sum ofthe waves traveling in the positive X and the negative Xdirections. For example, two voltage waves of the samepolarity and equal amplitudes, traveling in opposite directions,at a given point and time will add together to yield avoltage of twice the amplitude of the individual wave. Thesame reasoning applies to points of termination and discontinuitieson the line. The total voltage or current is thealgebraic sum of all of the incident and reflected waves.Polarities must be observed. A positive voltage reflectionresults in a negative current reflection and vice versa.Before considering reflections at the source, due to impedancemismatches between the source impedance and theline impedance, the behavior of the ideal line with variousloads will be analyzed when it is driven by a step function.~2Zor;-~Step Function Response of the Ideal Line forVarious LoadsThe voltage and current waveforms at point A (line input,Figure 2.3) and point B (the load) for various loads arepresented in Table 1. They have been reproduced from Table5.1, pages 158, 159 of Reference 1. Note that RS = Zoand that VA at t = 0 is equal to Vs/2, which means thatthere is no impedance mismatch between the source andthe line, so there will be no reflection from the source att = 2 To.To is the one way propation of the line.The time domain response of the reactive loads are obtainedby applying a step function to the LaPlace transformof the load and then taking the inverse transform.Note that the reflection coefficient at the load is not thetotal reflection coefficient (a complex number) but representsonly the real part of the load. The reason for doingthis is to eliminate the complex Owt) terms because we areperforming the bookkeeping involving the phase relationships,which are performed by them in classical transmissionline analysis.Also note that for the open circuit condition, Table 1 (b),ZL = infinity, so that pL = + 1. The voltage is reflectedback from the load to the source (at amplitude Vo =V s/2), so that at time = 2 To it adds to the original voltage,V 0 = V s/2 to give a value of 2 V 0 = V s. During thetime the voltage wave is traveling down to and back fromthe load a current of 10 = V O/ZO = V S/2 Zo exists. Thiscurrent charges up the distributed line capacitance to thevalue Vs, at which time it stops.'I Bl~~-x)SOURCELINELOAD0099-3Figure 2.3. Ideal Transmission Line Loaded and DrivenRLDirection of TravelVA,IA -+ +XVB, IB +- -X10-64

~PRE$'nICONDUcrORSystems Design Considerations When Using Cypress CMOS CircuitsThe Theory of Transmission Lines (Continued)TerminationTable 1. Step Function Response of Figure 2.3 for Various TerminationsVA = VS/2, 10 = VO/ZO, To = t,fLC, pL = (RL -(0) SHORT CIRCUIT VA hvInput waveformsVin, iinZO)/(RL + ZO)ALWAYS =0Output waveformsv f, ifIzt=o -"",---2T'"0--------21o----l "0 ~ ----, 0 t _____ I ___v 2TO v To2VVAA ~t Ir----(b~RCUIT c= . t _ .. 1_ ..._________Zt== i 2TO 1 To0----10 b _...It_A_L_W_AY_S_=_Ov 2~ v-~-----------, It. t______• t(c) SMALL RESISTOR V t--- v 2Rt -v Rt t~ A ~----- A ~: SRe+ZOu_-_-... l ___________. to---l~

Wr~Systems Design Considerations When Using Cypress CMOS CircuitsThe Theory of Transmission Lines (Continued)The waveforms at the source and load for (g) and (h) are ofparticular interest because (g) represents a series RC terminationthat dissipates no DC power and can be used toterminate a transmission line in its characteristic impedanceat the input to a Cypress Ie. The equivalent circuit ofthe input to a Cypress IC is represented by (h). The additionof (g) and (h) then models a Cypress IC driven by atransmission line terminated in its characteristic impedancewhen the values of Rand C are properly chosen.Reflections Due to DiscontinuitiesTable 2 illustrates three types of common discontinuitiesfound on transmission lines. When a discontinuity occursat a point on the line it causes a reflection and some energyis directed back to the source. The amount of energy reflectedback is determined by the reflection coefficient atthat point. Discontinuities are usually small (by design), somost of the energy is transmitted to the load.Discontinuity(a) Series InductancePulse Response of the IdealTransmission LineConsider next the behavior of the ideal transmission linewhen driven by a pulse whose width is short compared tothe electrical length of the line. In other words, when thewidth of the pulse is less than the one-way propagationdelay time, TO, of the line.The voltage waveforms at point A (line input, Figure 2.3)and point B (the load) for various loads are presented inTable 3. They have been reproduced from Table 5.2, pages160, 161 of Reference 1. Note that Rs = Zo and that VAat t = 0 is equal to V s/2, which means that there is noimpedance mismatch between the source and the line, sothere will be no reflection from the source at t = 2 To.Table 2. Reflections from Discontinuities with an Applied Step FunctionL'Voltage Seen at input End: V A = V s/2 also, Rs = Zo(b) Shunt CapacitanceVI'Ot=.~t~Izo0099-122V A ----------t'2TOT0099-15V" I Ie Izo~t'--lVA 1-----__0099-13t'2TOT(c) Series Resistance0099-16V" IRVtA!I~t'~Izo0099-14VAV lnIIt'2TOT(R+Zo)2VA R+ 2Z o0099-1710-66

(;r:~==roRSystems Design Considerations When Using Cypress CMOS CircuitsPulse Response of the Ideal Transmission Line (Continued)Table 3. Pulse Response of Figure 2·3 for Various TerminationsVA = V s/2, To = t..j[C, pv = (RL -Zo)/(RL + Zo)l' "-WM'='Termination Input waveform Yin Output waveform VBVln(5CI~IT "h n,Zt=O-v-Aof-[- __--"_-_-_-_'l""0----r-----· t(b) OPEN CIRCUIT0---0---(c) SMALL RESISTOR(d) LARGE RESISTORVlnVA h~Rt>ZO _ n- PLVAo---lh(9) SERIES RESISTANCE ANDINDUcrt.NCEV ln_JTvt ___ VA --zP'---+-=o Q--t-VA_L I·hV ln(f) PARALLEL RESISTANCE ANDINDUCTANCEP V:ilL Tvt _V~A~_T~IA~~~_____• tZTO .........Vln(g) SERIES RESISTANCE ANDCAPACITANCE"h "("t• tZToZTO• t(l+PL) V AtVBnToVB("'0"[0VBZV AVBVA (1 +P L )--I (l+P L)VA(l+P L )V AVBfl---)'"VBTo• t0099-18(h) PARALLEL RESISTANCE ANDCAPACITANCE0099-1910-67

Wr~Finite Rise Time EffectsNow consider the effects of step functions with finite risetimes driving the ideal transmission line.If TR is sufficiently fast, the voltage at the load will changein discrete steps. The amplitude of the steps is determinedby the impedance mismatch and the width of the steps isdetermined by the two-way propagation delay of the line.Systems Design Considerations When Using Cypress CMOS CircuitsAs the risetime becomes slower and the line shorter (smallerTo), or both, the result converges to the familiar RCtime constant, where C is the static capacitance. All devicesshould be treated as transmission lines for transient analysiswhen an ideal step function is applied. However, as therise time becomes larger (slower) and the traces shorter (orboth) the transmission line analysis reduces to conventionalAC circuit analysis.Reflections from Small DiscontinuitiesTable 4 shows a pulse with a linear rise time and roundededges driving the transmission line of Table 2 (a), (b). Theexpressions for V r are derived on pages 171 and 172 ofReference 1. The reflection caused by the small series inductanceis useful for calculating the value of the inductor,L', but little else.Table 4. Reflections from Small Discontinuities withFinite Rise Time Pulse(a) Applied Pulse from Generator(b) Reflection from Small Series Inductor L't'2To/(c) Reflection from Small Shunt Capacitor C'Vr:::::...!::...~~......Io. __ 2Zo TR0099-200099-21The reflection caused by the small shunt capacitor is moreinteresting because if it is sufficiently large it could cause adevice connected to the transmission line to see a logicZERO instead of a logic ONE.The Effect of Rise Time on WaveformsNext, consider the ideal line terminated in a resistance lessthan its characteristic impedance and driven by a step functionwith a linear rise time. The stimulus, the circuit, andthe response are illustrated in Figures 4.1 (a), (b) and (c),respectively. Once again, note that the source resistance isequal to the line characteristic impedance, so there are noreflections from the source.ZoF i v.APPLIED STEP FUNCTION(a)(b)Zo"

5r~Finite Rise Time Effects (Continued)Systems Design Considerations When Using Cypress CMOS CircuitsREFLECTED WAVE4T(a)TR = 2 To0099-26 Vln(a)0099-28REFLECTED WAVEII I I~TR~III•(b)0099-29(b)TR> 2 To0099-27Figure 4.2. Effects of Rise Time on Step Response forRf < Zo:(a)TR = 2 TO; (b)TR > 2ToMultiple Reflections and Effective TimeConstantWe will now consider the case of an ideal transmission linewith multiple reflections causes by improper terminationsat both ends of the line. The circuit and waveforms areillustrated in Figure 4.3. The reflection coefficients at thesource and the load are both negative. i.e., the source resistanceand the load resistance are both less than the linecharacteristic impedance. Refer to equations 2-11 and 2-12.When the switch is initially closed, a step function of am-VsZoplitude Va = Vin =appears on the line andRs + Zotravels toward the load. A one-way propagation delay timelater, To, the wave is reflected back with an amplitude ofpL Va.This first reflected wave then travels back to the source andat time t = 2 TO it reaches the input end of the line. Atthis time the first reflection at the source occurs and a waveof amplitude pS (pL Va) is reflected back to the load. Attime t = 3 TO this wave is again reflected from the loadback to the source with amplitude pL pS (pL Va) = pSpL2 Va. This back and forth reflection process continuesuntil the amplitudes of the reflections become so small thatthey cannot be observed, at which time the circuit is said tobe in a quiescent state.Effective Time ConstantFrom an examination of Figure 4.3 it is reasonable that ifthe voltage reflections occur in small increments that are ofshort durations the resultant waveform will approximatean exponential function, as indicated by the dashed line inFigure 4.3 (b). The smaller and narrower the steps become,the more closely the waveform will approach an exponential.(c)0099-30', .. ,"'[ ~T>~'To 3To 5To 7To(d)Figure 4.3. Step Function Applied to LineMismatched on both ends; waveforms shown fornegative values of Ps and pt.0099-31The mathematical derivation is presented on pages 178 and179 of Reference 1. The time constant is shown to be:2ToK=-----1 - pS pL(4-1)So that the resultant waveform can be approximated by;V(t) = Va E (i:) (4-2)In order for equation 4-2 to be accurate pL and ps must bereasonably large (approaching ± 1) so that the incrementalsteps are small. The product pS pL is a positive number,less than one, so the time constant is a negative number,which indicates that the exponential decreases with time.This is usually the case in transient circuits.Both reflection coefficients must also have the same sign inorder to yield a continually decreasing (or increasing)waveform. Opposite signs will give oscillatory behaviorthat cannot be represented by an exponential function.10-69

Systems Design Considerations When Using Cypress CMOS Circuits~~u=Finite Rise Time Effects (Continued)Types of Transmission LinesThe Transition from Transmission Line toThe types of transmission lines are:Coaxial cableCircuit AnalysisTwisted pairWhen a transmission line is terminated in its characteristic Wire over groundimpedance it behaves like a resistor and it usually does not Microstrip linesmatter if transmission line or circuit analysis is used; providedthat the propagation delays are taken intoStrip linesaccount.Consider the case of a short-circuited transmission linedriven by a step function with a source impedance unequalto the characteristic line impedance. The general case isshown in Figure 4.3 (a). For RL = 0 the reflection coefficientsare;Zs - ZopS = pL = -1.Zs + ZoThe approximate time constant is;-k = 2 TO = 2 TO = To (Zs + Zo) or1 - pS pL 1 + pS ZsTOZO-k = TO + -- (4-3)ZsRecall that To =t ~ (one-way delay)and Zo = ~, where t is the physical length of the lineand Land C are the per-unit-Iength parameters.Substitution of these into equation 4-3 yieldsL-k = To + t-.ZsIt is necessary to have Zs smaller than ZooThus the reflection coefficients have the same sign in orderto give exponential behavior. Opposite signs give oscillatorybehavior.If Zs « Zo, the exponential approximation becomes moreaccurate. If Zs is very small compared to Zo, then To isnegligible compared to t L/Zo, so that equation 4-5 reducesto;Lk = - t -.ZsBut t L is the total loop inductance and Zs is the totalseries impedance of the circuit. The time constant is then;L'k=-.RSThis is the same time constant that would have been obtainedby a circuit analysis approach if the line were considereda series combination of L' and RS.By open-circuiting the line and performing a similar analysisit can be shown that a RC time constant results.10-70Coaxial CableCoaxial cable offers many advantages for distributing highfrequency signals. The well defined and uniform characteristicimpedance permits easy matching. The ground shieldon the cable reduces crosstalk and the low attenuation athigh frequencies make it ideal for transmitting the fast riseand fall time signals generated by Cypress CMOS integratedcircuits. However, because of its high cost, coaxial cableis usually restricted to applications where there are no otheralternatives. These are usually clock distribution lines onPCBs or backplanes.Characteristic ImpedanceCoaxial cables have characteristic impedances of 50, 75, 93,or 150 ohms. Special cables can be made with other impedances,but these are the most common.Propagation DelayThe propagation delay is very low. It may be computedusing the formula;Tpd = 1.017 fe;ns/ft. (5-1)where er is the relative dielectric constant and dependsupon the dielectric material used. Forsolid teflon and polyethyleneit is 2.3. The propagation delay is 1.54 ns per foot.For maximum propagation velocity, coaxial cables with dielectricstyrofoam or polystyrene beads in air may be used.Many of these cables have high characteristic impedancesand are slowed considerably when capacitively loaded.Twisted PairTwisted pairs can be made from standard wire (A WG 24-28) twisted about 30 turns per foot. Typical characteristicimpedance is 11On. Because the propagation delay is directlyproportional to the characteristic impedance (equation2-5) the propagation delay will be approximately twicethat of coaxial cable. Twisted pairs are used for backplanewiring and for breadboarding.Wire Over GroundFigure 5.1 shows a wire over ground. The wire over groundis used for breadboarding and for backplane wiring. Thecharacteristic impedance is approximately 120n and mayvary as much as ±40%, depending upon the distance fromthe groundplane, the proximity of other wires, and the configurationof the ground.\0 1HL ~IIZZIZZIZZIZIZIZIZIZZ! GROUNDZo = ~ In (~),re; dFigure 5.1. Wire Over Ground0099-32

~CfPRRSS'I"?EMlCONDUcrORTypes of Transmission Lines (Continued)Microstrip LinesA microstrip line (Figure 5.2) is a strip conductor (signalline) on a PCB separated from a ground plane by a dielectric.If the thickness and width of the line, and the distancefrom the ground plane are controlled, the characteristicimpedance of the line can be predicted with a tolerance of±S%.l ---1 w r---L...t ----Twhere:er = relative dielectric constant of the board material (about 5for G-IO fiber-glass epoxy boards),w, h, t, = dimensions indicated.Figure 5.2. Microstrip LineSystems Design Considerations When Using Cypress CMOS CircuitsZ 87 In ( 5.98H )0= Jer + 1.41 0.8w + t 't :::: 0.0015" for I oz. Cu,0.003" for 2 oz. Cu.0099-33The formula of Figure 5.2 has proven to be very accuratefor ratios of width to height between 0.1 and 3.0 and fordielectric constants between 1 and IS.The inductance per foot for microstrip lines is;L = Z02 Cowhere Zo = characteristic impedance,Co =capacitance per foot.The propagation delay of a microstrip line is;T pd = 1.017 ~O.4S e r + 0.67 ns per foot(S-2)(S-3)Note that the propagation delay is dependent only uponthe dielectric constant and is not a function of the linewidth or spacing. For G-1O fiber-glass epoxy PCBs (dielectricconstant of 5) the propagation delay is 1.74 ns per foot.Strip LineA strip line consists of a copper strip centered in a dielectricbetween two conducting planes (Figure 5.3). If thethickness and width of the line, the dielectric constant, andthe distance between ground planes are all controlled, thetolerance of the characteristic impedance will be within± S%. The equation of Figure 5.3 is accurate for W I(b-t)< 0.3S and tlb < 0.2S.---I-STRIP LINE"""~~"""''''''''''''''''''''''~_''''''''' -GROUND PLANE0099-34ZO=~ln( 4b )re; 0.67 'TrW ( 0.8 + .;)Figure 5.3. Stripline10-71The inductance per foot is given by the formula;Lo = Zo2Co·The propagation delay of the line is given by the formula;Tpd = 1.017 Fe; ns perfoot. (S-4)For G-1O fiber-glass epoxy boards the propagation delay is2.27 ns per foot. The propagation delay is not a function ofline width or spacing.Power DistributionInstantaneous CurrentIn order to realize the fast rise and fall times that CypressCMOS integrated circuits are capable of achieving, thepower distribution system must be capable of supplying theinstantaneous current required when the device outputsswitch from LOW to HIGH.The energy is stored as charge on the local decoupling capacitors.It is standard practice to use one decoupling capacitorfor each IC that drives a transmission line and touse one for every three devices that do not.The value of the decoupling capacitor is determined byestimating the instantaneous current required when all theoutputs of the IC switch from LOW to HIGH, assuming areasonable "droop" of the voltage on the capacitor.CalculationsThe charge stored on the local decoupling capacitor of Figure6.1 is Q = C V. Differentiating yields;. dQ dV1(t) = dt = C dt' (6-1)The characteristic impedance of a typical transmission lineis son. Heavily (capacitively) loaded lines will have lowercharacteristic impedances (equation 2-7).vee BUS0099-35Figure 6.1. Local Decoupling CapacitorNext, assume that the IC is an eight output PROM, suchas the CY7C24S or the CY7C261. The outputs will reachVcc -Vt = SV-1V = 4V. Each output will then require4V ISO = 8 mA. Since there are eight outputs a total of 64mA will be required.Solving equation 6-1 for C yields;dtC = 1-. (6-2)dVThe signal rise and fall times are 2 to 4 ns so we will use dt= 3 ns.The last step is to assume a reasonable, tolerable droop inthe capacitor voltage. Assume dV = 100 mY.Therefore, substituting these values in equation 6-2 yields;64 X 10-3 X 3 X 10-9C = 100 X 10- 3= 0.192 X 10- 9 = 192pF.It is standard practice to use 0.01 to 0.1 p.F decouplingcapacitors. A 0.01 ""F capacitor is capable of supplying 330mA under the preceding conditions.

Q~Power Distribution (Continued)Decoupling capacitors for high speed Cypress CMOS circuitsshould be of the high K ceramic type with a low ESR(Equivalent Series Resistance). Capacitors using 5 ZU dielectricare a good choice.Low Frequency Filter CapacitorsA solid tantalum capacitor of 10 JLF is recommended foreach 50 to 100 ICs to reduce power supply ripple. Thiscapacitor should be as close as possible to where the Veeand ground enter the PCB or module.Systems Design Considerations When Using Cypress CMOS CircuitsWhen Should Transmission Lines BeTerminated?Transmission lines should be terminated when they arelong. From the preceding analysis it should be apparentthatTrLong Line> --.2TpdWhere T pd is the propagation delay per unit length.For Cypress products the rise time, T To is typically twonanoseconds.The propagation delay per unit length has been shown tobe as small as 1.7 ns per foot.2 nsLong Line>= 0.59 ft. or 7 inches.2 X 1.7 ns/ft.Not all lines exceeding 7 inches will need to be terminated.Terminations are usually only required on clock inputs,write and read strobe lines on SRAMs, and chip select oroutput enable lines on RAMs, PROMs, and PLDs. Addresslines and data lines on RAMs and PROMs usuallyhave time to settle.In the case where multiple loads are connected to a transmissionline, only one termination circuit is required. Thetermination network should be located at the load that iselectrically the longest distance from the source. This isusually the load that is the longest physical distance fromthe source.Types of TerminationsThere are three basic types of terminations. They are calledseries damping, parallel, and pullup/pulldown. Each hastheir advantages and disadvantages.Except for series damping, the termination network shouldbe attached to the input (load) that is electrically furthestaway from the source. Component leads should be as shortas possible in order to prevent reflections due to lead inductance.Series DampingSeries damping is accomplished by inserting a small resistor(typically Ion to 75n) in series with the transmissionline, as close to the source as possible, as illustrated inFigure 8.1. Series damping is a special case of damping inwhich the series resistor value plus the circuit output impedanceis equal to the transmission line impedance. Thestrategy is to prevent the wave that is reflected back fromthe load from reflecting back from the source by makingthe source reflection coefficient equal to zero.10-72The channel resistance (ON resistance) of the pulldowndevice for Cypress ICs is ten to twenty ohms (dependingupon the current sinking requirements), so this valueshould be subtracted from the series damping resistor, RS.Figure 8.1. Series Damping0099-36The disadvantage of the series damping technique is thatduring the two-way propagation delay time the voltage atthe input to the line is half-way between the logic levels,due to the voltage divider action of Rs. This means that noinputs can be attached along the line, because they wouldrespond incorrectly. However, any number of devices maybe attached to the load end of the line because all of thereflections will be absorbed at the source.Due to the low input current required by Cypress CMOSICs, there will be essentially no DC power dissipation andthe only AC power required will be to charge and dischargethe parasitic capacitances.Pullup/PulldownThe pullup/pulldown resistor termination shown in Figure8.2 is included only for the sake of completeness. If bothresistors are used there will be DC power dissipated all thetime and if only a pulldown resistor is used DC power willbe dissipated when the input is in the logic HIGH state.Due to these power dissipations, this termination is notrecommended.Figure 8.2. Pullup/Pulldown0099-37However, in special cases where inputs should be eitherpulled up (HIGH) for logic reasons or because of very slowrise and fall times, a pullup resistor to Vee may be used inconjunction with the terminating network described below.DC power will be dissipated when the source is LOW.Parallel AC Termination; Figure 8.3This is the recommended general purpose termination. Itdoes not have the disavantage of the half-voltage levels ofseries damping and it causes no DC power dissipation.Loads may be attached anywhere along the line and theywill see a full voltage swing.Figure 8.3. Parallel AC0099-38The disadvantages is that it requires two components, versusthe series damping termination of one.

(ir~Systems Design Considerations When Using Cypress CMOS CircuitsTypes of Terminations (Continued)The value of C should be as small as possible. Such that Xcis less than two ohms at the frequencyRS can then equal Zoo1F=--.2TpDSchottky Diode TerminationIn certain instances it may be expedient to use Schottkydiodes to terminate lines. Where line impedances are notwell defined, as in breadboards and backplanes, the use ofdiode terminations is convenient and may save time.A typical diode termination is shown in Figure 9.1. Thelow forward voltage, Vr, of the diode (typically 0.3 to0.45V) clamps the input signal to a V r below ground (lowerdiode) and Vee + V r (upper diode), thereby significantlyreducing signal undershoot and overshoot. In some applicationsboth diodes may not be required.strip trace on the PCB is eight inches and the characteristicline impedance is 50n. It is required to calculate the voltagewaveforms at the source (point A) and the load (pointB) as functions of time.··~tVcc:SVVI " O.8VZO"SOMAFigure 10.1. Equivalent Circuitfor Cypress PAL Driving RAM)24Im--{:2.2 2.4SMA0099-400099-39Figure 9.1. Schottky Diode TerminationThe advantages of diode terminations are:• Impedance matched lines are not required.• The diodes replace terminating resistors or RC terminations.• The clamping actions of the diodes reduce overshootand undershoot.• Although diodes are more expensive than resistors, thetotal cost of layout may be less because a precise, controlledtransmission line environment is not required.• If ringing is discovered to be a problem during systemcheckout the diodes can be easily added.As with resistor or RC terminations, the leads should be asshort as possible in order to avoid ringing due to lead inductance.A few of the types of Schottky diodes commercially availableare:• IN4148 (Switching)• lN57ll• MBD101 (Motorola)• HP5042 (Hewlett Packard)Example: Unterminated LineThe following example is presented to illustrate the procedurefor calculating the waveforms when a Cypress PLD isused to generate the write strobe for a Cypress SRAM. ThePLD is a PAL®C 20 device and the SRAM is theCY7CI89-25.The equivalent circuit is illustrated in Figure 10.1 and the(unmodified) driving waveform in Figure 10.2. The rise andfall times are two nanoseconds. The length of the micro-Figure 10.2. VA (t), Unmodified0099-41Equivalent Circuits for The PLD and SRAMThe equivalent ON channel resistance of the PLD pullupdevice, 28n, was calculated using the output source currentversus voltage graph over the region of interest (0 to2V) from the data sheet. The equivalent resistance of thepulldown device, lOn, was calculated in a similar manner,using the output sink current versus output voltage graph,also on the data sheet.The equivalent input circuit for the SRAM was constructedby approximating the input and stray capacitance with a10 pF capacitor and the resistance with a 5 million ohmresistor. The input leakage current for all Cypress productsis specified as a maximum of ± 10 p,A, which guarantees aminimum of 5oo,OOOn at Yin = 5V. Typical leakage currentis one microampere.Transmission Line CalculationsThe next step is to calculate the propagation delay andloaded characteristic impedance of the line.Propagation DelayThe unloaded propagation delay of the line is calculatedusing equation 5-3 with a dielectric constant of 5.Tpd = 1.74 nslft.In order to calculate the loaded line propagation delay, theintrinsic capacitance must first be calculated using equation2-5.Tpd = ZoCo,where Zo is the intrinsic characteristic impedance and Cois the intrinsic capacitance.Ttvl 1.74 ns/ft.Co = -c = = 34.8 pF/ft.Zo 50m10-73

~~Example: Unterminated Line (Continued)The line is loaded with 10 pF, so equation 2-6 is used tocompute the loaded propagation delay of the . line.Tpd , = Tpd ~D 1 +- CoTpd' = 1.74 ns/ft.T pd' = 2.08 ns/ft.Systems Design Considerations When Using Cypress CMOS Circuits10 pF1 + ------'-----8 in.34.8 pF/ft. X ---12 in./ft.Note that the capacitance per unit length must be multipliedby the line length to arrive at an equivalent lumpedcapacitance.Characteristic ImpedanceThe intrinsic line impedance is reduced by the same factorby which the propagation delay is increased (1.96). Seeequation 2-7.50.0ZO' = -- = 41.8.0.1.196Initial ConditionsAt time t = 0 the circuit of Figure 10.1 is in a quiescientstate. The voltage at points A and B must be the same.By inspection;VA = VB = (Vee - Vi) ( RL )RS +RL5X10 6 )= (5-1) (= 4V28 + 5 X 10 6The Falling Edge of the Write StrobeAt t = 0 the driving waveform changes from 4V to OV(approximately) with a fall time of two nanoseconds. Thisis represented in Figure 10.1 by the switch arm movingfrom position 1 to position 2. The wave propagates to theload at the rate of 2 ns per foot (approximately) and arrivesthere8 in.To = 2 ns/ft. X --- = 1.33 ns12 in'/ft.later, as illustrated in Figure 10.3 (b).The reflection coefficient at the load is pL = 1, so a nearlyequal and opposite polarity waveform is propagated backto the source from the load, arriving at t = 2 To = 2.66ns, as shown in Figure 10.3 (a). (See Table 3 {h}). Notethat the falltime is preserved. The reflection coefficient atthe source is;RS - Zo' 10 - 41.8ps = RS + ZO' = 10 + 41.8 = -0.61The magnitude· of the reflected voltage at the source isthen;4+-------\8ToVA 0 10 12-0.61 ::j::===I=~::t::tj::I:±t=t';;;:::±I--~'----:l;i:;4---:1~6--:18;;---:2tO:--::2::2-i24:;1--:2;t6;-t2:';-8-130~-3t2;--1.56 +_-----1f__--~---1I__,r_oJ -0.24V 0 2 4 6 8 10-4Figure 10.3 (a)2To4ToVB4-1----1-""2.44 +_----t-t-\:---__0.95 'T'----t---I-~-~-+_,!--.../0.37V~65mvO+_---f__~~~~_r~Hr_r~-+_-+_-f__~-_+-_r_+~-+_-~~-_+--0 12 14 16 18 20 22 24 26 28 30 320 2 4 6 8 10To 3To 5To 7To To I23.33 3To 5ToFigure 10.3 (b)0099-4210-74

~PFIBS Systems Design Considerations When Using Cypress CMOS Circuits.nEMICoNDucroR ============================================================Example: Unterminated Line (Continued) The Rising Edge of the Write StrobeVSl = -4V X (-0.61) = 2.44V. At t = 22 ns the rising edge of the write strobe begins,which is the equivalent of closing the switch in Figure 10.1This wave propagates from the source to the load and arrivesat t = 3 To, and adds to the (zero volts) signal. Thein the 1 position. For this analysis it its convenient to startthe time scale over at zero, as is shown in Figures 10.3 arisetime is preserved, so the time required for the signal toand b.go from OV to 2.44V is;tr = 2.44V X 2 ns/4V = 1.22 ns.The signal at the load thus reaches the 2.44V level at timet = 3 To + 1.22 ns = 5.22 ns and remains at that leveluntil the next reflection occurs at t = 5 To. The wave thatarrived at the load at 3 To is reflected back to the sourceand arrives at t = 4 TO (5.32 ns). The 2.44V level adds tothe -4V level, so that the resultant level is -1.56V. Therisetime is preserved, so that this level is reached at t = 4TO + 1.22 ns = 6.54 ns, and maintain.ed until the nextreflection occurs at t = 6 To. The 2.44V wave that arrivedat the source at t = 4 To is reflected back to the load andarrives at t = 5 TO. The portion that is reflected back is;VS2 = 2.44 X (-0.61) = -1.49V.This subtracts from the 2.44V level to give 2.44 -1.49 =0.95V. The falltime is preserved, so the time required forthe signal to go from 2.44V to 0.95V is;tf = 1.49V X 2 ns/4V = 0.75 ns.The 0.95V level is thus reached at time t = 5 TO + 0.75ns = 7.4 ns.At t = 6 To the 0.95V wave arrives back at the source,where it subtracts from the -1.56V level to give -0.61V.The risetime is tr = 0.95 X 0.5 nsIY = 0.45 ns.The 0.95V wave that arrived at the source at t = 6 To isreflected back to the load and arrives at t = 7 To. Theportion that is reflected back is;VS3 = 0.95 X (-0.61) = -0.58V.This subtracts from the 0.95V level to give 0.37V. Thefalltime is approximately 0.5 ns.This process continues until the voltages at points A and Bdecay to approximately zero volts.ObservationsThe positive reflection coefficient at the load and the negativereflection coefficient at the source result in an oscillatorybehavior that eventually decays to acceptable levels.The voltage at point A reaches -0.61V after 6 To delaysand the voltage at point Breaches 0.37V after 7 To delays.The reflection at the load that causes the voltage to exceedthe TTL minimum ONE level (2V) at T = 3 To couldcause a problem if either the data to be written in the RAMchanges up to 5 To delays after the falling edge of the writestrobe or if the observed shortening of the write strobe by 5TO delays violates the minimum write strobe specification.However, if this reflection occurred on a clock line to alogic device, registered PROM, or a PLD the reflectioncould be interpreted by the device as a second clock. Thewidth of the pulse caused by the reflection in this case is 2To = 2.66 ns, which is probably too short to be detected.If the line were either slightly longer or more heavily capacitivelyloaded the pulse would be wider and could bedetected as a second clock.If the forcing function were a step function, the equationsof Table 1 (h) would apply. The time constant in the equationis:RZo' CeT = --=--­R + Zo'(10-1)Because R ~ ZO', T = ZO' Ce, where Zo' = 41.80. andCe = 33.2 pF.This is the equivalent of saying that the five megohm deviceinput resistance can be ignored for transient circuitanalysis. Substitution of Zo' and Ce into the precedingequation yields a time constant of T = 1.39 ns.Writing the equation for the voltages for the circuit of Figure10.1VA(t) = i Zo' + -1 Itidt. (10-2)Ce 0Also, VA(t) = Kt U(t) - K(t - Tl) U(t - Tl). (10-3)Where Kt is the rising edge of the write strobe (K =2V Ins) applied at t = 0 using a unit step function, U(t),and - K (t - Tl) represents an equal but opposite waveformapplied at t = Tl (after the risetime) using a unit stepfunction, U(t - Tl).Equating the equations and taking the LaPlace transformsof both sides yields:K K E -TIS I(s) ( 1 )- - --- = Zo' I(s) + - = Zo' + - I(s).s2 s2 Ces Ces(10-4)1 It I(s)However, VB(t) = - i dt, or VB(s) = - .Ce 0 CesTherefore:K K E-TISS2 s2 ( zo' + _1_) Ce s VB(s). (10-5)CeSSolving for VB(s) yields:~ (1 -E-TIS)VB(s) = .Ces (zo' + _1_)CesWhich is equivalent to:K--(1 - E-TlS)Zo'CeVB(s) = ( 1) .s2 S +-­Zo'Ce(10-6)(10-7)10-75

~RPSS Systems Design Considerations When Using Cypress CMOS CircuitsWnlCONDucroR ==============================================================Example: Unterminated Line (Continued)Taking the inverse LaPlace transform yields:VB(t) = [K Zo' Ce ( E zoo Ce - 1) + Kt] U(t) -[-(t-Tl)-t(10-8)K ZO' Ce (E Zoo Ce - 1) + K(t - Tl) ]U(t - Tl)Equation 10-8 consists of two terms. The first term appliesfrom time zero up to and including Tl and the second termapplies after T1.KZo'Ce ~ KVB(t) = (E Zo Ce - 1) + - (t) t ~ Tl (10-9)TlTlKZ 'Ce ~ ~VB(t) = 0 (1 - E zoO Ce) E zoO Ce + Kl t > Tl (10-10)Tl .where Kl = final value = 4VSubstitution of the proper values into equation 10-9 yieldsat t = T 1 = 2 ns.VB(t = Tl) =2 X 41.8 X 33.2 X 10- 12 1439 2V---2-X-I-0--- 9---(E-' - 1) + ns X 2ns= - 1.057 + 4 = 2.94VIf the forcing function would have been a step function theequation would be:VB(t) = 4V (1 - E zoo Ce) (10-11)at t = 2 ns, VB = 3V, which is greater than the 2.94Vcalculated using equation 10-9.At t = (22 ns) + To the voltage waveform begins to buildup at the load and continues to build until the first reflectionfrom the source occurs at t = 3 To.Equation 10-10 is used to calculate the voltage at the loadat t = 2 To (because 1 To is used for propagation delaytime).VB(t = 2 To) =-2V X 41.8 X 33.2 X 10- 12 1439 22 X 10- 9(1 - E-' ) (E- ) + 4-t= -1.39 (0.762)(0.135) + 4= -0.143 + 4 = 3.86VThe voltage at the load will remain at this value until thefirst reflection from the source reaches the load at t = 3TO·Meanwhile, at t = To, the wave at the load is reflectedback to the source and arrives there at t = 2 To. It subtractsfrom the 4V level at the source as illustrated in Table4 (c). The amplitude of the "droop" is given by:for the case Vs = ZO'.C'Zo'VoV ""'---r - 2 TR(10-11)If Vs =1= Zo' equation 10-11 must be modified. Instead of-Vo the voltage is V 0 ( Rs ) , so that equation 10-112 RS + Zo'becomes:where: C' =V ~ C' ZO' Vo ( RS ).r TR RS + Zo'10 pFZo' = 41.80Rs = 280TR = 2 nsVo = 4VSubstitution of these values into equation 10-12 yields:Vr = 0.33V.(10-12)4V - 0.33V = 3.67V, so there is no danger of the voltagedropping below the minimum HIGH level.The reflection coefficient at the source is:_ Rs -Zo' .Rs = 280ps - , where. Z ' = 41 81"\Rs+Zo 0 .Ups = -0.198The amount of voltage reflected from the source back tothe load is then:VSl = (-0.33) X (-0.198) =+0.065V.This same result could have been obtained by applying theramp function of Figure 10.2 to a large resistor and then toa capacitive load and adding the results using superposition.ObservationsThe risetime of the waveform at the load is reduced by the10 pF load capacitor. The reflection at the source causedby the load capacitor is insufficient to reduce the 4V levelto less than the TTL one level (2V).The reflection coefficient at the source is sufficiently smallso that the energy reflected back to the load is insufficientto cause a problem.10-76

~~=SummaryThe example has demonstrated that, under certain conditions,the voltage reflections caused by the impedance mismatchbetween a PCB trace and the input of a CypressCMOS integrated circuit may cause a pulse whose energyis sufficient to be detected by another circuit.It is the responsibility of the system designer to identifyand to analyze these conditions and to then modify thedesign such that the reflections will not occur.Systems Design Considerations When Using Cypress CMOS CircuitsReferences1. Matick, Richard E,: Transmission Lines For Digital andCommunications Networks, McGraw Hill, 1969.2. Blood, Jr, William R.,: MECL System Design Handbook,Motorola Inc., 1983.10-77

CYPRESSSEMICONDUCTORMicrocoded Systems PerformanceThe microcoded processor family of devices offered by CypressSemiconductor are the fastest available. High performancesystems designed for specific applications can beconfigured using this high performance chip set. The performanceof these devices in 16- and 32-bit processors isdetailed below.Increasing functional integration is evident in theCY7C9101 16-bit slice, which is the equivalent to fourCY7C901s (4-bit slice) and a 2902 carry lookahead generator.By placing these functions on a single chip, the interconnectdelays between chips are reduced. Significant improvementin overall system throughput, reduced boardspace, and reduced power requirements are among the advantagesof the CY7C9101 systems over CY7C901 basedsystems. Following is a critical path timing analysis of thedata loop and control loop for generic 16- and 32-bit systems.A discussion of the speed and power advantages offeredby CY7C9101 systems will also be presented.Minimum Cycle Time Calculations for 16- and 32-Bit Systems~----------------MCNWIRED "OR" F=OFROM OTHER CY7C901 s~F=Ot-4 ..........'"'IMICROPROGRAMMEMORYCY7C901(1 )CY7C901(4)Cn+ 4OVR 1---+---.....F34DATAREGISTERDATAREGISTERFigure 1. CY7C901 Based 16-Bit System (Pipelined System, Add without Simultaneous Shift)0096-1CY7C245CY7C901Carry LogicCY7C901RegisterData LoopClock to OutputA,BtoG,PGo, Po to Cn +zC n to Worst CaseSetup1228918471 nsCY7C245MUXCY7C910CY7C245Control LoopClock to OutputSelect to OutputCCtoOutputAccess Time1212222066nsMinimum Clock Period = 71 ns10-78

~ Microcoded Systems Performance~~~NDUCTOR ==========================================================================Minimum Cycle Time Calculations for 16· and 32·Bit Systems (Continued)}TOCY7C901(6.7.8)}TOCY7C901 (2.3.4)FROt.! CY7C901(5.6.7)WIRED "OR" F=OFROt.! OTHER CY7C901s,--..Figure 2. CY7C901 Based 32-Bit System (Pipelined System, Add without Simultaneous Shift)Data LoopControl LoopCY7C245 Clock to Output 12 CY7C245 Clock to OutputCY7C901 A, BtoG, P 28 MUX Select to Output[ Go, Po toG,!' 12 CY7C91O CC to OutputCarryGo, Po to Cn + x 9 CY7C245 Access TimeLogicCn to Cn + x. y, z 14CY7C901 C n to Worst Case 18Register Setup 497 osMinimum Clock Period = 97 ns0096-21212222066 os0096-3Figure 3. CY7C9101 Based 16-Bit System (Pipelined System, Add without Simultaneous Shift)Data LoopControl LoopCY7C245 Clock to Output 12 CY7C245 Clock to OutputCY7C9101 A, B to Y, C n + 16, OVR 37 MUX Select to OutputRegister Setup 4 CY7C91O CCto Output53 os CY7C245 Access TimeMinimum Clock Period = 66 ns1212222066 os10-79

~ Microcoded Systems Performance~~~U~================================================================Minimum Cycle Time Calculations for 16· and 32·Bit Systems (Continued)0096-4Figure 4. CY7C9101 Based 32-Bit System (Pipelined System, Add without Simultaneous Shift)CY7C245CY7C9101CY7C9101RegisterData LoopClock to OutputA, BtoC n + 16C n to Worst CaseSetup123524475 nsCY7C245MUXCY7C91OCY7C245Minimum Clock Period = 75 nsControl LoopClock to OutputSelect to OutputCC to OutputAccess Time1212222066nsPower is an important consideration in microcoded systems.For an equivalent system, the CY7C901 offers substantialsavings in power over the bipolar devices. Coupledwith other low power Cypress CMOS devices, the powersavings over bipolar is clearly evident. The functional integrationof four CY7C90ls with carry lookahead gives theCY7C91Ol even greater advantages. The number of ALUelements is reduced by a factor of four, also, there is areduction in the carry logic needed. A comparison betweenbipolar, CY7C90l-based, and CY7C91Ol-based systems isgiven below in Table 1. Note that in this comparison, thedevices common to all 16- and 32-bit system configurationsare included in the Icc computations.Cypress CMOS devices offer the highest speed microcodedsolutions while keeping power consumption to reasonablelevels. The CY7C90l-based systems win over bipolar's fastestdevices in a speed comparison, while consuming roughlyYa the power. Upgrading to the CY7C9l0l will result ineven faster systems, at close to '13 the power of theCY7C90l-based systems. This comparison is illustrated below,in Table 2.Table 1ICC Calculations for 16·Blt Systems (All Figures in mAlCypress CMOSCY7C901 CY7C9101 BipolarBased BasedSequencer 100 100 340Registered PROM 90 90 185Carry Logic 110 - 110ALU Elements4x Four-Bit Slice 320 106016-Bit Slice 75Total 620 265 1695Icc Calculations for 32·Bit Systems (All Figures in mAlCypress CMOSCY7C901 CY7C9101 BipolarBased BasedSequencer 100 100 340Registered PROM 90 90 185Carry Logic 330 110 330ALU Elements8x Four-Bit Slice 640 21202x Sixteen-Bit Slice 150Total 1160 450 2975Table 2. SpeedlPower Comparison between Bipolar, CY7C901, CY7C9101Minimum Qock Cycle (ns) Maximum IcC (mA)Bipolar CY7C901 CY7C9101 Bipolar CY7C901 CY7C910116-Bit Systems 85 71 66 1695 620 26532-Bit Systems 111 97 75 2975 1160 45010-80

CYPRESSSEMICONDUCTORIntroduction to Diagnostic PROMsScope and PurposeThis Application Brief will provide the reader with a basicunderstanding of the concept of a diagnostic PROM, aswell as a brief introduction to possible applications.Beginning with a short tutorial on system diagnostics, thereason for incorporating diagnostics into a design and thespecial testability problems associated with sequential designsare presented. The concept of shadow-register-baseddiagnostics is presented, and the benefits of this approachare outlined.Next, a description of Diagnostic PROMs is given. Thiscovers the similarity/dissimilarity of diagnostic PROMsrelative to standard registered PROMs, as well as fundamentaloperation of a diagnostic PROM followed by a descriptionof the Cypress CY7C268 and CY7C269 8K x 8Diagnostic PROMs.In conclusion, an application example is presented.Introduction to System DiagnosticsAs electronic systems continue to grow in size, functionality,and complexity, it is becoming increasingly difficult totest them and determine their reliability, as well as to servicethe end product in the field. One way to simplify thetask of testing electronic systems is to design some form oftestability into the system.Controllability and observability are the key points of testability.These two qualities are easily obtained for a combinatorialsystem where the outputs are strictly a function ofthe current inputs. Test vector methods are easily devisedand implemented for combinatorial systems. But, for a sequentialsystem, where the outputs are a function of boththe current inputs and the previous state(s), controllabilityand observability may be lost due to lack of access to theinternal states of the machine. Consequently, building testabilityinto a system means being able to control and observeall possible states of a system.Consider the simple sequential machine in Figure 1. As isevident, access to internal states-which is necessary forcomplete controllability and observability-is either deniedor difficult to obtain. The obvious way to add testability tothis system is to pehnit access to these internal states. Oneway to gain this access is through addition of a diagnosticshadow register, as shown in Figure 2. Observability is effectedby adding a serial data output path (SDO) to allowshifting internal state information out of the system. Controllabilityis gained by permitting a serial data input path(SOl) to set the state of the internal registers. As a result,relatively simple test vector methods can again be used totest the system. Consider, for example, the complex sequentialmachine shown in Figure 3. This system would bevirtually impossible to test in the current configuration,due to the fact that we can not control or observe theinternal states of the machine. In order to increase the testabilityof this machine, observability must be added atpoints 01,02, and 03. If this were accomplished, one wouldbe able to observe the internal states of the machine. Additionally,controllability must be added at points Cl, C2,and C3. This would enable the internal states of themachine to set. This controllability and observability canbe attained by adding shadow registers, as depicted in Figure4. The result is a complex sequential machine with aINPUTSCOMBINATORIALlOGICI---_~--... OUTPUTSSTATEOUTPUTSClKINTERNAL STATE fEEDBACKSEQUENTIAL SYSTEMFigure 1. Simple Sequential Machine0125-110-81

~ Introduction to Diagnostic PROMs~~~ucrOR================================================================INPUTSCOMBINATORIALLOGIC1---+-------+ OUTPUTSSTATEOUTPUTSSEQUENTIAL SYSTEMFigure 2. Simple Sequential Machine with Diagnostic Capability0125-2COMBINATORIALLOGICOUTPUTSSYSTEM INPUTS•r-------------------------------COMBINATORIALLOGIC02DCLK01COMBINATORIALLOGICOUTPUTS03DCLKFigure 3. Complex Sequential Machine0125-3high degree of testability. As a result of these actions, simpletest vector methods can now be used to fully test themachine. For instance, the state of the register at point Clcan be set, the machine may be clocked through someknown number of cycles, and the state of the machine maybe observed at points 01, 02, and 03.Knowing what state the machine should be in at that particularpoint in time at each observation point, the known"correct" state of the machine can be compared with theobserved machine state (at each observation point), therebydetermining if: a) the machine is functioning correctly; andb) if not, which "machine primitive" is not functioningcorrectly (fault detection). Note that this approach to sequentialdesign will also permit testing to see what the machinewould do if a glitch caused a jump into an unusedstate, which in tum makes the design task of forcing themachine back into a known state much less complex.The real advantage of this approach is that it requires nochanges in architecture, minimal hardware changes, andresults in a minimal (5-10%) area hit when integrated intoexisting integrated circuits.Diagnostic PROMsDiagnostic PROMs are a relatively minor migration fromstandard registered PROMs. A block diagram of a diagnosticPROM is presented in Figure 5. The addition ofdiagnostic capability to a registered PROM includes theaddition of:-a shadow register-multiplexer-MODE pin-SDI (Serial Data In) pin-SDO (Serial Data Out) pin-diagnostic clock10-82

~ Introduction to Diagnostic PROMs~~~NDUcrOR=====================================================================3,COMBINATORIALfHT"r-~ LOGIC~"UX ~~ 2V,~ ~vPCLK ~r----I-- SHADOW ~ ,........-~ REGISTERr+ .....-~~I-COMBINATORIALLOGIC r-- r----~ ~ ~ 6"MUX REGISTER,.. I-~ 2vPCLK ,~r-----rL+41" T~vL. I-- SHADOW I---,COMBINATORIALLOGIC r-- r----~ ~ 6"MUX REGISTER;+ I-81" 2,PCLK ~----r----rL+1lSHADOWI---I I•0125-4Mode, SDI, SDO, and DCLK for each "Machine Primitive"Figure 4. Complex Sequential Machine with Diagnostic Capability.----------------------------------------IISTATEOUTPUTSCOMBINATORIALLOGICOUTPUTSMOOE--I-~SERIAL DATA IN (SOl)The shadow register is dynamically configured based onthe value of the mode signal. If mode is set such that theuser desires to input data to the PROM, the shadow registeris configured as serial-in, parallel-out; if the user desiresto extract information from the PROM, the shadow registeris configured as a parallel-in, serial-out. So the shadowFigure 5. Diagnostic PROM Block DiagramSERIAL DATA OUT (SOO)0125-5register serves two purposes: First, the shadow register canbe configured to serially receive the data that can be transferredto the register containing state information and appearat the outputs during the next cycle. The obvious advantageof this feature is that it allows the user to effectivelypreset the condition that will be sent through the part of10-83

~ Introduction to Diagnostic PROMs~~~UcrOR ==============================================================the system that "follows" the PROM; ie, the user can insertstate information into the system. This feature addscontrollability to the system.The second purpose that the shadow register serves is toallow the user transfer data from the register containingstate information and to serially shift that data out of thePROM. This feature adds observability by allowing theuser to observe the state of the PROMs pipeline register atany given point in time. Inclusion of the above named featuresin a registered PROM can therefore add testability toany system by providing the user with the mechanism tobuild both controllability and observability into his system.Note that this increase in functionality is effected withoutloss of other desirable registered PROM features such asprogrammable initialization, programmable output enable,etc.Cypress Diagnostic PROMsCypress Semiconductor manufactures two DiagnosticPROMs, the CY7C268 and CY7C269. These 64K bytewideDiagnostic PROMs are manufactured in CMOS forthe optimum speed/power tradeoff resulting in 550 m Wpower dissipation while maintaining 40 ns maximum setupand 20 ns clock-to-output. Both contain an edge-triggeredpipeline register and on-chip diagnostic shift register.Both are capable of withstanding > 200 1 V ESD. Both areproduced in our EPROM-based process, which allows testingfor 100% programmability. Both are available inPLCC/LCC and Dual Inline Packages, and both are availablein a windowed package for reprogrammability. TheCY7C268 features full diagnostic capability and is availablein 32-lead PLCC/LCC or 32-pin 0.5 in DIPs. TheCY7C269 features limited diagnostic capability and isavailable in 28-lead PLCC/LCC or 28-pin 0.3 in DIPs.For an in-depth description of functionality, refer to thedata sheet. The following discussion briefly describes thediagnostic functions available in each device.MODEPCLKENAINITCONTROLLOGICA condensed block diagram of the CY7C268 is presentedin Figure 6. The pin names and functions of the CY7C268are as follows:0 0 -0 7CY7C268Name I/O FunctionAo-AI2 I Address Input00-07 0 Data LinesENA I Synchronous or AsynchronousOutput EnableINIT I Asynchronous InitializeMODE I Sets PROM to Operate inPipelined or Diagnostic ModeDCLK I Diagnostic Clock (Used to Clockthe Shadow Register)PCLK I Pipeline Clock (Used to Clockthe Output Registers)SDI I Serial Data In (Used to SeriallyShift Data into the DiagnosticRegister)SDO 0 Serial Data Out (Used to SeriallyShift Data Out of the DiagnosticRegister)Note that full diagnostic capability is realized through theuse of four control signals: SDI (Serial Data In), SDO(Serial Data Out), MODE, and DCLK (diagnostic c1oc~).Inclusion of both DCLK and PCLK assures that senaldata can be shifted into or out of the diagnostic registerwhile the PROM is operating in normal pipeline fashion.As a result, the CY7C268 has three possible modes of operation:i. normal (pipelined)ii. diagnosticiii. both simultaneously88 - BIT DIAGNOSTICSHIFT REGISTERFigure 6. Condensed Block Diagram of the CY7C2688SOlSOO0125-610-84

~CYPRESSIntroduction to Diagnostic PROMs'nEMICONDucroR ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;============The following table summarizes the operational modes of the CY7C268:Data Flow Description Mode ENA[l] SDI SDO DCLK PCLKNormaIOperation[l] L H,L DATA IN SDO - tShadow to Pipeline[l] H H,L X SDI - tPipeline to Shadow H L L SDI t -Data In to Shadow H H L SDI t -Shift Shadow Reg.l1] L H,L DATA IN SDI t -No Operation[l] H H,L H SDI t -Note:1. For the asynchronous enable operation, data out is enabled on the first LOW to HIGH clock transition after E is brought LOW. When E goes fromLOW to HIGH (enable to disable) the outputs will go to the high impedance state (after a propagation delay) immediately if the asynchronousenable was programmed. If the synchronous enable was selected, a LOW to HIGH transition is required.CY7C269A condensed block diagram of the CY7C269 is presentedin Figure 7. As is evident, the CY7C269 has reduced diagnosticfunctionality relative to the CY7C268. TheCY7C269 is ideal for applications requiring limited diagnosticswith a premium on board space conservation, and isavailable in 28-pin, 300 mil DIPs (windowed or opaque)and in 28-lead PLCC/LCC packages. The pin names andfunctions of the CY7C269 are as follows:Name I/O FunctionAo-A12 I Address Inputs00-0 7 0 Data LinesE,! I Enable or InitializeClock I Pipeline and Diagnostic ClockMode I Sets PROM to operate in eitherdiagnostic or regular pipelinedmode (note that the two modesare mutually exclusive).SDI I Serial Data InSDO 0 Serial Data OutNote that limited diagnostic capability is realized throughinclusion of three diagnostic signals: MODE, SDI, andSDO. Since there is only one CLOCK, the regular anddiagnostic modes are mutually exclusive. The following tablesummarizes the operating modes of the CY7C269:Data Flow Description Mode E,I Clock SDI SDONormal Operation L [1][2]t X HighZShadow to Pipeline H L t L SDIPipe or Bus to Shadow H L t H SDIShift Shadow H H t Data In SDONotes:I. E or I function selected during programming.2. If I selected, outputs always enabled. IfE selected, outputs are enabledsynchronously or asynchronously as programmed.3. Ifl selected, outputs always enabled. IfE selected, during diagnosticoperation the data outputs will remain in the state they were in whenthe mode was entered. When enabled, the data outputs will reflect theoutputs of the pipeline register. Any changes in the data in the pipelineregister will appear on the output pins.MODEEfTCLOCKCONTROLLOGIC88 - BIT DIAGNOSTICSHIFT REGISTER8SOlSDO1m88-~------------------~0 0 -0 70125-7Figure 7. Condensed Block Diagram of the CY7C26910-85

~ Introduction to Diagnostic PROMs~~~UcroR ==================================================================~Design ExampleAs an example, consider the complex sequential machinepresented earlier. This machine could be easily implementedusing CY7C268's or CY7C269's, as shown in Figure 8.Note that the block labeled "diagnostic control" could consistof PLDs, PROMs a sequencer, or a small microcontroller.The choice between using the CY7C268 or theCY7C269 would be based complexity of the diagnosticfunction required. For full diagnostics that can functionsimultaneously with regular pipelined operation, theCY7C268 should be used. For an application where limiteddiagnostic capability is required-perhaps only a power-upor at some other well-defined point in time-the CY7C269may be used.SYSTEM INPUTS2~I ADDRESS DECODER IPROGRAMMABLE ARRAY I8!~~--+f DIAGNOSTIC MUXI4 IDIAGNOSTIC CONTROL4~r0-CONTROLLOGIC8 8PROG. INITIALIZE WORD I8 - BIT DIAGNOSTIC ~SHIFT REGISTERIr+tH 8 - BIT PIPELINE REGISTER ILl- ;,824873I ADDRESS DECODERPROGRAMMABLE ARRAY II ADDRESS DECODERPROGRAMMABLE ARRAYI8!~~--+l-DIAGNOSTIC MUXIr--4I8!-lDIAGNOSTIC MUXICONTROL4LOGIC--+I8 8PROG. INITIALIZE WORD I8 - BIT DIAGNOSTIC ~H 8 - BIT PIPELINE REGISTER I SHIFT REGISTERtlI8-1 ;,CONTROL....LOGICr-+I8 8PROG. INITIALIZE WORD I8 - BIT DIAGNOSTIC ~SHIFT REGISTERH 8 - BIT PIPELINE REGISTER Itl ~- b828868862Figure 8. Complex Sequential Machine Implemented with Cypress Diagnostic PROMs0125-810-86

CY7C330 Design Example:High Speed Asynchronous SCSIControllerIntroductionThis application note describes a minimal, though extremelyfast SCSI (Small Computer Systems Interface) controllerthat is built up from a few parts surrounding a CY7C330synchronous state machine PLD. The controller is compliantwith the SCSI standard for a host-based minimally featuredinterface.A speed of 12 Megacycles is achieved by efficiently usingvarious features of the CY7C330. The 50 MHz speed, theinput registers, and the device size including the array sizeare all features which help to achieve this level of performance.At 50 MHz, the register to register transfers can occur at20 ns intervals which is fast enough to keep datapath transfersout of the way of SCSI transfers. In order to achieveoptimal throughput, the SCSI handshake transfer must bemade the limiting factor, so this clock speed is necessary.The input registers are used to synchronize external signals.Synchronization is necessary so that the state machinecan respond to these signals, and the input section of thestate machine is the correct place to perform the task. Sincethe signals are synchronized at the input to the array, adherenceto grey code transitions can be ignored in the designand thus time critical transitions can be made in lesscycles.The device and array size of the CY7C330 are sufficient toaccommodate the entire control section of the interface. Infact, because the device is large enough, several signals areshared and therefore more features can be accommodatedin this design than would be the case if the interface wasconstructed from smaller PLDs.The minimally featured SCSI Host implementation is acomplete interface to one or more SCSI controllers from asingle host.ConventionsIn this document, conventions are followed so that signalnames in timing and state diagrams can be related to schematicsunambiguously.If a signal name appears suffixed by a minus sign ( - ) thenthat signal is active low. The minus sign is part of thesignal name, and not an operator. As an example, the signalACK - appears on several timing diagrams and theminus is there to remind the reader that a low on the timingdiagram is the asserted state.In state diagrams the asserted states appear as 1 'so Thismakes the diagram easier to read than one with T's andF's. In any case there is no ambiguity because the booleanvariables which are used in state diagrams are not circuitlevel signals. For example, the variable CDIT is used in astate diagram with a 1 being true, while the correspondingsignal name in the schematic and the timing diagram isCDIT- with a low assertion level.The slash 'j' is the inversion operator. This is similar to theBAR operator in boolean algebra, so j A has the sameCOt.lPUTERBUS INTERrACE....-DBO-DB7BSYACKRSTSELC/oREOI/Ot.lSGSCSI BUS--,.--,.....,.. t.lASSSTORESUBSYSTEt.I0130-1Figure 1. Mass Store Subsystem and Minimal SCSI Implementation10-87

~ CY7C330 SCSI Controller~~~~u~==~~~~~~~~~~==~====~==================~==~==========meaning as A. An operator does not signify activity level,so the inclusion of a signal suffix (- or blank) is additionalinformation.The PLO definitions and equations, the signal assertionlevel should only appear in the pin name declaration. PLOequations should then be written referring only to variablenames as they appear in state diagrams and truth tables.The design file for this CY7C330 application has not beenincluded in this note, but is available from Cypress Semiconductor.HistoryThe SCSI standard evolved from the SASI controller specificationby OTC and Shugart which was a widely adoptedparallel interface for disk controllers. The current SCSIstandard is upwards compatible from this original specification.Apart from the more rigorous timing and electrical specifications,most SCSI additions (i.e. reselection, arbitration,and synchronous mode) apply when the interface is beingused as a network. If the sole use of the interface is toaccess a mass storage subsystem, then these features maybe omitted and the resultant SCSI implementation will besmaller and faster.The current SCSI interface is 8 bits wide, and it is possibleto operate in asynchronous mode for a minimally featuredinterface at a rate of up to 16 Megacycles. The interfacemay be widened to 16 bits at some time in the near future;if so, then the SCSI throughput rate will double to a theoreticalmaximum of about 32 Megabytes per second.The SCSI standard is likely to prevail in storage systeminterfaces. The only competing standard is ESDI which,being a serial data interface, has a much lower datathroughput.System ConsiderationsA block diagram of a minimal SCSI implementation isshown in Figure 1. Normally the Mass Store Subsystem isinside the same enclosure as the computer; if it is not, thenfor emission considerations differential drivers and receiversshould be used. In this application note, it is assumedthat the flat cable SCSI bus is about a foot long so thattransmission delays are minimal (5 ns).The Mass' Store Subsystem consists of one or more diskdrives or other high density storage devices, and one ormore controllers with SCSI ports. Unused lines in the SCSIbus are not shown in Figure 1.The computer system itself will access the SCSI controllerfrom its own bus. Por this example, a simple asynchronousinterface has been implemented. This interface has onlyone data strobe and there are two signals - R TS (Requestto send) and CTS (Clear to send) to request or acknowledgedata access cycles. These signals allow for the connectionof a OMA device or another data interface.The SCSI Transfer ProtocolA SCSI data access consists of a command transfer followedby a data transfer. The command transfer proceedsas follows:1) The host waits for BSY to go inactive, then asserts SELand one of the 8 data bits (to select one of 8 controllers).10-88C/D-I~REQ-I rBSY-SEL-DBX-1/0-ACK-0130-2Figure 2. Command Transfer2) The controller drives BSY active when this selectioncombination is detected.3) The host releases SEL and the data bit used for selection.4) The controller assets C/O and REQ to read a commandbyte from the host.5) The host outputs the first byte of the command andasserts ACK.6) The controller accepts the data and deasserts REQ.7) The host then deasserts ACK.8) Steps 4 through 7 are repeated for 6 bytes (more inspecial cases).After the command has been read in by the controller, theoperation is either performed or aborted. After executing acommand, a status byte (C/O asserted) is sent to the hostto indicate success or an error condition.If the command is a write command, then data is firsttransferred from the host to a buffer on the controller. Afterthe data is written to the disk, a command completestatus message is sent to the host.If the command is a read command, then data is read fromthe disk, checked for validity, and passed to the host. Somecontrollers offer a 'Ply-by' mode which means data ispassed to the host as soon as it is read, and an error conditionis signalled afterwards.The normal data transfer protocol follows the above description(steps 4 to 7). At the end of the access, the statusbyte is transferred, then activity ceases. BSY goes inactiveto signal the end of the access.Interface Timing ConsiderationsThere is one major delay and one minor delay to be observedduring selection, and there is a data setup delay tobe observed during data transfer.For the host interface, under the single initiator option inthe SCSI specification, there is a 400 ns 'bus settle delay' to

~ CY7C330 SCSI Controller~~~~UcrOR==================================================================~be observed after BSY goes false, and before SEL is asserted.Additionally, SEL is to be deasserted at least two deskewdelays after BSY is asserted. A deskew delay is 45 ns.Data is to be setup for a minimum of one deskew delayplus one cable skew delay (45 + 10 ns) before the ACKsignal is given.Like the host interface, the controller interface has timingconstraints associated with selection and data access.The controller implements the same data setup delay as thehost, but the strobe which is accommodated from the controllerside is REQ.The response to SEL must be shorter than 200 microseconds.The setup time allowed for I/O and C/D [control signals]is specified as one 'bus settle delay' or 400 ns.It is worth nothing here that the response to SEL, and thevarious 'bus settle delay' constraints, are really system levelresponse times, and need not be of concern in the hardwaredesign at this level.Performance ConsiderationsThe 7C330 is a Moore machine; there are no combinatorialpaths from the inputs to the outputs. One problem thatarises in state machine design with Moore machines is thatthe turnaround time or handshake delay to external signalsbecomes the limiting factor in throughput. This problem ismost obvious in asynchronous interfaces.Figure 3 shows a hypothetical synchronized transfer cycle.This is the cycle as it could be implemented with a 7C330synchronous state machine, if the ACK - signal was directlycontrolled by the 7C330.Figure 3. Synchronized Transfer CycleDefinitions for Figure 3:1. Tsu: 55 ns setup time for data.0130-32. TLA: Latency time delay; this consists of device propagationdelays plus 0 or 1 clock cycles. For preliminary estimates,assume a 20 ns clock and 15 ns of delay.3. T c: Clock period.4. TD: Data delay (max) after REQ deasserted.The time for one cycle using synchronized transfer cycles isabout 180 ns. This cycle time corresponds to a throughputrate of just under 6 MHz, which is not as high a rate as the7C330 is capable of supporting.The problem is that for every edge there is a synchronizationor latency delay plus a clock delay before the corre-sponding handshake signal is given. These delays are undesirableand for the most part unnecessary, since the datapath is capable of accepting data at a higher rate.This result underscores the need for supervisory controlover the handshake sequence. If the output data is readyand waiting, there is no need to delay the handshake sequenceuntil the state machine synchronizes to the eventand reacts. Likewise, if the input buffer is empty then it canbe asynchronously loaded.In the schematic (Figure 10) a NOR buffer is used to drivethe output strobes, and to perform the asynchronous handshake,and to latch ACK - until the state machine has hadsufficient time to react. The signal COlT - is used by the7C330 to supervise the handshake sequence.The SCSI Interface: Transfer to theControllerFor transfers to the controller, the asynchronous signalthat needs to be controlled is ACK - (active low acknowledge).This signal should go low soon after REQ - is assertedby the controller, but only after data has been setupfor a minimum of 55 ns. This signal should go high whenREQ - is deasserted.To guarantee that the state machine sees the cycle takeplace, ACK - is latched low until released by a controllingsignal (CDIT-) that comes from the state machine. Thesame signal is used to hold off ACK - until the data setuphas been met (refer to Schematic for latch circuit details).Another signal is required to clock data into the outputregister (CAB). This signal has a duration of two clockcycles for data setup timing. In Figure 4 the signal CAB_Dis a delayed feedback version of CAB which is used to adda delay cycle.REO - I F2..J--31\+1.,.-5-1ACK-! ~ .,I~I - ...... C 5 -j- 2 T 3 1CDIT- ~2-+3:1 I ...CBA ------.... FF~_4 ____ _...i -----CAB_D __________________ ~~~ ________ _Figure 4. Host to Controller Transfer Cycle0130-4Definitions for Figure 4:1. TAT: Asynchronous turnaround time (8 ns).2. TLA: Latency time delay; this consists of device propagationdelays plus 0 or 1 clock cycles. For preliminary estimates,assume a 20 ns clock and 15 ns of delay (25 nsaverage).3. TC: Clock period (20 ns).4. TDO: Delay to output (15 ns).5. Asynchronous turnaround time for controller end (8 ns).10-89

~ CY7C330 SCSI Controller~~~NDU~R =====================================================================Figure 4 shows the resultant transfer cycle to the controllerfrom the host. The cycle time can be estimated from oneREQ - rising edge to another. This time works out to anexpected value of 108 ns.Outputs:COl T I CAB I CAB_D IFigure 5. SCSI Transfer to Controller0130-5The state diagram for the part of the controller that handlesthe interface timing is shown in Figure 5. At the startof the cycle, CD IT - is active because it is assumed thatdata has been at the interface for at least the setup requirement.CAB is the register clock for the output register, andit goes high after REQ - goes inactive (high), if there isdata available (DAY, which is a logic function yet to bedefined). The cycle then proceeds to completion and asCDIT- goes active another cycle can start.Outputs: I EO I El I CKO I CKl IInputs:IDS/DS'/CKO'/C~ICAB· ICDI T + COl T· ICAB· ACK· IREQICAB· ICDI T + COl T· ICAB· ACK· IREQFigure 6. System Transfer to SCSIThe state diagram for the associated system transfer to theSCSI controller is shown in Figure 6. EO- and E1- areoutput enables for the two input registers; CKO and CK1are clocks for the same two registers; CTS - is a signal tothe Host system that these registers are empty.At the beginning [state 0000], EO- and E1- are inactive,the clocks are low, and CTS - is active [0]. When DS - isasserted, the clocks go high to capture the data, EO - goesactive and CTS - goes inactive to signal that the registershave been loaded [state 1011, CTS- = 1].When either CKO or CK 1 are high, data is consideredavailable by the state machine in Figure 5 and consequently,DAY = CKO + CK1. After CAB goes high, E1-goes active, EO- inactive, and CKO goes low [state 0101].The next time CAB goes high, CK 1 goes low to signify thatthe input registers are empty again [state 0100]. The statecounter then automatically progresses [0000].The machine waits for DS - to go inactive before allowinganother cycle so that double clocking does not occur onone write cycle.Transfer to the HostWhen data is transferred to the Host from the controller,the handshake happens so quickly that there is a possibilitythat the interface will not see it and for this reason ACK -must be latched until the 7C330 signals [moves CD IT -high] to release it.In this case, CDIT- is a signal that signifies that there isroom in the receiving buffer for a data transfer. CBA is theclock for the input buffer and it goes high when CD IT -goes low or afterwards.ACK- 1 I 1 ....___COlT-~2-+3-F=3==t4~I ~~I -----CBA I IFigure 7. Controller to Host TransferDefinitions for Figure 7:1. TAT: Asynchronous turnaround time (8 ns).0130-72. TLA: Latency time delay; this consists of device propagationdelays plus 0 or 1 clock cycles. For preliminary estimates,assume a 20 ns clock and 15 ns of delay. (25 nsaverage).0130-6 3. TC: Clock period. (20 ns).4. TDO: Delay to output (15 ns).Figure 7 shows the relevant timing for this transfer cycle.The cycle time can be estimated from the rising edge ofCD IT - to the next similar edge. In this case, it is reasonableto expect a cycle time of about 80 ns.10-90

~ CY7C330 SCSI Controller~~~NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Output: ~In puts: '-1-A-CK---.I.... c-K-O-.I .... c-K-1 ... I-o-s ... 1IDS' (/CKO + ICK§CKFigure 8. SCSI Tranfer to HostFigure 8 shows the state diagram for this cycle.EO 1 E1 1 Outputs: 1 CKO 1 CK1 1 RTS 1~ Inputs: 1 COlT 1 OS 1~olOS OS11 OS0130-80130-9Figure 9. Transfer to Host SystemFigure 9 shows the data diagram for the system to interfacetransfer cycle.Staging ConsiderationsStaging considerations include the initialization, startup,and change of direction of the interface. The signal 'I/O'from the SCSI port mandates the direction of transfer, andthis changes during the process of command completion,so there is a need to make sure that the relevant state machinesare all qualified by '10'.A readback path is provided for the CPU on the Hostsystem to be able to read the SCSI signals directly. Thesignal DS - is reserved for normal data, but the signalsCSO - thru CS 1 - allow DO on the system data bus to beused to read SCSI signals.The following addresses apply:CSO = 0: enable readback to DOCSO = 1: disable readbackCS2,CS 1: 00 - BSYCS2,CSl: 01 - C/DCS2,CSl: 10 - I/OCS2,CSl: 11 - REQThe reset function for SCSI Controllers is independent ofthe Host interface controller. In the schematic of Figure 10,the signal RST is set by the Host system and this simplyforces the RST - signal low on the interface.The controller can be reset at any time by asserting INITfromthe Host system. If the code 001 is on CS2, CS 1, CSOthen a select is performed: SEL - is pulled low untilBSY - appears.The transfer of data to the interface, in particular the deviceselect code, should be done before the selection sequenceis performed. After INIT - is released, data can betransferred normally and the REQ, ACK handshake willoperate properly.The transfer of diagnostic data (i.e. sense byte, errors) tothe Host will be indicated by the DIAG - flag which is setuntil INIT - is asserted.10-91

~~...tD~P0 ::c-b =IV ~00nrJl"""' '"C~ =~II~dr:DBO ~~ SAB I ~ SAB22 ~eBA 22 ~CBA 74AS80SSYSTEW DATA BUS 0(0-7)< db(O-lS) U3 Ul SCSI Port DotDBOAl Bl 20 4 Al Bl 20DBO- >~1A2 B2B2 DB1- >.IlB26~:1>B3A3 B3 B3 ~-2DB4A4 B4 A4 B4 DB3- >DBS 9 AS B5 9AS B5*-~10 A6 B6 10A6 B6 ~ .DB7 11 ~~ :~ 1311 A7 ~ - >13VeeA8-1mL=->2121G DIR - G~ 1 USADIRD1R~~CAB VeeiCAB 3~ 2 2 SEL-SBA SBA 10'REQ-RE .74AS64674AS648DIRU2DB8 4 Al Bl 20JHt9 5,DBJJl 13A2 B2~-.~1)BllA3 B37-- 8 ~DB 12 8 A4 B4 74AS80S 74AS80SDB13 9AS B5A6 B6JlB.1A :::ro USDA7DB1S 11A8:~ 13U4SCK~ 1 13J~~ G m- 28 01 CKH 74AS80SDIRCKO ] 02 C/IH r--~ ~CAB 03 12~_~ SAB DBO rd_slg -=-1i 04 BSY':~ C/-22 ~CBA EI- 23 05 C D'SBAl;UII- :l~ 06 15SEL IS 07 16I10.YSTEt.4 CONTROL74AS6461718SIGNALS1950 ck 011 110~~' ~CTS- 012 111 t.4SG·CTS-RIS-RISniAG-DIAG-7C330::0--: ._ USE SCSI Port SlanaI csl -c~~::::::::::::::::::::::::::::::::::::::=----------------------------------------------~74AS80S0130-10!'~mS9o~=rJ'l@1-4n::ttD...=

PRODUCT,.INFORMATIONSTATIC RAMSPROMS•IIIEPLDSLOGICRISCBRIDGEMOSIIQUICKPROQUALITY ANDRELIABILITYAPPLICATION BRIEFSPACKAGESa

~ Section Contents~~~NDUcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~PackagesPage NumberThermal Management and Component Reliability ........................................................... 11-1Package Diagrams ..................................................................................... 11-6

CYPRESSSEMICONDUCTORThermal Management andComponent ReliabilityOne of the key variables determining the long-term reliabilityof an integrated circuit is the junction temperature ofthe device during operation. Long-term reliability of thesemiconductor chip degrades proportionally with increasingtemperatures following an exponential function describedby the Arrhenius equation of the kinetics of chem-ical reactions. The slope of the logarithmic plots is given bythe activation energy of the failure mechanisms causingthermally activated wear out of the device (Figure 1).Typical activation energies for commonly observed failuremechanism in CMOS devices are shown in Table 2.I ,I /~ 104:::iiii«:::iLaJ0:::/LaJ>~~LaJ0:::103102JJII'#II /N ~~N 1= .....-.:t' -enI I ,." -~'" en/10 1 II / /~ I-- ~ I... fj - ...... c:;,01'lI,I" /I,/If./'~~Nt-- ()...... , .JI'~t7 - ~e~ V~ ~~ ~./~()7 ./~e'>lO·0:::II .,-" ~~ en- enI'~ 01- 0 _0.", 9: ~ ~CD'- z- U200175 150 125 100 75 50 25TEMPERATURE (C)0064-1Figure 1. Arrhenius plot, which assumes a failure rate proportional to EXP (- EA/kT)where EA is the activation energy for the particular failure mechanismm11-1

~ Thermal Management~~~U~ ==================================================================Table 2. Failure Mechanisms andActivation Energies in CMOS DevicesFailure ModeOxide DefectsSilicon DefectsElectromigrationContact MetallurgySurface ChargeSlow TrappingPlastic ChemistryPolarizationMicrocracksContaminationApproximateActivation Energy (EQ)0.3eV0.3 eV0.6eV0.geV0.5-1.0 eV1.0eV1.0eV1.0eV1.3 eV1.4eVTo reduce thermally-activated reliability failures, CypressSemiconductor has optimized both their low power generating1.2,... CMOS device fabrication process and their highheat dissipation packaging capabilities. Table 3 demonstratesthis optimized thermal performance by comparingbipolar, NMOS and Cypress high speed lK SRAM CMOSdevices in their respective plastic packaging environmentsunder standard operating conditions.Table 3. Thermal Performance ofFast lK SRAMS in Plastic PackagesTechnology Bipolar NMOSDevice Number 93422 9122Speed (ns) 30 25IcC (mA) 150 110VccCV) 5.0 5.0PMAX(MW) 750 550Package RTH (JA) eCIW) 120 120Junction Temperature eq 160 136at Data Sheet PMAX*CypressCMOS7C122*T ambient = 70°CThe Cypress 7C122 device, during its normal operation,experiences a 91°C junction temperature, whereas competitivedevices in their respective packaging environments seea 45°C and 69°C higher junction temperature. In terms ofrelative reliability life expectancy, assuming a 1.0 eV activationenergy failure mechanisms, this translates into animprovement in excess of two orders of magnitude (lOOX)over the bipolar 93422 device and more than one order ofmagnitude (30X) over the NMOS 9122 device.25605.03007091Thermal Performance Data of CypressComponent PackagesThe thermal performance of a semiconductor device in itspackage is determined by many factors, including packagedesign and construction, packaging materials, chip size,chip thickness, chip attachment process and materials,package size, etc.Thermal Resistance (8 JA, e JdFor a packaged semiconductor device, heat generated nearthe junction of the powered chip causes the junction temperatureto rise above the ambient temperature. The totalthermal resistance is defined as,TJ - TAOJA=---Pand OJA physically represents the temperature differentialbetween the die junction and the surrounding ambient at apower dissipation of 1 watt.The junction temperature is given by the equation:TJ = TA + P [OJA1 = TA + P [OJC + OCA]where:TJ - TcTc - TAOJC = --- and OCA = ~-----'-"PPT A = Ambient temperature at which the device is operated;Most common standard temperature of operationequals 70°CTJ = Junction temperature of the IC chipTc = Temperature of the case (package)P = Power at which the device operatesOJC = Junction to case thermal resistanceOJA = Junction to ambient thermal resistanceOCA = Case to ambient thermal resistanceThe junction-to-ambient environment is a still-air environmentwhere the device is inserted into a low-cost standarddevice socket and mounted on a standard .062" GIO PCboard. For junction-to-case measurements, the same assemblyis immersed into a constant temperature liquid reservoirapproaching infinite heat sinking for the heat dissipatedfrom the package surface.The thermal resistance values of Cypress standard packagesare graphically illustrated in Figures 4 through 7.Each envelope represents a spread of typical Cypress integratedcircuit chip sizes (upper boundary = 5000 Mils 2 ,lower boundary = 30,000 Mils2) in their thermally optimizedpackaging environment.All thermal characteristics are measured using the TSP(Temperature Sensitive Parameter) test method describedin MIL STD 883C, Method 1012.1. A thermal silicon testchip, containing a 250. diffused resistor to heat the chipand a calibrated TSP diode to measure the junction temperature,is used for all characterizations.11-2

5r~,.-..I-~?;"'- u0~L.a.Juz

(ir~,..-..100.- DIE SIZE~ 90 - 5,000 SO MILS.~ -30,000 SO MILS."- u80070"'-"wu 60z« 50.-(f)(f) 40W0::: 30.....J« 20~ JC0:::wI10.- 0r16 20 24 28 32 36 40LEAD COUNT----.Figure 6. Thermal Resistance of Cypress Hermetic Chip Carriers (HLCC)!:::~10090u80~ 70L.Ju 60z~ 50IIIiii 40L.J0:: 30...JoCt 20~0::L.J 10:I:~016 20 24 28 32 36 40LEAD COUNT-0064-5Figure 7. Thermal Resistance of Cypress SOICsThermal Management0064-411-4

~ Thermal Management~~~~~==============================================================~Packaging MaterialsCYPRESS PLASTIC PACKAGESINCORPORATE:• High thermal conductivity copper lead frame.• Molding compound with high thermal conductivity.• Silver filled conductive epoxy as die attach material.• Gold bond wires.CYPRESS CERDIP PACKAGESINCORPORATE:• High conductivity Alumina substrates.• Silver filled glass as die attach material.• Alloy 42 lead frame.• Aluminum bond wires.III11-5

CYPRESSSEMICONDUCTORPackage Diagramso 005 MIN .• lor--~PIN16 Lead (300 MIL) Cerdip D21 MILM 38510 D·2CONFIG 1I DIMENSIONS IN INCHES0230 MINIJOMAX~ -I ~ ~SEATING PLANE• 0.745 . I 0.140 f.-- 0.2900.785 0.175 I c:: 0.320:;10.155 fEmmr11! ~."" t= ~ ~ :rs-J_~ ~~*'0.125 I I II 0.060 I 0.012 10200 I I -11-- I-0.330_. -- I-- 0.045 0.Q15 0.3900.090 0.065 0.020Q.1Tci18 Lead (300 MIL) Cerdip D4MIL M 385100-6CONFIG. 1DIMENSIONS IN INCHESMIN.MAX.SEATING PLAN EI--~--lI C 0.320 :::J I0.005M~r--20 Lead (300 MIL) Cerdip D6MIL. M 38510 0·8 CONFIG. 1PIN10.310~oaO.245~ ~:~j~-jDIMENSIONS IN INCHESMIN.SEATINGPLANEMAX.0.930 0.140 r;=~~0.970 0.175 0.3200.155~~T.~0.200 liC ,,,~g:.::: iiOiii I-:~-J0.110 M200.125 I 0.009 2:-0.200 I 0.015 0.012 15'1[1- -_ -_ TTTT'T"T"T+r-'122 Lead (400 MIL) Cerdip D8MIL M 38510 0-7 CONFIG. 10.005 MIN. PIN 10.360 DIMENSIONS MIN. IN INCHES15 MAX:0.025 I-- SEATING PLANE1 .050 0.045 0.140 0.390r---_~110 ---j 0.1751C0.420::J10.155rfim::~1! ~''':J;q ~ ~J--MI ~ ~ t:: -L~'.,. 1~~0.200 _I ~ o.ok- -d~ L:O.490-J0.090 0.065 0.0200.11011-6

Package Diagrams~~===~=DIMENSIONS IN INCHESMIN.MAX.600 MIL) Cerdip D1224 Lead ( 0 0-3 CONFIG. 1MIL M 3851PIN 1DIMENSIONS IN INCHESMIN.MAX.SEATING PLANE24 Lea d (300 MIL) Cerdip D14(600 MIL) Cerdip D1628 Lead Dl0CONFIG.lMll-M-38510 -DIMENSIONS IN INCHESMIN.MAX.SEATINGPLANEDIMENSIONS IN INCHESMIN.MAx:0.1550.2000.0900.110II11-7

~ C'lPFESSPackage Diagrams~~~~O~UaDR================================================~====~~~==~~0.005 Ml\-- / PIN 100I 15 JO40 Lead (600 MIL) Cerdip D18MIL M 38510 0-5 CONFIG. 1DIMENSIONS IN INCHESMIN.MAX.0.065 -i l-0.095 SEATING PLANE1-~';~-1I-- ~:~~ -------I 0.140I I 0.175 . ----.1::=tww~~f.t~~ I t~0.630 ---J0.090 0.060 0.D15 0.6900.110 0.020~:~[j ~ u 0.040 j L 0.060 L32 Lead (600 MIL) Cerdip D20(Preliminary)DIMENSIONS IN INCHESMIN.MAX.0.090Q.i1O0.045 0.0150.065 0.020I--0.630 ----l0.6900.005 MIN.11 ,/PIN128 Lead (300 MIL) Cerdip D22DO J~0.310~~ ~ 0'065DIMENSIONS IN INCHES!!!!!!:.SEATINGPLANE0.095L!t,11.430 0.140 02901.485 0.175 r-0:320 --j~~W-tl 0.200 11d II0.125 I I 0.009 o·0.200 I I 111 III 0.015 0.012 Wt ~Co.045 0.080 L j0.065 0.330Q;Ql!Q 0.Q15 o:39ii0.110 0.02011-8

4---1 -2:640~ Package Diagrams_r.~ucrOR =============================48 Lead (600 MIL) Sidebraze DIP D26[~===[::]~~~~~~~:' ~~~g~sSEATINGt 0.020-11+----2.370 o:oso 0.100 PLANEI 2.430 0.200'WllllllillhiNJ~~ , J ~ 0.070 ~0.0120.090 --I I- 0.035 0.015 --II- 0.120 ~ I 0.590' - I0.110 0.065 0.022 0.160 f.--0.620-152 Lead (900 MIL) Bottombraze DIP D281=~~~~=~~~~j:N' ;;~rSEATING'r bJ)PJ0.030 0.098 --I2560 . PLANE• ~::;:i~M0.090 -I I- 0.030 ~ ~ 0.015 -II- 0.120"3" t 1 ~:l g:g:;0.110 0.060 0.020 0.160 0.009 / 0.8800.012 --It 0.92064 Lead (900 MIL) Bottombraze DIP D30[~=~~~=~==~~~~=~~~===];"'0.030 'I;;flr'. 3.160 . PLANEr----_......;.;,;;;..3.240 __ ~0.075 ---l ~ SEATINGI0'15ill~~ ~0.200 ~ ~ t 0 0-I, 150 0.065 -l0.090 --I I- 0.030 0.015 --II- 0.120 -.J 1 0.0850.110 0.060 0.020 0.160 0.009 / _ 0.880-"\0.012--1t 0.920~ID11-9

~ CiPFESSPackage Diagrams~~~~u~==================================================~==========16 Lead Rectangular Fiatpack F69(MIL-M-38510 F'-5 CONF'IG 2)0.045 PIN 1 DIMENSIONS IN INCHES ~~~'.0.055 1_~D~~~0.045 PIN 1""\0.0551 \0.015 T-0.019Lr0.0120.020 1_18 Lead Rectangular Fiatpack F70-~DIMENSIONS IN INCHES ~~~'.~D~~:1~~+lTQ:.0040.007 0.250 0.040g:~~g r- ~:~~~ ]0.030 -l.J:-~L 0.050 q"'+---~;a.o -----1--g-:~.L~gLI.----.~1~0.2=0=0==0=.0=2~6~J~~t0.0450.0550.Q150.019Lr0.Q120.04520 Lead Rectangular Fiatpack F71PIN 1MIN.DIMENSIONS IN INCHES MAX.l_ t\:-.-T-1_'l g:~~g0.050-l~I g:~~~ J~0.4800.520&JL 0.070 qr~;;;;;;';;;;;;;;;;';;;;;;;;;;';;;;;;;;1~"'" -----1--g-:g.L:~l~-0-.2-24-.J.fl-~=0.;;01~0~J~~tTQ:.0040.007 0.236 0.03024 Lead Rectangular Flatpack F73(MIL-M-38510 F'-6 CONF'IG 2)0.045 PIN 1 DIMENSIONS IN INCHES ~0.055 1_0.0120. 1_ 045flL~:~~~~ ~:~~~ J0.050 I-IJ0.070 q _____ ...L..4 0.060~~~~n+~====~-1~~0.~090TQ:.003 ~ 0.270 .J 0.010 ] t0.006 0.290 0.03011-10

~ CYPRESSPackage Diagrams~~~IOO~Ucr~==================================================================42 Lead Rectangular Flatpack F760.045 PIN 10.0551 ~@)tTO0,0180.022 1.0701 MAXT0.0120.045TYP. ~ 0.100BonOM1~LR0.100MAX. J~.~00~7==1'~'~'~~1~~~~~1~~0.010 I--g::;g---l-g:;~;-1 f LO.0400.06068 Pin Grid Array Package G680.9881:012r-~:~~~I10000000$$000000000D 00 001.012~~11 III ~~ o.~,~~ ~~ ~:~~~00 00~00 00$000000000$0000'00$DIMENSIONS IN INCHESTOPPIN#1 I·1.088_1J1.11211.088f:fi2SIDEm11-11

~ Package Diagrams~~~NDUcrOR=====================================================================20 Lead Plastic Leadless Chip Carrier J61DIMENSIONS IN INCHESMIN.MAX.28 Lead Plastic Leadless Chip Carrier J64OIMENSIONS IN INCHESMIN.MAX.PIN 10.350 ~0.3560.3850.39532 Lead Plastic Leadless Chip Carrier J65']'25 TYP.~J;11 32 31 300.4900.530in O."'TYP.44 Lead Plastic Leadless Chip Carrier J67DIMENSIONS IN INCHESMIN.MAX.-11- 0.Q13 I [t t, 0.021 0.390 ---l 0.015MIN.10.43011-12

mPackage Diagrams52 Lead Plastic Leadless Chip Carrier J69DIMENSIONS IN INCHES~MAX.PIN 10.7850.7950.7500.756[G-0.7500.7560.7850.795.168 Lead Plastic Leadless Chip Carrier J81DIMENSIONS IN INCHES!A.!!!:.MAX.PIN 10.9850.995------ ~:::~0.95811-13

~ Package Diagrams~~~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~PIN 1 1.0.16 Lead Rectangular Cerpack K69(MIL-M-38510 F-5 CONFIG 1)PI1 1.0.18 Lead Rectangular Cerpack K70(MIL-M-38510 F-10 CONFIG 1)--1-0.0450.0550.0450.055TOP VIEWTOP VIEWg:g~; ,tI--O.246-j0.280I0.2500.3500.045 MAX.r0.004£0.0090.026 0.040 SEAnNO PLANE0.045 IO'T]I0.085 MAX.0.004£0.009::2=0.250 I--0.250------l0.250 I-L 0.026 SEATING0.350 0.300 0.350 0.040 PLANE20 Lead Rectangular Cerpack K7124 Lead Rectangular Cerpack K73(MIL-M-38510 F-8 CON FIG 1).~==J:======L __ £0.0040.009I :=2:i=0.=25=0:t:1 ===0.=25=0==:::l1r::0.=25=0~1-L 0.026 SEATING0.350 0.300 0.350 0.040 PLANE.tso==s======L-...... £g:;tj' : :2::0.0040.009Ti=0'=26=0+1 ===0.=36=0==:::f1 =0=.2=60~1 L 0.026 SEATING0.325 0.400 0.325 I- 0.040 PLANE11-14

~ Package Diagrams~~~NDUcrOR ==================================================================~===PIN 1 1.0.28 Lead Rectangular Cerpack K74(MIL-M-38510 F-ll CONFIG 1)18 Pin Rectangular Leadless Chip Carrier LSO(MIL-M-38510 C-l0A)0.008R18 PLCSDIMENSIONS IN INCHESMIN.MAX.TOPn0.4170.433t=~Jl0.300- 0.075I 0.060SIDEI _ 0.050~ 0.06820 Pin Rectangular Leadless Chip Carrier LSI(MIL-M-38510 C-13)22 Pin Rectangular Leadless Chip Carrier LS2BOTTOMI 0.045~0.055--.16PLCSI--t----

~ Package Diagrams~~~NDUcrOR =====================================================================24 Pin Rectangular Leadless Chip Carrier L5328 Pin Rectangular Leadless Chip Carrier L54(MIL-M-38510 C-11A)DIMENSIONS IN INCHES0.0200.030MIN.MAX.0.0450.055 ....--!!F't-----E3E-Ci..DIMENSIONS IN INCHESMIN.MAX.TOP0.008 Rn24 PLACES0.3920.408I- 0.062I 0.078SIDETOP--.l 0.022t 0.028I- 0.060I 0.075SIDE~_Q.ill~U0.3080.0500.066I 0.0541- 0 •06332 Pin Rectangular Leadless Chip Carrier L55(MIL-M-38510 C-12)DIMENSIONS IN INCHESMIN.MAX.20 Pin Square Leadless Chip Carrier L610.045 +0.055 -.---:EJ--(MIL-M-38510 C-2A)~*1 0.045.I""II"L.r"II.Ir"'LIIr""'UI~,r [0.055DIMENSIONS IN INCHESMIN.MAX.-.l 0.022t 0.028-1 0•022to.028I- 0.060I 0.075I-~I 0.090TOPSIDETO~SIDE0.5400.560~J0.458I-- 0.0500.080I 0.0541- 0 .06611-16

~ CYPRESSPackage Diagrams~~I~cr~================================================================28 Pin Square Leadless Chip Carrier L64(MIL-M-38510 C-4)0.0450.055 ..---F'I---DIMENSIONS IN INCHESMIN.MAX.- nTOPD:~ g:1~~I- 0.064I 0.078SIDE~~~u0.458-ILO.0451- 0.06644 Pin Square Leadless Chip Carrier L67(MIL-M-38510 C-5)DIMENSIONS IN INCHESMIN.MAX.0.0450.055 ....--E'I-----TOP~L-- I • .....:"' __,,_.....:"'...:-----l~ .... -*-.0.6400.880n0.640D.6&O:lJ-ISIDEI..- 0.054O.OBBII]11-17

~ Package Diagrams~~~U~================================================================48 Pin Square Leadless Chip Carrier L68I1 0.066-l0.066~ . I 0.078 0.05452 Pin Square Leadless Chip Carrier L69IPIN NO.1INDEX""',;;:I---------.----------IiI---------------------II10.086 ~0.1000.072_10.088 I~ 0.0075R, , ,REf.~ (48 PLCS.)~0.040:1: .003 0.020:1: .003 -J 1'- I "-- 0.0075 R REf.0.440:1: .005 (3 CORNERS)0.560 SQ.:I: .005l11-18

~ Package Diagrams~~~~UaoR==================================================================68 Pin Square Leadless Chip Carrier L81(MIL-M-38510 C-7)DIMENSIONS IN INCHESMIN.MAX.0.045~.-~~------------TOP1-------------- 0.938 _____________ +0.96216 Lead (300 MIL) Molded DIP PI 18 Lead (300 MIL) Molded DIP P30.015 SEATING PLANE0.035'''' =:j"~ r;:;.,~ ~.1,...____07_7_' ~fm'·'"0.009 15-0.015 0012II 0.060 I 0.310 . I--11-- I--- 0.385 ---I0.0150.020C--:d4PIN102~00270-- ~~ '~ SEATING PLANE~ rp:~~j~:~!~.,~ tVVV""mi\m~:::!: J~~~--l I-- 0.055 0.0150.090 0.065 0.0200.110DIMENSIONS IN INCHESMIN.MAX.r-- 0.280~I c:: 0.325 1~~+~ ~~I 0.310 ._--1f--- 0.385II11-19

~ Package Diagrams~~~~UcrOR=====================================================================20 Lead (300 MIL) Molded DIP P522 Lead (400 MIL) Molded DIP P7C --PIN 1__ .1 MAxDIMENSIONS IN INCHESMIN.o·15·0125 I I II 0.060 I 0.410 I0.200 I I --11-- I--- 0.485 -----+j--l I-- 0.055 0.0150.090 0.065 0.0200.11022 Lead (300 MIL) Molded DIP P924 Lead (600 MIL) Molded DIP PHI :::::::::A~0.065~ t-0.0900.110DIMENSIONS IN INCHESMIN.MAX.o150t===-'--- 0.1400.060 -IPIN 11230 M80 _ r,=o.0.155 ;wl~:ITTr1 j DE L5DIMENSIONS IN INCHES0.625570=J}0.200 !! lmfir ~~ 1\0.125 J . 0.055jt 0.015 I I0.200 0.065 0.015 0.060 I----~--.J0.090 0.020 0.6850.110o·15011-20

~ Package Diagrams~~~~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=24 Lead (300 MIL) Molded DIP PI3/PI3A/PINI00 ----' DIMENSIONSIMIN.0.250 MAX.0.270----*-IN INCHESNOTEB-.j fijSEATINGPLANE0.280~mr. 0.160 ~~ NOTU ~: 0.325O'l90lJd~m-1J0.125 0009 ~T O.055Cj~ 0.060 I I0065 f--0. 310 --l0200 ~ [0.015 0:012 15"0.090 . 0.015 0.3850.110 0.0201.170NOTE A: P13 = 1.200Pl3A = ~:::28 Lead (600 MIL) Molded DIP PIS0.0900.110PIN IDIMENSIONS IN INCHESMIN.MAx:NOTE B: P13 = ::::P13A= :::40 Lead (600 MIL) Molded DIP P1728 Lead (300 MIL) Molded DIP P21I DIMENSIONS IN INCHES~ MIN.0.250 MAX.0.270~DO/PIN0.030 ----I ijl SEATING PLANE0.080 I-- 0.280I' 1.370 "\ 0.120 rrQ.325 ~~:Lwr'w~,,~~~,Y ~ f--JL,.,:'" L:~-J0.110 0.055 0.0200.065II11-21

48 Lead (600 MIL) Molded DIP P25PIN#lDIMENSIONS IN INCHESMIN.t.lAX.0.065 i0.085 -II' 2.420 'I 0.150o,f.;J0.210.:LJ!2.440 o:i7O10.1250.200 0,015f ....0.090 0.045 0,0150.110 0.055 0.020SEATING PLANE0.625 0'570~~= I1-___ 0.600 ---+\'0.70064 Lead (900 MIL) Molded DIP P29PIN#lDIMENSIONS IN INCHESoMIN.t.lAX.SEATING PLANEI , 3.1~3.240o.~~"--------r---+0.225--0.-00-9---------J~~ 1~0.012 I\\-I-'-0.1200.160-t-~ ~0.0900.1100.0550.0650,0150.020" g~~'~~,~-I-~~~\-I 1.010 I• 1.062 '11-22

~ Package Diagrams~~~~UcrOR=======================================================================32 Pin Windowed Rectangular Leadless Chip Carrier QSS 20 Pin Windowed Square Leadless Chip Carrier Q610.0450.055 -r--E3--- ---E3io-

~ CYPRESSPackage Diagrams_F~f1CONDUCTOR ==================================16 Lead Molded SOIC SIPIN 1DIMENSIONS IN INCHESMIN.MAX.'L' 0.397 "I0.413I~o.ot0.105~~I I II 0.003 t-l I- - - 0.0120.0470.0530.0130.019LEAD COPLANIARITY 0.004 MAX.SEATING PLANE0.3930.4200.015 J0.05045° CHAMF'PIN#1 1.0.. r ~::';18 Lead Molded SOIC S3PIN 1'LDIMENSIONS IN INCHESMIN.MAX.LEAD COPLANIARITY 0.004 MAX.SEATING PLANE0.463I 0.447 "'~0.l20.105Uj L -IL g:g~~0.0470.0530.0130.019:10.0070.015 Q.0130.0500.3930.42011-24

~ CYPRESSPackage DiagramsWnICONDucroR ============================================================20 Lead Molded SOIC S5PIN 1DIMENSIONS IN INCHESMIN.MAX.I' 0.4971I0.513~"t,0.105~~tI I IL 0.003-1 I- - 0.0120.0470.0130.0530.019LEAD COPLANIARITY 0.004 MAX.SEATING PLANE0.3930.420:j0.05045° CHAM.PIN#1 1.0.===t 0.0070.015 __ Q.Oi324 Lead Molded SOIC S13DIMENSIONS IN INCHESMIN.MAX.LEAD COPLANIARITY 0.004 MAX.I 0.597 I0.615~'.'t, 0.105~~j L_11_ ~:i~~0.047 0.0130.053 o:oi9SEATING PLANE0.3930.420II00" J .11::,;0.05011-25

~ CfPRISSPackage Diagrams~~~oo~u~============================================~==========~~==28 Lead Molded SOIC S21PIN 1DIMENSIONS IN INCHESMIN.MAX.'LI' 0.697 0.713'I~"~2 0.105tU!I I IL 0.003-l I- - 0.0120.0470.0130.0530.019LEAD COPLANIARITY 0.004 MAX.SEATING PLANE:j 10 • 0070.015 _ 0.0130.0500.3930.42024 Lead Windowed Cerpack T73(Preliminary)~~0.004£ 0.0080.080 ==:::J:======t--o.~; :=2=T -l 0.260 I 0.360 I 0.260 lL 0.026 SEATING0.325 I---0.400 ---..I 0.325 0.040 PLANE11-26

I28 Lead Windowed Cerpack T74(Preliminary)0740 --------1MAX.CJ1- 0 . 295 _0.015 __ _ 0.3050.022" " " [I/V-- PIN0.005 r0.015-t0.245+------f----l-°·Y5III ILo.0501 I.D._11- 0 . 003I 0.009J~-r0.250I'0.3400.380J~0.026SEATING PLANE0.0400.0700.10020 Lead Molded SOJ VS0.0400.0500.3300.350!-~-g:g~~t~~I'IT'\ U 0.120I 0.140'0.4.7 U U~50.513---' L~8III11-27

~ CYPRESSPackage Diagrams~~~~~================================================~~~~~~~24 Lead Molded SOJ V130.0400.0500.2910.3000.3300.350!0.031 R0.042 •0.0470.05328 Lead Molded SOJ V210.0400.0500.2910.300~~l 0.3300.350!0.011 X 450 -I I0.016 1-"....---........../ ,I(I\\" '-0.2620.27211-28

~ Package Diagrams~~IOO~UcrOR==================================================~========~====20 Lead Windowed Cerdip W6PIN 1155t3r ____0.0.2000.015 -l0.0351'41_----- 0 . 930 -----0.-11 0.1400.970 ----ijt0.140 0.2450.310!DIMENSIONS IN INCHESMIN.MAX.II ·SEATIoNG'29POU~:::::I Io.175 ~0'3200.1 25 1---.---"'- ~ 00.200 0.015 _0.009 15°0.060 0.012I-l f.-0.0900.1100.0500.0650.0150.020I-- 0.330 ---10.39024 Lead (600 MIL) Windowed Cerdip W12DIMENSIONS IN INCHES0.2530.2750.065 __ I I0.085 l.-1.285 0.175I' 1.230 'I 0.140::~!:f5r--WJ[~5~:~;~ d0.010.020 ~1 L ~:~;;oMIN.MAX.SEATING PLANEr- 0 . 590 -j1 r::: 0.620 ::11lo.!o.' . ~,~,0.012 ~I--0.630 --10.690II11-29

~ CY'MSSPackage DiagramsW~IcONDUcrOR ==========================================24 Lead Windowed Cerdip W14r- g::!~ -10.005 MIN'-j ~ I0.1250.155~~~~~~~~I----~DIMENSIONS IN INCHESMIN.MAX.SEATING PLANEr- 0.290--j0.0900.1100.0450.0650.0150.0201 c: 0.320 ::tloLl1.~,~oI-- 0.330 --l0.3900.012 ~28 Lead (600 MIL) Windowed Cerdip W16DIMENSIONS IN INCHESMIN.MAX.::~:: ~ ~1.'90 ~J0200 LU11--< ____ 1.450 'I 0."0 rcUg:~~g~ -.1 ~ /- SEATING PLANE[=r 0.620IUI- 0.015O.D1d ~ g:;;;O0.0200.590;lo15°11-30

32 Lead (600 MIL) Windowed Cerdip W20(Preliminary)DIMENSIONS IN INCHESMIN.MAX.SEATING PLANE0.0450.0650.0150.020I 0.630 I1- 0 . 690 •GLASS LENSPIN 10.1250.155I0.2450.310~~~ '-T-r-.....i--I-!DIMENSIONS IN INCHESMIN.MAX.~ it/SEATING PLAN,g:~~~~I. m~::~~-~'11~ F~;l0.125L II t0.200 ~ ~ ~ L ~ I.- g:g!~0.090 0.045 0.0150.110 0.065 0.020m11-31

~RESSPackage DiagramsWnEMlCONDucrOf< ;;"-'=';==================================================Typical Marking for DIP Packages (P and D Type)PLACE OF MFG."USA"DATE CODE: SHIP CODE: ASSEMBLY CODE:----------------------XXYY IDENTIFIES SPECIFIC SHIPMENT IDENTIFIES THE SPECIFIC ASSEMBLYXX = YEAR LOTS TO CUSTOMERS. LOT THE PRODUCT CAME FROM.YY = WORK WEEKWEEK PARTS WERE MARKED (FOR PLASTIC)WEEK PARTS WERE SEALED (FOR HERMETIC)0047-111-32

~ Sales Representatives and Distribution~~~OIDucrOR==================================================================Direct Sales OfficesCaliforniaCypress SemiconductorCorporate Headquarters3901 N. First StreetSan Jose, CA 95134(408) 943-2600Telex: 821032 CYPRESS SNJ UDTWX: 910 997 0753FAX: 408-943-2741Cypress Semiconductor23586 Calabasas Rd., Ste. 201Calabasas, CA 91302(818) 884-7800FAX: (818) 348-6307Cypress Semiconductor2151 Michelson Dr., Ste. 284Irvine, CA 92715(714) 476-8211FAX: (714) 476-8317Cypress Semiconductor16496 Bernardo Center, Ste. 215San Diego, CA 92128(619) 487-9446ColoradoCypress Semiconductor4851 Independence St., Ste. 189Wheat Ridge, CO 80033(303) 424-9000FAX: (303) 424-0627FloridaCypress Semiconductor10014 N. Dale Mabry Hwy., 101Tampa, FL 33618(813) 968-1504FAX: (813) 468-8474IllinoisCypress Semiconductor1530 E. Dundee Rd., Ste. 190Palatine, IL 60067(312) 934-3144FAX: (312) 934-7364MarylandCypress Semiconductor9891 Brokenland Parkway, Ste. 300Columbia, MD 21045(301) 290-5921FAX: (301) 290-5285MassachusettsCypress Semiconductor2 Dedham Place, Ste. 1Dedham, MA 02026(617) 461-1778MinnesotaCypress Semiconductor14525 Hwy. 7, Ste. 115Minnetonka, MN 55345(612) 935-7747FAX: (612) 935-6982OregonCypress Semiconductor6950 S.W. Hampton St., Ste. 217Portland, OR 97223(503) 684-1112FAX: (503) 684-1113PennsylvaniaCypress Semiconductor2 Neshaminy Interplex, Ste. 203Trevose, P A 19047(215) 639-6663FAX: (215) 639-9024TexasCypress Semiconductor333 West Campbell Rd., Ste. 220Richardson, TX 75080(214) 437-0496FAX: (214) 644-4839Cypress Semiconductor International51 Rue du Moulin a Papier, Bte 111160 Brussels, BelgiumTel: (32) 02 672 2220Telex: 64677 CYPINT BFAX: (32) 02 660 0366FranceCypress Semiconductor FranceBureaux de Sevres72-78 Grande Rue92310 SevresTel: (33) 1 453 410 10Telex: 631606FAX: (33) 1 453 401 09GermanyCypres~ Sl:miconductor GmtH.Hohenlinder Str. 6D-8016 h:ldkin:henTel: (49) 089 903 10 71FAX: (49) 089 903 8427United KingdomCypress Semiconductor U.K.Business & Technology CentreBessemer Drive, StevenageHertfordshire, SG 1 2DXTel: (44) 0438 310 118Telex: 94013897 CYPR GFAX: (44) 438 740141

~ Sales Representatives and Distribution~~~~UcrOR==================================================================North American Sales RepresentativesAlabamaCSR Electronics303 Williams Ave., Ste. 931Huntsville, AL 35801(205) 533-2444TWX: 510-600-2831FAX: 205-536-4031ArizonaLuscombe Engineering7533 E. First StreetScottsdale, AZ 85251(602) 949-9333FAX: (602) 949-9095CaliforniaCypress SemiconductorCorporate Headquarters3901 N. First StreetSan Jose, CA 95134(408) 943-2600Telex: 821032 CYPRESS SNJ UDTWX: 910 997 0753FAX: 408-943-2741Cypress Semiconductor23586 Calabasas Rd., Ste. 201Calabasas, CA 91302(818) 884-7800FAX: (818) 348-6307Cypress Semiconductor2151 Michelson Dr.; Ste. 284Irvine, CA 92715(714) 476-8211FAX: (714) 476-8317Cypress Semiconductor16496 Bernardo Center, Ste. 215San Diego, CA 92128(619) 487-9446Taarcom451 N. Bailey AvenueMountain View, CA 94043(415) 960-1550CanadaE.S.P.447 McLeod St. Unit 3Ottawa, Ontario K1R 5P5(613) 236-1221FAX: (613) 236-7119E.S.P.5200 Dixie Road, Ste. 201Mississauga, Ontario L4W 1E4(416) 626-8221FAX: (416) 238-3277E.S.P.116 McKee St.Chateauguay, Quebec J6J 3N2(514) 592-1323FAX: (514) 691-2726ColoradoCypress Semiconductor4851 Independence St., Ste. 189Wheat Ridge, CO 80033(303) 424-9000FAX: (303) 424-0627ConnecticutHLM3 Pembroke RoadDanbury, CT 06810(203) 791-1878FAX: (203) 791-1876Delaware*L. D. Lowery2801 West Chester PikeBroomall, P A 19008(215) 356-5300FAX: (215) 356-8710FloridaCM Marketing14350 Gulf to Bay Blvd.Clearwater, FL 34615(813) 443-6390CM Marketing6091-A Buckeye Ct.Tamarac, FL 33319(305) 722-9369CM MarketingPO Box 560776Orlando, FL 32856(305) 898-3596Cypress Semiconductor10014 N. Dale Mabry Hwy., 101Tampa, FL 33618(813) 968-1504FAX (813) 468-8474GeorgiaCSR Electronics1651 Mt. Vernon Rd., Ste. 200Atlanta, GA 30338(404) 396-3720TWX: 510 600 2162FAX: 404-394-8387IllinoisCypress Semiconductor1530 E. Dundee Rd., Ste. 190Palatine, IL 60067(312) 934-3144FAX: (312) 934-7364Micro Sales Inc.54 West Seegers RoadArlington Hts., IL 60005(312) 956-1000Telex: 510 6000756FAX: (312) 956-0189IndianaTechnology Mktg. Corp.599 Industrial Dr.Carmel, IN 46032(317) 844-8462FAX: (317) 573-5472Technology Mktg. Corp.3428 W. TaylorFt. Wayne, IN 46802(219) 432-5553FAX: (219) 432-5555IowaMidwest Tech. Sales2510 White Eagle Trail S.E.Cedar Rapids, IA 52403(319) 365-4011FAX: (319) 362-9832KansasMidwest Tech. Sales21901 LavistaGoddard, KS 67052(316) 794-8565Midwest Tech. Sales15301 W. 87 Parkway, Ste. 200Lenexa, KS 66219(913) 888-5100FAX: (913) 888-1103KentuckyTechnology Mktg Corp.4012 Dupont CircleLouisville, KY 40207(502) 893-1377MarylandCypress Semiconductor9891 Brokenland Parkway, Ste. 300Columbia, MD 21045(301) 290-5921FAX: (301) 290-5285MassachusettsCypress Semiconductor2 Dedham Place, Ste. 1Dedham, MA 02026(617) 461-1778MichiganTechrep2950 Packard RoadYpsilanti, MI 48197(313) 572-1950FAX: (313) 572-0263MinnesotaCypress Semiconductor14525 Hwy. 7, Ste. 115Minnetonka, MN 55345(612) 935-7747FAX: (612) 935-6982*This office is a duplicate of the listing that appears under its state of residence.

~ Sales Representatives and Distribution~~~~UcrOR==================================================================North American Sales Representatives (Continued)MissouriMidwest Tech. Sales1314 RobertridgeSt. Charles, MO 63303(314) 441-1012FAX: (314) 447-3657New JerseyHLM1300 Route 46Parsippany, NJ 07054(201) 263-1535*L. D. Lowery Inc.2801 West Chester PikeBroomall, P A 19008(215) 356-5300FAX: (215) 356-8710New MexicoQuatra Associates9704 Admiral Dewey N.E.Albuquerque, NM 87111(505) 821-1455New YorkHLM64 Mariners LaneNorthport, NY 11768(516) 757-1606Reagan/Compar3449 St. Paul Blvd.Rochester, NY 14617(716) 338-3198Reagan/Compar41 Woodberry RoadNew Hartford, NY 13413(315) 732-3775Reagan/Compar42 Winding Brook DriveFairport, NY 14450(716) 271-2230Reagan/Compar3215 East Main St.P.O. Box 135Endwell, NY 13760(607) 754-2171(607) 754-8946North CarolinaTingen Tech. Sales2809 Millbrook Rd., Ste. 203Raleigh, NC 27604(919) 878-4440TWX: 510 928 0540FAX: 919 878 8681OhioLyons4812 Frederick Rd., Ste. 101Dayton, OH 45414(513) 278-0714FAX: (513) 278-3609Lyons4615 W. Streetsboro RoadRichfield, OH 44286(216) 659-9224FAX: (216) 659-6214Lyons248 N. State St.Westerville, OH 43081(614) 895-1447OregonCypress Semiconductor6950 S.W. Hampton St., Ste. 217Portland, OR 97223(503) 684-1112FAX: (503) 684-1113Pennsylvania* L. D. Lowery Inc.2801 West Chester PikeBroomall, P A 19008(215) 356-5300FAX: (215) 356-8710Cypress Semiconductor2 N eshaminy Interplex, Ste. 203Trevose, P A 19047(215) 639-6663Puerto RicoETS Inc.P.O. Box 10758Caparra Heights StationSan Juan, P.R. 00922(809) 720-1300FAX: (809) 720-1178TennesseeCSR Electronics2728 Davenport Rd., Ste. 1Knoxville, TN 37902(615) 577-1317TWX: 510 600 2162FAX: 615-577-1306TexasCypress Semiconductor333 W. Campbell Rd #220Richardson, TX 75080(214) 437-0496TexasSouthern States Marketing1143 Rockingham, Ste. 106Richardson, TX 75080(214) 238-7500FAX: (214) 231-7662TWX: 910 8674754Southern States Marketing400 E. Anderson Lane, Ste. 111Austin, TX 78752(512) 835-5822FAX: (512) 835-1404TWX: 910 8742006Southern States Marketing5644 Westheimer Ste. 308Houston, TX 77056(713) 960-9556FAX: (713) 960-9706UtahSierra Technical Sales4700 South 900 East 3-150Salt Lake City, UT 84117(801) 566-9719Virginia*L. D. Lowery Inc.2801 West Chester PikeBroomall, PA 19008(215) 356-5300FAX: (215) 356-8710WashingtonElectronic Sources300 120 St. N.E.Bldg. 1, Ste. 100Bellevue, W A 98005(206) 451-3500Washington, D.C.*L. D. Lowery Inc.2801 West Chester PikeBroomall, P A 19008(215) 356-5300FAX: (215) 356-8710WisconsinMicro Sales Inc.N. 81 W. 12920 Leon Rd., Ste. 115Menomonee Falls, WI 53051(414) 251-0151FAX: (414) 251-4720*This office is a duplicate of the listing that appears under its state of residence.

~ CfPFJSSSales Representatives and Distribution~~~IOO~UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~International Sales RepresentativesCypress Semiconductor International51 Rue du Moulin a Papier, Bte 111160 Brussels, BelgiumTel: (32) 2 672 2220Telex: 64677 CYPINT BFAX: (32) 2 660 0366AustriaHitronik Vertriebs GmBHSt. Veitgasse 51A-I130 Wien, AustriaTel: (43) 222 824199Telex: 133404 HIT AFAX: (43) 222 826 440BelgiumMicrotronicaKeiberg/Brussels AirportExcelsiorlaan 53/B21930 Zaventem-BelgiumTel: (32) 02 720 6010Telex: 64709 MICRO BFAX: (32) 02 720 8490DenmarkA/S N ordisk ElectronikTransformervej 17DK-2730 HerlevTel: (45) 2 842000Telex: 35200 NORDEL DKFAX: (45) 2 921552FinlandOY Fintronic ABMelkonkatu 24 ASF-0021O HelsinkiTel: (358) 0-6926022Telex: 124224 FTRON SFFAX: (358) 0-674886FranceCypress Semiconductor FranceBureaux de Sevres72 78 Grande Rue92310 SevresTel. (33) 1 453 410 10Telex: 631606FAX: (33) 1 453 401 09Newtek8 Rue de L'Esterel, Silic 58394663 Rungis CedexTel: (33) 1 4687 6025Telex: 263046 COSERMFAX: (33) 1 4687 8049GermanyCypress Semiconductor GmbHHohenlindner Str. 6D-8016 FeldkirchenTel. (49) 089 903 10 71FAX: (49) 089 903 84 27GermanyAPI Electronik GmbH15, AhornstrasseD-8062 Markt, IndersdorfTel: (49) 8136 7092Telex: 527 0505FAX: (49) 81367398Astek GmbHGottlieb-Daimler-Str. 7D-2358 KaltenkirchenTel: (49) 4191 8711Telex: 2180120 ASK DFAX: (49) 4191 8249Metronik GmbHLeonhardsweg 2, Postfach 1328D-8025 Unterhaching b. MunichTel: (49) 89-611080Telex: 17 897434 METRO DFAX: (49) 89 611 6468Metronik GmbHLaufamholzstrasse 118D-8500 NiirnbergTel: (49) 9 11 59 00 61Telex: 6 26 205Metronik GmbHLowenstrasse 37D-7000 Stuttgart 70Tel: (49) 7 11 76 40 33Telex: 7 255 228Metronik GmbHSiemensstrasse 4-6D-6805 HeddesheimTel: (49) 6203 47 01Telex: 4 65 035Metronik GmbHSemerteichstrasse 92D-4600 Dortmund 30Tel: (49) 2 31 423037Telex: 8 227 082FAX: (49) 0231-41 8232Metronik GmbHOsterbrooksweg 61D-2oo0 SchenefeldTel: (49) 40 8 30 40 61Telex: 2 162488Hong KongTekcomp Electronics1603 Bank Centre636 Nathan RoadKowloon, Hong KongTel: (852) 3 710 9220Telex: 38513 TEKHLFAX: (852) 3 710 9220IsraelTalviton ElectronicsPO Box 21104, 9 Biltmore StreetTel Aviv 61 210Tel: (972) 3 444572Telex: 33400 VITKOFAX: (972) 3 455626ItalyCramer Italia s.p.a.134, Via C. Colombo00147 RomaTel: (39) 6 517 981Telex: 611517 CramerFAX: (39) 6 5140722Dott.lng. Giuseppe De Mico s.p.a.V. Le Vittorio Veneto, 81-20060 Cassina d'PecchiMilanoTel: (39) 2 95 20 551Telex: 330869 DEMICO IFAX: (39) 2 952 2227JapanTomen Electronics2-1-1 Uchisaiwai-Cho, Chiyoda-KuTokyo 100Tel: (81) 3 5063670Telex: 23548 TMELCAFAX: (81) 3 506 3497NorwayNordisk Elektronik (Norge) A/SSmedsvingen 4, PO Box 123N-1364 HvalstadTel: (47) 2 846210Telex: 77546 NENAS NFAX: (47) 2 846 545SingaporeDesner Electronics PTE Ltd.190 Middle Rd # 16-07Fortune Center, SingaporeTel: (65) 337 3188FAX: (65) 337 3180SpainComelta S.A.Emilio Munoz, 41 Nave 1-1-2E-Madrid 17Tel: (34) 1 754 3001Telex: 42007 CET A EFAX: (34) 1 7542151SwedenNordisk Electronik ABHuvudstagatan 1, PO Box 1409S-171 27 SolnaTel: 8 635 040Telex: 10547 Nortron SFAX: (46) 8 272 204

~ Sales Representatives and Distribution~~~UcrOR==================================================================International Sales Representatives (Continued)SwitzerlandBaerlocher AGForrlibuckstrasse 150CH-8oo5 ZurichTel: (41) 1 429 900Telex: 822762 BAEZ CHFAX: (41) 1 445023Taiwan R.O.C.Prospect Technology Corp.5, Lane 55, Long-Chiang RoadTaipeiTel: (886) 2 721 9533Telex: 14391 PROSTECHFAX: (886) 2 773 3756The NetherlandsSemicon B.Y.P.O. Box 408,5600 AK EindhovenOffice: Gulberg 33 5674 TE NuenenNL-5672 AD NuenenTel: (31) 040 837 075Telex: 59418 INTRA NLFAX: (31) 040 838 635United KingdomCypress Semiconductor U.K.Business & Technology CentreBessemer Drive, StevenageHertfordshire, SG 1 2DXTel: (44) 0438 310 118Telex: 94013897 CYPR GFAX: (44) 0438 740141United KingdomPronto Electronic System LTD.City Gate House399-425 Eastern AvenueGants Hill lIford, Essex IG2 6LRTel: (44) 01 5546222Telex: 8954213 PRONTO GFAX: (44) 01 518 3222Ambar Cascom Ltd.Rabans CloseAylesbury Bucks HP19 3R5Tel: (44) 0296 434 141Telex: 837427FAX: (44) 0296 296 70

~ Sales Representatives and Distribution~~~~u~================================================================DistributionMarshall Industries:AlabamaHuntsville, AL 35801(205) 881-9235ArizonaPhoenix, AZ 85044(602) 496-0290CaliforniaMarshall Industries,Corp. HeadquartersEI Monte, CA 91731-3004(818) 459-5500Irvine, CA 92718(714) 458-5301Chatsworth, CA 91311(818) 407-4100Rancho Cordova, CA 95670(916) 635-9700San Diego, CA 92131(619) 578-9600Milpitas, CA 95035(408) 943-4600ColoradoThornton, CO 80241(303) 451-8383ConnecticutWallingford, CT 06492-0200(203) 265-3822FloridaFt. Lauderdale, FL 33309(305) 977-4880Altamonte, FL 32701(305) 767-8585St. Petersburg, FL 33716(813) 576-1399GeorgiaNorcross, GA 30093(404) 923-5750IllinoisSchaumburg, IL 60173(312) 490-0155IndianaIndianapolis, IN 46278(317) 297-0483KansasLenexa, KS 66214(913) 492-3121MarylandGaithersburg, MD 20877(301) 840-9450MassachusettsWilmington, MA 01887(617) 658-0810MichiganLivonia, MI 48150(313) 525-5850MinnesotaPlymouth, MN 55441(612) 559-2211MissouriBridgeton, MO 63044(314) 291-4650New JerseyFairfield, NJ 07006(201) 882-0320Mt. Laurel, NJ 08054(609) 234-9100New YorkJohnson City, NY 13790(607) 798-1611Hauppauge, LI, NY 11788(516) 273-2424Rochester, NY 14624(716) 235-7620North CarolinaRaleigh, NC 27604(919) 878-9882OhioSolon, OH 44139(216) 248-1788Dayton, OH 45414(513) 898-4480OregonBeaverton, OR 97005(503) 644-5050PennsylvaniaMt. Laurel, NJ 08054(609) 234-9100Pittsburgh, PA 15238(412) 963-0441TexasAustin, TX 78754(512) 837-1991Carrollton, TX 75006(214) 233-5200Houston, TX 77040(713) 895-9200UtahSalt Lake City, UT 84115(801) 485-1551WashingtonBellevue, W A 98007(206) 747-9100WisconsinWaukesha, WI 53186(414) 797-8400

~ Sales Representatives and Distribution~~~~UcrOR================================================================Distribution (Continued)Semad:CanadaTorontoMarkham, Ontario L3R 4Z4(416) 475-3922FAX: 416-475-4158MontrealPointe Claire, Quebec H9R 427(514) 694-08601-800-363-6610FAX: 514-694-0965OttawaOttawa, Ontario K2C OR3(613) 727-8325FAX: (613) 727-9489VancouverBurnaby, B.C. V3N 4S9(604) 420-98891-800-663-8956FAX: (604) 420-0124CalgaryCalgary, Alberta T2H 2S8(403) 252-5664FAX: 403-255-0966Cypress Electronics:Santa Clara, CA 95050(408) 980-2500Falcon Electronics:Hauppauge, LI, NY 11788 'C.(516) 724-0980Framingham, MA 01701(617) 626-2128Milford, CT 06460(203) 878-5272Anthem Electronics, Inc.:Tempe, AZ 85281(602) 966-6600Chatsworth, CA 91311(818) 700-1000East Irvine, CA 92718(714) 768-4444Sacramento, CA 95834(916) 922-6800San Jose, CA 95131(408) 295-4200San Diego, CA 92121(619) 453-9005Englewood, CO 80112(303) 790-4500Elk Grove Village, IL 60007(312) 640-6066Lake Oswego, OR 97034(503) 603-1114Salt Lake City, UT 84119(801) 973-8555Redmond, W A 98052(206) 881-0850Zeus Components, Inc.:Yorba Linda, CA 92686(714) 921-9000San Jose, CA 95131(408) 998-5121Oviedo, FL 32765(305) 365-3000Lexington, MA 02173(617) 863-8800Columbia, MD 21045(301) 997-1118Port Chester, NY 10573(914) 937-7400Richardson, TX 75081(214) 763-7010Quality Components:Huntsville, AL 35816(205) 830-1881Addison, TX 75001(214) 733-4300Austin, TX 78758(512) 835-0220Sugarland, TX 77478(713) 240-2255Tulsa, OK 74129(918) 664-8812Lionex Corporation:Meriden, CT 06450(203) 237-2282Wilmington, MA 01887(617) 657-5170Columbia, MD 21045(301) 995-6640Fairfield, NJ 07006(201) 227-7960Hauppauge, NY 11787(516) 273-1660Horsham, P A 19044(215) 443-5150

CYPRESS SEMICONDUCTOR CORPORATION3901 NORTH FIRST STREETSAN JOSE, CALIFORNIA 95134TELEPHONE (408) 943-2600

CYPRESS SEMICONDUCTOR CORPORATION3901 NORTH FIRST STREETSAN JOSE, CALIFORNIA 95134TELEPHONE (408) 943-2600