SSD1926 Application Note - Solomon Systech Limited

SOLOMON SYSTECHSEMICONDUCTOR TECHNICAL DATASSD1926 Application NoteThis document contains information on a product under development. Solomon Systech reserves the right to changeor discontinue this product without notice.http://www.solomon-systech.comSSD1926Rev 1.0 P 1/1 Jul 2009 Copyright © 2009 Solomon Systech LimitedApplication Note

CONTENTS1 DISPLAY DATA FORMATS..................................................................................................... 52 REGISTERS TABLE .................................................................................................................. 62.1 REGISTER MAPPING...................................................................................................................................................62.2 READ-ONLY CONFIGURATION REGISTERS.................................................................................................................62.3 CLOCK CONFIGURATION REGISTERS .........................................................................................................................82.4 LOOK-UP TABLE REGISTERS ...................................................................................................................................102.4.1 Monochrome Modes....................................................................................................................................102.4.2 Color Modes ...............................................................................................................................................122.5 PANEL CONFIGURATION REGISTERS........................................................................................................................172.5.1 Monochrome 8-Bit Panel Timing................................................................................................................192.5.2 Color 8-Bit Panel Timing (Format stripe) ..................................................................................................202.5.3 Color 16-Bit Panel Timing..........................................................................................................................212.5.4 Generic TFT Panel Timing .........................................................................................................................232.5.5 Serial TFT Panel Timing ............................................................................................................................242.6 SMART PANEL CONFIGURATION REGISTERS............................................................................................................402.6.1 Write Through Mode...................................................................................................................................402.7 INTERRUPT REGISTERS ............................................................................................................................................522.8 POWER UP REGISTERS.............................................................................................................................................532.9 DISPLAY MODE REGISTERS .....................................................................................................................................552.10 MAIN WINDOW REGISTERS .....................................................................................................................................572.11 SCRATCH BIT REGISTERS.........................................................................................................................................592.12 GENERAL IO PINS REGISTERS .................................................................................................................................592.13 2D ENGINE REGISTERS............................................................................................................................................832.14 DISPLAY ROTATE MODE..........................................................................................................................................842.14.1 90° Display Rotate Mode............................................................................................................................842.14.2 180° Display Rotate Mode..........................................................................................................................852.14.3 270° Display Rotate Mode..........................................................................................................................862.15 FLOATING WINDOW MODE......................................................................................................................................872.15.1 Floating window under 90°Display Rotate Mode.......................................................................................872.15.2 Floating window under 180°Display Rotate Mode.....................................................................................882.15.3 Floating window under 270°Display Rotate Mode.....................................................................................882.16 CURSOR MODE ........................................................................................................................................................952.16.2 Cursor with 270° Display Rotate Mode...................................................................................................1012.17 DRAW2D MODE ....................................................................................................................................................1182.18 JPEG DECODE REGISTERS ....................................................................................................................................1302.18.1 Decode Procedure ....................................................................................................................................1302.19 MMC/SD/SDIO REGISTERS .................................................................................................................................145Solomon Systech Jul 2009 P 2/3 Rev 1.0SSD1926Application Note

TABLESTABLE 2-1: SUGGESTED M & N VALUE ................................................................................................................................9TABLE 2-2: PANEL TIMING PARAMETER DEFINITION AND REGISTER SUMMARY ................................................................18TABLE 2-3: PANEL DATA WIDTH SELECTION......................................................................................................................27TABLE 2-4: LCD PANEL TYPE SELECTION..........................................................................................................................27TABLE 2-5: THE SETTING FOR DISPLAY POST-PROCESSING SATURATION.............................................................................34TABLE 2-6: THE SETTING FOR DISPLAY POST-PROCESSING BRIGHTNESS.............................................................................35TABLE 2-7: THE SETTING FOR DISPLAY POST-PROCESSING CONTRAST................................................................................35TABLE 2-8: THE RGB SEQUENCE FOR SERIAL-TFT INTERFACE..........................................................................................37TABLE 2-9: DATA TYPE FOR PARALLEL INTERFACE OF ALL PANEL TYPES............................................................................40TABLE 2-10: INPUT DATA FORMAT FOR WRITE THROUGH MODE........................................................................................40TABLE 2-11: DATA OUTPUT FORMAT FOR DISPLAY PIXEL IN PARALLEL INTERFACE............................................................41TABLE 2-12: DATA OUTPUT FORMAT FOR 4-WIRE SERIAL INTERFACE (REG[260H] BIT 6= 1) ............................................41TABLE 2-13: DATA OUTPUT FORMAT FOR 3-WIRE SERIAL INTERFACE (REG[260H] BIT 6= 0) ............................................42TABLE 2-14: DATA INPUT FORMAT FOR AUTO REFRESH MODE ..........................................................................................42TABLE 2-15: OUTPUT TIMING FOR 6800 PARALLEL INTERFACE..........................................................................................42TABLE 2-16: OUTPUT TIMING FOR 8080 PARALLEL INTERFACE..........................................................................................43TABLE 2-17: OUTPUT TIMING FOR SERIAL INTERFACE........................................................................................................44TABLE 2-18: REGISTER FOR SMART PANEL INTERFACE........................................................................................................46TABLE 2-19: LCD BIT-PER-PIXEL SELECTION.....................................................................................................................56TABLE 2-20: DISPLAY ROTATE MODE SELECT OPTIONS.....................................................................................................84TABLE 2-21: 32-BIT ADDRESS X INCREMENTS FOR VARIOUS COLOR DEPTHS....................................................................91TABLE 2-22: 32-BIT ADDRESS Y INCREMENTS FOR VARIOUS COLOR DEPTHS....................................................................92TABLE 2-23: 32-BIT ADDRESS X INCREMENTS FOR VARIOUS COLOR DEPTHS....................................................................93TABLE 2-24: 32-BIT ADDRESS Y INCREMENTS FOR VARIOUS COLOR DEPTHS....................................................................94TABLE 2-25: INDEXING SCHEME FOR HARDWARE CURSOR .................................................................................................95TABLE 2-26: X INCREMENT MODE FOR VARIOUS COLOR DEPTHS....................................................................................106TABLE 2-27: Y INCREMENT MODE FOR VARIOUS COLOR DEPTHS....................................................................................107TABLE 2-28: YUV OUTPUT RANGE SELECTION................................................................................................................131TABLE 2-29: JPEG FIFO THRESHOLD STATUS .................................................................................................................131TABLE 2-30: JPEG FIFO THRESHOLD STATUS .................................................................................................................133TABLE 2-31: JPEG FIFO TRIGGER THRESHOLD SELECTION.............................................................................................137TABLE 2-32: JPEG FIFO THRESHOLD STATUS .................................................................................................................137TABLE 2-33: YUV FORMAT SELECTION ...........................................................................................................................140TABLE 2-34: RST MARKER SELECTION ............................................................................................................................144TABLE 2-35: JPEG ERROR STATUS...................................................................................................................................145TABLE 2-36: DETERMINATION OF TRANSFER TYPE...........................................................................................................150TABLE 2-37: COMMAND REGISTER ...................................................................................................................................152TABLE 2-38: RELATION BETWEEN PARAMETERS AND THE NAME OF RESPONSE TYPE .....................................................152TABLE 2-39: RESPONSE BIT DEFINITION FOR EACH RESPONSE TYPE................................................................................153TABLE 2-40: THE RELATION BETWEEN COMMAND CRC ERROR AND COMMAND TIMEOUT ERROR..................................168TABLE 2-41: THE RELATION BETWEEN COMMAND CRC ERROR AND COMMAND TIMEOUT ERROR FOR AUTO CMDI2 ...173SSD1926Application NoteRev 1.0 P 3/4 Jul 2009 Solomon Systech

FIGURESFIGURE 1-1: DISPLAY DATA MEMORY ORGANIZATION........................................................................................................5FIGURE 2-1: CLOCK CONFIGURATION....................................................................................................................................8FIGURE 2-2: 1 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH.........................................................................10FIGURE 2-3: 2 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH.........................................................................11FIGURE 2-4: 4 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH.........................................................................11FIGURE 2-5: 8 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH.........................................................................11FIGURE 2-6: 1 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH.....................................................................................12FIGURE 2-7: 2 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH.....................................................................................12FIGURE 2-8: 4 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH.....................................................................................13FIGURE 2-9: 8 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH .....................................................................................14FIGURE 2-10: PANEL TIMING PARAMETERS ........................................................................................................................18FIGURE 2-11: MONOCHROME 8-BIT PANEL TIMING ............................................................................................................19FIGURE 2-12: COLOR 8-BIT PANEL TIMING (FORMAT STRIPE) ............................................................................................20FIGURE 2-13: COLOR 16-BIT PANEL TIMING.......................................................................................................................21FIGURE 2-14: GENERIC TFT PANEL TIMING .......................................................................................................................23FIGURE 2-15: SERIAL TFT PANEL TIMING ..........................................................................................................................25FIGURE 2-16: 6800 TIMING DIAGRAM.................................................................................................................................43FIGURE 2-17: 8080 TIMING DIAGRAM.................................................................................................................................44FIGURE 2-18: 4 WIRES TIMING DIAGRAM ...........................................................................................................................45FIGURE 2-19: 3 WIRES TIMING DIAGRAM ...........................................................................................................................45FIGURE 2-20: GPIO[4:0] OUTPUT SETUP .............................................................................................................................61FIGURE 2-21: EXAMPLES FOR LCD SIGNALX BY NDPOFF AND ODD / EVEN BITS ............................................................79FIGURE 2-22: DISPLAY DATA BYTE/WORD SWAP...............................................................................................................83FIGURE 2-23: RELATIONSHIP BETWEEN SCREEN IMAGE AND IMAGE REFRESHED IN 90° DISPLAY ROTATE MODE.............84FIGURE 2-24: RELATIONSHIP BETWEEN SCREEN IMAGE AND IMAGE REFRESHED IN 180° DISPLAY ROTATE MODE...........85FIGURE 2-25: RELATIONSHIP BETWEEN SCREEN IMAGE AND IMAGE REFRESHED IN 270° DISPLAY ROTATE MODE...........86FIGURE 2-26: FLOATING WINDOW WITH DISPLAY ROTATE MODE DISABLED .....................................................................87FIGURE 2-27: FLOATING WINDOW WITH DISPLAY ROTATE MODE 90° ENABLED................................................................87FIGURE 2-28: FLOATING WINDOW WITH DISPLAY ROTATE MODE 180° ENABLED..............................................................88FIGURE 2-29: FLOATING WINDOW WITH DISPLAY ROTATE MODE 270° ENABLED..............................................................88FIGURE 2-30: DISPLAY PRECEDENCE IN HARDWARE CURSOR ............................................................................................96FIGURE 2-31: CURSORS ON THE MAIN WINDOW...................................................................................................................96FIGURE 2-32: CURSORS WITH DISPLAY ROTATE MODE 90° ENABLED.................................................................................97FIGURE 2-33: CURSORS WITH DISPLAY ROTATE MODE 180° ENABLED...............................................................................99FIGURE 2-34: CURSORS WITH DISPLAY ROTATE MODE 270° ENABLED.............................................................................101FIGURE 2-35: TIMING OF COMMAND INHIBIT (DAT) AND COMMAND INHIBIT (CMD) WITH DATA TRANSFER .................158FIGURE 2-36: TIMING OF COMMAND INHIBIT (DAT) FOR THE CASE OF RESPONSE WITH BUSY..........................................159FIGURE 2-37: TIMING OF COMMAND INHIBIT (CMD) FOR THE CASE OF NO RESPONSE COMMAND....................................159Solomon Systech Jul 2009 P 4/5 Rev 1.0SSD1926Application Note

1 Display Data FormatsThe following diagrams show the display mode data formats.1 bpp:Byte 0bit 7 bit 0A0 A1 A2 A3 A4 A5 A6 A7P0 P1 P2 P3 P4 P5 P6 P7Byte 1Byte 2A8 A9 A10 A11 A12 A13 A14 A15A16 A17 A18 A19 A20 A21 A22 A23LUTPn = RGB value from LUTIndex (An)Host AddressDisplay BufferPanel Display2 bpp:Byte 0bit 7 bit 0A0 B0 A1 B1 A2 B2 A3 B3P0 P1 P2 P3 P4 P5 P6 P7Byte 1Byte 2A4 B4 A5 B5 A6 B6 A7 B7A8 B8 A9 B9 A10 B10 A11 B11LUTPn = RGB value from LUTIndex (An, Bn)Host AddressDisplay BufferA is MSB, B is LSBPanel Display4 bpp:Byte 0bit 7 bit 0A0 B0 C0 D0 A1 B1 C1 D1P0 P1 P2 P3 P4 P5 P6 P7Byte 1Byte 2A2 B2 C2 D2 A3 B3 C3 D3A4 B4 C4 D4 A5 B5 C5 D5LUTPn = RGB value from LUTIndex (An, Bn, Cn, Dn)Host AddressDisplay BufferA is MSB, D is LSBPanel Display8 bpp:Byte 0bit 7 bit 0A0 B0 C0 D0 E0 F0 G0 H0P0 P1 P2 P3 P4 P5 P6 P7Byte 1Byte 2A1 B1 C1 D1 E1 F1 G1 H1A2 B2 C2 D2 E2 F2 G2 H2LUTPn = RGB value from LUT Index(An, Bn, Cn, Dn, En, Fn, Gn, Hn)Host AddressDisplay BufferA is MSB, H is LSBPanel Display16 bpp: bit 7 bit 0P0 P1 P2 P3 P4 P5 P6 P7Byte 0Byte 1Byte 2Byte 3Host Address2G04R02G14R11G03R01G13R1G00 4B02R01R0G10 4B12R11R13B03B12B0R00 5G02B1R10 5G1Display Buffer1B04G01B14G10B03G00B13G1Bypasses LUTPn = (Rn4-0 , Gn5-0 , Bn4-0 )Panel DisplayR032 bpp:bit 7 bit 0Byte 07R06R05R04R01R00R0R03 2Byte 1G0 7 G0 6 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0Byte 27B06B05B04B03B02B01B00B07 6 5 4 3 2 1 3Byte 3A0 A0 A0 A0 A0 A0 A0 A0Byte 4 75 41R16R1 R1 20R1R1 R1 R1Host AddressDisplay BufferBypasses LUTP0 P1 P2 P3 P4 P5 P6 P7Pn = (Rn7-0 , Gn7-0 , Bn7-0 , An7-0 )Panel DisplayFigure 1-1: Display Data Memory OrganizationNote1. For 16 bpp format, Rn, Gn, Bn represent the red, green, and blue color components.2. For 32 bpp format, Rn, Gn, Bn, An represent the red, green, blue color and alpha blending components.SSD1926Application NoteRev 1.0 P 5/6 Jul 2009 Solomon Systech

2 REGISTERS TABLEThis document discusses how and where to access the SSD1926 registers. It also provides detailedinformation about the layout and usage of each register.2.1 Register MappingThe SSD1926 registers are memory-mapped. When the system decodes the input pins as CS# = 0 andM/R# = 0, the registers may be accessed. The register space is decoded by A[18:0].Unless specified otherwise, all register bits are set to 0 during power-on or software reset (REG[A2h]bit 0 = 1). All bits marked “0” should be programmed as zero. All bits marked “1” should beprogrammed as one.Key :RO : Read Only. Writes to these bits are ignored.ROC : Read Only and initialized to zero at reset. Writes to these bits are ignored.WO : Write OnlyRW : Read / WriteRW1C : Read Only. Write 1 to clear status. Writing a 0 to these bits has no effect.RWAC : Read-Write, automatic clear. Writing a 0 to these bits has no effect.NA : Not ApplicableX : Don’t care2.2 Read-Only Configuration RegistersDebug Code RegisterREG[00h]Bit 7 6 5 4 3 2 1 0DebugCodeBit 7DebugCodeBit 6DebugCodeBit 5DebugCodeBit 4DebugCodeBit 3DebugCodeBit 2DebugCodeBit 1DebugCodeBit 0Type RO RO RO RO RO RO RO ROResetstate0 0 1 0 1 0 0 0Bits 7-0Debug CodeThese bits show the dummy value for debug purpose. The readback code is 00101000.Read Dummy RegisterREG[01h]Bit 7 6 5 4 3 2 1 0DebugCodeBit 7DebugCodeBit 6DebugCodeBit 5DebugCodeBit 4DebugCodeBit 3DebugCodeBit 2DebugCodeBit 1DebugCodeBit 0Type RO RO RO RO RO RO RO ROResetstate1 0 0 0 0 0 0 0Bits 7-0Debug CodeThese bits show the dummy value for debug purpose. The readback code is 10000000.Solomon Systech Jul 2009 P 6/7 Rev 1.0SSD1926Application Note

Configuration Readback RegisterREG[02h]Bit 7 6 5 4 3 2 1 0Reserved CNF6StatusReserved CNF4StatusCNF3StatusCNF2StatusCNF1StatusCNF0StatusType RO RO RO RO RO RO RO ROResetstateX X X X X X X XBits 7-0CNF[6:0] StatusThese status bits return the status of the configuration pins CNF[6:0]. CNF[4:0] are latched atthe rising edge of RESET# or software reset (REG[A2h] bit 0 = 1).Bit 7 = Bit 6Bit 5 = Bit 4Product Code RegisterREG[03h]Bit 7 6 5 4 3 2 1 0ProductCodeProductCodeProductCodeProductCodeProductCodeProductCodeRevisionCode Bit 1RevisionCode Bit 0Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Type RO RO RO RO RO RO RO ROResetstate1 0 0 0 0 0 0 0Bits 7-2 Product Code Bits [5:0]These are read-only bits that indicate the product code.The product code of SSD1926 is 100000.Bits 1-0 Revision Code Bits [1:0]These are read-only bits that indicate the revision code which readback value is 00.Memory status RegisterREG[05h]Bit 7 6 5 4 3 2 1 0Reserved Reserved AD_MODE Reserved Reserved Reserved Reserved ReservedStatusType RO RO RO RO RO RO RO ROResetstate1 X X 0 0 0 0 0Bits 7, 4-0Bits 6-5Reserved bitsAD_MODE StatusThese status bits return the status of the configuration pin AD_MODE which is latched at therising edge of RESET# or software reset (REG[A2h] bit 0 = 1).Bit 6 = Bit 5SSD1926Application NoteRev 1.0 P 7/8 Jul 2009 Solomon Systech

2.3 Clock Configuration RegistersPLL_CLKREG[126-127h]MCLK DividerREG[04h] orCNF7:6MCLKSDHC DividerREG[1001h]andREG[112Dh]SD_CLKPCLK DividerREG[15A-158h]PCLKFigure 2-1: Clock configurationPLL Clock Setting Register 0REG[126h]Bit 7 6 5 4 3 2 1 0PLL enablebitReserved Reserved N value bit4N value bit3N value bit2N value bit1N value bit0Type RW RW RW RW RW RW RW RWResetstate0 0 0 1 0 0 0 0Bit 7PLL enable bit1 Enable PLL. PLL_DIS should tie to IOVSS and clock source should be providedthrough CLKI and CLKO(optional).0 Disable PLL. PLL_DIS should tie to IOVDD and clock source should be providedthrough CLKI2.Bits 6-5Reserved bitsBits 4-0 N value bits [4:0]This register is used to program the N value for clock frequencyNote : The value of N should be greater than 1.PLL Clock Setting Register 1REG[127h]Bit 7 6 5 4 3 2 1 0M value bit7M value bit6M value bit5M value bit4M value bit3M value bit2M value bit1M value bit0Type RW RW RW RW RW RW RW RWResetstate1 0 0 0 0 0 0 0Bits 7-0 M value bits [7:0]This register is used to program the M value for clock frequencyNote : The value of M should be greater than 1.Solomon Systech Jul 2009 P 8/9 Rev 1.0SSD1926Application Note

PLL Clock Setting Register 2REG[12Bh]Bit 7 6 5 4 3 2 1 0PLL configvalue bit 7PLL configbit 6PLL configbit 5PLL configbit 4PLL configbit 3PLL configbit 2PLL configbit 1PLL configbit 0Type RW RW RW RW RW RW RW RWResetstate1 0 0 0 1 1 1 0Bits 7-0 PLL configuration value bits [7:0]This register is used to config the PLL setting. This register should be programmed to 0xAE.Bits 7:5 : control the internal reference clock value when PLL is not lockedBits 4:0 : control the bias current of PLL (b’0x00000 is not allowed)Program sequence (example input clock frequency = 2MHz) :1. Write the N value (REG[126h] = 0x05)2. Write the M value (REG[127h] = 0xC8)3. Write the PLL Conf value (REG[12Bh] = 0xAE)4. Enable the PLL (REG[126h] = 0x85)Then, the PLL output clock frequency = Input clock frequency * (M / N) = 80MHzMaximum output clock frequency = 85MHzTable 2-1: Suggested M & N valueInput clock frequency N value M value2MHz 0x05 0xC82.5MHz 0x06 0xC03MHz 0x08 0xD53.5MHz 0x09 0xCE4Mz 0x0A 0xC8Memory Clock Configuration RegisterREG[04h]Bit 7 6 5 4 3 2 1 00 0 0 MCLKDivideSelect Bit 4MCLKDivideSelect Bit 3MCLKDivideSelect Bit 2MCLKDivideSelect Bit 1MCLKDivideSelect Bit 0Type RO RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-5Reserved bitsBits 4-0 MCLK Divide Select Bits [4:0]These bits determine the divide used to generate the Memory Clock (MCLK) from the PLLoutput frequency. Refer to REG[126h], REG[127h] for the PLL output frequency.MCLK Frequency = PLL output frequency / (MCLK divide value + 1)SSD1926Application NoteRev 1.0 P 9/10 Jul 2009 Solomon Systech

PCLK Frequency Ratio Register 0REG[158h]Bit 7 6 5 4 3 2 1 0PCLKRatio bit 7PCLKRatio bit 6PCLKRatio bit 5PCLKRatio bit 4PCLKRatio bit 3PCLKRatio bit 2PCLKRatio bit 1PCLKRatio bit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0PCLK Frequency Ratio Register 1REG[159h]Bit 7 6 5 4 3 2 1 0PCLKRatio bit 15PCLKRatio bit 14PCLKRatio bit 13PCLKRatio bit 12PCLKRatio bit 11PCLKRatio bit 10PCLKRatio bit 9PCLKRatio bit 8Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0PCLK Frequency Ratio Register 2REG[15Ah]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved PCLKRatio bit 19PCLKRatio bit 18PCLKRatio bit 17PCLKRatio bit 16Type RO RO RO RO RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[15Ah] Bits 3-0,REG[159h] Bits 7-0,REG[158h] Bits 7-0PCLK Frequency Ratio [19:0]These bits determine the Frequency for PCLK.PCLK frequency = MCLK frequency * (PCLK Frequency Ratio + 1) / (2 20 )Note(1)Bit[19:0] are used for non Serial-TFT panel type (REG[10h] bit 2:0 not equal to 010)(2)Bit[17:0] are used for Serial-TFT panel type (REG[10h] bit 2:0 equal to 010)(3)PCLK = MCLK (Bit[19:0] = 0xFFFFF) for smart panel interface.2.4 Look-Up Table RegistersThe following sections are the Look-up Table architecture which shows the display data output path only.2.4.1 Monochrome ModesThe green Look-Up Table (LUT) is used for all monochrome modes.Green Look-Up Table 256x61 bit-per-pixel datafrom Display Buffer00016-bit Gray DataFigure 2-2: 1 Bit-per-pixel Monochrome Mode Data Output PathSolomon Systech Jul 2009 P 10/11 Rev 1.0SSD1926Application Note

Green Look-Up Table 256x62 bit-per-pixel datafrom Display Buffer000102036-bit Gray DataFigure 2-3: 2 Bit-per-pixel Monochrome Mode Data Output PathGreen Look-Up Table 256x64 bit-per-pixel datafrom Display Buffer000102030405060708090A0B0C0D0E0F6-bit Gray DataFigure 2-4: 4 Bit-per-pixel Monochrome Mode Data Output PathGreen Look-Up Table 256x68 bit-per-pixel datafrom Display Buffer0001020304050607F8F9FAFBFCFDFEFF6-bit Gray DataFigure 2-5: 8 Bit-per-pixel Monochrome Mode Data Output PathFor 16/32 bit-per-pixel monochrome Mode, the LUT is bypassed and the green data is directly mapped for this colordepth – See Figure 1-1.SSD1926Application NoteRev 1.0 P 11/12 Jul 2009 Solomon Systech

2.4.2 Color ModesRed Look-Up Table 256x600016-bit Red Data1 bit-per-pixel datafrom Display BufferGreen Look-Up Table 256x600016-bit Green DataBlue Look-Up Table 256x600016-bit Blue DataFigure 2-6: 1 Bit-Per-Pixel Color Mode Data Output PathRed Look-Up Table 256x6000102036-bit Red DataGreen Look-Up Table 256x62 bit-per-pixel datafrom Display Buffer000102036-bit Green DataBlue Look-Up Table 256x6000102036-bit Blue DataFigure 2-7: 2 Bit-Per-Pixel Color Mode Data Output PathSolomon Systech Jul 2009 P 12/13 Rev 1.0SSD1926Application Note

Red Look-Up Table 256x6000102030405060708090A0B0C0D0E0F6-bit Red Data4 bit-per-pixel datafrom Display BufferGreen Look-Up Table 256x6000102030405060708090A0B0C0D0E0F6-bit Green DataBlue Look-Up Table 256x6000102030405060708090A0B0C0D0E0F6-bit Blue DataFigure 2-8: 4 Bit-Per-Pixel Color Mode Data Output PathSSD1926Application NoteRev 1.0 P 13/14 Jul 2009 Solomon Systech

Red Look-Up Table 256x600010203040506076-bit Red DataF8F9FAFBFCFDFEFF8 bit-per-pixel datafrom Display BufferGreen Look-Up Table 256x60001020304050607F8F9FAFBFCFDFEFF6-bit Green DataBlue Look-Up Table 256x600010203040506076-bit Blue DataF8F9FAFBFCFDFEFFFigure 2-9: 8 Bit-per-pixel Color Mode Data Output PathFor 16/32 bit-per-pixel color mode, the LUT is bypassed and the color data is directly mapped for this color depth – SeeFigure 1-1.Solomon Systech Jul 2009 P 14/15 Rev 1.0SSD1926Application Note

Look-Up Table Blue Write Data RegisterREG[08h]Bit 7 6 5 4 3 2 1 0LUT BlueWrite DataBit 7LUT BlueWrite DataBit 6LUT BlueWrite DataBit 5LUT BlueWrite DataBit 4LUT BlueWrite DataBit 3LUT BlueWrite DataBit 2LUT BlueWrite DataBit 1LUT BlueWrite DataBit 0Type WO WO WO WO WO WO WO WOResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Blue Write Data Bits [7:0]This register contains the data to be written to the blue component of the Look-Up Table.The data is stored in this register until a write to the LUT Write Address register (REG[0Bh])moves the data into the Look-Up Table.NoteThe LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written.Look-Up Table Green Write Data RegisterREG[09h]Bit 7 6 5 4 3 2 1 0LUT GreenWrite DataBit 7LUT GreenWrite DataBit 6LUT GreenWrite DataBit 5LUT GreenWrite DataBit 4LUT GreenWrite DataBit 3LUT GreenWrite DataBit 2LUT GreenWrite DataBit 1LUT GreenWrite DataBit 0Type WO WO WO WO WO WO WO WOResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Green Write Data Bits [7:0]This register contains the data to be written to the green component of the Look-Up Table.The data is stored in this register until a write to the LUT Write Address register (REG[0Bh])moves the data into the Look-Up Table.NoteThe LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written.Look-Up Table Red Write Data RegisterREG[0Ah]Bit 7 6 5 4 3 2 1 0LUT RedWrite DataBit 7LUT RedWrite DataBit 6LUT RedWrite DataBit 5LUT RedWrite DataBit 4LUT RedWrite DataBit 3LUT RedWrite DataBit 3LUT RedWrite DataBit 1LUT RedWrite DataBit 0Type WO WO WO WO WO WO WO WOResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Red Write Data Bits [7:0]This register contains the data to be written to the red component of the Look-Up Table.The data is stored in this register until a write to the LUT Write Address register (REG[0Bh])moves the data into the Look-Up Table.NoteThe LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written.SSD1926Application NoteRev 1.0 P 15/16 Jul 2009 Solomon Systech

Look-Up Table Write Address RegisterREG[0Bh]Bit 7 6 5 4 3 2 1 0LUT WriteAddress Bit7LUT WriteAddress Bit6LUT WriteAddress Bit5LUT WriteAddress Bit4LUT WriteAddress Bit3LUT WriteAddress Bit2LUT WriteAddress Bit1LUT WriteAddress Bit0Type WO WO WO WO WO WO WO WOResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Write Address Bits [7:0]This register is a pointer to the Look-Up Table (LUT) which is used to write LUT data stored inREG[08h], REG[09h], and REG[0Ah]. The data is updated to the LUT only with thecompletion of a write to this register. This is a write-only register and returns 00h if read.NoteThe SSD1926 has three 256-entry, 8-bit-wide LUTs, one for each of red, green and blue (seeSection “Look-Up Table Architecture” in datasheet).Look-Up Table Blue Read Data RegisterREG[0Ch]Bit 7 6 5 4 3 2 1 0LUT BlueRead DataBit 7LUT BlueRead DataBit 6LUT BlueRead DataBit 5LUT BlueRead DataBit 4LUT BlueRead DataBit 3LUT BlueRead DataBit 2LUT BlueRead DataBit 1LUT BlueRead DataBit 0Type RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Blue Read Data Bits [7:0]This register contains the data from the blue component of the Look-Up Table. The LUT entryread is controlled by the LUT Read Address Register (REG[0Fh]).NoteThis register is updated only when the LUT Read Address Register (REG[0Fh]) is written.Look-Up Table Green Read Data RegisterREG[0Dh]Bit 7 6 5 4 3 2 1 0LUT GreenRead DataBit 7LUT GreenRead DataBit 6LUT GreenRead DataBit 5LUT GreenRead DataBit 4LUT GreenRead DataBit 3LUT GreenRead DataBit 2LUT GreenRead DataBit 1LUT GreenRead DataBit 0Type RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Green Read Data Bits [7:0]This register contains the data from the green component of the Look-Up Table. The LUT entryread is controlled by the LUT Read Address Register (REG[0Fh]).NoteThis register is updated only when the LUT Read Address Register (REG[0Fh]) is written.Solomon Systech Jul 2009 P 16/17 Rev 1.0SSD1926Application Note

Look-Up Table Red Read Data RegisterREG[0Eh]Bit 7 6 5 4 3 2 1 0LUT RedRead DataBit 7LUT RedRead DataBit 6LUT RedRead DataBit 5LUT RedRead DataBit 4LUT RedRead DataBit 3LUT RedRead DataBit 2LUT RedRead DataBit 1LUT RedRead DataBit 0Type RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Red Read Data Bits [7:0]This register contains the data from the red component of the Look-Up Table. The LUT entryread is controlled by the LUT Read Address Register (REG[0Fh]).NoteThis register is updated only when the LUT Read Address Register (REG[0Fh]) is written.Look-Up Table Read Address RegisterREG[0Fh]Bit 7 6 5 4 3 2 1 0LUT ReadAddress Bit7LUT ReadAddress Bit6LUT ReadAddress Bit5LUT ReadAddress Bit4LUT ReadAddress Bit3LUT ReadAddress Bit2LUT ReadAddress Bit1LUT ReadAddress Bit0Type WO WO WO WO WO WO WO WOResetstate0 0 0 0 0 0 0 0Bits 7-0 LUT Read Address Bits [7:0]This register is a pointer to the Look-Up Table (LUT) which is used to read LUT data and storeit in REG[0Ch], REG[0Dh], REG[0Eh]. The data is read from the LUT only when a write tothis register is completed. This is a write-only register and returns 00h if read.NoteThe SSD1926 has three 256-entry, 8-bit-wide LUTs, one for each of red, green and blue (seeSection “Look-Up Table Architecture” in datasheet).2.5 Panel Configuration RegistersFigure 2-10 shows the timing parameters required to drive a flat panel display. Timing details for eachsupported panel types are provided in the remainder of this section.SSD1926Application NoteRev 1.0 P 17/18 Jul 2009 Solomon Systech

HTHDPSHPSHPWVDPSHDPVTVPSVDPVPWFigure 2-10: Panel Timing ParametersTable 2-2: Panel Timing Parameter Definition and Register SummarySymbol Description Derived From UnitsHT Horizontal Total ((REG[12h] bits 7-0) + 1) x 8 + (REG[13h] bits 2-0)HDP 2 Horizontal Display Period 2 ((REG[14h] bits 6-0) + 1) x 8HDPS Horizontal Display Period Start Position ((REG[17h]bits 2-0,REG[16h]bits7-0))Ts 1HPS LLINE Pulse Start Position (REG[23h] bits 2-0, REG[22h] bits 7-0) + 1HPW LLINE Pulse Width (REG[20h] bits 6-0) + 1VT Vertical Total ((REG[19h] bits 2-0, REG[18h] bits 7-0) + 1) xHTVDP 3 Vertical Display Period 3 ((REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1) xHTVDPS Vertical Display Period Start Position (REG[1Fh] bits 2-0, REG[1Eh] bits 7-0) x HTVPS LFRAME Pulse Start Position (REG[27h] bits 2-0, REG[26h] bits 7-0) x HT +Ts 1(REG[31h] bits 2-0, REG[30h] bits 7-0)VPW LFRAME Pulse Width ((REG[24h] bits 2-0) + 1) x HT + (REG[35h] bits2-0, REG[34h] bits 7-0) – (REG[31h] bits 2-0,REG[30h] bits 7-0)The following conditions must be fulfilled for all panel timings:HDPS + HDP < HTVDPS + VDP < VT1Ts = pixel clock period2The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.3The VDP must be a minimum of 2 lines.Solomon Systech Jul 2009 P 18/19 Rev 1.0SSD1926Application Note

2.5.1 Monochrome 8-Bit Panel TimingVDPVNDPLFRAMELLINELDEN (MOD)LDATA[7:0]LINE1LINE2LINE3LINE479LINE480LINE1LINE2LLINELDEN (MOD)LSHIFTHDPHNDPLDATA71-11-91-633LDATA61-21-101-634LDATA51-31-111-635LDATA41-41-121-636LDATA31-51-131-637LDATA21-61-141-638LDATA11-71-151-639LDATA01-81-161-640*Diagram drawn with 2 LLINE vertical blank periodExample timing for a 640x480 panelFigure 2-11: Monochrome 8-Bit Panel TimingVDP = Vertical Display Period= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 LinesVNDP = Vertical Non-Display Period= VT-VDPHDP= (REG[19h] bits 2:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines= Horizontal Display Period= ((REG[14h] bits 6:0) + 1) x 8TsHNDP = Horizontal Non-Display Period= HT - HDP= (((REG[12h] bits 7:0) + 1) x 8Ts + (REG[13h] bits 2-0)) - (((REG[14h] bits 6:0) + 1) x 8Ts)SSD1926Application NoteRev 1.0 P 19/20 Jul 2009 Solomon Systech

2.5.2 Color 8-Bit Panel Timing (Format stripe)VDPVNDPLFRAMELLINELDEN (MOD)LDATA[7:0]LINE1LINE2LINE3LINE479LINE480LINE1LINE2LLINELDEN (MOD)LSHIFTHDPHNDPLDATA71-R11-B31-G61-G638LDATA61-G11-R41-B61-B638LDATA51-B11-G41-R71-R639LDATA41-R21-B41-G71-G639LDATA31-G21-R51-B71-B639LDATA21-B21-G51-R81-R640LDATA11-R31-B51-G81-G640LDATA01-G31-R61-B81-B640*Diagram drawn with 2 LLINE vertical blank periodExample timing for a 640X480 panelFigure 2-12: Color 8-Bit Panel Timing (Format stripe)VDP = Vertical Display Period= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 LinesVNDP = Vertical Non-Display Period= VT-VDPHDP= (REG[19h] bits 2:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines= Horizontal Display Period= ((REG[14h] bits 6:0) + 1) x 8TsHNDP = Horizontal Non-Display Period= HT - HDP= (((REG[12h] bits 7:0) + 1) x 8Ts + (REG[13h] bits 2-0) ) - (((REG[14h] bits 6:0) + 1) x 8Ts)Solomon Systech Jul 2009 P 20/21 Rev 1.0SSD1926Application Note

2.5.3 Color 16-Bit Panel TimingVDPVNDPLFRAMELLINELDEN (MOD)LDATA[7:0]LINE1LINE2LINE3LINE479LINE480LINE1LINE2LLINELDEN (MOD)LSHIFTHDPHNDPLDATA151-R11-G61-B111-G635LDATA141-B11-R71-G121-G636LDATA131-G21-B71-R131-R637LDATA121-R31-G81-B131-B637LDATA71-B31-R91-G141-G638LDATA61-G41-B91-R151-R639LDATA51-R51-G10 1-B151-B639LDATA41-B51-R11 1-G161-G640LDATA111-G11-B61-R121-R636LDATA101-R21-G71-B121-B636LDATA91-B21-R81-G131-G637LDATA81-G31-B81-R141-R638LDATA31-R41-G91-B141-B638LDATA21-B41-R10 1-G151-G639LDATA11-G51-B101-R161-R640LDATA01-R61-G11 1-B161-B640*Diagram drawn with 2 LLINE vertical blank periodExample timing for a 640X480 panelFigure 2-13: Color 16-Bit Panel TimingSSD1926Application NoteRev 1.0 P 21/22 Jul 2009 Solomon Systech

VDP = Vertical Display Period= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 LinesVNDP = Vertical Non-Display Period= VT-VDPHDP= (REG[19h] bits 2:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines= Horizontal Display Period= ((REG[14h] bits 6:0) + 1) x 8TsHNDP = Horizontal Non-Display Period= HT - HDP= (((REG[12h] bits 7:0) + 1) x 8Ts + (REG[13h] bits 2-0) ) - (((REG[14h] bits 6:0) + 1) x 8Ts)Solomon Systech Jul 2009 P 22/23 Rev 1.0SSD1926Application Note

Analyse de la professionPeintre en production industrielleTÂCHE 6 :EXÉCUTER DES TESTSOPÉRATIONSSOUS-OPÉRATIONS6.1 Prendre connaissance des spécifications.6.2 Préparer les appareils et les instruments.6.3 Appliquer la procédure de test.6.4 Consigner les résultats.6.5 Transmettre les résultats.6.1.1 Prendre connaissance des spécificationsdu client, du fournisseur ou desspécifications à l’interne.6.1.2 Prendre connaissance des normesapplicables (environnementales etpropres au domaine de référence).6.2.1 Calibrer les appareils et les instruments.Commentaire : il faut effectuer une lecturevisuelle en conformité avec les standardsreconnus (ASTM, SSPC, etc.) et avec lesstandards du client et les procédures reconnues àl’interne.6.4.1 Rédiger un rapport (sur papier ou àl’aide d’un logiciel).6.4.2 Compiler des statistiques.6.4.3 Archiver les résultats selon la procédureinterne ou la demande du client.6.4.4 Prendre les mesures nécessaires à latraçabilité.6.5.1 Transmettre un rapport.6.5.2 Transmettre une procédure.6.5.3 Afficher de l’information.6.5.4 Organiser une rencontre ou une activitéde formation.CSMOFMI 23

= [(REG[1Dh]bits1-0,REG[1Ch]bits7-0) + 1] lines* The VDP must be a minimum of 2 linesHT = Horizontal Total= [((REG[12h] bits 7-0) + 1) x 8 + (REG[13h] bits 2-0)] pixelsHPS = LLINE Pulse Start Position= [(REG[23h] bits 2-0, REG[22h] bits 7-0) + 1] pixelsHPW = LLINE Pulse Width= [(REG[20h] bits 6-0)+ 1] pixelsHDPS = Horizontal Display Period Start Position= [(REG[17h] bits 2-0, REG[16h] bits 7-0) + 5] pixelsHDP = Horizontal Display Period= [((REG[14h] bits 6-0) + 1) x 8] pixelsThe HDP must be a minimum of 32 pixels and can be increased by multiples of 8.*Panel Type Bits (REG[10h] bits 2-0) = 001 (TFT)*LLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)*LFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)2.5.5 Serial TFT Panel TimingSolomon Systech Jul 2009 P 24/25 Rev 1.0SSD1926Application Note

VT (= 1 Frame)VPSVPWLFRAMEVDPSVDPLLINELDENLDATA[7:0]HT (= 1 Line)HPSHPWLLINELSHIFTLDENHDPSHDPLDATA[7:0]Figure 2-15: Serial TFT Panel TimingVT = Vertical Total= [(REG[19h] bits 2-0, REG[18h] bits 7-0) + 1] linesVPS = LFRAME Pulse Start Position= [(REG[27h] bits 2-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 2-0, REG[30h] bits 7-0) pixelsVPW = LFRAME Pulse Width= [(REG[24h]bits2-0)+ 1] x HT + (REG[35h] bits 2-0, REG[34h] bits 7-0) – (REG[31h] bits 2-0,REG[30h] bits 7-0) pixelsVDPS = Vertical Display Period Start Position= [(REG[1Fh]bits2-0,REG[1Eh]bits7-0)] linesVDP = Vertical Display Period= [(REG[1Dh]bits1-0,REG[1Ch]bits7-0)+ 1] lines* The VDP must be a minimum of 2 linesSSD1926Application NoteRev 1.0 P 25/26 Jul 2009 Solomon Systech

HT = Horizontal Total= [(REG[12h] bits 7-0) x 8 + (REG[13h] bits 2-0) + 1] pixelsHPS = LLINE Pulse Start Position= [(REG[23h] bits 2-0, REG[22h] bits 7-0) + 1] pixelsHPW = LLINE Pulse Width= [(REG[20h] bits 6-0)+ 1] pixelsHDPS = Horizontal Display Period Start Position= [(REG[17h] bits 2-0, REG[16h] bits 7-0) ] pixelsHDP = Horizontal Display Period= [((REG[14h] bits 6-0) + 1) x 8] pixelsThe HDP must be a minimum of 32 pixels and can be increased by multiples of 8.*Panel Type Bits (REG[10h] bits 2-0) = 010 (Serial 8-bit TFT)*LLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)*LFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)In horizontal display period, one cycle out of every four LSHIFT clock is off. In horizontal non-displayperiod, all LSHIFT clock cycles are on.So, Horizontal Total (REG[13h] bits 2-0, REG[12h] bits 7-0) = [(no of subpixel clock of horizontal total – noof subpixel clock of horizontal display period)/4 + (no of subpixel clock of horizontal display period)/3] - 1LLINE Pulse Start Position (REG[23h] bits 2-0, REG[22h] bits 7-0) = (no of subpixel clock of LLINE PulseStart Position)/4 - 1LLINE Pulse Width (REG[20h] bits 6-0) = (no of subpixel clock of LLINE Pulse Width)/4 – 1Horizontal Display Period Start Position (REG[17h] bits 2-0, REG[16h] bits 7-0) = (no of subpixel clock ofHorizontal Display Period Start Position)/4 - 1Horizontal Display Period (REG[14h] bits 6-0) = [(no of subpixel clock of horizontal display period)/3]/8 – 1The frequency of LSHIFT was different during display and non-display period.During horizontal display period:LSHIFT frequency = (¾) * MCLK frequency * (PCLK Frequency Ratio + 1) / (2 18 )During horizontal non-display period:LSHIFT frequency = MCLK frequency * (PCLK Frequency Ratio + 1) / (2 18 )Solomon Systech Jul 2009 P 26/27 Rev 1.0SSD1926Application Note

Panel Type RegisterREG[10h]Bit 7 6 5 4 3 2 1 0Color STNPanelColor/MonoPanel DataWidth Bit 1Panel DataWidth Bit 0Reserved Panel TypeBit 2Panel TypeBit 1Panel TypeBit 0Select PanelSelectType RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bit 7Color STN Panel SelectWhen this bit = 0, non CSTN LCD panel is selected.When this bit = 1, CSTN LCD panel is selected.Bit 6Color/Mono Panel SelectWhen this bit = 0, monochrome LCD panel is selected.When this bit = 1, color LCD panel is selected.Bits 5-4 Panel Data Width Bits [1:0]These bits are determined by the data width of the LCD panel. Refer to Table 2-3: Panel DataWidth Selection for the selection.Note : These 2 bits are not effective for Serial TFT panel.Table 2-3: Panel Data Width SelectionPanel Data Width Bits [1:0] Passive Panel Data Width Active Panel Data Width(for TFT only)00 4-bit 9-bit01 8-bit 12-bit10 Reserved 18-bit11 Reserved 24-bitBit 3Reserved bitThis bit should be programmed by 0.Bits 2-0 Panel Type Bit [2:0]This bit selects the panel type.Table 2-4: LCD Panel Type SelectionPanel Type Bit[2:0] Panel Type000 STN001 TFT010 Serial-TFT011 Reserved100 Smart TFT101 Smart CSTN110 Smart OLED111 ReservedSSD1926Application NoteRev 1.0 P 27/28 Jul 2009 Solomon Systech

MOD Rate RegisterREG[11h]Bit 7 6 5 4 3 2 1 00 0 MOD RateBit 5MOD RateBit 4MOD RateBit 3MOD RateBit 2MOD RateBit 1MOD RateBit 0Type RO RO RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 5-0 MOD Rate Bits [5:0]When these bits are all 0, the MOD output signal (LDEN) toggles every LFRAME.For any non-zero value n, the MOD output signal (LDEN) toggles every n LLINE.Note: These bits are for passive LCD panels and REG[340h] = 0 only.Horizontal Total Register 1REG[12h]Bit 7 6 5 4 3 2 1 0HorizontalTotal Bit 10HorizontalTotal Bit 9HorizontalTotal Bit 8HorizontalTotal Bit 7HorizontalTotal Bit 6HorizontalTotal Bit 5HorizontalTotal Bit 4HorizontalTotal Bit 3Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Horizontal Total Register 0REG[13h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 HorizontalTotal Bit 2HorizontalTotal Bit 1HorizontalTotal Bit 0Type RO RW RW RW RW RW RW RWResetstate0 0 0 0 0 1 1 1REG[12h], Bits 6-0REG[13h], Bits 2-0Horizontal Total Bits [10:0]This register is used for both dumb and smart panel interface.For dumb panel interface, these bits specify the LCD panel Horizontal Total period. TheHorizontal Total is the sum of the Horizontal Display period and the Horizontal Non-Displayperiod.The maximum Horizontal Total is 2048 pixels.Horizontal Total in number of pixels = REG[12h] Bits [7:0] x 8 + REG[13h] Bits [2:0] + 1Note(1)This register must be programmed such that the following condition is fulfilled.HDPS + HDP < HT(2)For panel AC timing and timing parameter definitions, see Section “Display Interface” indatasheet.(3)For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), REG[12h] willbe used as horizontal number of pixels and REG[13h] = 0x07.Horizontal width of smart panel = REG[12h] Bits[7:0] x 8 + 8Solomon Systech Jul 2009 P 28/29 Rev 1.0SSD1926Application Note

Horizontal Display Period RegisterREG[14h]Bit 7 6 5 4 3 2 1 00 HorizontalDisplayPeriod Bit 6HorizontalDisplayPeriod Bit 5HorizontalDisplayPeriod Bit 4HorizontalDisplayPeriod Bit 3HorizontalDisplayPeriod Bit 2HorizontalDisplayPeriod Bit 1HorizontalDisplayPeriod Bit 0Type RO RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bit 7Reserved bitBits 6-0 Horizontal Display Period Bits [6:0]This register is used for both dumb and smart panel interface.For dumb panel interface, these bits specify the LCD panel Horizontal Display period, in 8pixel resolution. The Horizontal Display period should be less than the Horizontal Total toallow for a sufficient Horizontal Non-Display period.Horizontal Display Period in number of pixels = (Bits [6:0] + 1) x 8Note(1)Maximum value of REG[14h] ≤ 0x3F when Display Rotate Mode (90° or 270°) is selected.(2)For panel AC timing and timing parameter definitions, see Section “Display Interface” indatasheet.(3)For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), these bitsshould be set as same as REG[12h].Horizontal Display Period Start Position Register 0REG[16h]Bit 7 6 5 4 3 2 1 0HorizontalDisplayPeriod StartPosition Bit7HorizontalDisplayPeriod StartPosition Bit6HorizontalDisplayPeriod StartPosition Bit5HorizontalDisplayPeriod StartPosition Bit4HorizontalDisplayPeriod StartPosition Bit3HorizontalDisplayPeriod StartPosition Bit2HorizontalDisplayPeriod StartPosition Bit1HorizontalDisplayPeriod StartPosition Bit0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Horizontal Display Period Start Position Register 1REG[17h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 HorizontalDisplayPeriod StartPosition Bit10HorizontalDisplayPeriod StartPosition Bit9HorizontalDisplayPeriod StartPosition Bit8Type RO RO RO RO RO RO RW RWResetstate0 0 0 0 0 0 0 0REG[17h] bits1-0,REG[16h] bits 7-0Horizontal Display Period Start Position Bits [10:0]These bits specify the Horizontal Display Period Start Position in 1 pixel resolution.Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” indatasheet.(2)These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)SSD1926Application NoteRev 1.0 P 29/30 Jul 2009 Solomon Systech

Vertical Total Register 0REG[18h]Bit 7 6 5 4 3 2 1 0VerticalTotal Bit 7VerticalTotal Bit 6VerticalTotal Bit 5VerticalTotal Bit 4VerticalTotal Bit 3VerticalTotal Bit 2VerticalTotal Bit 1VerticalTotal Bit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Vertical Total Register 1REG[19h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 VerticalTotal Bit 10VerticalTotal Bit 9VerticalTotal Bit 8Type RO RO RO RO RO RW RW RWResetstate0 0 0 0 0 0 0 0REG[19h] bits 1-0,REG[18h] bits 7-0Vertical Total Bits [10:0]This register is used for both dumb and smart panel interface.For dumb panel interface, these bits specify the LCD panel Vertical Total period, in 1 lineresolution. The Vertical Total is the sum of the Vertical Display Period and the Vertical Non-Display Period.The maximum Vertical Total is 2048 lines. See “Display Interface” in datasheet.Vertical Total in number of lines = Bits [10:0]+ 1Note(1)This register must be programmed such that the following condition is fulfilled.VDPS + VDP < VT(2)For panel AC timing and timing parameter definitions, see Section “Display Interface”.(3)For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), these bits willbe used as vertical number of lines in smart panel.Vertical height of smart panel = REG[19h] 2:0, REG[18h] 7:0 + 1Vertical Display Period Register 0REG[1Ch]Bit 7 6 5 4 3 2 1 0VerticalDisplayPeriod Bit 7VerticalDisplayPeriod Bit 6VerticalDisplayPeriod Bit 5VerticalDisplayPeriod Bit 4VerticalDisplayPeriod Bit 3VerticalDisplayPeriod Bit 2VerticalDisplayPeriod Bit 1VerticalDisplayPeriod Bit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Solomon Systech Jul 2009 P 30/31 Rev 1.0SSD1926Application Note

Vertical Display Period Register 1REG[1Dh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 VerticalDisplayPeriod Bit 9VerticalDisplayPeriod Bit 8Type RO Ro RO RO RO RO RW RWResetstate0 0 0 0 0 0 0 0REG[1Dh] bits 1-0,REG[1Ch] bits 7-0Vertical Display Period Bits [9:0]This register is used for both main and smart panel interface.For dumb panel interface, these bits specify the LCD panel Vertical Display period, in 1 lineresolution. The Vertical Display period should be less than the Vertical Total to allow for asufficient Vertical Non-Display period.Vertical Display Period in number of lines = Bits [9:0] + 1Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” indatasheet.(2)For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), these bitsshould be set as same as REG[19h-18h].Vertical Display Period Start Position Register 0REG[1Eh]Bit 7 6 5 4 3 2 1 0VerticalDisplayPeriod StartPosition Bit7VerticalDisplayPeriod StartPosition Bit6VerticalDisplayPeriod StartPosition Bit5VerticalDisplayPeriod StartPosition Bit4VerticalDisplayPeriod StartPosition Bit3VerticalDisplayPeriod StartPosition Bit2VerticalDisplayPeriod StartPosition Bit1VerticalDisplayPeriod StartPosition Bit0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Vertical Display Period Start Position Register 1REG[1Fh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 VerticalDisplayStartPositionPeriod BitVerticalDisplayStartPositionPeriod Bit 9VerticalDisplayStartPositionPeriod Bit 810Type NA NA NA NA NA NA RW RWResetstate0 0 0 0 0 0 0 0REG[1Fh] bits 1-0,REG[1Eh] bits 7-0Vertical Display Period Start Position Bits [10:0]These bits specify the Vertical Display Period Start Position in 1 line resolution.NoteFor panel AC timing and timing parameter definitions, see Section “Display Interface” indatasheet.SSD1926Application NoteRev 1.0 P 31/32 Jul 2009 Solomon Systech

LLINE Pulse Width RegisterREG[20h]Bit 7 6 5 4 3 2 1 0LLINEPulsePolarityLLINEPulseWidth Bit 6LLINEPulseWidth Bit 5LLINEPulseWidth Bit 4LLINEPulseWidth Bit 3LLINEPulseWidth Bit 2LLINEPulseWidth Bit 1LLINEPulseWidth Bit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bit 7LLINE Pulse PolarityThis bit determines the polarity of the horizontal sync signal. The horizontal sync signal istypically named as LLINE or LP, depending on the panel type.When this bit = 0, the horizontal sync signal is active low.When this bit = 1, the horizontal sync signal is active high.Note(1)These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)Bits 6-0 LLINE Pulse Width Bits [6:0]These bits specify the width of the panel horizontal sync signal, in number of PCLK. Thehorizontal sync signal is typically named as LLINE or LP, depending on the panel type.LLINE Pulse Width in PCLK = Bits [6:0] + 1Note(1)These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.LLINE Pulse Start Sub-pixel Position RegisterREG[21h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Sub-pixelPosition Bit1Sub-pixelPosition Bit0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-2Reserved bitsBits 1-0 Sub-pixel Position Bits [1:0]00 : No sub-pixel delay01 : 1 sub-pixel clock delay10 : 2 sub-pixel clock delay11 : 3 sub-pixel clock delayNote(1)This register is effective for Serial-TFT panel only.Solomon Systech Jul 2009 P 32/33 Rev 1.0SSD1926Application Note

LLINE Pulse Start Position Register 0REG[22h]Bit 7 6 5 4 3 2 1 0LLINEPulse StartPosition Bit7LLINEPulse StartPosition Bit6LLINEPulse StartPosition Bit5LLINEPulse StartPosition Bit4LLINEPulse StartPosition Bit3LLINEPulse StartPosition Bit2LLINEPulse StartPosition Bit1LLINEPulse StartPosition Bit0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0LLINE Pulse Start Position Register 1REG[23h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 LLINEPulse StartPosition Bit10LLINEPulse StartPosition Bit9LLINEPulse StartPosition Bit8Type NA NA NA NA NA NA RW RWResetstate0 0 0 0 0 0 0 0REG[23h] bits 1-0,REG[22h] bits 7-0LLINE Pulse Start Position Bits [10:0]These bits specify the start position of the horizontal sync signal, in number of PCLK.LLINE Pulses Start Position in PCLK = Bits [10:0] + 1Note(1)These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet”.LFRAME Pulse Width RegisterREG[24h]Bit 7 6 5 4 3 2 1 0LFRAMEPulsePolarity0 0 0 0 LFRAMEPulseWidth Bit 2LFRAMEPulseWidth Bit 1LFRAMEPulseWidth Bit 0Type RW NA NA NA NA RW RW RWResetstate0 0 0 0 0 0 0 0Bit 7LFRAME Pulse PolarityThis bit selects the polarity of the vertical sync signal. The vertical sync signal is typicallynamed as LFRAME or SPS, depending on the panel type.When this bit = 0, the vertical sync signal is active low.When this bit = 1, the vertical sync signal is active high.Note(1)These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)Bits 2-0 LFRAME Pulse Width Bits [2:0]These bits specify the width of the panel vertical sync signal, in 1 line resolution. The verticalsync signal is typically named as LFRAME or SPS, depending on the panel type.LFRAME Pulse Width in number of pixels = (Bits [2:0] + 1) x Horizontal Total + offsetNote(1)These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.SSD1926Application NoteRev 1.0 P 33/34 Jul 2009 Solomon Systech

LFRAME Pulse Start Position Register 0REG[26h]Bit 7 6 5 4 3 2 1 0LFRAMEPulse StartPosition Bit7LFRAMEPulse StartPosition Bit6LFRAMEPulse StartPosition Bit5LFRAMEPulse StartPosition Bit4LFRAMEPulse StartPosition Bit3LFRAMEPulse StartPosition Bit2LFRAMEPulse StartPosition Bit1LFRAMEPulse StartPosition Bit0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0LFRAME Pulse Start Position register 1REG[27h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 LFRAMEPulse StartPosition Bit10LFRAMEPulse StartPosition Bit9LFRAMEPulse StartPosition Bit8Type NA NA NA NA NA NA RW RWResetstate0 0 0 0 0 0 0 0REG[27h] bits 1-0REG[26h] bits 7-0LFRAME Pulse Start Position Bits [10:0]These bits specify the start position of the vertical sync signal, in 1 line resolution.LFRAME Pulse Start Position in number of pixels = (Bits [10:0]) x Horizontal Total + offsetNote(1)These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.Display Post-processing Saturation Control RegisterREG[2Ch]Bit 7 6 5 4 3 2 1 0DisplayPost-procSaturationBit 7DisplayPost-procSaturationBit 6DisplayPost-procSaturationBit 5DisplayPost-procSaturationBit 4DisplayPost-procSaturationBit 3DisplayPost-procSaturationBit 2DisplayPost-procSaturationBit 1DisplayPost-procSaturationBit 0Type NA NA NA NA NA NA RW RWResetstate0 1 0 0 0 0 0 0Bits 7-0 Display Post-processing Saturation Control [7:0]These bits control the saturation of the display.Table 2-5: The setting for display post-processing saturationControl Bits [7:0] Saturation Control0x00 Gain = 00x01 Gain = 1/64…0x40 (Default) Gain = 1…0x7F Gain = 127/64Solomon Systech Jul 2009 P 34/35 Rev 1.0SSD1926Application Note

Display Post-processing Brightness Control RegisterREG[2Dh]Bit 7 6 5 4 3 2 1 0DisplayPost-procBrightnessBit 7DisplayPost-procBrightnessBit 6DisplayPost-procBrightnessBit 5DisplayPost-procBrightnessBit 4DisplayPost-procBrightnessBit 3DisplayPost-procBrightnessBit 2DisplayPost-procBrightnessBit 1DisplayPost-procBrightnessBit 0Type NA NA NA NA NA NA RW RWResetstate1 0 0 0 0 0 0 0Bits 7-0 Display Post-processing Brightness Control [7:0]These bits control the brightness of the display.Table 2-6: The setting for Display Post-processing brightnessControl Bits [7:0] Brightness Control0x00 Value = 0…0x80 (Default) Value = 128…0xFF Value = 255Display Post-processing Contrast Control RegisterREG[2Eh]Bit 7 6 5 4 3 2 1 0DisplayPost-procContrast Bit7DisplayPost-procContrast Bit6DisplayPost-procContrast Bit5DisplayPost-procContrast Bit4DisplayPost-procContrast Bit3DisplayPost-procContrast Bit2DisplayPost-procContrast Bit1DisplayPost-procContrast Bit0Type NA NA NA NA NA NA RW RWResetstate0 1 0 0 0 0 0 0Bits 7-0 Display Post-processing Contrast Control [7:0]These bits control the contrast of the display.Table 2-7: The setting for Display Post-processing contrastControl Bits [7:0] Contrast Control0x00 Gain = 00x01 Gain = 1/64…0x40 (Default) Gain = 1…0x7F Gain = 127/64SSD1926Application NoteRev 1.0 P 35/36 Jul 2009 Solomon Systech

Display Post-processing Control RegisterREG[2Fh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 DisplayPost-procEnableType RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-1Bit 0Reserved bitsThese bits should be programmed by 0.Display Post-processing EnableWhen this bit = 1, display post-processing is enabled.When this bit = 0, display post-processing is disabled.LFRAME Pulse Start Offset Register 0REG[30h]Bit 7 6 5 4 3 2 1 0LFRAMEStart OffsetBit 7LFRAMEStart OffsetBit 6LFRAMEStart OffsetBit 5LFRAMEStart OffsetBit 4LFRAMEStart OffsetBit 3LFRAMEStart OffsetBit 2LFRAMEStart OffsetBit 1LFRAMEStart OffsetBit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0LFRAME Pulse Start Offset Register 1REG[31h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 LFRAMEStart OffsetBit 10LFRAMEStart OffsetBit 9LFRAMEStart OffsetBit 8Type NA NA NA NA NA NA RW RWResetstate0 0 0 0 0 0 0 0REG[31h] bits 2-0REG[30h] bits 7-0LFRAME Pulse Start Offset [10:0]These bits specify the start offset of the vertical sync signal within a line, in 1 pixel resolution.Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.LFRAME Pulse Stop Offset Register 0REG[34h]Bit 7 6 5 4 3 2 1 0LFRAMEStop OffsetBit 7LFRAMEStop OffsetBit 6LFRAMEStop OffsetBit 5LFRAMEStop OffsetBit 4LFRAMEStop OffsetBit 3LFRAMEStop OffsetBit 2LFRAMEStop OffsetBit 1LFRAMEStop OffsetBit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Solomon Systech Jul 2009 P 36/37 Rev 1.0SSD1926Application Note

LFRAME Pulse Stop Offset Register 1REG[35h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 LFRAMEStop OffsetBit 10LFRAMEStop OffsetBit 9LFRAMEStop OffsetBit 8Type NA NA NA NA NA NA RW RWResetstate0 0 0 0 0 0 0 0REG[35h] bits 2-0REG[34h] bits 7-0LFRAME Pulse Stop Offset [10:0]These bits specify the stop offset of the vertical sync signal within a line, in 1 pixel resolution.Note(1)For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.LSHIFT Polarity RegisterREG[38h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 LSHIFTPolarityswapType RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-1Reserved bitsThese bits should be programmed by 0.Bit 0LSHIFT Polarity SwapWhen this bit = 1, LSHIFT signal is falling trigger.When this bit = 0, LSHIFT signal is rising trigger.Note(1)Bit 0 is effective for TFT panels only (REG[10h] bit 0 = 1).RGB sequence RegisterREG[42h]Bit 7 6 5 4 3 2 1 00 0 Even lineRGBsequence Bit2Even lineRGBsequence Bit1Even lineRGBsequence Bit0Odd lineRGBsequence Bit2Odd lineRGBsequence Bit1Odd lineRGBsequence Bit0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-6Reserved bitsBits 5-3 Even line RGB sequence Bits [2:0]Bits 2-0 Odd line RGB sequence Bits [2:0]The first display line is the odd line.NoteThis register is effective for Serial-TFT panel only. The first line is the even line.Table 2-8: The RGB sequence for Serial-TFT interfaceRGB sequence bits [2:0] RGB output sequence000 RGB001 RBG010 GRB011 GBR100 BRG101 BGR11xReservedSSD1926Application NoteRev 1.0 P 37/38 Jul 2009 Solomon Systech

MOD Time Period Register 0REG[340h]Bit 7 6 5 4 3 2 1 00 0 0 0 MOD TimePeriodBit 3MOD TimePeriodBit 2MOD TimePeriodBit 1MOD TimePeriodBit 0Type RO RO RO RO RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[340h] bits 3-0 MOD Period position Register [3:0]This register define the period of MOD output signal, in terms of display line.0 : Disable and MOD output will follow the setting of REG[11h]n : MOD polarity will repeat every n frames with the patterns defined in REG[342-343h]. Thesetting of REG[11h] will be ignored.Note: These bits are for passive LCD panels only.MOD Time Pattern Register 0REG[342h]Bit 7 6 5 4 3 2 1 0MOD TimePatternBit 7MOD TimePatternBit 6MOD TimePatternBit 5MOD TimePatternBit 4MOD TimePatternBit 3MOD TimePatternBit 2MOD TimePatternBit 1MOD TimePatternBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateMOD Time Pattern Register 1REG[343h]Bit 7 6 5 4 3 2 1 0MOD TimePatternBit 15MOD TimePatternBit 14MOD TimePatternBit 13MOD TimePatternBit 12MOD TimePatternBit 11MOD TimePatternBit 10MOD TimePatternBit 9MOD TimePatternBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[343h] bits 7-0,REG[342h] bits 7-0MOD Time pattern register [15:0]This register defines MOD pattern.1 : Positive polarity0 : Negative polarityFor example,REG[340h] = 0x4REG[343-342h] = 0x0001 (i.e. b0001)Then the frame #1 is positive polarity, frame #2-4 are negative polarity. And such pattern willbe repeated for every 4 frames.Note(1)These bits are for passive LCD panels only.Solomon Systech Jul 2009 P 38/39 Rev 1.0SSD1926Application Note

LSHIFT signal start position Register 0REG[350h]Bit 7 6 5 4 3 2 1 0LSHIFTstartBit 7LSHIFTstartBit 6LSHIFTstartBit 5LSHIFTstartBit 4LSHIFTstartBit 3LSHIFTstartBit 2LSHIFTstartBit 1LSHIFTstartBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLSHIFT signal start position Register1REG[351h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LSHIFTstartBit 10LSHIFTstartBit 9LSHIFTstartBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateLSHIFT signal end position Register 0REG[354h]Bit 7 6 5 4 3 2 1 0LCD shiftendBit 7LCD shiftendBit 6LCD shiftendBit 5LCD shiftendBit 4LCD shiftendBit 3LCD shiftendBit 2LCD shiftendBit 1LCD shiftendBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLSHIFT signal end position Register1REG[355h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCD shiftendBit 10LCD shiftendBit 9LCD shiftendBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[351h] bits 1-0,REG[350h] bits 7-0REG[355h] bits 1-0,REG[354h] bits 7-0LSHIFT signal start position Register [10:0]These bits define the start position of LSHIFT within a line for active lcd signal.LSHIFT signal end position Register [10:0]These bit defines the end position of LSHIFT within a line for active lcd signal.If REG[351-350h] and REG[355-354h] are 0, LSHIFT will be enabled on the time (i.e. bothdisplay and non-display period).If REG[351-350h] and REG[355-354h] are not equal to 0, LSHIFT will be enabled within therange defined by start and end position within each line.The end position > The start positionFor example,Horizontal display period = 16Horizontal total = 24Horizontal period start = 4LSHIFT start = 3 and LSHIFT end = 20Then the LSHIFT will enabled between horizontal position pixel 3 and 20 within a line.SSD1926Application NoteRev 1.0 P 39/40 Jul 2009 Solomon Systech

2.6 Smart Panel Configuration RegistersTo operate with smart panel module, first is to enable the smart display (REG[250h] bit 5 = 1), then select theoperation mode (Write Through or Auto Reflesh Mode), panel type and panel interface (REG[260h] &REG[10h]). The maximum resolution for main smart panel is 2048 x 2048.Then next step is to configure the type of data to be transferred for Write Through Mode. Detail will becovered in section 2.6.1.Data transfer is initiated by writing data to REG[26Ch] and REG[26Dh] for Write Through Mode while bysetting REG[A0h] to enable the Auto Reflesh Mode of smart panel interface.2.6.1 Write Through ModeThere are three types of data for Write Through Mode:- Display pixel data- Command- Command argumentWrite Through Mode will send either pixel display data or command or command argument to the paneldriver at each time by issuing an enable pulse together with the 16-bit data or command.Table 2-9: Data type for parallel interface of all panel typesData TypeData / Command SelectionREG[26Eh] Bit 0Data / ArgumentSelectionREG[26Eh] Bit 7Command 0 xCommand Argument 1 0Pixel Data 1 12.6.1.1 Input FormatMCU data for Write Through mode are stored in REG[26Ch-26Dh]. Input data format from MCU in WriteThrough Mode as Table 2-10: Input data format for Write Through Mode.Table 2-10: Input data format for Write Through ModeInput Data Type Smart Display Input Data [15:0](REG[26Dh-26Ch])Command/Argument (8 bit)XXXXXXXXDDDDDDDDPixel Data (16bpp)RRRRRGGGGGGBBBBB2.6.1.2 Output FormatConsidering parallel output interface, only TFT will support 8-bit and 9-bit interface while CSTN and OLEDwill only have 8-bit interface (LCD_DATA8 will be 0). Refer to Table 2-11 for output data format of differentpanel interface.Solomon Systech Jul 2009 P 40/41 Rev 1.0SSD1926Application Note

Panel TypeTFTCSTNOLEDTable 2-11: Data output format for display pixel in Parallel interfaceParallel InterfaceWidthREG[260h] Bit 5Byte per pixelREG[261h] Bits 1-0Pixel DataDescription0 xx 2 transfersper pixel(18bpp)1 10 2 transfersperpixel(16bpp)1 11 3 transfersper pixel(18bpp)x 00 1 transfer perpixel (8bpp)x 01 3 transfersper 2 pixels(12bpp)x 10 2 transfersper pixel(16bpp)x 11 3 transfersper pixel(18bpp)x 00 1 transfer perpixel (8bpp)x 01 3 transfersper 2 pixels(12bpp)x 10 2 transfersper pixel(16bpp)x 11 3 transfersper pixel(18bpp)Parallel Pixel DataFormat(LCD_DATA[8:0])RRRRRRGGGGGGBBBBBBRRRRRGGG0GGGBBBBB0RRRRRR000GGGGGG000BBBBBB0000RRRGGGBB0RRRRGGGG0BBBBRRRR0GGGGBBBB0RRRRRGGG0GGGBBBBB0RRRRRR000GGGGGG000BBBBBB000RRRGGGBB0RRRRGGGG0BBBBRRRR0GGGGBBBB0RRRRRGGG0GGGBBBBB000RRRRRR000GGGGGG000BBBBBBPanelTypeTFT/CSTNOLEDTable 2-12: Data output format for 4-wire serial interface (REG[260h] Bit 6= 1)Output Data Type Byte per pixel Data Length Serial Output Format (SDA)REG[261h] Bits 1-0 per burstCommand/Argument xx 8 bit DDDDDDDDPixel (8bpp) 00 8 bit RRRGGGBBPixel (12bpp) 01 8 bit, 16 bit RRRRGGGG, BBBBRRRRGGGGBBBBPixel (16bpp) 10 16 bit RRRRRGGGGGGBBBBBPixel (18bpp) 11 24 bit RRRRRR00GGGGGG00BBBBBB00Command/Argument xx 8 bit DDDDDDDDPixel (8bpp) 00 8 bit RRRGGGBBPixel (12bpp) 01 8 bit, 16 bit RRRRGGGG BBBBRRRRGGGGBBBBPixel (16bpp) 10 16 bit RRRRRGGGGGGBBBBBPixel (18bpp) 11 24 bit 00RRRRRR00GGGGGG00BBBBBBSSD1926Application NoteRev 1.0 P 41/42 Jul 2009 Solomon Systech

Panel TypeTFT/CSTNOLEDTable 2-13: Data output format for 3-wire serial interface (REG[260h] Bit 6= 0)Output Data Byte per pixel Data Length Serial Output Format (SDA)TypeREG[261h] Bits 1-0 per burstCommand xx 9 bit 0DDDDDDDDArgument xx 9 bit 1DDDDDDDDPixel (8bpp) 00 9 bit 1RRRGGGBBPixel (12bpp) 01 9 bit, 18 bit 1RRRRGGGG, 1BBBBRRRR1GGGGBBBBPixel (16bpp) 10 18 bit 1RRRRRGGG1GGGBBBBBPixel (18bpp) 11 27 bit 1RRRRRR001GGGGGG001BBBBBB00Command xx 9 bit 0DDDDDDDDArgument xx 9 bit 1DDDDDDDDPixel (8bpp) 00 9 bit 1RRRGGGBBPixel (12bpp) 01 9 bit, 18 bit 1RRRRGGGG 1BBBBRRRR1GGGGBBBBPixel (16bpp) 10 18 bit 1RRRRRGGG1GGGBBBBBPixel (18bpp) 11 27 bit 100RRRRRR100GGGGGG100BBBBBB2.6.1.3 Auto Refresh ModeAuto Refresh Mode will accept 32-bit (32 bits per pixel or 16 bits per pixel) display data from displaymemory and transfer them to panel driver continuously.There is only display pixel data transfer (no command or argument transfer) for Auto Refresh Mode. So thereis no need to configure the data type.Before transfer the pixel data to smart panel, it should configure the panel parameter with REG[12h] -REG[13h], REG[18h]- REG[19h], REG[74h]- REG[76h], REG[78h]- REG[79h].The data input is set according to the format below in memory:Table 2-14: Data input format for Auto Refresh ModeBit per pixelData [31:0]REG[70h] Bits 2:0100 (16 bit per pixel) RRRRRGGGGGGBBBBBRRRRRGGGGGGBBBBB (2 pixels)101 (32 bit per pixel) RRRRRRRRGGGGGGGGBBBBBBBBXXXXXXXX (1 pixel)The output data format is as same as the output pixel data format in Write Through Mode.2.6.1.4 Output Interface TimingTable 2-15: Output Timing for 6800 Parallel interfaceSymbol Parameter Min Typ Max Unitt cycle Clock Cycle Time (write cycle) (note2) 2 - 36 Ts (note1)t CSL Chip Select Low Width (note3) 1 - 16 Tst CSH Chip Select High Width (note4) 3 - 20 Tst AS Address Setup Time - 1 - Tst AH Address Hold Time - 1 - Tst DS Data Setup Time (note5) 1 - 16 Tst DH Data Hold Time (note6) 3 - 20 TsSolomon Systech Jul 2009 P 42/43 Rev 1.0SSD1926Application Note

D / Ct ASt AHR / WCSt cycleEt CSLt CSHD 0 ~D 8t DSWValid Datat DHWFigure 2-16: 6800 Timing DiagramNote(1)Ts = 1/(MCLK frequency / 2 (REG[252h] bit 2-0) )(2)t cycle = t CSL + t CSH(3)t CSL = REG [270h] bit 3-0 + 1(4)t CSH = REG [271h] bit 3-0 + 1 + t during a burst ort CSH = REG [271h] bit 3-0 + 1 + t*2 at the end of the burst, t = 2(5)t DSW = t CSL(6)t DHW = t CSHTable 2-16: Output Timing for 8080 Parallel interfaceSymbol Parameter Min Typ Max Unitt cycle Clock Cycle Time (write cycle) (note2) 2 - 36 Ts (note1)t CSL Control Pulse Low Width (note3) 1 - 16 Tst CSH Control Pulse High Width (note4) 3 - 20 Tst AS Address Setup Time - 1 - Tst AH Address Hold Time - 1 - Tst DSW Data Setup Time (note5) 1 - 16 Tst DHW Data Hold Time (note6) 3 - 20 TsSSD1926Application NoteRev 1.0 P 43/44 Jul 2009 Solomon Systech

D / Ct ASt AHCSWRt CSLt cyclt CSHRDt DSWt DHWD 0 ~D 8Valid DataFigure 2-17: 8080 Timing DiagramNote(1)Ts = 1/(MCLK frequency / 2 (REG[252h] bit 2-0) )(2)t cycle = t CSL + t CSH(3)t CSL = REG [270h] bit 3-0 + 1(4)t CSH = REG [271h] bit 3-0 + 1 + t during a burst ort CSH = REG [271h] bit 3-0 + 1 + t*2 at the end of the burst, t = 2(5)t DSW = t CSL(6)t DHW = t CSHTable 2-17: Output Timing for Serial interfaceSymbol Parameter Min Typ Max Unitt cycle Clock Cycle Time (write cycle) (note2) 2 - 32 Ts (note1)t CLKL SCK Low Width (note3) 1 - 16 Tst CLKH SCK High Width (note4) 1 - 16 Tst CSS Chip Select Setup Time (note5) 2 - 17 Tst CSH Chip Select Hold Time (note6) 2 - 17 Tst DSW Data Setup Time (note7) 1 - 16 Tst DHW Data Hold Time (note8) 1 - 16 TsSolomon Systech Jul 2009 P 44/45 Rev 1.0SSD1926Application Note

D / CCSt CSSt CSHt cycleSCK (D 6)t CLKLt CLKHSDA(D 7)t DSWValid Datat DHWFigure 2-18: 4 Wires Timing DiagramCSt CSSt cycleSCK (D 6)t CLKLt CLKHt DHWSDA(D 7)t DSWD/CValid DataFigure 2-19: 3 Wires Timing DiagramNote(1)Ts = 1/(MCLK frequency / 2 (REG[252h] bit 2-0) )(2)t cycle = t CLKL + t CLKH(3)t CLKL = REG [263h] bit 3-0 + 1(4)t CLKH = REG [263h] bit 3-0 + 1(5)t CSS = REG [270h] bit 3-0 + 2(6)t CSH = REG [271h] bit 3-0 + 2(7)t DSW = t CLKL(8)t DHW = t CLKHSSD1926Application NoteRev 1.0 P 45/46 Jul 2009 Solomon Systech

Table 2-18: Register for smart panel interfaceRegister DescriptionSmart DisplayDisplay reset250h[7]Display EnableA0h[0]Smart Select Enable250h[5]Display mode [1] (YUV/RGB)1A4h[7:6]Display mode [0] (32/16 bpp) 70h[2:0] (1)Divide input clock source Ration [2:0]252h[2:0]Display horizontal panel size [7:0]13h[2:0] -12h[7:0]Display vertical panel size [7:0]19h[2:0] -18h[7:0]Display Operation Mode Selection260h[7]Serial Input Interface Width260h[6]Parallel Input Interface Width260h[5]Parallel/Serial Output Interface Selection [1:0]260h[3:2]Panel Type Selection [1:0] 10h[2:0] (2)Byte per pixel Bit [1:0]261h[1:0]Serial Clock divide ratio [3:0]263h[3:0]Hold count1 Bit [3:0]270h[3:0]Hold count2 Bit [3:0]271h[3:0]Display CSC Mode1A8h[7]Display Y Offset Registers [7:0]1A9h[7:0]Display CB Offset Registers [7:0]1AAh[7:0]Display CR Offset Registers [7:0]1ABh[7:0]Display Write Through Mode input data bit [15:8]26Ch[7:0]Display Write Through Mode input data bit [7:0]26Dh[7:0]Pixel data/Argument Selection26Eh[7]Data/Command Selection26Eh[0]Window Display Start Address Bit [7:0]74h[7:0]Window Display Start Address Bit [15:8]75h[7:0]Window Display Start Address Bit [16]76h[0]Window Line Address Offset Bit [7:0]78h[7:0]Window Line Address Offset Bit [9:8]79h[1:0]Display ready27Dh[0]Note(1)For Smart panel interface, 1/2/4/8/16/32 bit per pixel will be supported, 1/2/4/8 bpp will use lookup table.(2)REG[10h] bit 2 should be set to 1 to enable Smart panel interface.Smart Display Mode RegisterREG[250h]Bit 7 6 5 4 3 2 1 0Smart Reserved Smart Reserved Reserved Reserved Reserved ReservedDisplayresetSelectEnableType RW RW RW RO RO RO RW RWResetstate0 0 0 0 0 0 0 0REG [250h] Bit 7Smart Display Reset1 : Reset0 : Normal0 -> 1 : transmission stop immediately1 -> 0 : start transmission from beginning of display frameThis bit should be set to 0 before smart panel command send.Solomon Systech Jul 2009 P 46/47 Rev 1.0SSD1926Application Note

REG [250h] Bit 6REG [250h] Bit 5REG [250h] Bits 4-0Reserved bitsThese bits should be programmed by 0.Smart Enable1: Enable0 : DisableReserved bitsThese bits should be programmed by 0.Clock Divide RegisterREG[252h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Divideinput clocksourceRatio Bit 2Divideinput clocksourceRatio Bit 1Divideinput clocksourceRatio Bit 0Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG [252h] Bits 7-3 Reserved bitsThese bits should be programmed by 0.REG [252h] Bits 2-0 Divide input clock source ratio register [2:0]This register is used for both main and smart panel interface.REG[252h] bit 2:0Sub_CLK frequency = MCLK frequency / 2000 : MCLK divide by 1001 : MCLK divide by 2010 : MCLK divide by 4011 : MCLK divide by 8100 : MCLK divide by 16101 : MCLK divide by 3211x : reservedSmart Display Control RegisterREG[260h]Bit 7 6 5 4 3 2 1 0Smart panel Serial Parallel Reserved Output Output Reserved ReservedOperationModeSelectioninterfaceWidthInterfaceWidthInterfaceSelectionBit 1InterfaceSelectionBit 0Type RW RW RW RO RW RW RW RWResetstate0 0 0 0 0 0 0 0This register is used for both main and smart panel interface.REG [260h] Bit 7REG [260h] Bit 6Smart panel Operation Mode Selection register1 : Write-Through Mode0 : Auto-Refresh Mode0 -> 1 : Stop immediately1 -> 0 : continueSerial interface WidthDefine the width of serial interface mode1 : 4 wire serial interface0 : 3 wire serial interfaceSSD1926Application NoteRev 1.0 P 47/48 Jul 2009 Solomon Systech

REG [260h] Bit 5 Parallel Interface widthDefine the width of parallel interface for TFT1 : 8-bit parallel interface0 : 9-bit parallel interfaceNote(1)This bit is effective for 6800/8080 parallel TFT interface onlyREG [260h] Bit 4 Reserved bitThis bit should be programmed by 0REG [260h] Bits 3-2 Output Interface Selection bits [1:0]00 : 6800 parallel interface01 : 8080 parallel interface10 : serial interface11 : reservedREG [260h] Bits 1-0 Reserved bitThis bit should be programmed by 0Display Byte Per Pixel RegisterREG[261h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Byte perpixel Bit 1Byte perpixel Bit 0Type RO RO RO RO RO RO RW RWResetstate0 0 0 0 0 0 0 0Bit 4 Byte Per Pixel register [1:0]00 : 8 bits per pixel output color resolution01 : 12 bits per pixel output color resolution10 :16 bits per pixel output color resolution11 : 18 bits per pixel output color resolutionSerial Clock divide RegisterREG[263h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved SerialClockdivide ratioBit 3SerialClockdivide ratioBit 2SerialClockdivide ratioBit 1SerialClockdivide ratioBit 0Type RO RO RO RO RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-4Reserved bitsThese bits should be programmed by 0.Bits 3-0 Serial Clock divide register [3:0]This register is used for both main and smart panel interface.SCK frequency = Sub_CLK frequency / (REG[263h] * 2 +2)0000 : Sub_CLK divide by 20001 : Sub_CLK divide by 40010 : Sub_CLK divide by 60011 : Sub_CLK divide by 8…1101 : Sub_CLK divide by 281110 : Sub_CLK divide by 301111 : Sub_CLK divide by 32Solomon Systech Jul 2009 P 48/49 Rev 1.0SSD1926Application Note

SCK(s+1) Sub_CLK(s+1) Sub_CLKNote(1) Sub_CLK refer to REG[252h] bits 2-0(2) s : Serial clock divide value, REG[263h] bits 3-0Hold count for Count 1 RegisterREG[270h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Hold count2 Bit 3Hold count2 Bit 2Hold count2 Bit 1Hold count2 Bit 0Type RO RO RO RO RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-4Reserved bitsBits 3-0 Hold count register [3:0]If 6800 interface, Hold count for E high register [3:0]E will hold high for 1-16 extra clock cyclesIf 8080 interface, Hold count for WR low register [3:0]WR will hold low for 1-16 extra clock cyclesIf SPI interface, CS to SCK cycle count register [3:0]2-17 extra clock cycles for CS hold low before SCK startSmart Display Hold Count 2 RegisterREG[271h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Hold count Hold count Hold 1 Bit Hold 1Bit 01 Bit 3 1 Bit 2 1Type RO RO RO RO RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-4Reserved bitsBits 3-0 Hold count register [3:0]If 6800 interface, Hold count for E low register [3:0]E will hold low for 3-20 extra clock cyclesIf 8080 interface, Hold count for WR high register [3:0]WR will hold high for 3-20 extra clock cyclesIf SPI interface, SCK to CS cycle count register [3:0]2-17 extra clock cycles for SCK hold high before CS returnSSD1926Application NoteRev 1.0 P 49/50 Jul 2009 Solomon Systech

For 6800 interfaceECSDuring retrieval ofinternal buffer(t + h2 + 1) Sub_CLK (h1 + 1) Sub_CLK (t*2 + h2 + 1) Sub_CLKNote :t = 2Sub_CLK refer to REG[252] bits 2-0h1 : Hold count for Count 1, REG[270h] bits 3:0h2 : Hold count for Count 2, REG[271h] bits 3:0For 8080 interfaceWRCSDuring retrieval ofinternal buffer(t + h2 + 1) Sub_CLK (h1 + 1) Sub_CLK (t*2 + h2 + 1) Sub_CLKNote :t = 2Sub_CLK refer to REG[252] bits 2-0h1 : Hold count for Count 1, REG[270h] bits 3:0h2 : Hold count for Count 2, REG[271h] bits 3:0For SPI interfaceCSSCKStart of eachserial burstEnd of eachserial burst(h1 + 2) Sub_CLKNote :Sub_CLK refer to REG[252] bits 2-0h1 : Hold count for Count 1, REG[270h] bits 3:0h2 : Hold count for Count 2, REG[271h] bits 3:0(h2 + 2) Sub_CLKSolomon Systech Jul 2009 P 50/51 Rev 1.0SSD1926Application Note

Smart Display Write Through Mode input data Register 0REG[26Ch]Bit 7 6 5 4 3 2 1 0SmartDisplayWriteThroughMode inputdata Bit 7SmartDisplayWriteThroughMode inputdata Bit 6SmartDisplayWriteThroughMode inputdataBit 5SmartDisplayWriteThroughMode inputdata Bit 4SmartDisplayWriteThroughMode inputdata Bit 3SmartDisplayWriteThroughMode inputdata Bit 2SmartDisplayWriteThroughMode inputdata Bit 1SmartDisplayWriteThroughMode inputdata Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateSmart Display Write Through Mode input data Register 1REG[26Dh]Bit 7 6 5 4 3 2 1 0SmartDisplayWriteThroughMode inputdata Bit 15SmartDisplayWriteThroughMode inputdata Bit 14SmartDisplayWriteThroughMode inputdataBit 13SmartDisplayWriteThroughMode inputdata Bit 12SmartDisplayWriteThroughMode inputdata Bit 11SmartDisplayWriteThroughMode inputdata Bit 10SmartDisplayWriteThroughMode inputdata Bit 9SmartDisplayWriteThroughMode inputdata Bit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[26Dh] Bits 7-0REG[26Ch] Bits 7-0Write Through Mode input data register [15:0]NB : for byte access,Please update REG[26Ch], then REG[26Dh]Smart Display Output Data Format RegisterREG[26Eh]Bit 7 6 5 4 3 2 1 0Pixeldata/ArgumentSelectionReserved Reserved Reserved Reserved Reserved Reserved Data/CommandSelectionType RW RO RO RO RO RO RO RWReset 0 0 0 0 0 0 0 0stateREG[26Eh] Bit 7REG[26Eh] Bits 6-1REG[26Eh] Bit 0Pixel data/Argument Selection1 : Pixel Data0 : ArgumentNote :This bit is effective for Write Through mode only.Reserved bitsThese bits should be programmed by 0.Data/Command Selection1 : Data0 : CommandNote :This bit is effective for Write Through mode only.SSD1926Application NoteRev 1.0 P 51/52 Jul 2009 Solomon Systech

Smart Display Ready RegisterREG[27Dh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 SmartDisplayreadyType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[27Dh] Bit 0Smart Display ready register0 : idle1 : busy2.7 Interrupt RegistersInterrupt Status Flag RegisterREG[48h]Bit 7 6 5 4 3 2 1 0SDHC 0 I2C 0 0 JPEG DRAW2D ReservedInterruptStatus Flag0InterruptStatus Flag0InterruptStatus FlagInterruptStatus FlagType RW RW RW RO RO RW RW RResetstate0 0 0 0 0 0 0 0Bit 7Bits 6, 4, 3, 0Bit 5Bit 2Bit 1SDHC Interrupt Status FlagWhen this bit = 1, SDHC Interrupt Status detected. Write 1 to clear the status flag. Write 0 hasno hardware effect.When this bit = 0, SDHC Interrupt Status is not detected.Reserved bitsI2C Interrupt Status FlagWhen this bit = 1, I2C Interrupt Status detected. Write 1 to clear the status flag. Write 0 has nohardware effect.When this bit = 0, I2C Interrupt Status is not detected.JPEG Interrupt Status FlagWhen this bit = 1, JPEG Interrupt Status detected. Write 1 to clear the status flag. Write 0 hasno hardware effect.When this bit = 0, JPEG Interrupt Status is not detected.DRAW2D Interrupt Status FlagWhen this bit = 1, DRAW2D Interrupt Status detected. Write 1 to clear the status flag. Write 0has no hardware effect.When this bit = 0, DRAW2D Interrupt Status is not detected.Solomon Systech Jul 2009 P 52/53 Rev 1.0SSD1926Application Note

Interrupt Enable RegisterREG[4Ah]Bit 7 6 5 4 3 2 1 0SDHC 0 I2C 0 0 JPEG DRAW2D ReservedInterruptEnableInterruptEnableInterruptEnableInterruptEnableType RW RW RW RO RO RW RW ROResetstate0 0 0 0 0 0 0 0Bit 7Bits 6, 4, 3, 0Bit 5Bit 2Bit 1SDHC Interrupt EnableWhen this bit = 1, SDHC Interrupt Enable.When this bit = 0, SDHC Interrupt Disable.Reserved bitsThese bits should be programmed as 0I2C Interrupt EnableWhen this bit = 1, I2C Interrupt Enable.When this bit = 0, I2C Interrupt Disable.JPEG Interrupt EnableWhen this bit = 1, JPEG Interrupt Enable.When this bit = 0, JPEG Interrupt Disable.DRAW2D Interrupt EnableWhen this bit = 1, DRAW2D Interrupt Enable.When this bit = 0, DRAW2D Interrupt Disable.2.8 Power Up RegistersPower Saving Configuration RegisterREG[A0h]Bit 7 6 5 4 3 2 1 0VerticalNon-DisplayPeriodStatus0 0 MemoryControllerPowerSavingStatus BitDisplayPowerSavingStatus BitPowerSavingModeEnable Bit2PowerSavingModeEnable Bit1PowerSavingModeEnable Bit0Type RO NA RO RO RO RW RW RWReset 1 0 0 0 0 0 0 1stateBit 7Bits 6-5Bit 4Vertical Non-Display Period StatusWhen this bit = 0, the LCD panel is in Vertical Display Period.When this bit = 1, the LCD panel is in Vertical Non-Display Period.Reserved bitsMemory Controller Power Saving Status BitThis bit indicates the Power Saving status of the Main MemoryWhen this bit = 0, the Main memory is onWhen this bit = 1, the Main memory is offBit 3Display Power Saving Status BitThis bit indicates the Power Saving status of the Main displayWhen this bit = 0, the Main display is onWhen this bit = 1, the Main display is offBit 2 Power Saving Mode Enable Bit 2This bit control MCLK generationWhen this bit = 1, all MCLK will be off.When this bit = 0, all MCLK will be on.Bit 1 Power Saving Mode Enable Bit 1This bit control Display Memory ClockWhen this bit = 1, MCLK for display SRAM will be off.When this bit = 0, MCLK for display SRAM will be on.SSD1926Application NoteRev 1.0 P 53/54 Jul 2009 Solomon Systech

Bit 0 Power Saving Mode Enable Bit 0This bit control Main display power save mode.When this bit = 1, Power Saving mode is enabled.When this bit = 0, Power Saving mode is disabled.Note :Power saving mode sequence :Set power saving mode bit 0 = 1 -> check the display power saving status bit until = 1 -> Setpower saving mode bits 2:1 = 11Memory can not be access if bits 2:1 = 11Power save frame count RegisterREG[A1h]Bit 7 6 5 4 3 2 1 0Power saveframe countBit 7Power saveframe countBit 6Power saveframe countBit 5Power saveframe countBit 4Power saveframe countBit 3Power saveframe countBit 2Power saveframe countBit 1Power saveframe countBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-0 Power save frame count Bits [7:0]These bit control main panel switch count once power save is enabled (REG[A0h] bit 0 = 1).0 : Switch off immediatelyn : Switch off at the end of n – 1 framesSoftware Reset RegisterREG[A2h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 SoftwareResetType RW RW RW RW RW RW RW WOResetstate0 0 0 0 0 0 0 0Bit 0Software ResetWhen a one is written to this bit, the SSD1926 registers are reset. This bit has no effect on thecontents of the display buffer.Solomon Systech Jul 2009 P 54/55 Rev 1.0SSD1926Application Note

2.9 Display Mode RegistersSTN Color Depth Control RegisterREG[45h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved STN ColorDepthControl /FRC BitSelectBit 0Type NA NA NA NA RW RW RW RWReset 0 0 0 0 0 0 0 0stateBit 0STN Color Depth controlThis bit controls the maximum number of color available for STN panels.When this bit = 0, it allows maximum 32k color depth.When this bit = 1, it allows maximum 256k color depth.Refer Table 2-19: LCD Bit-per-pixel Selection for the color depth relationship.NoteThis register is effective for STN panel only (REG[10h] bits 2:0 = 000).This register can be reset by the RESET signal pin only.Dithering / FRC Control RegisterREG[50h]Bit 7 6 5 4 3 2 1 0DynamicDithering0 0 FRC SeedRotateReserved Reserved FRC PeriodSelect Bit 1FRC PeriodSelect Bit 0EnableEnableType RW NA NA RW RW RW RW RWResetstate0 0 0 0 0 0 1 0Bit 7Dynamic Dithering EnableThis bit will enable the dynamic dithering, the dithering mask will change after each 16 frames.When this bit = 0, dynamic dithering is disabled.When this bit = 1, dynamic dithering is enabled.Bit 4Bits 3, 2Bits 1:0NoteThis register is effective for both STN panel and dithering enabled (REG[10h] bits 2:0 = 000and REG[70h] bit 6 = 0).FRC Seed Rotate Enable1 – Enable0 – DisableReserved bitsThese bits should be programmed by 0.FRC Period Select00 – 14 frames01 – 15 frames10 – 16 frames11 – 17 framesSSD1926Application NoteRev 1.0 P 55/56 Jul 2009 Solomon Systech

Display Mode RegisterREG[70h]Bit 7 6 5 4 3 2 1 0DisplayBlankDitheringDisable0 SoftwareColorInvert0 Bit-perpixelSelectBit 2Bit-perpixelSelectBit 1Bit-perpixelSelectBit 0Type RW RW RW RW RO RW RW RWResetstate0 0 0 0 0 0 0 0Bit 7Bit 6Display BlankWhen this bit = 0, the LCD display output is enabled.When this bit = 1, the LCD display output is blank and all LCD data outputs are forced to zero(i.e., the screen is blanked).Dithering DisableSSD1926 use a combination of FRC and 4 pixel square formation dithering to achieve morecolors per pixel.In 256K mode (REG[45h] bit 0 = 1), the 4-bit MSB will be considered as FRC and the 2-bitLSB will be dithering. In the 32K mode (REG[45h] bit 0 = 0), the 3-bit MSB will be consideredas FRC, the next 2-bit MSB will be dithering and the last LSB will be neglected.When this bit = 0, dithering is enabled on the passive LCD panel. It allows maximum 64intensity levels for each color component (RGB).When this bit = 1, dithering is disabled on the passive LCD panel. It allows maximum 16intensity levels for each color component (RGB).Bits 5, 3Bit 4NoteThis bit does not refer to the number of simultaneously displayed colors but rather themaximum available colors (refer Table 2-19: LCD Bit-per-pixel Selection for the maximumnumber of displayed colors).Reserved bitsSoftware Color InvertWhen this bit = 0, display color is normal.When this bit = 1, display color is inverted.This bit has no effect if REG[70h] bit 7 = 1.NoteDisplay color is inverted after the Look-Up Table.Bits 2-0 Bit-per-pixel Select Bits [2:0]These bits select the color depth (bit-per-pixel) for the displayed data for both the main windowand the floating window (if active).Note1, 2, 4 and 8 bpp modes use three 8-bit LUTs, allowing maximum 256 colors. 16 and 32 bppmode bypasses the LUT, allowing 64K and 16M colors respectively.Bit-per-pixelSelect Bits [2:0]Color Depth(bpp)Table 2-19: LCD Bit-per-pixel SelectionMaximum Number of Colors/ShadesPassive Panel(Dithering On)TFT PanelREG[45h] REG[45h]Max. No. OfSimultaneouslyDisplayedColors/Shadesbit 0 = 0 bit 0 = 1000 1 bpp 32K/32 256K/64 256K/64 2/2001 2 bpp 32K/32 256K/64 256K/64 4/4010 4 bpp 32K/32 256K/64 256K/64 16/16011 8 bpp 32K/32 256K/64 256K/64 256/64100 16 bpp 32K/32 64K/64 64K/64 64K/64101 32 bpp 32K/32 256K/64 16M/256 16M/256110, 111 Reserved n/a n/a n/a n/aSolomon Systech Jul 2009 P 56/57 Rev 1.0SSD1926Application Note

TFT FRC Enable Bit RegisterREG[346h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved TFT FRCEnableBitType RO RO RO RO RO RO RO RWResetstate0 0 0 0 0 0 0 0REG[346h] bits 7-1REG[346h] bit 0Reserved bitsThese bits should be programmed by 0.TFT FRC Enable Bit RegisterSSD1926 use 2-bits Frame Rate Control (FRC) to achieve more colors for TFT. So 2 LSB areused for each RGB color component.TFT FRC will be enabled if this bit is set to 1.Note : This register is effective for 9/12/18 bit TFT only.2.10 Main Window RegistersMain Window Display Start Address Register 0REG[74h]Bit 7 6 5 4 3 2 1 0MainwindowDisplayStartAddressBit 7MainwindowDisplayStartAddressBit 6MainwindowDisplayStartAddressBit 5MainwindowDisplayStartAddressBit 4MainwindowDisplayStartAddressBit 3MainwindowDisplayStartAddressBit 2MainwindowDisplayStartAddressBit 1MainwindowDisplayStartAddressBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateMain Window Display Start Address Register 1REG[75h]Bit 7 6 5 4 3 2 1 0MainwindowDisplayStartAddressBit 15MainwindowDisplayStartAddressBit 14MainwindowDisplayStartAddressBit 13MainwindowDisplayStartAddressBit 12MainwindowDisplayStartAddressBit 11MainwindowDisplayStartAddressBit 10MainwindowDisplayStartAddressBit 9MainwindowDisplayStartAddressBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateMain Window Display Start Address Register 2REG[76h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 MainwindowDisplayStartAddressBit 16Type NA NA NA NA NA NA NA RWResetstate0 0 0 0 0 0 0 0SSD1926Application NoteRev 1.0 P 57/58 Jul 2009 Solomon Systech

REG[76h] bit 0,REG[75h] bits 7-0,REG[74h] bits 7-0Main Window Display Start Address Bits [16:0]These bits form the 17-bit address for the starting double-word of the LCD image in the displaybuffer for the main window.Note that this is a double-word (32-bit) address. An entry of 00000h into these registersrepresents the first double-word of display memory, an entry of 00001h represents the seconddouble-word of the display memory, and so on.Calculate the Display Start Address as follows :Main Window Display Start Address Bits 16:0= Image address ÷ 4 (valid only for Display Rotate Mode 0°)Note(1)For information on setting this register for other Display Rotate Mode, see Section “Display Rotate Mode” indatasheet.Main Window Line Address Offset Register 0REG[78h]Bit 7 6 5 4 3 2 1 0MainwindowLineAddressOffset Bit 7MainwindowLineAddressOffset Bit 6MainwindowLineAddressOffset Bit 5MainwindowLineAddressOffset Bit 4MainwindowLineAddressOffset Bit 3MainwindowLineAddressOffset Bit 2MainwindowLineAddressOffset Bit 1MainwindowLineAddressOffset Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateMain Window Line Address Offset Register 1REG[79h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 MainwindowLineAddressOffset Bit 9MainwindowLineAddressOffset Bit 8Type NA NA NA NA NA NA RW RWReset 0 0 0 0 0 0 0 0stateREG[79h] bits 1-0,REG[78h] bits 7-0Main Window Line Address Offset Bits [9:0]This register specifies the offset, in double words, from the beginning of one display line to thebeginning of the next display line in the main window. Note that this is a 32-bit addressincrement.Calculate the Line Address Offset as follows :Main Window Line Address Offset bits 9-0= Display Width in pixels ÷ (32 ÷ bpp)Note(1)A virtual display can be created by programming this register with a value greater than theformula requires. When a virtual display is created the image width is larger than the displaywidth and the displayed image becomes a window into the larger virtual image.Solomon Systech Jul 2009 P 58/59 Rev 1.0SSD1926Application Note

RGB Setting RegisterREG[1A4h]Bit 7 6 5 4 3 2 1 0Floating Main 0 0 0 0 0 0WindowRGBWindowRGBType RW RW RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bit 7Bit 6Bits 5-0Floating Window RGB1 : RGB0 : YUVMain Window RGB1 : RGB0 : YUVReserved bitsThese bits should be programmed by 0.2.11 Scratch bit RegistersScratch bit Register 0REG[A4h]Bit 7 6 5 4 3 2 1 0Scratch PadBit 7Scratch PadBit 6Scratch PadBit 5Scratch PadBit 4Scratch PadBit 3Scratch PadBit 2Scratch PadBit 1Scratch PadBit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Scratch bit Register 1REG[A5h]Bit 7 6 5 4 3 2 1 0Scratch PadBit 15Scratch PadBit 14Scratch PadBit 13Scratch PadBit 12Scratch PadBit 11Scratch PadBit 10Scratch PadBit 9Scratch PadBit 8Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[A5h] bits 7-0,REG[A4h] bits 7-0Scratch Pad Bits [15:0]This register contains general purpose read/write bits. These bits have no effect on hardwareconfiguration.2.12 General IO Pins RegistersGeneral Purpose I/O Pins Configuration Register 0REG[A8h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved GPIO4 I/O GPIO3 I/O GPIO2 I/O GPIO1 I/O GPIO0 I/OConfiguration Configuration Configuration Configuration ConfigurationType RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-5Bit 4Reserved bitsGPIO4 I/O ConfigurationWhen this bit = 0, GPIO4 is configured as an input pin.When this bit = 1, GPIO4 is configured as an output pin.SSD1926Application NoteRev 1.0 P 59/60 Jul 2009 Solomon Systech

Bit 3Bit 2Bit 1Bit 0GPIO3 I/O ConfigurationWhen this bit = 0, GPIO3 is configured as an input pin.When this bit = 1, GPIO3 is configured as an output pin.GPIO2 I/O ConfigurationWhen this bit = 0, GPIO2 is configured as an input pin.When this bit = 1, GPIO2 is configured as an output pin.GPIO1 I/O ConfigurationWhen this bit = 0, GPIO1 is configured as an input pin.When this bit = 1, GPIO1 is configured as an output pin.GPIO0 I/O ConfigurationWhen this bit = 0, GPIO0 is configured as an input pin.When this bit = 1, GPIO0 is configured as an output pin.Note(1)The input functions of the GPIO pins are not enabled until REG[A9h] bit 7 is set to 1.General Purpose IO Pins Configuration Register 1REG[A9h]Bit 7 6 5 4 3 2 1 0GPIO Pin 0 0 0 0 0 0 0InputEnableType RW RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bit 7GPIO Pin Input EnableThis bit is used to enable the input function of the GPIO[4:0] pins. It must be changed to a 1after power-on reset to enable the input function of the GPIO[4:0] pins.General Purpose IO Pins Status/Control RegisterREG[ACh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved GPIO4 PinIO StatusGPIO3 PinIO StatusGPIO2 PinIO StatusGPIO1 PinIO StatusGPIO0 PinIO StatusType RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-5Bit 4Bit 3Bit 2Bit 1Reserved bitsGPIO4 Pin IO StatusWhen GPIO4 is configured as an output, writing a 1 to this bit drives GPIO4 high and writing a0 to this bit drives GPIO4 low or controlled by LCD Gen4 (REG[334h]).When GPIO4 is configured as an input, a read from this bit returns the status of GPIO4.GPIO3 Pin IO StatusWhen GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and writing a0 to this bit drives GPIO3 low or controlled by LCD Gen3 (REG[333h]).When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3.GPIO2 Pin IO StatusWhen GPIO2 is configured as an output, writing a 1 to this bit drives GPIO2 high and writing a0 to this bit drives GPIO2 low or controlled by LCD Gen2 (REG[332h]).When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2.GPIO1 Pin IO StatusWhen GPIO1 is configured as an output, writing a 1 to this bit drives GPIO1 high and writing a0 to this bit drives GPIO1 low or controlled by LCD Gen1 (REG[331h]).When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1.Solomon Systech Jul 2009 P 60/61 Rev 1.0SSD1926Application Note

Bit 0GPIO0 Pin IO StatusWhen GPIO0 is configured as an output, writing a 1 to this bit drives GPIO0 high and writing a0 to this bit drives GPIO0 low or controlled by LCD Gen0 (REG[330h]).When GPIO0 is configured as an input, a read from this bit returns the status of GPIO0.Signal source1 for Gen xREG[330-334h]Signal 0-7REG[2B0-32Ch]Signal source2 for Gen xREG[330-334h]LCD Gen xConfig,REG[338h-33Ch]GPIO[4:0]OutputSignal source3 for Gen xREG[330-334h]GPIO[4:0]Outputsetting,REG[ACh]Figure 2-20: GPIO[4:0] output setupGeneral Purpose I/O (LDATA) Pins Configuration Register 0REG[AAh]Bit 7 6 5 4 3 2 1 0GPIO12(LDATA17)I/OConfigurationGPIO11(LDATA16)I/OConfigurationGPIO10(LDATA15)I/OConfigurationGPIO9(LDATA14)I/OConfigurationGPIO8(LDATA13) I/OConfigurationGPIO7(LDATA12) I/OConfigurationGPIO6(LDATA11) I/OConfigurationGPIO5(LDATA10) I/OConfigurationType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0GPIO12 (LDATA17) I/O ConfigurationWhen this bit = 0, GPIO12 (LDATA17) is configured as an input pin.When this bit = 1, GPIO12 (LDATA17) is configured as an output pin.GPIO11 (LDATA16) I/O ConfigurationWhen this bit = 0, GPIO11 (LDATA16) is configured as an input pin.When this bit = 1, GPIO11 (LDATA16) is configured as an output pin.GPIO10 (LDATA15) I/O ConfigurationWhen this bit = 0, GPIO10 (LDATA15) is configured as an input pin.When this bit = 1, GPIO10 (LDATA15) is configured as an output pin.GPIO9 (LDATA14) I/O ConfigurationWhen this bit = 0, GPIO9 (LDATA14) is configured as an input pin.When this bit = 1, GPIO9 (LDATA14) is configured as an output pin.GPIO8 (LDATA13) I/O ConfigurationWhen this bit = 0, GPIO8 (LDATA13) is configured as an input pin.When this bit = 1, GPIO8 (LDATA13) is configured as an output pin.GPIO7 (LDATA12) I/O ConfigurationWhen this bit = 0, GPIO7 (LDATA12) is configured as an input pin.When this bit = 1, GPIO7 (LDATA12) is configured as an output pin.GPIO6 (LDATA11) I/O ConfigurationWhen this bit = 0, GPIO6 (LDATA11) is configured as an input pin.When this bit = 1, GPIO6 (LDATA11) is configured as an output pin.GPIO5 (LDATA10) I/O ConfigurationWhen this bit = 0, GPIO5 (LDATA10) is configured as an input pin.When this bit = 1, GPIO5 (LDATA10) is configured as an output pin.Note(1) The input functions of the GPIO pins are not enabled until REG[ABh] bit 7 is set to 1.(2) This register is effective when the specified LDATA is not used for LCD interface.SSD1926Application NoteRev 1.0 P 61/62 Jul 2009 Solomon Systech

General Purpose IO (LDATA) Pins Configuration Register 1REG[ABh]Bit 7 6 5 4 3 2 1 0LDATA 0 0 0 0 0 0 0PinInputEnableType RW RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bit 7LDATA Pin Input EnableThis bit is used to enable the input function of the LDATA17:10 pins. It must be changed to a 1after power-on reset to enable the input function of the LDATA17:10 pins.Note(1) This register is effective when the specified LDATA is not used for LCD interface.General Purpose IO (LDATA) Pins Status/Control RegisterREG[AEh]Bit 7 6 5 4 3 2 1 0GPIO12(LDATA17) Pin IOStatusGPIO11(LDATA16) Pin IOStatusGPIO10(LDATA15) Pin IOStatusGPIO9(LDATA14) Pin IOStatusGPIO8(LDATA13) Pin IOStatusGPIO7(LDATA12) Pin IOStatusGPIO6(LDATA11) Pin IOStatusGPIO5(LDATA10) Pin IOStatusType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBit 7Bit 6Bit 5Bit 4Bit 3Bit 2GPIO12 (LDATA17) Pin IO StatusWhen GPIO12 (LDATA17) is configured as an output, writing a 1 to this bit drives GPIO12(LDATA17) high and writing a 0 to this bit drives GPIO11 (LDATA17) low.When GPIO12 (LDATA17) is configured as an input, a read from this bit returns the status ofGPIO12 (LDATA17).GPIO11 (LDATA16) Pin IO StatusWhen GPIO11 (LDATA16) is configured as an output, writing a 1 to this bit drives GPIO11(LDATA16) high and writing a 0 to this bit drives GPIO11 (LDATA16) low.When GPIO11 (LDATA16) is configured as an input, a read from this bit returns the status ofGPIO11 (LDATA16).GPIO10 (LDATA15) Pin IO StatusWhen GPIO10 (LDATA15) is configured as an output, writing a 1 to this bit drives GPIO10(LDATA15) high and writing a 0 to this bit drives LDATA15 low.When GPIO10 (LDATA15) is configured as an input, a read from this bit returns the status ofGPIO10 (LDATA15).GPIO9 (LDATA14) Pin IO StatusWhen GPIO9 (LDATA14) is configured as an output, writing a 1 to this bit drives GPIO9(LDATA14) high and writing a 0 to this bit drives GPIO9 (LDATA14) low.When GPIO9 (LDATA14) is configured as an input, a read from this bit returns the status ofGPIO9 (LDATA14).GPIO8 (LDATA13) Pin IO StatusWhen GPIO8 (LDATA13) is configured as an output, writing a 1 to this bit drives GPIO8(LDATA13) high and writing a 0 to this bit drives LDATA13 low.When GPIO8 (LDATA13) is configured as an input, a read from this bit returns the status ofGPIO8 (LDATA13).GPIO7 (LDATA12) Pin IO StatusWhen GPIO7 (LDATA12) is configured as an output, writing a 1 to this bit drives GPIO7(LDATA12) high and writing a 0 to this bit drives LDATA12 low.When GPIO7 (LDATA12) is configured as an input, a read from this bit returns the status ofGPIO7 (LDATA12).Solomon Systech Jul 2009 P 62/63 Rev 1.0SSD1926Application Note

Bit 1Bit 0GPIO6 (LDATA11) Pin IO StatusWhen GPIO6 (LDATA11) is configured as an output, writing a 1 to this bit drives GPIO6(LDATA11) high and writing a 0 to this bit drives LDATA11 low.When GPIO6 (LDATA11) is configured as an input, a read from this bit returns the status ofGPIO6 (LDATA11).GPIO5 (LDATA10) Pin IO StatusWhen GPIO5 (LDATA10) is configured as an output, writing a 1 to this bit drives GPIO5(LDATA10) high and writing a 0 to this bit drives LDATA10 low.When GPIO5 (LDATA10) is configured as an input, a read from this bit returns the status ofGPIO5 (LDATA10).Note(1) This register is effective when the specified LDATA is not used for LCD interface.LCD Power Control RegisterREG[ADh]Bit 7 6 5 4 3 2 1 0LPOWER 0 0 0 0 0 0 0ControlType RW NA NA NA NA NA NA NAResetstate0 0 0 0 0 0 0 0Bit 7LPOWER ControlThis bit controls the General Purpose Output pin.Writing a 0 to this bit drives LPOWER to low.Writing a 1 to this bit drives LPOWER to high.Note(1)Many implementations use the LPOWER pin to control the LCD bias power (see Section“LCD Power Sequencing” in datasheet).LCD Signal0 Rise Location Register 0REG[2B0h]Bit 7 6 5 4 3 2 1 0LCDSignal0RiseLocationBit 7LCDSignal0RiseLocationBit 6LCDSignal0RiseLocationBit 5LCDSignal0RiseLocationBit 4LCDSignal0RiseLocationBit 3LCDSignal0RiseLocationBit 2LCDSignal0RiseLocationBit 1LCDSignal0RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal0 0 Rise Location Register 1REG[2B1h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal0RiseLocationBit 10LCDSignal0RiseLocationBit 9LCDSignal0RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2B1h] bits 2-0,REG[2B0h] bits 7-0LCD Signal0 Rise position Register [10:0]This register define the lcd Signal0 rise position.SSD1926Application NoteRev 1.0 P 63/64 Jul 2009 Solomon Systech

LCD Signal0 Fall Location Register 0REG[2B4h]Bit 7 6 5 4 3 2 1 0LCDSignal0FallLocationBit 7LCDSignal0FallLocationBit 6LCDSignal0FallLocationBit 5LCDSignal0FallLocationBit 4LCDSignal0FallLocationBit 3LCDSignal0FallLocationBit 2LCDSignal0FallLocationBit 1LCDSignal0FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal0 Fall Location Register 1REG[2B5h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal0FallLocationBit 10LCDSignal0FallLocationBit 9LCDSignal0FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2B5h] bits 2-0,REG[2B4h] bits 7-0LCD Signal0 Fall position Register [10:0]This register define the lcd Signal0 Fall position.LCD Signal0 Period Location Register 0REG[2B8h]Bit 7 6 5 4 3 2 1 0LCDSignal0PeriodLocationBit 7LCDSignal0PeriodLocationBit 6LCDSignal0PeriodLocationBit 5LCDSignal0PeriodLocationBit 4LCDSignal0PeriodLocationBit 3LCDSignal0PeriodLocationBit 2LCDSignal0PeriodLocationBit 1LCDSignal0PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal0 Period Location Register 1REG[2B9h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal0PeriodLocationBit 10LCDSignal0PeriodLocationBit 9LCDSignal0PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2B9h] bits 2-0,REG[2B8h] bits 7-0LCD Signal0 Period position Register [10:0]This register define the lcd Signal0 Period position.Note(1)This register is ignored if toggle by frame (REG[2BCh] bit 1:0 = 11).Solomon Systech Jul 2009 P 64/65 Rev 1.0SSD1926Application Note

LCD Signal0 Control RegisterREG[2BCh]Bit 7 6 5 4 3 2 1 0LCDSignal0ResetBitLCDSignal0NDPOFFLCDSignal0Odd / EvenBit 1LCDSignal0Odd / EvenBit 0Reserved Reserved LCDSignal0ToggleBit 1LCDSignal0ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7Bit 6LCD Signal0 Reset RegisterThis LCD Signal0 will be under frame reset state when this reset bit is set to 1.LCD Signal0 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal0 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal0 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameLCD Signal1 Rise Location Register 0REG[2C0h]Bit 7 6 5 4 3 2 1 0LCDSignal1RiseLocationBit 7LCDSignal1RiseLocationBit 6LCDSignal1RiseLocationBit 5LCDSignal1RiseLocationBit 4LCDSignal1RiseLocationBit 3LCDSignal1RiseLocationBit 2LCDSignal1RiseLocationBit 1LCDSignal1RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal1 Rise Location Register 1REG[2C1h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal1RiseLocationBit 10LCDSignal1RiseLocationBit 9LCDSignal1RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2C1h] bits 2-0,REG[2C0h] bits 7-0LCD Signal1 Rise position Register [10:0]This register define the lcd Signal1 rise position.SSD1926Application NoteRev 1.0 P 65/66 Jul 2009 Solomon Systech

LCD Signal1 Fall Location Register 0REG[2C4h]Bit 7 6 5 4 3 2 1 0LCDSignal1 FallLocationBit 7LCDSignal1FallLocationBit 6LCDSignal1FallLocationBit 5LCDSignal1FallLocationBit 4LCDSignal1FallLocationBit 3LCDSignal1FallLocationBit 2LCDSignal1FallLocationBit 1LCDSignal1FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal1 Fall Location Register 1REG[2C5h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal1FallLocationBit 10LCDSignal1FallLocationBit 9LCDSignal1FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2C5h] bits 2-0,REG[2C4h] bits 7-0LCD Signal1 Fall position Register [10:0]This register define the lcd Signal1 Fall position.LCD Signal1 Period Location Register 0REG[2C8h]Bit 7 6 5 4 3 2 1 0LCDSignal1PeriodLocationBit 7LCDSignal1PeriodLocationBit 6LCDSignal1PeriodLocationBit 5LCDSignal1PeriodLocationBit 4LCDSignal1PeriodLocationBit 3LCDSignal1PeriodLocationBit 2LCDSignal1PeriodLocationBit 1LCDSignal1PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal1 Period Location Register 1REG[2C9h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal1PeriodLocationBit 10LCDSignal1PeriodLocationBit 9LCDSignal1PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2C9h] bits 2-0,REG[2C8h] bits 7-0LCD Signal1 Period position Register [10:0]This register define the lcd Signal1Period position.Note(1)This register is ignored if toggle by frame (REG[2CCh] bit 1:0 = 11).Solomon Systech Jul 2009 P 66/67 Rev 1.0SSD1926Application Note

LCD Signal1 Control RegisterREG[2CCh]Bit 7 6 5 4 3 2 1 0LCDSignal1ResetBitLCDSignal1NDPOFFLCDSignal1Odd / EvenBit 1LCDSignal1Odd / EvenBit 0Reserved Reserved LCDSignal1ToggleBit 1LCDSignal1ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7Bit 6LCD Signal1 Reset RegisterThis LCD Signal1 will be under reset state when this reset bit is set to 1.LCD Signal1 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal1 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal1 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameLCD Signal2 Rise Location Register 0REG[2D0h]Bit 7 6 5 4 3 2 1 0LCDSignal2RiseLocationBit 7LCDSignal2RiseLocationBit 6LCDSignal2RiseLocationBit 5LCDSignal2RiseLocationBit 4LCDSignal2RiseLocationBit 3LCDSignal2RiseLocationBit 2LCDSignal2RiseLocationBit 1LCDSignal2RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal2 0 Rise Location Register 1REG[2D1h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal2RiseLocationBit 10LCDSignal2RiseLocationBit 9LCDSignal2RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2D1h] bits 2-0,REG[2D0h] bits 7-0LCD Signal2 Rise position Register [10:0]This register define the lcd Signal2 rise position.SSD1926Application NoteRev 1.0 P 67/68 Jul 2009 Solomon Systech

LCD Signal2 Fall Location Register 0REG[2D4h]Bit 7 6 5 4 3 2 1 0LCDSignal2FallLocationBit 7LCDSignal2FallLocationBit 6LCDSignal2FallLocationBit 5LCDSignal2FallLocationBit 4LCDSignal2FallLocationBit 3LCDSignal2FallLocationBit 2LCDSignal2FallLocationBit 1LCDSignal2FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal2 Fall Location Register 1REG[2D5h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal2FallLocationBit 10LCDSignal2FallLocationBit 9LCDSignal2FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2D5h] bits 2-0,REG[2D4h] bits 7-0LCD Signal2 Fall position Register [10:0]This register define the lcd Signal2 Fall position.LCD Signal2 Period Location Register 0REG[2D8h]Bit 7 6 5 4 3 2 1 0LCDSignal2PeriodLocationBit 7LCDSignal2PeriodLocationBit 6LCDSignal2PeriodLocationBit 5LCDSignal2PeriodLocationBit 4LCDSignal2PeriodLocationBit 3LCDSignal2PeriodLocationBit 2LCDSignal2PeriodLocationBit 1LCDSignal2PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal2 Period Location Register 1REG[2D9h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal2PeriodLocationBit 10LCDSignal2PeriodLocationBit 9LCDSignal2PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2D9h] bits 2-0,REG[2D8h] bits 7-0LCD Signal2 Period position Register [10:0]This register define the lcd Signal2 Period position.Note(1)This register is ignored if toggle by frame (REG[2DCh] bit 1:0 = 11).Solomon Systech Jul 2009 P 68/69 Rev 1.0SSD1926Application Note

LCD Signal2 Control RegisterREG[2DCh]Bit 7 6 5 4 3 2 1 0LCDSignal2ResetBitLCDSignal2NDPOFFLCDSignal2Odd / EvenBit 1LCDSignal2Odd / EvenBit 0Reserved Reserved LCDSignal2ToggleBit 1LCDSignal2ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7LCD Signal2 Reset RegisterThis LCD Signal2 will be under reset state when this reset bit is set to 1.Bit 6LCD Signal2 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal2 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal2 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameLCD Signal3 Rise Location Register 0REG[2E0h]Bit 7 6 5 4 3 2 1 0LCDSignal3RiseLocationBit 7LCDSignal3RiseLocationBit 6LCDSignal3RiseLocationBit 5LCDSignal3RiseLocationBit 4LCDSignal3RiseLocationBit 3LCDSignal3RiseLocationBit 2LCDSignal3RiseLocationBit 1LCDSignal3RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal3 0 Rise Location Register 1REG[2E1h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal3RiseLocationBit 10LCDSignal3RiseLocationBit 9LCDSignal3RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2E1h] bits 2-0,REG[2E0h] bits 7-0LCD Signal3 Rise position Register [10:0]This register define the lcd Signal3 rise position.SSD1926Application NoteRev 1.0 P 69/70 Jul 2009 Solomon Systech

LCD Signal3 Fall Location Register 0REG[2E4h]Bit 7 6 5 4 3 2 1 0LCDSignal3FallLocationBit 7LCDSignal3FallLocationBit 6LCDSignal3FallLocationBit 5LCDSignal3FallLocationBit 4LCDSignal3FallLocationBit 3LCDSignal3FallLocationBit 2LCDSignal3FallLocationBit 1LCDSignal3FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal3 Fall Location Register 1REG[2E5h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal3FallLocationBit 10LCDSignal3FallLocationBit 9LCDSignal3FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2E5h] bits 2-0,REG[2E4h] bits 7-0LCD Signal3 Fall position Register [10:0]This register define the lcd Signal3 fall location.LCD Signal3 Period Location Register 0REG[2E8h]Bit 7 6 5 4 3 2 1 0LCDSignal3PeriodLocationBit 7LCDSignal3PeriodLocationBit 6LCDSignal3PeriodLocationBit 5LCDSignal3PeriodLocationBit 4LCDSignal3PeriodLocationBit 3LCDSignal3PeriodLocationBit 2LCDSignal3PeriodLocationBit 1LCDSignal3PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal3 Period Location Register 1REG[2E9h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal3PeriodLocationBit 10LCDSignal3PeriodLocationBit 9LCDSignal3PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2E9h] bits 2-0,REG[2E8h] bits 7-0LCD Signal3 Period position Register [10:0]This register define the lcd Signal3 Period position.Note(1)This register is ignored if toggle by frame (REG[2ECh] bit 1:0 = 11).Solomon Systech Jul 2009 P 70/71 Rev 1.0SSD1926Application Note

LCD Signal3 Control RegisterREG[2ECh]Bit 7 6 5 4 3 2 1 0LCDSignal3ResetBitLCDSignal3NDPOFFLCDSignal3Odd / EvenBit 1LCDSignal3Odd / EvenBit 0Reserved Reserved LCDSignal3ToggleBit 1LCDSignal3ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7LCD Signal3 Reset RegisterThis LCD Signal3 will be under reset state when this reset bit is set to 1.Bit 6LCD Signal3 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal3 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal3 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameLCD Signal4 Rise Location Register 0REG[2F0h]Bit 7 6 5 4 3 2 1 0LCDSignal4RiseLocationBit 7LCDSignal4RiseLocationBit 6LCDSignal4RiseLocationBit 5LCDSignal4RiseLocationBit 4LCDSignal4RiseLocationBit 3LCDSignal4RiseLocationBit 2LCDSignal4RiseLocationBit 1LCDSignal4RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal4 Rise Location Register 1REG[2F1h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal4RiseLocationBit 10LCDSignal4RiseLocationBit 9LCDSignal4RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2F1h] bits 2-0,REG[2F0h] bits 7-0LCD Signal4 Rise position Register [10:0]This register define the lcd Signal4 rise position.SSD1926Application NoteRev 1.0 P 71/72 Jul 2009 Solomon Systech

LCD Signal4 Fall Location Register 0REG[2F4h]Bit 7 6 5 4 3 2 1 0LCDSignal4FallLocationBit 7LCDSignal4FallLocationBit 6LCDSignal4FallLocationBit 5LCDSignal4FallLocationBit 4LCDSignal4FallLocationBit 3LCDSignal4FallLocationBit 2LCDSignal4FallLocationBit 1LCDSignal4FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal4 Fall Location Register 1REG[2F5h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal4FallLocationBit 10LCDSignal4FallLocationBit 9LCDSignal4FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2F5h] bits 2-0,REG[2F4h] bits 7-0LCD Signal4 Fall position Register [10:0]This register define the lcd Signal4 Fall position.LCD Signal4 Period Location Register 0REG[2F8h]Bit 7 6 5 4 3 2 1 0LCDSignal4PeriodLocationBit 7LCDSignal4PeriodLocationBit 6LCDSignal4PeriodLocationBit 5LCDSignal4PeriodLocationBit 4LCDSignal4PeriodLocationBit 3LCDSignal4PeriodLocationBit 2LCDSignal4PeriodLocationBit 1LCDSignal4PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal4 Period Location Register 1REG[2F9h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal4PeriodLocationBit 10LCDSignal4PeriodLocationBit 9LCDSignal4PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[2F9h] bits 2-0,REG[2F8h] bits 7-0LCD Signal4 Period position Register [10:0]This register define the lcd Signal4 Period position.Note(1)This register is ignored if toggle by frame (REG[2FCh] bit 1:0 = 11).Solomon Systech Jul 2009 P 72/73 Rev 1.0SSD1926Application Note

LCD Signal4 Control RegisterREG[2FCh]Bit 7 6 5 4 3 2 1 0LCDSignal4ResetBitLCDSignal4NDPOFFLCDSignal4Odd / EvenBit 1LCDSignal4Odd / EvenBit 0Reserved Reserved LCDSignal4ToggleBit 1LCDSignal4ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7LCD Signal4 Reset RegisterThis LCD Signal4will be under reset state when this reset bit is set to 1.Bit 6LCD Signal4 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal4 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal4 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameLCD Signal5 Rise Location Register 0REG[300h]Bit 7 6 5 4 3 2 1 0LCDSignal5RiseLocationBit 7LCDSignal5RiseLocationBit 6LCDSignal5RiseLocationBit 5LCDSignal5RiseLocationBit 4LCDSignal5RiseLocationBit 3LCDSignal5RiseLocationBit 2LCDSignal5RiseLocationBit 1LCDSignal5RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal5 Rise Location Register 1REG[301h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal5RiseLocationBit 10LCDSignal5RiseLocationBit 9LCDSignal5RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[301h] bits 2-0,REG[300h] bits 7-0LCD Signal5 Rise position Register [10:0]This register define the lcd Signal5 rise position.SSD1926Application NoteRev 1.0 P 73/74 Jul 2009 Solomon Systech

LCD Signal5 Fall Location Register 0REG[304h]Bit 7 6 5 4 3 2 1 0LCDSignal5FallLocationBit 7LCDSignal5FallLocationBit 6LCDSignal5FallLocationBit 5LCDSignal5FallLocationBit 4LCDSignal5FallLocationBit 3LCDSignal5FallLocationBit 2LCDSignal5FallLocationBit 1LCDSignal5FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal5 Fall Location Register 1REG[305h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal5FallLocationBit 10LCDSignal5FallLocationBit 9LCDSignal5FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[305h] bits 2-0,REG[304h] bits 7-0LCD Signal5 Fall position Register [10:0]This register define the lcd Signal5 Fall position.LCD Signal5 Period Location Register 0REG[308h]Bit 7 6 5 4 3 2 1 0LCDSignal5PeriodLocationBit 7LCDSignal5PeriodLocationBit 6LCDSignal5PeriodLocationBit 5LCDSignal5PeriodLocationBit 4LCDSignal5PeriodLocationBit 3LCDSignal5PeriodLocationBit 2LCDSignal5PeriodLocationBit 1LCDSignal5PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal5 Period Location Register 1REG[309h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal5PeriodLocationBit 10LCDSignal5PeriodLocationBit 9LCDSignal5PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[309h] bits 2-0,REG[308h] bits 7-0LCD Signal5 Period position Register [10:0]This register define the lcd Signal5 Period position.Note(1)This register is ignored if toggle by frame (REG[30Ch] bit 1:0 = 11).Solomon Systech Jul 2009 P 74/75 Rev 1.0SSD1926Application Note

LCD Signal5 Control RegisterREG[30Ch]Bit 7 6 5 4 3 2 1 0LCDSignal5ResetBitLCDSignal5NDPOFFLCDSignal5Odd / EvenBit 1LCDSignal5Odd / EvenBit 0Reserved Reserved LCDSignal5ToggleBit 1LCDSignal5ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7LCD Signal5 Reset RegisterThis LCD Signal5 will be under reset state when this reset bit is set to 1.Bit 6LCD Signal5 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal5 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal5 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameLCD Signal6 Rise Location Register 0REG[310h]Bit 7 6 5 4 3 2 1 0LCDSignal6RiseLocationBit 7LCDSignal6RiseLocationBit 6LCDSignal6RiseLocationBit 5LCDSignal6RiseLocationBit 4LCDSignal6RiseLocationBit 3LCDSignal6RiseLocationBit 2LCDSignal6RiseLocationBit 1LCDSignal6RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal6 0 Rise Location Register 1REG[311h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal6RiseLocationBit 10LCDSignal6RiseLocationBit 9LCDSignal6RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[311h] bits 2-0,REG[310h] bits 7-0LCD Signal6 Rise position Register [10:0]This register define the lcd Signal6 rise position.SSD1926Application NoteRev 1.0 P 75/76 Jul 2009 Solomon Systech

LCD Signal6 Fall Location Register 0REG[314h]Bit 7 6 5 4 3 2 1 0LCDSignal6FallLocationBit 7LCDSignal6FallLocationBit 6LCDSignal6FallLocationBit 5LCDSignal6FallLocationBit 4LCDSignal6FallLocationBit 3LCDSignal6FallLocationBit 2LCDSignal6FallLocationBit 1LCDSignal6FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal6 Fall Location Register 1REG[315h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal6FallLocationBit 10LCDSignal6FallLocationBit 9LCDSignal6FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[315h] bits 2-0,REG[314h] bits 7-0LCD Signal6 Fall position Register [10:0]This register define the lcd Signal6 Fall position.LCD Signal6 Period Location Register 0REG[318h]Bit 7 6 5 4 3 2 1 0LCDSignal6PeriodLocationBit 7LCDSignal6PeriodLocationBit 6LCDSignal6PeriodLocationBit 5LCDSignal6PeriodLocationBit 4LCDSignal6PeriodLocationBit 3LCDSignal6PeriodLocationBit 2LCDSignal6PeriodLocationBit 1LCDSignal6PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal6 Period Location Register 1REG[319h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal6PeriodLocationBit 10LCDSignal6PeriodLocationBit 9LCDSignal6PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[319h] bits 2-0,REG[318h] bits 7-0LCD Signal6 Period position Register [10:0]This register define the lcd Signal6 Period position.Note(1)This register is ignored if toggle by frame (REG[31Ch] bit 1:0 = 11).Solomon Systech Jul 2009 P 76/77 Rev 1.0SSD1926Application Note

LCD Signal6 Control RegisterREG[31Ch]Bit 7 6 5 4 3 2 1 0LCDSignal6ResetBitLCDSignal6NDPOFFLCDSignal6Odd / EvenBit 1LCDSignal6Odd / EvenBit 0Reserved Reserved LCDSignal6ToggleBit 1LCDSignal6ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7LCD Signal6 Reset RegisterThis LCD Signal6 will be under reset state when this reset bit is set to 1.Bit 6LCD Signal6 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal6 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal6 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameLCD Signal7 Rise Location Register 0REG[320h]Bit 7 6 5 4 3 2 1 0LCDSignal7RiseLocationBit 7LCDSignal7RiseLocationBit 6LCDSignal7RiseLocationBit 5LCDSignal7RiseLocationBit 4LCDSignal7RiseLocationBit 3LCDSignal7RiseLocationBit 2LCDSignal7RiseLocationBit 1LCDSignal7RiseLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal7 0 Rise Location Register 1REG[321h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal7RiseLocationBit 10LCDSignal7RiseLocationBit 9LCDSignal7RiseLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[321h] bits 2-0,REG[320h] bits 7-0LCD Signal7 Rise position Register [10:0]This register define the lcd Signal7 rise position.SSD1926Application NoteRev 1.0 P 77/78 Jul 2009 Solomon Systech

LCD Signal7 Fall Location Register 0REG[324h]Bit 7 6 5 4 3 2 1 0LCDSignal7FallLocationBit 7LCDSignal7FallLocationBit 6LCDSignal7FallLocationBit 5LCDSignal7FallLocationBit 4LCDSignal7FallLocationBit 3LCDSignal7FallLocationBit 2LCDSignal7FallLocationBit 1LCDSignal7FallLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal7 Fall Location Register 1REG[325h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal7FallLocationBit 10LCDSignal7FallLocationBit 9LCDSignal7FallLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[325h] bits 2-0,REG[324h] bits 7-0LCD Signal7 Fall position Register [10:0]This register define the lcd Signal7 Fall position.LCD Signal7 Period Location Register 0REG[328h]Bit 7 6 5 4 3 2 1 0LCDSignal7PeriodLocationBit 7LCDSignal7PeriodLocationBit 6LCDSignal7PeriodLocationBit 5LCDSignal7PeriodLocationBit 4LCDSignal7PeriodLocationBit 3LCDSignal7PeriodLocationBit 2LCDSignal7PeriodLocationBit 1LCDSignal7PeriodLocationBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateLCD Signal7 Period Location Register 1REG[329h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved LCDSignal7PeriodLocationBit 10LCDSignal7PeriodLocationBit 9LCDSignal7PeriodLocationBit 8Type RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[329h] bits 2-0,REG[328h] bits 7-0LCD Signal7 Period position Register [10:0]This register define the lcd Signal7 Period position.Note(1)This register is ignored if toggle by frame (REG[32Ch] bit 1:0 = 11).Solomon Systech Jul 2009 P 78/79 Rev 1.0SSD1926Application Note

LCD Signal7 Control RegisterREG[32Ch]Bit 7 6 5 4 3 2 1 0LCDSignal7ResetBitLCDSignal7NDPOFFLCDSignal7Odd / EvenBit 1LCDSignal7Odd / EvenBit 0Reserved Reserved LCDSignal7ToggleBit 1LCDSignal7ToggleBit 0Type RW RW RW RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateBit 7LCD Signal7 Reset RegisterThis LCD Signal7 will be under reset state when this reset bit is set to 1.Bit 6LCD Signal7 NDPOFFThis bit enables signal output in non-display period.0 : enable signal in non-display period1 : disable signal in non-display periodNote(1)This bit effective only when LCD signal toggle by PCLK.Bits 5-4 LCD Singal7 Odd / Even [1:0]These bits enable signal output in odd or even lines00/11 : enable signal in all lines01 : enable signal in even lines10 : enable signal in odd linesNote(1)These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.Bits 3-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 LCD Signal7 Toggle Register [1:0]00 : Disable01 : toggle by PCLK10 : toggle by Line11 : toggle by FrameVDPLFRAMELine 0 Line 1 Line 2 Line 3LLINENDPOFF=0ODD/EVEN = 00SignalxNDPOFF=1ODD/EVEN = 00/11NDPOFF=1ODD/EVEN = 01NDPOFF=1ODD/EVEN = 10Assume VDP = 4Figure 2-21: Examples for LCD signalx by NDPOFF and ODD / Even bitsSSD1926Application NoteRev 1.0 P 79/80 Jul 2009 Solomon Systech

LCD Gen0 Configure RegisterREG[330h]Bit 7 6 5 4 3 2 1 0LCD SignalSelect forsource 1Bit 2LCD SignalSelect forsource 1Bit 1LCD SignalSelect forsource 1Bit 0LCD SignalSelect forsource 2Bit 2LCD SignalSelect forsource 2Bit 1LCD SignalSelect forsource 2Bit 0LCD SignalSelect forsource 3Bit 1LCD SignalSelect forsource 3Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-5 LCD Signal Select for source 1 Register [2:0]This register select signal generator for source 1.Bits 4-2 LCD Signal Select for source 2 Register [2:0]This register select signal generator for source 2.Bits 1-0 LCD Signal Select for source 3 Register [1:0]This register select signal generator for source 3.LCD Gen1 Configure RegisterREG[331h]Bit 7 6 5 4 3 2 1 0LCD SignalSelect forsource 1Bit 2LCD SignalSelect forsource 1Bit 1LCD SignalSelect forsource 1Bit 0LCD SignalSelect forsource 2Bit 2LCD SignalSelect forsource 2Bit 1LCD SignalSelect forsource 2Bit 0LCD SignalSelect forsource 3Bit 1LCD SignalSelect forsource 3Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-5 LCD Signal Select for source 1 Register [2:0]This register select signal generator for source 1.Bits 4-2 LCD Signal Select for source 2 Register [2:0]This register select signal generator for source 2.Bits 1-0 LCD Signal Select for source 3 Register [1:0]This register select signal generator for source 3.LCD Gen2 Configure RegisterREG[332h]Bit 7 6 5 4 3 2 1 0LCD SignalSelect forsource 1Bit 2LCD SignalSelect forsource 1Bit 1LCD SignalSelect forsource 1Bit 0LCD SignalSelect forsource 2Bit 2LCD SignalSelect forsource 2Bit 1LCD SignalSelect forsource 2Bit 0LCD SignalSelect forsource 3Bit 1LCD SignalSelect forsource 3Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-5 LCD Signal Select for source 1 Register [2:0]This register select signal generator for source 1.Bits 4-2 LCD Signal Select for source 2 Register [2:0]This register select signal generator for source 2.Bits 1-0 LCD Signal Select for source 3 Register [1:0]This register select signal generator for source 3.Solomon Systech Jul 2009 P 80/81 Rev 1.0SSD1926Application Note

LCD Gen3 Configure RegisterREG[333h]Bit 7 6 5 4 3 2 1 0LCD SignalSelect forsource 1Bit 2LCD SignalSelect forsource 1Bit 1LCD SignalSelect forsource 1Bit 0LCD SignalSelect forsource 2Bit 2LCD SignalSelect forsource 2Bit 1LCD SignalSelect forsource 2Bit 0LCD SignalSelect forsource 3Bit 1LCD SignalSelect forsource 3Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-5 LCD Signal Select for source 1 Register [2:0]This register select signal generator for source 1.Bits 4-2 LCD Signal Select for source 2 Register [2:0]This register select signal generator for source 2.Bits 1-0 LCD Signal Select for source 3 Register [1:0]This register select signal generator for source 3.LCD Gen4 Configure RegisterREG[334h]Bit 7 6 5 4 3 2 1 0LCD SignalSelect forsource 1Bit 2LCD SignalSelect forsource 1Bit 1LCD SignalSelect forsource 1Bit 0LCD SignalSelect forsource 2Bit 2LCD SignalSelect forsource 2Bit 1LCD SignalSelect forsource 2Bit 0LCD SignalSelect forsource 3Bit 1LCD SignalSelect forsource 3Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-5 LCD Signal Select for source 1 Register [2:0]This register select signal generator for source 1.Bits 4-2 LCD Signal Select for source 2 Register [2:0]This register select signal generator for source 2.Bits 1-0 LCD Signal Select for source 3 Register [1:0]This register select signal generator for source 3.LCD Gen0 ROP Configure RegisterREG[338h]Bit 7 6 5 4 3 2 1 0LCD Gen0ConfigureBit 7LCD Gen0ConfigureBit 6LCD Gen0ConfigureBit 5LCD Gen0ConfigureBit 4LCD Gen0ConfigureBit 3LCD Gen0ConfigureBit 2LCD Gen0ConfigureBit 1LCD Gen0ConfigureBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-0 LCD Gen0 ROP Configure Register [1:0]This register configures signal generator operation for source 1, 2 and 3LCD Gen1 ROP Configure RegisterREG[339h]Bit 7 6 5 4 3 2 1 0LCD Gen1ConfigureBit 7LCD Gen1ConfigureBit 6LCD Gen1ConfigureBit 5LCD Gen1ConfigureBit 4LCD Gen1ConfigureBit 3LCD Gen1ConfigureBit 2LCD Gen1ConfigureBit 1LCD Gen1ConfigureBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-0 LCD Gen1 ROP Configure Register [1:0]This register configures signal generator operation for source 1, 2 and 3SSD1926Application NoteRev 1.0 P 81/82 Jul 2009 Solomon Systech

LCD Gen2 ROP Configure RegisterREG[33Ah]Bit 7 6 5 4 3 2 1 0LCD Gen2ConfigureBit 7LCD Gen2ConfigureBit 6LCD Gen2ConfigureBit 5LCD Gen2ConfigureBit 4LCD Gen2ConfigureBit 3LCD Gen2ConfigureBit 2LCD Gen2ConfigureBit 1LCD Gen2ConfigureBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-0 LCD Gen2 ROP Configure Register [1:0]This register configures signal generator operation for source 1, 2 and 3LCD Gen3 ROP Configure RegisterREG[33Bh]Bit 7 6 5 4 3 2 1 0LCD Gen3ConfigureBit 7LCD Gen3ConfigureBit 6LCD Gen3ConfigureBit 5LCD Gen3ConfigureBit 4LCD Gen3ConfigureBit 3LCD Gen3ConfigureBit 2LCD Gen3ConfigureBit 1LCD Gen3ConfigureBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-0 LCD Gen3 ROP Configure Register [1:0]This register configures signal generator operation for source 1, 2 and 3LCD Gen4 ROP Configure RegisterREG[33Ch]Bit 7 6 5 4 3 2 1 0LCD Gen4ConfigureBit 7LCD Gen4ConfigureBit 6LCD Gen4ConfigureBit 5LCD Gen4ConfigureBit 4LCD Gen4ConfigureBit 3LCD Gen4ConfigureBit 2LCD Gen4ConfigureBit 1LCD Gen4ConfigureBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-0 LCD Gen4 ROP Configure Register [1:0]This register configures signal generator operation for source 1, 2 and 3Note(1)Refer to WindowCE for the detailed Raster Operation (ROP).Solomon Systech Jul 2009 P 82/83 Rev 1.0SSD1926Application Note

2.13 2D Engine RegistersSpecial Effects RegisterREG[71h]Bit 7 6 5 4 3 2 1 0DisplayDataWord SwapDisplayDataByte Swap0 FloatingWindowEnable0 DisplayMirrorModeDisplayRotateModeSelectBit 1Type RW RW RO RW RO RO RW RWReset 0 0 0 0 0 0 0 0stateDisplayRotateModeSelectBit 0Bit 7Bit 6Display Data Word SwapThe display pipe fetches 32-bit of data from the display buffer. This bit enables the lower 16-bitword and the upper 16-bit word to be swapped before sending them to the LCD display. If theDisplay Data Byte Swap bit is also enabled, then the byte order of the fetched 32-bit data isreversed.Display Data Byte SwapThe display pipe fetches 32-bit of data from the display buffer. This bit enables swapping ofbyte 0 and byte 1, byte 2 and byte 3, before sending them to the LCD. If the Display Data WordSwap bit is also set, then the byte order of the fetched 32-bit data is reversed.byte 032-bit display datafrom display bufferbyte 1byte 2DataSerializationTo LUTbyte 3Byte SwapWord SwapFigure 2-22: Display Data Byte/Word SwapBit 4Floating Window EnableThis bit enables the floating window within the main window used for the FloatingWindow feature. The location of the floating window within the main window is determinedby the Floating Window Position X registers (REG[84h], REG[85h], REG[8Ch], REG[8Dh])and Floating Window Position Y registers (REG[88h], REG[89h], REG[90h], REG[91h]). Thefloating window has its own Display Start Address register (REG[7Ch, REG[7Dh], REG[7Eh])and Memory Address Offset register (REG[80h], REG[81h]). The floating window shares thesame color depth and display orientation as the main window.When this bit = 1, Floating Window is enabled.When this bit = 0, Floating Window is disabled.Bit 2Display Mirror ModeWhen this bit = 1,When this bit = 1, Mirror Mode is enabled.When this bit = 0, Mirror Mode is disable.Bits 1-0 Display Rotate Mode Select Bits [1:0]These bits select different display orientations:SSD1926Application NoteRev 1.0 P 83/84 Jul 2009 Solomon Systech

Table 2-20: Display Rotate Mode Select OptionsDisplay Rotate Mode Display OrientationSelect Bits [1:0]00 0° (Normal)01 90°10 180°11 270°2.14 Display Rotate ModeThe image is not actually rotated in the display buffer since there is no address translation during CPUread/write. The image is rotated during display refresh.2.14.1 90° Display Rotate ModeThe following figure shows how the programmer sees a 320x480 rotated image and how the image is beingdisplayed. The application image is written to the SSD1926 in the following sense: A–B–C–D. The display isrefreshed by the SSD1926 in the following sense: B-D-A-C.physical memorystart addressAB480DisplayRotateWindowdisplay start address(panel origin)A BDisplayRotateWindowC D320CD480320image seen by programmer= image in display bufferimage refreshed by SSD1926Figure 2-23: Relationship Between Screen Image and Image Refreshed in 90° Display Rotate Mode.Enable 90° Display Rotate ModeSet Display Rotate Mode Select bits to 01 (REG[71h] bits 1:0 = 01).Display Start AddressThe display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start Address registers (REG[74h],REG[75h], REG[76h]) must be programmed with the address of pixel “B”.To calculate the value of the address of pixel “B” use the following formula (assumes 8bpp color depth).Main Window Display Start Address bits 16-0= ((Image address + (panel height x bpp ÷ 8)) ÷ 4) –1= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) – 1= 79 (4Fh)Line Address OffsetThe Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display width and programmedusing the following formula.Main Window Line Address Offset bits 9-0= Display width in pixels ÷ (32 ÷ bpp)= 320 pixels ÷ (32 ÷ 8 bpp)= 80 (50h)Solomon Systech Jul 2009 P 84/85 Rev 1.0SSD1926Application Note

2.14.2 180° Display Rotate ModeThe following figure shows how the programmer sees a 480x320 landscape image and how the image isbeing displayed. The application image is written to the SSD1926 in the following sense: A–B–C–D. Thedisplay is refreshed by the SSD1926 in the following sense: D-C-B-A.physical memorystart addressdisplay start address(panel origin)ACDisplayRotateWindowBD320C DDisplayRotateWindowA B320480 480image seen by programmer= image in display bufferimage refreshed by SSD1926Figure 2-24: Relationship Between Screen Image and Image Refreshed in 180° Display Rotate Mode.Enable 180° Display Rotate ModeSet Display Rotate Mode Select bits to 10 (REG[71h] bits 1:0 = 10).Display Start AddressThe display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start Address registers(REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “D”.To calculate the value of the address of pixel “D” use the following formula (assumes 8bpp color depth).Main Window Display Start Address bits 16-0= ((Image address + (image width x (panel height – 1) + panel width) x bpp ÷ 8) ÷ 4) –1= ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp ÷ 8) ÷ 4) – 1= 38399 (95FFh)Line Address OffsetThe Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display width andprogrammed using the following formula.Main Window Line Address Offset bits 9-0= Display width in pixels ÷ (32 ÷ bpp)= 480 pixels ÷ (32 ÷ 8 bpp)= 120 (78h)SSD1926Application NoteRev 1.0 P 85/86 Jul 2009 Solomon Systech

2.14.3 270° Display Rotate ModeThe following figure shows how the programmer sees a 320x480 rotated image and how the image is beingdisplayed. The application image is written to the SSD1926 in the following sense: A–B–C–D. The display isrefreshed by the SSD1926 in the following sense: C-A-D-B.physical memorystart addressAB480DisplayRotateWindowdisplay start address(panel origin)CDisplayRotateWindowA320BDCD480320image seen by programmer= image in display bufferimage refreshed by SSD1926Figure 2-25: Relationship Between Screen Image and Image Refreshed in 270° Display Rotate Mode.Enable 270° Display Rotate ModeSet Display Rotate Mode Select bits to 11 (REG[71h] bits 1:0 = 11).Display Start AddressThe display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start Address registers(REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “C”.To calculate the value of the address of pixel “C” use the following formula (assumes 8bpp color depth).Main Window Display Start Address bits 16-0= (Image address + ((panel width – 1) x image width x bpp ÷ 8) ÷ 4)= (0 + ((480 pixels – 1) x 320 pixels x 8 bpp ÷ 8) ÷ 4)= 38320 (95B0h)Line Address OffsetThe Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display width andprogrammed using the following formula.Main Window Line Address Offset bits 9-0= Display width in pixels ÷ (32 ÷ bpp)= 320 pixels ÷ (32 ÷ 8 bpp)= 80 (50h)Solomon Systech Jul 2009 P 86/87 Rev 1.0SSD1926Application Note

2.15 Floating Window ModeThis mode enables a floating window within the main display window. The floating window can bepositioned anywhere within the virtual display and is controlled through the Floating Window controlregisters (REG[7Ch] through REG[91h]). The floating window retains the same color depth and displayorientation as the main window.The following diagram shows an example of a floating window within a main window and the registers usedto position it.Normal Orientation Modepanel’s originMain WindowFloating Window Start Y Position(REG[89h],REG[88h])Floating Window End Y Position(REG[91h],REG[90h])Floating WindowFloating Window Start X Position(REG[85h],REG[84h])Floating Window End X Position(REG[8Dh],REG[8Ch])Figure 2-26: Floating Window with Display Rotate Mode disabled2.15.1 Floating window under 90°Display Rotate Mode90° Display Rotate Modepanel’s originFloating Window End X Position(REG[8Dh],REG[8Ch])Floating Window Start X Position(REG[85h],REG[84h])Floating windowFloating Window Start Y Position(REG[89h],REG[88h])Main WindowFloating Window End Y Position(REG[91h],REG[90h])Figure 2-27: Floating Window with Display Rotate Mode 90° enabledSSD1926Application NoteRev 1.0 P 87/88 Jul 2009 Solomon Systech

2.15.2 Floating window under 180°Display Rotate Mode180° Display Rotate ModeFloating Window End X Position(REG[8Dh],REG[8Ch])Floating Window Start X Position(REG[85h],REG[84h])Floating WindowMain WindowFloating Window End Y Position(REG[91h],REG[90h]) Floating Window Start Y Position(REG[89h],REG[88h])panel’s originFigure 2-28: Floating Window with Display Rotate Mode 180° enabled2.15.3 Floating window under 270°Display Rotate Mode270° Display Rotate ModeFloating Window End Y Position(REG[91h],REG[90h])Main WindowFloating Window Start Y Position(REG[89h],REG[88h])Floating WindowFloating Window Start X Position(REG[85h],REG[84h])panel’s originFloating Window End X Position(REG[8Dh],REG[8Ch])Figure 2-29: Floating Window with Display Rotate Mode 270° enabledSolomon Systech Jul 2009 P 88/89 Rev 1.0SSD1926Application Note

Floating Window Display Start Address Register 0REG[7Ch]Bit 7 6 5 4 3 2 1 0FloatingWindowDisplayStartAddressBit 7FloatingWindowDisplayStartAddressBit 6FloatingWindowDisplayStartAddressBit 5FloatingWindowDisplayStartAddressBit 4FloatingWindowDisplayStartAddressBit 3FloatingWindowDisplayStartAddressBit 2FloatingWindowDisplayStartAddressBit 1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowDisplayStartAddressBit 0Floating Window Display Start Address Register 1REG[7Dh]Bit 7 6 5 4 3 2 1 0FloatingWindowDisplayStartAddressBit 15FloatingWindowDisplayStartAddressBit 14FloatingWindowDisplayStartAddressBit 13FloatingWindowDisplayStartAddressBit 12FloatingWindowDisplayStartAddressBit 11FloatingWindowDisplayStartAddressBit 10FloatingWindowDisplayStartAddressBit 9FloatingWindowDisplayStartAddressBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateFloating Window Display Start Address Register 2REG[7Eh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 FloatingWindowDisplayStartAddressBit 16Type NA NA NA NA NA NA NA RWResetstate0 0 0 0 0 0 0 0REG[7Eh] bit 0,REG[7Dh] bits 7-0,REG[7Ch] bits 7-0Floating Window Display Start Address Bits [16:0]These bits form the 17-bit address for the starting double-word of the floating window.Note that this is a double-word (32-bit) address. An entry of 00000h into these registersrepresents the first double-word of display memory, an entry of 00001h represents the seconddouble-word of the display memory, and so on.NoteThese bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit4=1).SSD1926Application NoteRev 1.0 P 89/90 Jul 2009 Solomon Systech

Floating Window Line Address Offset Register 0REG[80h]Bit 7 6 5 4 3 2 1 0FloatingWindowLineAddressOffset Bit 7FloatingWindowLineAddressOffset Bit 6FloatingWindowLineAddressOffset Bit 5FloatingWindowLineAddressOffset Bit 4FloatingWindowLineAddressOffset Bit 3FloatingWindowLineAddressOffset Bit 2FloatingWindowLineAddressOffset Bit 1FloatingWindowLineAddressOffset Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateFloating Window Line Address Offset Register 1REG[81h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 FloatingWindowLineAddressOffset Bit 9FloatingWindowLineAddressOffset Bit 8Type NA NA NA NA NA NA RW RWReset 0 0 0 0 0 0 0 0stateREG[81h] bits 1-0,REG[80h] bits 7-0Floating Window Line Address Offset Bits [9:0]These bits are the LCD display’s 10-bit address offset from the starting double-word of line “n”to the starting double-word of line “n + 1” for the floating window.Note(1)This is a 32-bit address increment.Note(1)These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit4=1).Solomon Systech Jul 2009 P 90/91 Rev 1.0SSD1926Application Note

Floating Window Start Position X Register 0REG[84h]Bit 7 6 5 4 3 2 1 0FloatingWindowStart XPosition Bit7FloatingWindowStart XPosition Bit6FloatingWindowStart XPosition Bit5FloatingWindowStart XPosition Bit4FloatingWindowStart XPosition Bit3FloatingWindowStart XPosition Bit2FloatingWindowStart XPosition Bit1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowStart XPosition Bit0Floating Window Start Position X Register 1REG[85h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 FloatingWindowStart XPosition Bit9Type NA NA NA NA NA NA RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowStart XPosition Bit8REG[85h] bits 1-0,REG[84h] bits 7-0Floating Window Start Position X Bits [9:0]These bits determine the start position X of the floating window in relation to the origin of thepanel. Due to the SSD1926 Display Rotate feature, the start position X may not be a horizontalposition value (only true in 0° and 180° rotation). For further information on defining the valueof the Start Position X register, see Section “Floating Window Mode” in datasheet.The value of register is also increased differently based on the display orientation. For 0° and180° Display Rotate Mode, the start position X is incremented by x pixels where x is relative tothe current color depth. Refer to Table 2-21. For 90° and 270° Display Rotate Mode, the startposition X is incremented by 1 line.Depending on the color depth, some of the higher bits in this register are unused because themaximum horizontal display width is 1024 pixels.Note(1)These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit4=1).Table 2-21: 32-bit Address X Increments for Various Color DepthsColor Depth (bpp) Pixel Increment (x)1 322 164 88 416 232 1SSD1926Application NoteRev 1.0 P 91/92 Jul 2009 Solomon Systech

Floating Window Start Position Y Register 0REG[88h]Bit 7 6 5 4 3 2 1 0FloatingWindowStart YPosition Bit7FloatingWindowStart YPosition Bit6FloatingWindowStart YPosition Bit5FloatingWindowStart YPosition Bit4FloatingWindowStart YPosition Bit3FloatingWindowStart YPosition Bit2FloatingWindowStart YPosition Bit1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowStart YPosition Bit0Floating Window Start Position Y Register 1REG[89h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 FloatingWindowStart YPosition Bit9Type NA NA NA NA NA NA RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowStart YPosition Bit8REG[89h] bits 1-0,REG[88h] bits 7-0Floating Window Start Position Y Bits [9:0]These bits determine the start position Y of the floating window in relation to the origin of thepanel. Due to the SSD1926 Display Rotate feature, the start position Y may not be a verticalposition value (only true in 0° and 180° Floating Window). For further information on definingthe value of the Start Position Y register, see Section “Floating Window Mode” in datasheet.The register is also incremented according to the display orientation. For 0° and 180° DisplayRotate Mode, the start position Y is incremented by 1 line. For 90° and 270° Display RotateMode, the start position Y is incremented by y pixels where y is relative to the current colordepth. Refer to Table 2-22: 32-bit Address Y Increments for Various Color Depths.Depending on the color depth, some of the higher bits in this register are unused because themaximum vertical display height is 1024 pixels.Note(1)These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit4=1).Table 2-22: 32-bit Address Y Increments for Various Color DepthsColor Depth (bpp) Pixel Increment (y)1 322 164 88 416 232 1Solomon Systech Jul 2009 P 92/93 Rev 1.0SSD1926Application Note

Floating Window End Position X Register 0REG[8Ch]Bit 7 6 5 4 3 2 1 0FloatingWindowEnd XPosition Bit7FloatingWindowEnd XPosition Bit6FloatingWindowEnd XPosition Bit5FloatingWindowEnd XPosition Bit4FloatingWindowEnd XPosition Bit3FloatingWindowEnd XPosition Bit2FloatingWindowEnd XPosition Bit1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowEnd XPosition Bit0Floating Window End Position X Register 1REG[8Dh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 FloatingWindowEnd XPosition Bit9Type NA NA NA NA NA NA RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowEnd XPosition Bit8REG[8Dh] bits 1-0,REG[8Ch] bits 7-0Floating Window End Position X Bits [9:0]These bits determine the end position X of the floating window in relation to the origin of thepanel. Due to the SSD1926 Display Rotate feature, the end position X may not be a horizontalposition value (only true in 0° and 180° rotation). For further information on defining the valueof the End Position X register, see “Floating Window Mode” in datasheet.The value of register is also increased according to the display orientation. For 0° and 180°Display Rotate Mode, the end position X is incremented by x pixels where x is relative to thecurrent color depth. Refer to Table 2-23: 32-bit Address X Increments for Various ColorDepths. For 90° and 270° Display Rotate Mode, the end position X is incremented by 1 line.Depending on the color depth, some of the higher bits in this register are unused because themaximum horizontal display width is 1024 pixels.Note(1)These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit4=1).Table 2-23: 32-bit Address X Increments for Various Color DepthsColor Depth (bpp) Pixel Increment (x)1 322 164 88 416 232 1SSD1926Application NoteRev 1.0 P 93/94 Jul 2009 Solomon Systech

Floating Window End Position Y Register 0REG[90h]Bit 7 6 5 4 3 2 1 0FloatingWindowEnd YPosition Bit7FloatingWindowEnd YPosition Bit6FloatingWindowEnd YPosition Bit5FloatingWindowEnd YPosition Bit4FloatingWindowEnd YPosition Bit3FloatingWindowEnd YPosition Bit2FloatingWindowEnd YPosition Bit1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowEnd YPosition Bit0Floating Window End Position Y Register 1REG[91h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 FloatingWindowEnd YPosition Bit9Type NA NA NA NA NA NA RW RWReset 0 0 0 0 0 0 0 0stateFloatingWindowEnd YPosition Bit8REG[91h] bits 1-0,REG[90h] bits 7-0Floating Window End Position Y Bits [9:0]These bits determine the end position Y of the floating window in relation to the origin of thepanel. Due to the SSD1926 Display Rotate feature, the end position Y may not be a verticalposition value (only true in 0° and 180° Display Rotate Mode). For further information ondefining the value of the End Position Y register, see Section “Floating Window Mode” indatasheet.The value of register is also increased according to the display orientation. For 0° and 180°Display Rotate Mode, the end position Y is incremented by 1 line. For 90° and 270° DisplayRotate Mode, the end position Y is incremented by y pixels where y is relative to the currentcolor depth. Refer to Table 2-24: 32-bit Address Y Increments for Various Color Depths.Depending on the color depth, some of the higher bits in this register are unused because themaximum vertical display height is 1024 pixels.Note(1)These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit4=1).Table 2-24: 32-bit Address Y Increments for Various Color DepthsColor Depth (bpp)Pixel Increment (y)1 322 164 88 416 232 1Solomon Systech Jul 2009 P 94/95 Rev 1.0SSD1926Application Note

2.16 Cursor ModeThis mode enables two cursors on the main display window. The cursors can be positioned anywhere withinthe display and are controlled through Cursor Mode registers (REG[C0h] through REG[111h]). Cursorsupport is available only at 4/8/16/32-bpp display modes.Each cursor pixel is 2-bit and the indexing scheme is as follows:Table 2-25: Indexing scheme for Hardware CursorValue Color of Cursor 1 / Cursor 200 Transparent01 Content of color index 1 register (REG[E31h-E0h] / REG[10Bh-108h])10 Content of color index 2 register (REG[E7h-E4h] / REG[10Fh-10Ch])11 Content of color index 3 register (REG[EBh-E8h] / REG[1131h-110h])Three 16-bit color index registers (REG[E0h] through REG[E9h] and REG[108h] through REG[111h]) havebeen implemented for each cursor. Only the lower portion of the color index register is used in 4/8-bppdisplay modes. The LUT is bypassed and the color data is directly mapped for 16/32-bpp display mode.4 Bit-per-pixel15 12 11 8 7 4 3 0Don’t Care4-bit Color Index8 Bit-per-pixel15 12 11 8 7 4 3 0Don’t Care8-bit Color Index16 Bit-per-pixel (the index registers represents the 16-bit color component)15 13 12 8 7 3 2 0Green ComponentBits 2-0Blue ComponentBits 4-0Red ComponentBits 4-0Green ComponentBits 5-332 Bit-per-pixel (the index registers represents the 32-bit color component)31 24 23 16Alpha ComponentBits 7-0Blue ComponentBits 5-315 8 7 0Green ComponentBits 7-0Red ComponentBits 5-3The display precedence is Cursor1 > Cursor2 > Floating window > Main Window.SSD1926Application NoteRev 1.0 P 95/96 Jul 2009 Solomon Systech

Cursor 1Cursor 2Floating WindowMain WindowFigure 2-30: Display Precedence in Hardware CursorNote(1)The minimum size varies for different color depths and display orientations.The cursors retains the same color depth and display orientation as the main window. The following diagramshows an example of two cursors within a main window and the registers used to position it.panel’s originCursor1 Position Y(REG[D5h],REG[D4h])Cursor2 Position Y(REG[FDh],REG[FCh])Main-WindowCursor1 Position X(REG[D1h],REG[D0h])Cursor1Cursor2Cursor2 Position X(REG[F9h],REG[F8h])Figure 2-31: Cursors on the main windowAssume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bitboundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and ycoordinate, C(y,x). Following are the pixel format.Solomon Systech Jul 2009 P 96/97 Rev 1.0SSD1926Application Note

For 4/8/16 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(0,0) C(0,1) C(0,2) C(0,3)Addr. n + 1 C(0,4) C(0,5) C(0,6) C(0,7)Addr. n + 2 C(0,8) C(0,9) C(0,10) C(0,11)Addr. n + 3 C(0,12) C(0,13) C(0,14) C(0,15)Addr. n + 4 C(1,0) C(1,1) C(1,2) C(1,3)...Addr. n + 60 C(15,0) C(15,1) C(15,2) C(15,3)Addr. n + 61 C(15,4) C(15,5) C(15,6) C(15,7)Addr. n + 62 C(15,8) C(15,9) C(15,10) C(15,11)Addr. n + 63 C(15,12) C(15,13) C(15,14) C(15,15)2.16.1.1 Cursor with 90° Display Rotate ModeCursor2 Position X(REG[F9h],REG[F8h])Cursor1 Position X(REG[D1h],REG[D0h])panel’s originCursor2Cursor2 Position Y(REG[FDh],REG[FCh])Cursor1Main-WindowCursor1 Position Y(REG[D5h],REG[D4h])Figure 2-32: Cursors with Display Rotate Mode 90° enabledAssume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bitboundary). In this example, a 16x16 cursor is displayed which each cursor index is defined x and ycoordinate, C(y,x). Following are the pixel format.SSD1926Application NoteRev 1.0 P 97/98 Jul 2009 Solomon Systech

For 4 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(0,8) C(0,9) C(0,10) C(0,11)Addr. n + 1 C(0,12) C(0,13) C(0,14) C(0,15)Addr. n + 2 C(1,8) C(1,9) C(1,10) C(1,11)Addr. n + 3 C(1,12) C(1,13) C(1,14) C(1,15)...Addr. n + 28 C(14,8) C(14,9) C(14,10) C(14,11)Addr. n + 29 C(14,12) C(14,13) C(14,14) C(14,15)Addr. n + 30 C(15,8) C(15,9) C(15,10) C(15,11)Addr. n + 31 C(15,12) C(15,13) C(15,14) C(15,15)Addr. n + 32 C(0,0) C(0,1) C(0,2) C(0,3)Addr. n + 33 C(0,4) C(0,5) C(0,6) C(0,7)Addr. n + 34 C(1,0) C(1,1) C(1,2) C(1,3)Addr. n + 35 C(1,4) C(1,5) C(1,6) C(1,7)...Addr. n + 60 C(14,0) C(14,1) C(14,2) C(14,3)Addr. n + 61 C(14,4) C(14,5) C(14,6) C(14,7)Addr. n + 62 C(15,0) C(15,1) C(15,2) C(15,3)Addr. n + 63 C(15,4) C(15,5) C(15,6) C(15,7)For 8 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(0,12) C(0,13) C(0,14) C(0,15)Addr. n + 1 C(1,12) C(1,13) C(1,14) C(1,15)Addr. n + 2 C(2,12) C(2,13) C(2,14) C(2,15)Addr. n + 3 C(3,12) C(3,13) C(3,14) C(3,15)...Addr. n + 12 C(12,12) C(12,13) C(12,14) C(12,15)Addr. n + 13 C(13,12) C(13,13) C(13,14) C(13,15)Addr. n + 14 C(14,12) C(14,13) C(14,14) C(14,15)Addr. n + 15 C(15,12) C(15,13) C(15,14) C(15,15)Addr. n + 16 C(0,8) C(0,9) C(0,10) C(0,11)Addr. n + 17 C(1,8) C(1,9) C(1,10) C(1,11)Addr. n + 18 C(2,8) C(2,9) C(2,10) C(2,11)Addr. n + 19 C(3,8) C(3,9) C(3,10) C(3,11)...Addr. n + 60 C(12,0) C(12,1) C(12,2) C(12,3)Addr. n + 61 C(13,0) C(13,1) C(13,2) C(13,3)Addr. n + 62 C(14,0) C(14,1) C(14,2) C(14,3)Addr. n + 63 C(15,0) C(15,1) C(15,2) C(15,3)Solomon Systech Jul 2009 P 98/99 Rev 1.0SSD1926Application Note

For 16 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(0,14) C(0,15) C(1,14) C(1,15)Addr. n + 1 C(2,14) C(2,15) C(3,14) C(3,15)Addr. n + 2 C(4,14) C(4,15) C(5,14) C(5,15)Addr. n + 3 C(6,14) C(6,15) C(7,14) C(7,15)Addr. n + 4 C(8,14) C(8,15) C(9,14) C(9,15)Addr. n + 5 C(10,14) C(10,15) C(11,14) C(11,15)Addr. n + 6 C(12,14) C(12,15) C(12,14) C(12,15)Addr. n + 7 C(14,14) C(14,15) C(15,14) C(15,15)Addr. n + 8 C(0,12) C(0,13) C(1,12) C(1,13)Addr. n + 9 C(2,12) C(2,13) C(3,12) C(3,13)Addr. n + 10 C(4,12) C(4,13) C(5,12) C(5,13)Addr. n + 11 C(6,12) C(6,13) C(7,12) C(7,13)...Addr. n + 60 C(8,0) C(8,1) C(9,0) C(9,1)Addr. n + 61 C(10,0) C(10,1) C(11,0) C(11,1)Addr. n + 62 C(12,0) C(12,1) C(12,0) C(12,1)Addr. n + 63 C(14,0) C(14,1) C(15,0) C(15,1)2.16.1.2 Cursor with 180° Display Rotate ModeCursor2 Position X(REG[F9h],REG[F8h])Cursor1 Position X(REG[D1h],REG[D0h])Main-WindowCursor1Cursor2Cursor1 Position Y(REG[D5h],REG[D4h])Cursor2 Position Y(REG[FDh],REG[FCh])panel’s originFigure 2-33: Cursors with Display Rotate Mode 180° enabledAssume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bitboundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and ycoordinate, C(y,x). Following are the pixel format.SSD1926Application NoteRev 1.0 P 99/100 Jul 2009 Solomon Systech

For 4 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(15,8) C(15,9) C(15,10) C(15,11)Addr. n + 1 C(15,12) C(15,13) C(15,14) C(15,15)Addr. n + 2 C(15,0) C(15,1) C(15,2) C(15,3)Addr. n + 3 C(15,4) C(15,5) C(15,6) C(15,7)Addr. n + 4 C(14,8) C(14,9) C(14,10) C(14,11)...Addr. n + 60 C(0,8) C(0,9) C(0,10) C(0,11)Addr. n + 61 C(0,12) C(0,13) C(0,14) C(0,15)Addr. n + 62 C(0,0) C(0,1) C(0,2) C(0,3)Addr. n + 63 C(0,4) C(0,5) C(0,6) C(0,7)For 8 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(15,12) C(15,13) C(15,14) C(15,15)Addr. n + 1 C(15,8) C(15,9) C(15,10) C(15,11)Addr. n + 2 C(15,4) C(15,5) C(15,6) C(15,7)Addr. n + 3 C(15,0) C(15,1) C(15,2) C(15,3)Addr. n + 4 C(14,12) C(14,13) C(14,14) C(14,15)...Addr. n + 60 C(0,12) C(0,13) C(0,14) C(0,15)Addr. n + 61 C(0,8) C(0,9) C(0,10) C(0,11)Addr. n + 62 C(0,4) C(0,5) C(0,6) C(0,7)Addr. n + 63 C(0,0) C(0,1) C(0,2) C(0,3)For 16 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(15,14) C(15,15) C(15,12) C(15,13)Addr. n + 1 C(15,10) C(15,11) C(15,8) C(15,9)Addr. n + 2 C(15,6) C(15,7) C(15,4) C(15,5)Addr. n + 3 C(15,2) C(15,3) C(15,0) C(15,1)Addr. n + 4 C(14,14) C(14,15) C(14,12) C(14,13)...Addr. n + 60 C(0,14) C(0,15) C(0,12) C(0,13)Addr. n + 61 C(0,10) C(0,11) C(0,8) C(0,9)Addr. n + 62 C(0,6) C(0,7) C(0,4) C(0,5)Addr. n + 63 C(0,2) C(0,3) C(0,0) C(0,1)Solomon Systech Jul 2009 P 100/101 Rev 1.0SSD1926Application Note

2.16.2 Cursor with 270° Display Rotate ModeCursor1 Position Y(REG[D5h],REG[D4h])Cursor2 Position Y(REG[FDh],REG[FCh])Main-WindowCursor1Cursor2Cursor1 Position X(REG[D1h],REG[D0h])panel’s originCursor2 Position X(REG[F9h],REG[F8h])Figure 2-34: Cursors with Display Rotate Mode 270° enabledAssume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bitboundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and ycoordinate, C(y,x). Following are the pixel format.Fro 4 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(15,0) C(15,1) C(15,2) C(15,3)Addr. n + 1 C(15,4) C(15,5) C(15,6) C(15,7)Addr. n + 2 C(14,0) C(14,1) C(14,2) C(14,3)Addr. n + 3 C(14,4) C(14,5) C(14,6) C(14,7)...Addr. n + 28 C(1,0) C(1,1) C(1,2) C(1,3)Addr. n + 29 C(1,4) C(1,5) C(1,6) C(1,7)Addr. n + 30 C(0,0) C(0,1) C(0,2) C(0,3)Addr. n + 31 C(0,4) C(0,5) C(0,6) C(0,7)Addr. n + 32 C(15,8) C(15,9) C(15,10) C(15,11)Addr. n + 33 C(15,12) C(15,13) C(15,14) C(15,15)Addr. n + 34 C(14,8) C(14,9) C(14,10) C(14,11)Addr. n + 35 C(14,12) C(14,13) C(14,14) C(14,15)...Addr. n + 60 C(1,8) C(1,9) C(1,10) C(1,11)Addr. n + 61 C(1,12) C(1,13) C(1,14) C(1,15)Addr. n + 62 C(0,8) C(0,9) C(0,10) C(0,11)Addr. n + 63 C(0,12) C(0,13) C(0,14) C(0,15)SSD1926Application NoteRev 1.0 P 101/102 Jul 2009 Solomon Systech

For 8 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(15,0) C(15,1) C(15,2) C(15,3)Addr. n + 1 C(14,0) C(14,1) C(14,2) C(14,3)Addr. n + 2 C(13,0) C(13,1) C(13,2) C(13,3)Addr. n + 3 C(12,0) C(12,1) C(12,2) C(12,3)...Addr. n + 12 C(3,0) C(3,1) C(3,2) C(3,3)Addr. n + 13 C(2,0) C(2,1) C(2,2) C(2,3)Addr. n + 14 C(1,0) C(1,1) C(1,2) C(1,3)Addr. n + 15 C(0,0) C(0,1) C(0,2) C(0,3)Addr. n + 16 C(15,4) C(15,5) C(15,6) C(15,7)Addr. n + 17 C(14,4) C(14,5) C(14,6) C(14,7)Addr. n + 18 C(13,4) C(13,5) C(13,6) C(13,7)Addr. n + 19 C(12,4) C(12,5) C(12,6) C(12,7)...Addr. n + 60 C(3,12) C(3,13) C(3,14) C(3,15)Addr. n + 61 C(2,12) C(2,13) C(2,14) C(2,15)Addr. n + 62 C(1,12) C(1,13) C(1,14) C(1,15)Addr. n + 63 C(0,12) C(0,13) C(0,14) C(0,15)For 16 Bit-per-pixel7 6 5 4 3 2 1 0Addr. n C(15,0) C(15,1) C(14,0) C(14,1)Addr. n + 1 C(13,0) C(13,1) C(12,0) C(12,1)Addr. n + 2 C(11,0) C(11,1) C(10,0) C(10,1)Addr. n + 3 C(9,0) C(9,1) C(8,0) C(8,1)Addr. n + 4 C(7,0) C(7,1) C(6,0) C(6,1)Addr. n + 5 C(5,0) C(5,1) C(4,0) C(4,1)Addr. n + 6 C(3,0) C(3,1) C(2,0) C(2,1)Addr. n + 7 C(1,0) C(1,1) C(0,0) C(0,1)Addr. n + 8 C(15,2) C(15,3) C(14,2) C(14,3)Addr. n + 9 C(13,2) C(13,3) C(12,2) C(12,3)Addr. n + 10 C(11,2) C(11,3) C(10,2) C(10,3)Addr. n + 11 C(9,2) C(9,3) C(8,2) C(8,3)...Addr. n + 60 C(7,14) C(7,15) C(6,14) C(6,15)Addr. n + 61 C(5,14) C(5,15) C(4,14) C(4,15)Addr. n + 62 C(3,14) C(3,15) C(2,14) C(2,15)Addr. n + 63 C(1,14) C(1,15) C(0,14) C(0,15)Solomon Systech Jul 2009 P 102/103 Rev 1.0SSD1926Application Note

Cursor Feature RegisterREG[C0h]Bit 7 6 5 4 3 2 1 0Cursor1 Cursor2 0 0 0 0 0 0Enable EnableType RW RW RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bit 7Bit 6Cursor1 EnableWhen this bit = 0 Cursor1 is disabled.When this bit = 1 Cursor1 is enabled.Cursor2 EnableWhen this bit = 0, Cursor2 is disabled.When this bit = 1, Cursor2 is enabled.Note(1)This register is effective for 4/8/16/32 bpp (REG[70h] Bits 2:0 = 010/011/100/101)Cursor1 Blink Total Register 0REG[C4h]Bit 7 6 5 4 3 2 1 0Cursor1Blink TotalBit 7Cursor1Blink TotalBit 6Cursor1Blink TotalBit 5Cursor1Blink TotalBit 4Cursor1Blink TotalBit 3Cursor1Blink TotalBit 2Cursor1Blink TotalBit 1Cursor1Blink TotalBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Blink Total Register 1REG[C5h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor1Blink TotalBit 9Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateCursor1Blink TotalBit 8REG[C5h] bits 1-0,REG[C4h] bits 7-0Cursor1 Blink Total Bits [9:0]This is the total blinking period per frame for cursor1. This register must be set to a non-zerovalue in order to make the cursor visible.Note(1)These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).SSD1926Application NoteRev 1.0 P 103/104 Jul 2009 Solomon Systech

Cursor1 Blink On Register 0REG[C8h]Bit 7 6 5 4 3 2 1 0Cursor1Blink OnBit 7Cursor1Blink OnBit 6Cursor1Blink OnBit 5Cursor1Blink OnBit 4Cursor1Blink OnBit 3Cursor1Blink OnBit 2Cursor1Blink OnBit 1Cursor1Blink OnBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Blink On Register 1REG[C9h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor1Blink OnBit 9Cursor1Blink OnBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[C9h] bits 1-0,REG[C8h] bits 7-0Cursor1 Blink On Bits [9:0]This is the blink on frame period for Cursor1.This register must be set to a non-zero value in order to make the cursor1 visible. Also, cursor1will start to blink if the following conditions are fulfilled :Cursor1 Blink Total Bits [9:0] > Cursor1 Blink On Bits [9:0] > 0To enable cursor1 without blinking, user must program cursor1 blink on register with a nonzerovalue, and this value must be greater than or equal to Cursor1 Blink Total Register.Cursor1 Blink On Bits [9:0] > Cursor1 Blink Total Bits [9:0] > 0These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).Cursor1 Memory Start Register 0REG[CCh]Bit 7 6 5 4 3 2 1 0Cursor1MemoryStart Bit 7Cursor1MemoryStart Bit 6Cursor1MemoryStart Bit 5Cursor1MemoryStart Bit 4Cursor1MemoryStart Bit 3Cursor1MemoryStart Bit 2Cursor1MemoryStart Bit 1Cursor1MemoryStart Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Memory Start Register 1REG[CDh]Bit 7 6 5 4 3 2 1 0Cursor1MemoryStart Bit 15Cursor1MemoryStart Bit 14Cursor1MemoryStart Bit 13Cursor1MemoryStart Bit 12Cursor1MemoryStart Bit 11Cursor1MemoryStart Bit 10Cursor1MemoryStart Bit 9Cursor1MemoryStart Bit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Memory Start Register 2REG[CEh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 Cursor1MemoryStart Bit 16Type RO RO RO RO RO RO RO RWResetstate0 0 0 0 0 0 0 0Solomon Systech Jul 2009 P 104/105 Rev 1.0SSD1926Application Note

REG[CEh] bit 0,REG[CDh] bits 7-0,REG[CCh] bits 7-0Cursor1 Memory Start Bits [16:0]These bits form the 17-bit address for the starting double-word of the LCD image in the displaybuffer for the Cursor1 image.Note(1)That this is a double-word (32-bit) address.An entry of 00000h into these registers represents the first double-word of display memory, anentry of 00001h represents the second double-word of the display memory, and so on.Calculate the Cursor1 Start Address as follows :Cursor1 Memory Start Bits 16:0= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)Note(1)These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).Cursor1 Position X Register 0REG[D0h]Bit 7 6 5 4 3 2 1 0Cursor1Position XBit 7Cursor1Position XBit 6Cursor1Position XBit 5Cursor1Position XBit 4Cursor1Position XBit 3Cursor1Position XBit 2Cursor1Position XBit 1Cursor1Position XBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Position X Register 1REG[D1h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor1Position XBit 9Cursor1Position XBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[D1h] bits 1-0,REG[D0h] bits 7-0Cursor1 Position X Bits [9:0]This is starting position X of Cursor1 image. The definition of this register is same as FloatingWindow Start Position X Register.Note(1)These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).Cursor1 Position Y Register 0REG[D4h]Bit 7 6 5 4 3 2 1 0Cursor1Position YBit 7Cursor1Position YBit 6Cursor1Position YBit 5Cursor1Position YBit 4Cursor1Position YBit 3Cursor1Position YBit 2Cursor1Position YBit 1Cursor1Position YBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Position Y Register 1REG[D5h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor1Position YBit 9Cursor1Position YBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateSSD1926Application NoteRev 1.0 P 105/106 Jul 2009 Solomon Systech

REG[D5h] bits 1-0,REG[D4h] bits 7-0Cursor1 Position Y Bits [9:0]This is starting position Y of Cursor1 image. The definition of this register is same as FloatingWindow Y Start Position Register.Note(1)These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).Cursor1 Horizontal Size Register 0REG[D8h]Bit 7 6 5 4 3 2 1 0Cursor1HorizontalSize Bit 7Cursor1HorizontalSize Bit 6Cursor1HorizontalSize Bit 5Cursor1HorizontalSize Bit 4Cursor1HorizontalSize Bit 3Cursor1HorizontalSize Bit 2Cursor1HorizontalSize Bit 1Cursor1HorizontalSize Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Horizontal Size Register 1REG[D9h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor1HorizontalSize Bit 9Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateCursor1HorizontalSize Bit 8REG[D9h] bits 1-0,REG[D8h] bits 7-0Cursor1 Horizontal Size Bits [9:0]These bits specify the horizontal size of Cursor1.NoteThe definition of this register various under different panel orientation and color depth settings.These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).Table 2-26: X Increment Mode for Various Color DepthsOrientation Main window ColorIncrement (x)Depth (bpp)0˚416 pixels increment8e.g. 0000h = 16 pixels; 0001h = 32 pixels160˚32 16 pixels incremente.g. 0000h = 16 pixels; 0001h = 32 pixels4 2 lines increment90˚8 4 lines increment16 8 lines increment90˚ 32 16 lines increment180˚4816 pixels increment1690˚ 32 2 lines increment4 2 lines increment270˚8 4 lines increment16 8 lines increment90˚ 32 16 lines incrementSolomon Systech Jul 2009 P 106/107 Rev 1.0SSD1926Application Note

Cursor1 Vertical Size Register 0REG[DCh]Bit 7 6 5 4 3 2 1 0Cursor1VerticalSize Bit 7Cursor1VerticalSize Bit 6Cursor1VerticalSize Bit 5Cursor1VerticalSize Bit 4Cursor1VerticalSize Bit 3Cursor1VerticalSize Bit 2Cursor1VerticalSize Bit 1Cursor1VerticalSize Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Vertical Size Register 1REG[DDh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor1VerticalSize Bit 9Cursor1VerticalSize Bit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[DDh] bits 1-0,REG[DCh] bits 7-0Cursor1 Vertical Size Bits [9:0]These bits specify the vertical size of Cursor1.Note(1)The definition of this register various under different panel orientation and color depthsettings.These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).Orientation0˚90˚180˚270˚Table 2-27: Y Increment Mode for Various Color DepthsMain window ColorIncrement (y)Depth (bpp)481 line increment16e.g. 0000h = 1 line; 0001h = 2 lines324 8 pixels increment8 4 pixels increment16 2 pixels increment32 1 pixel increment481 line increment16324 8 pixels increment8 4 pixels increment16 2 pixels increment32 1 pixel incrementSSD1926Application NoteRev 1.0 P 107/108 Jul 2009 Solomon Systech

Cursor1 Color Index1 Register 0REG[E0h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex1 Bit7Cursor1ColorIndex1 Bit6Cursor1ColorIndex1 Bit5Cursor1ColorIndex1 Bit4Cursor1ColorIndex1 Bit3Cursor1ColorIndex1 Bit2Cursor1ColorIndex1 Bit1Cursor1ColorIndex1 Bit0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index1 Register 1REG[E1h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex1 Bit15Cursor1ColorIndex1 Bit14Cursor1ColorIndex1 Bit13Cursor1ColorIndex1 Bit12Cursor1ColorIndex1 Bit11Cursor1ColorIndex1 Bit10Cursor1ColorIndex1 Bit9Cursor1ColorIndex1 Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index1 Register 2REG[E2h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex1 Bit23Cursor1ColorIndex1 Bit22Cursor1ColorIndex1 Bit21Cursor1ColorIndex1 Bit20Cursor1ColorIndex1 Bit19Cursor1ColorIndex1 Bit18Cursor1ColorIndex1 Bit17Cursor1ColorIndex1 Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index1 Register 3REG[E3h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex1 Bit31Cursor1ColorIndex1 Bit30Cursor1ColorIndex1 Bit29Cursor1ColorIndex1 Bit28Cursor1ColorIndex1 Bit27Cursor1ColorIndex1 Bit26Cursor1ColorIndex1 Bit25Cursor1ColorIndex1 Bit24Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[E3h] bits 7-0,REG[E2h] bits 7-0,REG[E1h] bits 7-0,REG[E0h] bits 7-0Cursor1 Color Index1 Bits [31:0]Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 01of Cursor1.Note(1)These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.Solomon Systech Jul 2009 P 108/109 Rev 1.0SSD1926Application Note

Cursor1 Color Index2 Register 0REG[E4h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex2 Bit7Cursor1ColorIndex2 Bit6Cursor1ColorIndex2 Bit5Cursor1ColorIndex2 Bit4Cursor1ColorIndex2 Bit3Cursor1ColorIndex2 Bit2Cursor1ColorIndex2 Bit1Cursor1ColorIndex2 Bit0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index2 Register 1REG[E5h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex2 Bit15Cursor1ColorIndex2 Bit14Cursor1ColorIndex2 Bit13Cursor1ColorIndex2 Bit12Cursor1ColorIndex2 Bit11Cursor1ColorIndex2 Bit10Cursor1ColorIndex2 Bit9Cursor1ColorIndex2 Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index2 Register 2REG[E6h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex2 Bit23Cursor1ColorIndex2 Bit22Cursor1ColorIndex2 Bit21Cursor1ColorIndex2 Bit20Cursor1ColorIndex2 Bit19Cursor1ColorIndex2 Bit18Cursor1ColorIndex2 Bit17Cursor1ColorIndex2 Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index2 Register 3REG[E7h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex2 Bit31Cursor1ColorIndex2 Bit30Cursor1ColorIndex2 Bit29Cursor1ColorIndex2 Bit28Cursor1ColorIndex2 Bit27Cursor1ColorIndex2 Bit26Cursor1ColorIndex2 Bit25Cursor1ColorIndex2 Bit24Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[E7h] bits 7-0,REG[E6h] bits 7-0,REG[E5h] bits 7-0,REG[E4h] bits 7-0Cursor1 Color Index2 Bits [31:0]Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 10of Cursor1.Note(1)These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.SSD1926Application NoteRev 1.0 P 109/110 Jul 2009 Solomon Systech

Cursor1 Color Index3 Register 0REG[E8h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex3 Bit7Cursor1ColorIndex3 Bit6Cursor1ColorIndex3 Bit5Cursor1ColorIndex3 Bit4Cursor1ColorIndex3 Bit3Cursor1ColorIndex3 Bit2Cursor1ColorIndex3 Bit1Cursor1ColorIndex3 Bit0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index3 Register 1REG[E9h]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex3 Bit15Cursor1ColorIndex3 Bit14Cursor1ColorIndex3 Bit13Cursor1ColorIndex3 Bit12Cursor1ColorIndex3 Bit11Cursor1ColorIndex3 Bit10Cursor1ColorIndex3 Bit9Cursor1ColorIndex3 Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index3 Register 2REG[EAh]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex3 Bit23Cursor1ColorIndex3 Bit22Cursor1ColorIndex3 Bit21Cursor1ColorIndex3 Bit20Cursor1ColorIndex3 Bit19Cursor1ColorIndex3 Bit18Cursor1ColorIndex3 Bit17Cursor1ColorIndex3 Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor1 Color Index3 Register 3REG[EBh]Bit 7 6 5 4 3 2 1 0Cursor1ColorIndex3 Bit31Cursor1ColorIndex3 Bit30Cursor1ColorIndex3 Bit29Cursor1ColorIndex3 Bit28Cursor1ColorIndex3 Bit27Cursor1ColorIndex3 Bit26Cursor1ColorIndex3 Bit25Cursor1ColorIndex3 Bit24Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[EBh] bits 7-0,REG[EAh] bits 7-0,REG[E9h] bits 7-0,REG[E8h] bits 7-0Cursor1 Color Index3 Bits [31:0]Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 11of Cursor1.Note(1)These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.Solomon Systech Jul 2009 P 110/111 Rev 1.0SSD1926Application Note

Cursor2 Blink Total Register 0REG[ECh]Bit 7 6 5 4 3 2 1 0Cursor2Blink TotalBit 7Cursor2Blink TotalBit 6Cursor2Blink TotalBit 5Cursor2Blink TotalBit 4Cursor2Blink TotalBit 3Cursor2Blink TotalBit 2Cursor2Blink TotalBit 1Cursor2Blink TotalBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Blink Total Register 1REG[EDh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor2Blink TotalBit 9Cursor2Blink TotalBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[EDh] bits 1-0,REG[ECh] bits 7-0Cursor2 Blink Total Bits [9:0]This is the total blinking period per frame for Cursor2. This register must be set to a non-zerovalue in order to make the cursor visible.Note(1)These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).Cursor2 Blink On Register 0REG[F0h]Bit 7 6 5 4 3 2 1 0Cursor2Blink OnBit 7Cursor2Blink OnBit 6Cursor2Blink OnBit 5Cursor2Blink OnBit 4Cursor2Blink OnBit 3Cursor2Blink OnBit 2Cursor2Blink OnBit 1Cursor2Blink OnBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Blink On Register 1REG[F1h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor2Blink OnBit 9Cursor2Blink OnBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[F1h] bits 1-0,REG[F0h] bits 7-0Cursor2 Blink On Bits [9:0]This is the blink on frame period for Cursor2. This register must be set to a non-zero value inorder to make the Cursor2 visible. Also, Cursor2 will start to blink if the following conditionsare fulfilled:Cursor2 Blink Total Bits [9:0] > Cursor2 Blink On Bits [9:0] > 0To enable Cursor2 without blinking, user must program Cursor2 Blink On Register with a nonzerovalue, and this value must be greater than or equal to Cursor2 Blink Total Register.Cursor2 Blink On Bits [9:0] > Cursor2 Blink Total Bits [9:0] > 0These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).SSD1926Application NoteRev 1.0 P 111/112 Jul 2009 Solomon Systech

Cursor2 Memory Start Register 0REG[F4h]Bit 7 6 5 4 3 2 1 0Cursor2MemoryStart Bit 7Cursor2MemoryStart Bit 6Cursor2MemoryStart Bit 5Cursor2MemoryStart Bit 4Cursor2MemoryStart Bit 3Cursor2MemoryStart Bit 2Cursor2MemoryStart Bit 1Cursor2MemoryStart Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Memory Start Register 1REG[F5h]Bit 7 6 5 4 3 2 1 0Cursor2MemoryStart Bit 15Cursor2MemoryStart Bit 14Cursor2MemoryStart Bit 13Cursor2MemoryStart Bit 12Cursor2MemoryStart Bit 11Cursor2MemoryStart Bit 10Cursor2MemoryStart Bit 9Cursor2MemoryStart Bit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Memory Start Register 2REG[F6h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 0 Cursor2MemoryStart Bit 16Type RO RO RO RO RO RO RO RWResetstate0 0 0 0 0 0 0 0REG[F6h] bit 0,REG[F5h] bits 7-0,REG[F4h] bits 7-0Cursor2 Memory Start Bits [16:0]These bits form the 17-bit address for the starting double-word of the LCD image in the displaybuffer for the Cursor2 image.Note that this is a double-word (32-bit) address. An entry of 00000h into these registersrepresents the first double-word of display memory, an entry of 00001h represents the seconddouble-word of the display memory, and so on.Calculate the Cursor2 Start Address as follows :Cursor2 Memory Start Bits 16:0= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)Note(1)These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).Solomon Systech Jul 2009 P 112/113 Rev 1.0SSD1926Application Note

Cursor2 Position X Register 0REG[F8h]Bit 7 6 5 4 3 2 1 0Cursor2Position XBit 7Cursor2Position XBit 6Cursor2Position XBit 5Cursor2Position XBit 4Cursor2Position XBit 3Cursor2Position XBit 2Cursor2Position XBit 1Cursor2Position XBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Position X Register 1REG[F9h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor2Position XBit 9Cursor2Position XBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[F9h] bits 1-0,REG[F8h] bits 7-0Cursor2 Position X Bits [9:0]This is starting position X of Cursor2 image. The definition of this register is same as FloatingWindow Start Position X Register.Note(1)These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).Cursor2 Position Y Register 0REG[FCh]Bit 7 6 5 4 3 2 1 0Cursor2Position YBit 7Cursor2Position YBit 6Cursor2Position YBit 5Cursor2Position YBit 4Cursor2Position YBit 3Cursor2Position YBit 2Cursor2Position YBit 1Cursor2Position YBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Position Y Register 1REG[FDh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor2Position YBit 9Cursor2Position YBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[FDh] bits 1-0,REG[FCh] bits 7-0Cursor2 Position Y Bits [9:0]This is starting position Y of Cursor2 image. The definition of this register is same as FloatingWindow Y Start Position Register.Note(1)These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).SSD1926Application NoteRev 1.0 P 113/114 Jul 2009 Solomon Systech

Cursor2 Horizontal Size Register 0REG[100h]Bit 7 6 5 4 3 2 1 0Cursor2HorizontalSize Bit 7Cursor2HorizontalSize Bit 6Cursor2HorizontalSize Bit 5Cursor2HorizontalSize Bit 4Cursor2HorizontalSize Bit 3Cursor2HorizontalSize Bit 2Cursor2HorizontalSize Bit 1Cursor2HorizontalSize Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Horizontal Size Register 1REG[101h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor2HorizontalSize Bit 9Cursor2HorizontalSize Bit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[101h] bits 1-0,REG[100h] bits 7-0Cursor2 Horizontal Size Bits [9:0]These bits specify the horizontal size of Cursor2.Note(1)The definition of this register various under different panel orientation and color depthsettings. Refer to Table 2-26.These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).Cursor2 Vertical Size Register 0REG[104h]Bit 7 6 5 4 3 2 1 0Cursor2VerticalSize Bit 7Cursor2VerticalSize Bit 6Cursor2VerticalSize Bit 5Cursor2VerticalSize Bit 4Cursor2VerticalSize Bit 3Cursor2VerticalSize Bit 2Cursor2VerticalSize Bit 1Cursor2VerticalSize Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Vertical Size Register 1REG[105h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Cursor2VerticalSize Bit 9Cursor2VerticalSize Bit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[105h] bits 1-0,REG[104h] bits 7-0Cursor2 Vertical Size Bits [9:0]These bits specify the vertical size of Cursor2.Note(1)The definition of this register various under different panel orientation and color depthsettings. Refer to Table 2-27.These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).Solomon Systech Jul 2009 P 114/115 Rev 1.0SSD1926Application Note

Cursor2 Color Index1 Register 0REG[108h]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex1 Bit7Cursor2ColorIndex1 Bit6Cursor2ColorIndex1 Bit5Cursor2ColorIndex1 Bit4Cursor2ColorIndex1 Bit3Cursor2ColorIndex1 Bit2Cursor2ColorIndex1 Bit1Cursor2ColorIndex1 Bit0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index1 Register 1REG[109h]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex1 Bit15Cursor2ColorIndex1 Bit14Cursor2ColorIndex1 Bit13Cursor2ColorIndex1 Bit12Cursor2ColorIndex1 Bit11Cursor2ColorIndex1 Bit10Cursor2ColorIndex1 Bit9Cursor2ColorIndex1 Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index1 Register 2REG[10Ah]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex1 Bit23Cursor2ColorIndex1 Bit22Cursor2ColorIndex1 Bit21Cursor2ColorIndex1 Bit20Cursor2ColorIndex1 Bit19Cursor2ColorIndex1 Bit18Cursor2ColorIndex1 Bit17Cursor2ColorIndex1 Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index1 Register 3REG[10Bh]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex1 Bit31Cursor2ColorIndex1 Bit30Cursor2ColorIndex1 Bit29Cursor2ColorIndex1 Bit28Cursor2ColorIndex1 Bit27Cursor2ColorIndex1 Bit26Cursor2ColorIndex1 Bit25Cursor2ColorIndex1 Bit24Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[10Bh] bits 7-0REG[10Ah] bits 7-0REG[109h] bits 7-0REG[108h] bits 7-0Cursor2 Color Index1 Bits [31:0]Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 01of Cursor2.Note(1)These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.SSD1926Application NoteRev 1.0 P 115/116 Jul 2009 Solomon Systech

Cursor2 Color Index2 Register 0REG[10Ch]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex2 Bit7Cursor2ColorIndex2 Bit6Cursor2ColorIndex2 Bit5Cursor2ColorIndex2 Bit4Cursor2ColorIndex2 Bit3Cursor2ColorIndex2 Bit2Cursor2ColorIndex2 Bit1Cursor2ColorIndex2 Bit0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index2 Register 1REG[10Dh]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex2 Bit15Cursor2ColorIndex2 Bit14Cursor2ColorIndex2 Bit13Cursor2ColorIndex2 Bit12Cursor2ColorIndex2 Bit11Cursor2ColorIndex2 Bit10Cursor2ColorIndex2 Bit9Cursor2ColorIndex2 Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index2 Register 0REG[10Eh]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex2 Bit23Cursor2ColorIndex2 Bit22Cursor2ColorIndex2 Bit21Cursor2ColorIndex2 Bit20Cursor2ColorIndex2 Bit19Cursor2ColorIndex2 Bit18Cursor2ColorIndex2 Bit17Cursor2ColorIndex2 Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index2 Register 1REG[10Fh]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex2 Bit31Cursor2ColorIndex2 Bit30Cursor2ColorIndex2 Bit29Cursor2ColorIndex2 Bit28Cursor2ColorIndex2 Bit27Cursor2ColorIndex2 Bit26Cursor2ColorIndex2 Bit25Cursor2ColorIndex2 Bit24Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[10Fh] bits 7-0REG[10Eh] bits 7-0REG[10Dh] bits 7-0REG[10Ch] bits 7-0Cursor2 Color Index2 Bits [31:0]Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 10of Cursor2.Note(1)These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.Solomon Systech Jul 2009 P 116/117 Rev 1.0SSD1926Application Note

Cursor2 Color Index3 Register 0REG[110h]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex3 Bit7Cursor2ColorIndex3 Bit6Cursor2ColorIndex3 Bit5Cursor2ColorIndex3 Bit4Cursor2ColorIndex3 Bit3Cursor2ColorIndex3 Bit2Cursor2ColorIndex3 Bit1Cursor2ColorIndex3 Bit0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index3 Register 1REG[111h]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex3 Bit15Cursor2ColorIndex3 Bit14Cursor2ColorIndex3 Bit13Cursor2ColorIndex3 Bit12Cursor2ColorIndex3 Bit11Cursor2ColorIndex3 Bit10Cursor2ColorIndex3 Bit9Cursor2ColorIndex3 Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index3 Register 2REG[112h]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex3 Bit23Cursor2ColorIndex3 Bit22Cursor2ColorIndex3 Bit21Cursor2ColorIndex3 Bit20Cursor2ColorIndex3 Bit19Cursor2ColorIndex3 Bit18Cursor2ColorIndex3 Bit17Cursor2ColorIndex3 Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateCursor2 Color Index3 Register 3REG[113h]Bit 7 6 5 4 3 2 1 0Cursor2ColorIndex3 Bit31Cursor2ColorIndex3 Bit30Cursor2ColorIndex3 Bit29Cursor2ColorIndex3 Bit28Cursor2ColorIndex3 Bit27Cursor2ColorIndex3 Bit26Cursor2ColorIndex3 Bit25Cursor2ColorIndex3 Bit24Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[113h] bits 7-0REG[112h] bits 7-0REG[111h] bits 7-0REG[110h] bits 7-0Cursor2 Color Index3 Bits [31:0]Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 11of Cursor2.Note(1)These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.SSD1926Application NoteRev 1.0 P 117/118 Jul 2009 Solomon Systech

2.17 Draw2D ModeDraw 2D Command Register 1REG[1D0h]Bit 7 6 5 4 3 2 1 0Draw 2DCommandBit 7Draw 2DCommandBit 6Draw 2DCommandBit 5Draw 2DCommandBit 4Draw 2DCommandBit 3Draw 2DCommandBit 2Draw 2DCommandBit 1Draw 2DCommandBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Command Register 2REG[1D1h]Bit 7 6 5 4 3 2 1 0Draw 2DCommandBit 15Draw 2DCommandBit 14Draw 2DCommandBit 13Draw 2DCommandBit 12Draw 2DCommandBit 11Draw 2DCommandBit 10Draw 2DCommandBit 9Draw 2DCommandBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[1D1h] Bits 7-4Draw 2D Command Registers [15:0]These bits are rotation extension decoded as below:Rotation extension is used for bitblt, alpha blending, rop and stretch blt operations.Bits 7:6 is the x orientationBits 5:4 is y orientation2’b00: original orientation2’b01: mirror in own axis2’b10: mirror in opposite axis2’b11: original orientation using opposite axisNote(1)Restriction: when x axis orientation setting is opposite axis, y axis orientation cannot be ownaxis. Same restriction applies when x axis orientation setting is own axis (mirror or not mirror),y axis orientation cannot be opposite axis.REG[1D1h] Bits 3-0REG[1D0h] Bits 7:0Some example settings:0 degree: 4’b0000horizontal mirror: 4’b0100vertical mirror: 4’b0001rotate CW 90: 4’b1110rotate CCW 90: 4’b1011These bits are the command decode:0x00: nop0x01: line draw0x02: rect draw0x03: ellipse draw0x04: transparent blt0x05: bitblt0x06: clut setup0x07: alpha blending0x08: stretchblt0x09: ropIn the color expansion mode, these 8 bits specifies the default alpha value.In the CLUT operation, these 8 bits specifies the color index to be set.In the alpha blending operation, these 8 bits is the default alpha in 16bpp modes.Solomon Systech Jul 2009 P 118/119 Rev 1.0SSD1926Application Note

Draw 2D Command FIFO StatusREG[1D2h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw2DAutoModeInType RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DCommandstartBit 1Bit 0Draw2D AutoMode inAfter setting up the appropriate parameters, set this bit to 1 and then set the draw2d commandstart bit (REG[1D2h] Bit 0) to 1. The draw2d operation’s start timing will switch to automode.In automode, the 2D engine will start only once after DV stream in non display period.There are some limitations in automode, 1) only a single command is possible, 2)draw2d_brush_win_start will be behave as designed. This is because DV window is doublebuffered, and we will have to find some way to specify a secondary destination address to 2Dengine. We’ve chosen draw2d_brush_win_start as the secondary destination address pointer.Note : ROP256 operations are not allowed in automode.Draw 2D Command start BitWrite this bit = 1, draw2d operation will be started.SSD1926Application NoteRev 1.0 P 119/120 Jul 2009 Solomon Systech

Draw 2D Source Window Start Address Register 0REG[1D4h]Bit 7 6 5 4 3 2 1 0Draw 2DWindowSrc StartAddressBit 7Draw 2DWindowSrc StartAddressBit 6Draw 2DWindowSrc StartAddressBit 5Draw 2DWindowSrc StartAddressBit 4Draw 2DWindowSrc StartAddressBit 3Draw 2DWindowSrc StartAddressBit 2Draw 2DWindowSrc StartAddressBit 1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DWindowSrc StartAddressBit 0Draw 2D Source Window Start Address Register 1REG[1D5h]Bit 7 6 5 4 3 2 1 0Draw 2DWindowSrc StartAddressBit 15Draw 2DWindowSrc StartAddressBit 14Draw 2DWindowSrc StartAddressBit 13Draw 2DWindowSrc StartAddressBit 12Draw 2DWindowSrc StartAddressBit 11Draw 2DWindowSrc StartAddressBit 10Draw 2D 1WindowSrc StartAddressBit 9Draw 2DWindowSrc StartAddressBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Source Window Start Address Register 2REG[1D6h]Bit 7 6 5 4 3 2 1 0x Draw 2DWindowSrc StartAddressBit 22Draw 2DWindowSrc StartAddressBit 21Draw 2DWindowSrc StartAddressBit 20Draw 2DWindowSrc StartAddressBit 19Draw 2DWindowSrc StartAddressBit 18Draw 2DWindowSrc StartAddressBit 17Draw 2DWindowSrc StartAddressBit 16Type RO RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[1D6h] bits6-0,REG[1D5h] bits 7-0,REG[1D4h] bits 7-0Draw 2D Source Window Start Address Bits [22:0]These bits form the 16bit internal start address of draw2d source window in SSD1926 memorywith 64bit width (in term of bit per pixel).E.g. to specify a 1bpp source buffer located physically at ram address 0x0001, the value of thisregister should be 0x0040.This is a multi-usage registerIn bitBlt, alpha-blend, stretchblt, transparent blt operations, this register is the source windowstart address. When operations do not require a source window, it will not be interpreted as anaddress.In CLUT setup command, bits 15:0 is the {red, green} color of the table being set.In ellipse draw operation, bits 8:0 is ellipse’s center x coordinate and bits 17:9 is ellipse’s yclipping boundary.Solomon Systech Jul 2009 P 120/121 Rev 1.0SSD1926Application Note

Draw 2D Source Window Line Address Offset Register 0REG[1D8h]Bit 7 6 5 4 3 2 1 0Draw 2DSrcWindowLineAddressOffset Bit 7Draw 2DSrcWindowLineAddressOffset Bit 6Draw 2DSrcWindowLineAddressOffset Bit 5Draw 2DSrcWindowLineAddressOffset Bit 4Draw 2DSrcWindowLineAddressOffset Bit 3Draw 2DSrcWindowLineAddressOffset Bit 2Draw 2DSrcWindowLineAddressOffset Bit 1Draw 2DSrcWindowLineAddressOffset Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Source Window Line Address Offset Register 1REG[1D9h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DSrcWindowLineAddressOffset Bit 9Draw 2DSrcWindowLineAddressOffset Bit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[1D9h] bits 1-0,REG[1D8h] bits 7-0Draw 2D Source Window Line Address Offset Bits [9:0]This register is the screen pixel width, (not necessarily same as draw2d window width)Draw 2D Source Window Color ModeREG[1DChBit 7 6 5 4 3 2 1 00 0 0 0 0 SRC ColorBit 2SRC ColorBit 1SRC ColorBit 0Type RO RO RO RO RO RW RW RWResetstate0 0 0 0 0 0 0 0REG[1DCh] Bits 2-0 Source Window Color Bits [2:0]000 : 16 bpp001 : 32 bpp010 : YUV100 : 1 bpp101 : 8 bppDraw 2D Destination Window Color Mode RegisterREG[1DDh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DDestWindowColor ModeBit 1Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[1DDh] Bits 1-0 Destination Window Color Bits [1:0]00 : 16 bpp01 : 32 bpp10 : YUVDraw 2DDestWindowColor ModeBit 0SSD1926Application NoteRev 1.0 P 121/122 Jul 2009 Solomon Systech

Draw 2D Source Window Width Register 0REG[1E4h]Bit 7 6 5 4 3 2 1 0Draw 2DSrcWindowWidthBit 7Draw 2DSrcWindowWidthBit 6Draw 2DSrcWindowWidthBit 5Draw 2DSrcWindowWidthBit 4Draw 2DSrcWindowWidthBit 3Draw 2DSrcWindowWidthBit 2Draw 2DSrcWindowWidthBit 1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DSrcWindowWidthBit 0Draw 2D Source Window Width Register 1REG[1E5h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DSrcWindowWidthBit 9Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DSrcWindowWidthBit 8REG[1E5h] bits 1-0,REG[1E4h] bits 7-0Draw 2D Source Window Width Register [9:0]This is a multi purpose registerIn line draw mode, this register is the starting x coordinate of the line drawnFor “blting” operations (alpha blend, stretchblt, bitblt etc), this register is the width of thesource window (in pixel). Alpha blend is for RGB mode only. In YUV mode, this value shouldbe a multiple of 2 (This limitation is not applicable in RGB mode).In ellipse draw mode, this register is the y coordinate of the ellipse’s center.Draw 2D Source Window Height Register 0REG[1E8h]Bit 7 6 5 4 3 2 1 0Draw 2DSrcWindowHeightBit 7Draw 2DSrcWindowHeightBit 6Draw 2DSrcWindowHeightBit 5Draw 2DSrcWindowHeightBit 4Draw 2DSrcWindowHeightBit 3Draw 2DSrcWindowHeightBit 2Draw 2DSrcWindowHeightBit 1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DSrcWindowHeightBit 0Draw 2D Source Window Height Register 1REG[1E9h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DSrcWindowHeightBit 9Draw 2DSrcWindowHeightBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateSolomon Systech Jul 2009 P 122/123 Rev 1.0SSD1926Application Note

REG[1E9h] bits 1-0,REG[1E8h] bits 7-0Draw 2D Source Window Height Register [9:0]This is a multi purpose registerFor “blting” operations (alpha blend, stretchblt, bitblt etc), this register is the height of thesource window (in pixel).In line draw mode, this register is the starting y coordinateIn ellipse draw mode, this register is the “radius” of the ellipse in x axis.Draw 2D Destination Window Width Register 0REG[1ECh]Bit 7 6 5 4 3 2 1 0Draw 2DDestWindowWidthBit 7Draw 2DDestWindowWidthBit 6Draw 2DDestWindowWidthBit 5Draw 2DDestWindowWidthBit 4Draw 2DDestWindowWidthBit 3Draw 2DDestWindowWidthBit 2Draw 2DDestWindowWidthBit 1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DDestWindowWidthBit 0Draw 2D Destination Window Width Register 1REG[1EDh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DDestWindowWidthBit 9Draw 2DDestWindowWidthBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[1EDh] bits 1-0,REG[1ECh] bits 7-0Draw 2D Destination Window Width Register [9:0]This is a multi purpose registerFor stretchblt operation, this is the width of destination window in pixel. In YUV mode, thisvalue should be a multiple of 2 (This limitation is not applicable in RGB mode).In line draw mode, this register is the ending x coordinateIn ellipse draw mode, this register is the starting angle of the ellipse (360 < register value < 0 )SSD1926Application NoteRev 1.0 P 123/124 Jul 2009 Solomon Systech

Draw 2D Destination Window Height Register 0REG[1F0h]Bit 7 6 5 4 3 2 1 0Draw 2DDestWindowHeightBit 7Draw 2DDestWindowHeightBit 6Draw 2DDestWindowHeightBit 5Draw 2DDestWindowHeightBit 4Draw 2DDestWindowHeightBit 3Draw 2DDestWindowHeightBit 2Draw 2DDestWindowHeightBit 1Draw 2DDestWindowHeightBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Destination Window Y Height Register 1REG[1F1h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DDestWindowHeightBit 9Draw 2DDestWindowHeightBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[1F1h] bits 1-0,REG[1F0h] bits 7-0Draw 2D Destination Window Height Register [9:0]This is a multi-purpose registerIn stretch blit operation, this register is the height of destination window in pixel.In line draw operation, this register is the ending y coordinate.In ellipse draw operation, this register is the “radius” of the ellipse in y axis.Draw 2D Destination Window Start Address Register 0REG[1F4h]Bit 7 6 5 4 3 2 1 0Draw 2DDestWindowStartAddressBit 7Draw 2DDestWindowStartAddressBit 6Draw 2DDestWindowStartAddressBit 5Draw 2DDestWindowStartAddressBit 4Draw 2DDestWindowStartAddressBit 3Draw 2DDestWindowStartAddressBit 2Draw 2DDestWindowStartAddressBit 1Draw 2DDestWindowStartAddressBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Destination Window Start Address Register 1REG[1F5h]Bit 7 6 5 4 3 2 1 0Draw 2DDestWindowStartAddressBit 15Draw 2DDestWindowStartAddressBit 14Draw 2DDestWindowStartAddressBit 13Draw 2DDestWindowStartAddressBit 12Draw 2DDestWindowStartAddressBit 11Draw 2DDestWindowStartAddressBit 10Draw 2DDestWindowStartAddressBit 9Draw 2DDestWindowStartAddressBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateSolomon Systech Jul 2009 P 124/125 Rev 1.0SSD1926Application Note

Draw 2D Destination Window Start Address Register 2REG[1F6h]Bit 7 6 5 4 3 2 1 00 Draw 2DDestWindowStartAddressBit 22Draw 2DDestWindowStartAddressBit 21Draw 2DDestWindowStartAddressBit 20Draw 2DDestWindowStartAddressBit 19Draw 2DDestWindowStartAddressBit 18Draw 2DDestWindowStartAddressBit 17Type RO RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DDestWindowStartAddressBit 16REG[1F6h] bits 6-0,REG[1F5h] bits 7-0,REG[1F4h] bits 7-0Draw 2D Destination Window Start Address Bits [22:0]These bits form the 16bit internal start address of draw2d destination window in SSD1926memory with 64bit width (in term of bit per pixel).E.g. to specify a 1bpp destination buffer located at physically ram address 0x0001, the value ofthis register should be 0x0040.This is a multi-usage registerThis register is the destination window start address of all draw2d operations, expect CLUTsetup.In the CLUT setup command, bits 15:0 is the {blue, alpha} color of the table being set.Draw 2D Destination Window Line Address Offset Register 0REG[1f8h]Bit 7 6 5 4 3 2 1 0Draw 2DLineAddressOffset Bit 7Draw 2DLineAddressOffset Bit 6Draw 2DLineAddressOffset Bit 5Draw 2DLineAddressOffset Bit 4Draw 2DLineAddressOffset Bit 3Draw 2DLineAddressOffset Bit 2Draw 2DLineAddressOffset Bit 1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DLineAddressOffset Bit 0Draw 2D Destination Window Line Address Offset Register 1REG[1f9h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DLineAddressOffset Bit 9Draw 2DLineAddressOffset Bit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[1D9h] bits 1-0,REG[1D8h] bits 7-0Draw Destination Window Line Address Offset Bits [9:0]This register is the number of pixels between lines inside the display screen size.SSD1926Application NoteRev 1.0 P 125/126 Jul 2009 Solomon Systech

Draw 2D Write Value Pattern (Command Parameter) Register 0REG[1FCh]Bit 7 6 5 4 3 2 1 0Draw 2DWindowWritePatternBit 7Draw 2DWindowWritePatternBit 6Draw 2DWindowWritePatternBit 5Draw 2DWindowWritePatternBit 4Draw 2DWindowWritePatternBit 3Draw 2DWindowWritePatternBit 2Draw 2DWindowWritePatternBit 1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DWindowWritePatternBit 0Draw 2D Window Write Pattern (Command Parameter) Register 1 REG[1FDh]Bit 7 6 5 4 3 2 1 0Draw 2DWindowWritePatternBit 15Draw 2DWindowWritePattern Bit14Draw 2DWindowWritePatternBit 13Draw 2DWindowWritePatternBit 12Draw 2DWindowWritePatternBit 11Draw 2DWindowWritePatternBit 10Draw 2DWindowWritePatternBit 9Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2DWindowWritePatternBit 8Draw 2D Window Write Pattern (Command Parameter) Register 2 REG[1FEh]Bit 7 6 5 4 3 2 1 0Draw 2DWindowWritePattern Bit23Draw 2DWindowWritePattern Bit22Draw 2DWindowWritePatternBit 21Draw 2DWindowWritePatternBit 20Draw 2DWindowWritePatternBit 19Draw 2DWindowWritePatternBit 18Draw 2DWindowWritePatternBit 17Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Draw 2DWindowWritePatternBit 16REG[1FEh] bits 7-0,REG[1FDh] bits 7-0,REG[1FCh] bits 7-0Draw 2D Window Write Pattern Bits [23:0]Multi-purpose registerIn ROP mode, [7:0] marks the ROP code specified by Microsoft’s ROP3 operation.In transparent blt mode, this register represents the transparent color’s BGR value. However,since this register is 24bit in width, when a 16bit color is compared to, the 16bit red color willbe shifted left by 3, Green is shifted left by 2, and blue shifted left by 2.In alpha blending mode, [1:0] is 2 different modes:2’b00 => Microsoft pre-blend:dst = (src * const_alpha + dst * (255-const_alpha)) / 2552’b01 => Microsoft pre-blend2:if (draw2d_cmd[7:0] == 7’hff)dst = src + (1 – src.alpha/255) * dstelse // 2 cycle blendingdst = (src + (1 – src.alpha) * dst) * const_alpha2’b10, 2’b11 => reserved modeIn drawing lines, ellipse, this register is the {R,G,B} colorSolomon Systech Jul 2009 P 126/127 Rev 1.0SSD1926Application Note

Draw 2D Brush Window Start Address Register 0REG[204h]Bit 7 6 5 4 3 2 1 0Draw 2DBrushWindowStartAddressBit 7Draw 2DBrushWindowStartAddressBit 6Draw 2DBrushWindowStartAddressBit 5Draw 2DBrushWindowStartAddressBit 4Draw 2DBrushWindowStartAddressBit 3Draw 2DBrushWindowStartAddressBit 2Draw 2DBrushWindowStartAddressBit 1Draw 2DBrushWindowStartAddressBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Brush Window Start Address Register 1REG[205h]Bit 7 6 5 4 3 2 1 0Draw 2DBrushWindowStartAddressBit 15Draw 2DBrushWindowStartAddressBit 14Draw 2DBrushWindowStartAddressBit 13Draw 2DBrushWindowStartAddressBit 12Draw 2DBrushWindowStartAddressBit 11Draw 2DBrushWindowStartAddressBit 10Draw 2DBrushWindowStartAddressBit 9Draw 2DBrushWindowStartAddressBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Brush Window Start Address Register 2REG[206h]Bit 7 6 5 4 3 2 1 00 Draw 2DBrushWindowStartAddressBit 22Draw 2DBrushWindowStartAddressBit 21Draw 2DBrushWindowStartAddressBit 20Draw 2DBrushWindowStartAddressBit 19Draw 2DBrushWindowStartAddressBit 18Draw 2DBrushWindowStartAddressBit 17Draw 2DBrushWindowStartAddressBit 16Type RO RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0state6REG[206h] bits 6-0,REG[205h] bits 7-0,REG[204h] bits 7-0Draw 2D Brush Window Start Address Bits [22:0]These bits form the 16bit internal start address of draw2d brush window in SSD1926 memoryfor ROP operation (in term of bit per pixel).E.g. to specify a 1bpp destination buffer located at physically ram address 0x0001, the value ofthis register should be 0x0040.Draw 2D Brush Window Line Address Offset Register 0REG[208h]Bit 7 6 5 4 3 2 1 0Draw 2DBrush LineAddressOffset Bit 7Draw 2DBrush LineAddressOffset Bit 6Draw 2DBrush LineAddressOffset Bit 5Draw 2DBrush LineAddressOffset Bit 4Draw 2DBrush LineAddressOffset Bit 3Draw 2DBrush LineAddressOffset Bit 2Draw 2DBrush LineAddressOffset Bit 1Draw 2DBrush LineAddressOffset Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateSSD1926Application NoteRev 1.0 P 127/128 Jul 2009 Solomon Systech

Draw 2D brush Window Line Address Offset Register 1REG[209h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DBrush LineAddressOffset Bit 9Draw 2DBrush LineAddressOffset Bit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[209h] bits 1-0,REG[208h] bits 7-0Draw Brush Window Line Address Offset Bits [9:0]This register is the width of the pattern in memory in terms of number of pixelsDraw 2D Brush Window width Register 0REG[214h]Bit 7 6 5 4 3 2 1 0Draw 2DBrushWindowWidthBit 7Draw 2DBrushWindowWidthBit 6Draw 2DBrushWindowWidthBit 5Draw 2DBrushWindowWidthBit 4Draw 2DBrushWindowWidthBit 3Draw 2DBrushWindowWidthBit 2Draw 2DBrushWindowWidthBit 1Draw 2DBrushWindowWidthBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDraw 2D Brush Window Width Register 1REG[215h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DBrushWindowWidthBit 9Draw 2DBrushWindowWidthBit 8Type RO RO RO RO RO RO RW RWReset 0 0 0 0 0 0 0 0stateREG[215h] bits 1-0,REG[214h] bits 7-0Draw 2D Brush Window Width[9:0]This register is the operation region width. Note that “operation width” is not necessarily equalto Brush Window line offset (i.e. line offset is related to the brush’s layout in memory, whileone might choose a smaller part of the brush to operate on)Draw 2D Brush Window Height Register 0REG[[218h]Bit 7 6 5 4 3 2 1 0Draw 2DBrushWindowHeightBit 7Draw 2DBrushWindowHeightBit 6Draw 2DBrushWindowHeightBit 5Draw 2DBrushWindowHeightBit 4Draw 2DBrushWindowHeightBit 3Draw 2DBrushWindowHeightBit 2Draw 2DBrushWindowHeightBit 1Draw 2DBrushWindowHeightBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateSolomon Systech Jul 2009 P 128/129 Rev 1.0SSD1926Application Note

Draw 2D brush Window Y Height Register 1REG[219h]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Draw 2DBrushWindowHeightBit 9Draw 2DBrushWindowHeightBit 8Type RO RO RO RO RO RO RW RWResetstate0 0 0 0 0 0 0 0REG[219h] bits 1-0,REG[218h] bits 7-0Draw 2D Brush Window Height Register [9:0]This register is Draw2D Brush Window height.Draw 2D Command FIFO Interrupt enableREG[21Ch]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Reserved Draw 2DCommandFIFOInterruptEnableType RO RO RO RO RO RO RW RWResetstate0 0 0 0 0 0 0 0Bit 1Bit 0Reserved bitThis bit should be programmed as 0.Draw 2D Command FIFI Interrupt EnableWhen this bit = 1 : Enable Command FIFO Ready.When this bit = 0 : Enable Command FIFO Busy.Draw 2D Command FIFO Interrupt StatusREG[21Eh]Bit 7 6 5 4 3 2 1 00 0 0 0 0 0 Reserved Draw 2Dcmd fifostatus flagType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bit 1Bit 0Reserved bitDraw 2D Cmd FIFO Status FlagWhen this bit = 1: Cmd FIFO ready. Write 1 to clear the flag .Write 0 has not hardware effectWhen this bit = 0 : BusyRaw Draw 2D Command FIFO FLAGREG[220h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved RawDraw2DCommandStatus flagType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 1Bit 1Bit 0Reserved bitRAW Draw 2D CMD status flagWhen this bit = 1 : ReadyWhen this bit = 0 : BusySSD1926Application NoteRev 1.0 P 129/130 Jul 2009 Solomon Systech

2.18 JPEG Decode Registers2.18.1 Decode Procedure1) Enable the JPEG Codec (REG[380h] bit 0 = 1).2) Initialize the JPEG Codec registers.a) Software reset the JPEG Codec (REG[402h] bit 7 = 1).b) Set operation mode to decode (REG[400h] bit 2).c) Set JPEG MJPEG Mode (REG[400h] bit 5).d) Set the RST Marker Operation Setting (REG[41Ch] bit 1-0).3) Initialize the JPEG module registers (i.e. JPEG Line Buffer and FIFO).a) Set the JPEG Source Start Address (REG[410h] – REG[412h]).b) Set the JPEG Destination Address (REG[414h] – REG[416h]).c) Set the JPEG FIFO Size (REG[3A4h]).d) Set the JPEG File Size (REG[3B8h] – REG[3BAh]).e) Set JPEG YUV Output Data Range Select (REG[380h] bit 4).4) Start the decode process:a) Clear all status of JPEG Line Buffer and FIFO (REG[382h] – REG[383h] = 0000h).b) Enable required interrupts (REG[386h] – REG[387h]).c) Start JPEG operation (REG[402h] bit 0 = 1).d) Start decoding (REG[38Ah] bit 0 = 1).5) Write data to JPEG FIFO (REG[414h – REG[416h]]6) Wait for FIFO condition is met (i.e Empty/Half-Full/Quad-Full) by interrupt or polling. If Decode MarkerRead Interrupt is detected, read the Vertical Pixel Size (REG[3DCh] – REG[3DDh]) and Horizontal PixelSize (REG[3D8h] – REG[3D9h]) and set the registers for display.7) Repeat steps 5 and 6 until the end of file.8) Wait for JPEG Decode Complete Flag (REG[383h] bit 5) .9) Verify the decode process is complete with the JPEG Operation Status (REG[404h] bit 0 = 0).Note: 64-bit unit data is required to write to the JPEG FIFO. Pad the end of the JPEG data stream with 8’h00sto complete the last 64-bit data for the last FIFO entry is necessary.Followings description for Error Handling:If JPEG Codec Interrupt Flag is high and both the Decode Marker Read Interrupt and JPEG Decode CompleteInterrupt are low, the JPEG codec encountered error in the JPEG data stream and cannot finish decoding.Check the JPEG Operation Status and JPEG Error Status for debug.If RST Marker Operation is set to enable the data revise function, JPEG codec may finish decoding even ifthe JPEG data stream is corrupted. In this case, the decode process is complete according to steps 1 and 9 buta corrupted JPEG image will be displayed. Check the RST Revise Code to confirm if a revise operation isdone and the type of error is indicated by the JPEG Error Status.Solomon Systech Jul 2009 P 130/131 Rev 1.0SSD1926Application Note

JPEG Control RegisterREG[380h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved YUVOutputData RangeSelectReserved Reserved Reserved JPEGModuleEnableType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-5Bit 4Reserved bitsThese bits should be programmed by 0.YUV Output Data Range SelectThe YUV output range depends on the display data range.Table 2-28: YUV Output Range SelectionREG[0380h] bit 401YUV Output Data Range0 =< Y =< 255-128 =< U =< 127-128 =< V =< 1270 =< Y =< 2550 =< U =< 2550 =< V =< 255Bits 3-1Bit 0Reserved bitsThese bits should be programmed by 0.JPEG Module EnableThis bit enables/disables the JPEG module and its associated registers.When this bit = 1, the JPEG module is enabled and a clock source is supplied.When this bit = 0, the JPEG module is disabled and the clock source is disabled.JPEG Status Flag Register 0REG[382h]Bit 7 6 5 4 3 2 1 0Reserved Reserved JPEG FIFOThresholdStatus Bit 1JPEG FIFOThresholdStatus Bit 0ReservedJPEG FIFOThresholdTriggerFlagJPEG FIFOFull FlagJPEG FIFOEmpty FlagType RW RO RO RO RW RW RW RWReset 0 0 0 0 0 0 0 0stateBit 7Bit 6Reserved bitThis bit should be programmed as 0.Reserved bitBit 5-4 JPEG FIFO Threshold Status bits [1:0]These bits indicate how much data is currently in the JPEG FIFO. See the JPEG FIFO Sizeregister (REG[03A4h]) for information on setting the JPEG FIFO size.Table 2-29: JPEG FIFO Threshold StatusREG[0382h] bits 5-4JPEG FIFO Threshold Status00 no data (same as empty)01 more than 4 bytes of data exist10 more than 1/4 of specified FIFO size data exists11 more than 1/2 of specified FIFO size data existsSSD1926Application NoteRev 1.0 P 131/132 Jul 2009 Solomon Systech

Bit 3Bit 2Bit 1Bit 0Reserved bitThis bit should be programmed as 0.JPEG FIFO Threshold Trigger FlagThis flag is asserted when the amount of data in the JPEG FIFO meets the condition specifiedby the JPEG FIFO Trigger Threshold bits (REG[03A0h] bits 5-4). This flag is masked by theJPEG FIFO Threshold Trigger Interrupt Enable bit and is only available when REG[0386h] bit2 = 1.For Reads:When this bit = 1, the amount of data in the JPEG FIFO has reached the JPEG FIFO TriggerThreshold.When this bit = 0, the amount of data in the JPEG FIFO is less than the JPEG FIFO TriggerThreshold.For Writes:When a 1 is written to this bit, the FIFO Threshold Trigger Flag is cleared.When a 0 is written to this bit, there is no hardware effect.JPEG FIFO Full FlagThis flag is asserted when the JPEG FIFO is full. This flag is masked by the JPEG FIFO FullInterrupt Enable bit and is only available when REG[0386h] bit 1 = 1.For Reads:When this bit = 1, the JPEG FIFO is full.When this bit = 0, the JPEG FIFO is not full.For Writes:When a 1 is written to this bit, the JPEG FIFO Full Flag is cleared.When a 0 is written to this bit, there is no hardware effect.JPEG FIFO Empty FlagThis flag is asserted when the JPEG FIFO is empty. This flag is masked by the JPEG FIFOEmpty Interrupt Enable bit and is only available when REG[0386h] bit 0 = 1.For Reads:When this bit = 1, the JPEG FIFO is empty.When this bit = 0, the JPEG FIFO is not empty.For Writes:When a 1 is written to this bit, the JPEG FIFO Empty Flag is cleared.When a 0 is written to this bit, there is no hardware effect.JPEG Status Flag Register 1REG[383h]Bit 7 6 5 4 3 2 1 0Reserved Reserved JPEG JPEG Reserved JPEG JPEG ReservedDecodeCompleteFlagDecodeMarkerReadFlagLineBufferOverflowFlagCodecInterruptFlagType RW RW RW RW RW RO RO RWResetstate0 0 0 0 0 0 0 0Bits 7-6Bit 5Reserved bitsThese bits should be programmed by 0.JPEG Decode Complete FlagThis flag is asserted when the JPEG decode operation is finished. This flag is masked by theJPEG Decode Complete Interrupt Enable bit and is only available when REG[0387h] bit 5 = 1.For Reads:When this bit = 1, the JPEG decode operation is finished.When this bit = 0, the JPEG decode operation is not finished yet.For Writes:When a 1 is written to this bit after disabling the interrupt, this bit is cleared.When a 0 is written to this bit, there is no hardware effect.Solomon Systech Jul 2009 P 132/133 Rev 1.0SSD1926Application Note

Bit 4Bit 3Bit 2Bit 1Bit 0JPEG Decode Marker Read FlagThis flag is asserted during the JPEG decoding process when decoded marker information isread from the JPEG file. This flag is masked by the JPEG Decode Marker Read InterruptEnable bit and is only available when REG[0387h] bit 4 = 1.For Reads:When this bit = 1, a JPEG decode marker has been read.When this bit = 0, a JPEG decode marker has not been read.For Writes:When a 1 is written to this bit after disabling the interrupt, this bit is cleared.When a 0 is written to this bit, there is no hardware effect.Reserved bitThis bit should be programmed by 0.JPEG Line Buffer Overflow FlagThis flag is asserted when a JPEG Line Buffer overflow occurs. This flag is masked by theJPEG Line Buffer Overflow Interrupt Enable bit and is only available when REG[387h] bit 2 =1.When this bit = 1, a JPEG Line Buffer overflow has occurred.When this bit = 0, a JPEG Line Buffer overflow has not occurred.To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).JPEG Codec Interrupt FlagThis flag is asserted when the JPEG codec generates an interrupt. This flag is masked by theJPEG Codec Interrupt Enable bit and is only available when REG[0387h] bit 1 = 1).When this bit = 1, the JPEG codec has generated an interrupt.When this bit = 0, the JPEG codec has not generated an interrupt.To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).Reserved bitThis bit should be programmed by 0.JPEG RAW Status Flag Register 0REG[384h]Bit 7 6 5 4 3 2 1 0Reserved Reserved JPEG FIFOThresholdStatus Bit 1JPEG FIFOThresholdStatus Bit 0ReservedRaw JPEGFIFOThresholdTriggerFlagRaw JPEGFIFO FullFlagType RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateRaw JPEGFIFOEmpty FlagBits 7-6Reserved bitBits 5-4 JPEG FIFO Threshold Status bits [1:0]These bits indicate how much data is currently in the JPEG FIFO. See the JPEG FIFO SizeRegister (REG[3A4h] for information on setting the JPEG FIFO Size.Table 2-30: JPEG FIFO Threshold StatusREG[0384h] bits 5-4JPEG FIFO Threshold Status00 no data (same as empty)01 more than 4 bytes of data exist10 more than 1/4 of specified FIFO size data exists11 more than 1/2 of specified FIFO size data existsSSD1926Application NoteRev 1.0 P 133/134 Jul 2009 Solomon Systech

Bit 3Bit 2Bit 1Bit 0Reserved bitRaw JPEG FIFO Threshold Trigger FlagThis flag is asserted when the amount of data in the JPEG FIFO meets the condition specifiedby the JPEG FIFO Trigger Threshold bits (REG[3A0] bits 5-4). This flag is not affected by theJPEG FIFO Threshold Trigger Interrupt Enable bit (REG[386h] bit 2).When this bit = 1, the amount of data in the JPEG FIFO has reached the JPEG FIFO TriggerThreshold.When this bit = 0, the amount of data in the JPEG FIFO is less than the JPEG FIFO TriggerThreshold.To clear this flag, write a 1 to the JPEG FIFO Threshold Trigger Flag (REG[382h] bit 2 = 1).Raw JPEG FIFO Full FlagThis flag is asserted when the JPEG FIFO is full. This flag is not affected by the JPEGFIFO Full Interrupt Enable bit (REG[386h] bit 1).When this bit = 1, the JPEG FIFO is full.When this bit = 0, the JPEG FIFO is not full.To clear this flag, write a 1 to the JPEG FIFO Full Flag (REG[382h] bit 1 = 1).Raw JPEG FIFO Empty FlagThis flag is asserted when the JPEG FIFO is empty. This flag is not affected by the JPEG FIFOEmpty Interrupt Enable bit (REG[386h] bit 0).When this bit = 1, the JPEG FIFO is empty.When this bit = 0, the JPEG FIFO is not empty.To clear this flag, write a 1 to the JPEG FIFO Empty Flag (REG[382h] bit 0 = 1).JPEG RAW Status Flag Register 1REG[385h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Raw JPEG Raw JPEG Reserved Raw JPEG Raw JPEG ReservedDecodeCompleteFlagDecodeMarkerRead FlagLine BufferOverflowFlagCodecInterruptFlagType RW RW RO RO RW RO RO RWResetstate0 0 0 0 0 0 0 0Bits 7-6Bit 5Bit 4Bit 3Bit 2Reserved bitsThese bits should be programmed by 0.Raw JPEG Decode Complete FlagThis flag is asserted when the JPEG decode operation is finished and ready to display.This flag is not affected by the JPEG Decode Complete Interrupt Enable bit (REG[387h] bit 5).When this bit = 1, the JPEG decode operation is finished.When this bit = 0, the JPEG decode operation is not finished yet.To clear this flag, write a 1 to the JPEG Decode Complete Flag (REG[383h] bit 5 = 1).Raw JPEG Decode Marker Read FlagThis flag is asserted during the JPEG decoding process when decoded marker information isread from the JPEG file.When this bit = 1, a JPEG decode marker has been read.When this bit = 0, a JPEG decode marker has not been read.To clear this flag, write a 1 to the JPEG Decode Marker Read Flag (REG[383h] bit 4 = 1).Reserved bitThis bit should be programmed by 0.Raw JPEG Line Buffer Overflow FlagThis flag is asserted when a JPEG Line Buffer overflow occurs. This flag is not affected by theJPEG Line Buffer Overflow Interrupt Enable (REG[387h] bit 2).When this bit = 1, a JPEG Line Buffer overflow has occurred.When this bit = 0, a JPEG Line Buffer overflow has not occurred.To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).Solomon Systech Jul 2009 P 134/135 Rev 1.0SSD1926Application Note

Bit 1Bit 0Raw JPEG Codec Interrupt FlagThis flag is asserted when an interrupt is generated by the JPEG codec. This flag is not affectedby the JPEG Codec Interrupt Enable bit (REG[387h] bit 1).When this bit = 1, the JPEG codec has generated an interrupt.When this bit = 0, no interrupt has been generated.To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).Reserved bitThis bit should be programmed by 0.JPEG Interrupt Control Register 0REG[386h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved JPEG FIFOThresholdTriggerInterruptEnableJPEG FIFOFullInterruptEnableJPEG FIFOEmptyInterruptEnableType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-3Bit 2Bit 1Bit 0Reserved bitsThis bit should be programmed as 0.JPEG FIFO Threshold Trigger Interrupt EnableThis bit controls the JPEG FIFO threshold trigger interrupt. The status of this interrupt can bedetermined using the JPEG FIFO Threshold Trigger Flag bit (REG[382h] bit 2).When this bit = 1, the interrupt is enabled.When this bit = 0, the interrupt is disabled.JPEG FIFO Full Interrupt EnableThis bit controls the JPEG FIFO full interrupt. The status of this interrupt can be determinedusing the JPEG FIFO Full Flag bit (REG[382h] bit 1).When this bit = 1, the interrupt is enabled.When this bit = 0, the interrupt is disabled.JPEG FIFO Empty Interrupt EnableThis bit controls the JPEG FIFO empty interrupt. The status of this interrupt can be determinedusing the JPEG FIFO Empty Flag bit (REG[382h] bit 0).When this bit = 1, the interrupt is enabled.When this bit = 0, the interrupt is disabled.JPEG Interrupt Control Register 1REG[387h]Bit 7 6 5 4 3 2 1 0Reserved Reserved JPEG JPEG Reserved JPEG Line JPEG ReservedDecodeCompleteInterruptEnableDecodeMarkerReadInterruptEnableBufferOverflowInterruptEnableCodecInterruptEnableType RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-6Bit 5Reserved bitsThese bits should be programmed by 0.JPEG Decode Complete Interrupt EnableThis bit controls the JPEG decode complete interrupt. The status of this interrupt can bedetermined using the JPEG Decode Complete Flag bit (REG[383h] bit 5).When this bit = 1, the interrupt is enabled.When this bit = 0, the interrupt is disabled.SSD1926Application NoteRev 1.0 P 135/136 Jul 2009 Solomon Systech

Bit 4Bit 3Bit 2Bit 1Bit 0JPEG Decode Marker Read Interrupt EnableThis bit controls the JPEG decode marker read interrupt. The status of this interrupt can bedetermined using the JPEG Decode Marker Read Flag (REG[383h] bit 4).When this bit = 1, the interrupt is enabled.When this bit = 0, the interrupt is disabled.Reserved bitThis bit should be programmed by 0.JPEG Line Buffer Overflow Interrupt EnableThis bit controls the JPEG Line Buffer overflow interrupt. The status of this interrupt can bedetermined using the JPEG Line Buffer Overflow Flag (REG[383h] bit 2).When this bit = 1, the interrupt is enabled.When this bit = 0, the interrupt is disabled.JPEG Codec Interrupt EnableThis bit controls the JPEG codec interrupt. The status of this interrupt can be determined usingthe JPEG Codec Interrupt Flag (REG[383h] bit 1).When this bit = 1, the interrupt is enabled.When this bit = 0, the interrupt is disabled.Reserved bitThis bit should be programmed by 0.JPEG Code Start / Stop Control Register)REG[38Ah]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved JPEGStart/StopControlType RW RW RW RW RW RW RW WOResetstate0 0 0 0 0 0 0 0Bits 7-1Bit 0Reserved bitsThese bits should be programmed by 0.JPEG Start/Stop ControlThis bit controls the JPEG decode mode.When this bit is set to 1, the JPEG codec starts to decode the image.When this bit is set to 0, the JPEG codec will be ready to read the JPEG markers.JPEG FIFO Control RegisterREG[3A0h]Bit 7 6 5 4 3 2 1 0Reserved Reserved JPEG FIFO JPEG FIFO Reserved Reserved Reserved ReservedTriggerThresholdBit 1TriggerThresholdBit 0Type RW RW RW RW RW RW RO RWResetstate0 0 0 0 0 0 0 0Bits 7-6Reserved bitsThese bits should be programmed by 0.Bit 5-4 JPEG FIFO Trigger Threshold bits [1:0]These bits set the JPEG FIFO Threshold Trigger Flag (REG[382h] bit 2) when the specifiedconditions are met.Solomon Systech Jul 2009 P 136/137 Rev 1.0SSD1926Application Note

Table 2-31: JPEG FIFO Trigger Threshold SelectionREG[03A0h] bits 5-4JPEG FIFO Trigger Threshold00 Never trigger01 Trigger when the JPEG FIFO contains 4 bytes of data ormore10 Trigger when the JPEG FIFO contains more than 1/4 ofthe specified JPEG FIFO size (REG[3A4h] bits 6-0)11 Trigger when the JPEG FIFO contains more than 1/2 ofthe specified JPEG FIFO size (REG[3A4h] bits 6-0)Bits 3-2Bit 1Bit 0Reserved bitsThis bit should be programmed by 0.Reserved bitReserved bitThis bit should be programmed by 0.JPEG FIFO Status RegisterREG[3A2h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved JPEG FIFOThresholdStatus Bit 1JPEG FIFOThresholdStatus Bit 0JPEG FIFOFull StatusJPEG FIFOEmptyStatusType RW RW RW RW RO RO RO ROReset 0 0 0 0 0 0 0 0stateBits 7-4Reserved bitsThese bits should be programmed by 0.Bit 3-2 JPEG FIFO Threshold Status bits [1:0]These bits indicate the amount of data in the JPEG FIFO.Table 2-32: JPEG FIFO Threshold StatusREG[03A2h] bits 3-2JPEG FIFO Threshold Status00 No data (Same as Empty)01 4 bytes of data or more exists10 More than 1/4 of the specified JPEG FIFO size data exists(see REG[03A4h] bits 6-0)11 More than 1/2 of the specified JPEG FIFO size data exists(see REG[03A4h] bits 6-0)Bit 1Bit 0JPEG FIFO Full StatusThis bit indicates whether the JPEG FIFO is full.When this bit = 1, the JPEG FIFO is full.When this bit = 0, the JPEG FIFO is not full.JPEG FIFO Empty StatusThis bit indicates that the JPEG FIFO is empty.When this bit = 1, the JPEG FIFO is empty.When this bit = 0, the JPEG FIFO is not empty.SSD1926Application NoteRev 1.0 P 137/138 Jul 2009 Solomon Systech

JPEG FIFO Size RegisterREG[3A4h]Bit 7 6 5 4 3 2 1 0Reserved JPEG FIFOSize Bit 6JPEG FIFOSize Bit 5JPEG FIFOSize Bit 4JPEG FIFOSize Bit 3JPEG FIFOSize Bit2JPEG FIFOSize Bit 1JPEG FIFOSize Bit 0Type RW RW RW RW RO RO RO ROResetstate0 0 0 0 0 0 0 0Bit 7Reserved bitThis bit should be programmed by 0.Bits 6-0 JPEG FIFO Size bits [6:0]These bits determine the JPEG FIFO size in 4K byte units. The maximum size of theJPEG FIFO is 512K bytes. These bits also specify the amount of memory reserved for the JPEGFIFO.JPEG FIFO size = (REG[3A4h] bits 6-0 + 1) x 4K bytesJPEG File Size Register 0REG[3B8h]Bit 7 6 5 4 3 2 1 0JPEG FileSize Bit 7JPEG FileSize Bit 6JPEG FileSize Bit 5JPEG FileSize Bit 4JPEG FileSize Bit 3JPEG FileSize Bit 2JPEG FileSize Bit 1JPEG FileSize Bit 0Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0JPEG File Size Register 1REG[3B9h]Bit 7 6 5 4 3 2 1 0JPEG FileSize Bit 15JPEG FileSize Bit 14JPEG FileSize Bit 13JPEG FileSize Bit 12JPEG FileSize Bit 11JPEG FileSize Bit 10JPEG FileSize Bit 9JPEG FileSize Bit 8Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0JPEG File Size Register 2REG[3BAh]Bit 7 6 5 4 3 2 1 0JPEG FileSize Bit 23JPEG FileSize Bit 22JPEG FileSize Bit 21JPEG FileSize Bit 20JPEG FileSize Bit 19JPEG FileSize Bit 18JPEG FileSize Bit 17JPEG FileSize Bit 16Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[3BAh] Bits 7-0,REG[3B9h] Bits 7-0,REG[3B8h] Bits 7-0JPEG File Size bits [23:0]These bits specify the JPEG file size in bytes and must be set before the Host begins writingdecoded data to the JPEG FIFO.Solomon Systech Jul 2009 P 138/139 Rev 1.0SSD1926Application Note

JPEG Decode Horizontal Pixel Size Register 0REG[3D8h]Bit 7 6 5 4 3 2 1 0JPEGDecodeHorizontalPixel SizeBit 7JPEGDecodeHorizontalPixel SizeBit 6JPEGDecodeHorizontalPixel SizeBit 5JPEGDecodeHorizontalPixel SizeBit 4JPEGDecodeHorizontalPixel SizeBit 3JPEGDecodeHorizontalPixel SizeBit 2JPEGDecodeHorizontalPixel SizeBit 1JPEGDecodeHorizontalPixel SizeBit 0Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateJPEG Decode Horizontal Pixel Size Register 1REG[3D9h]Bit 7 6 5 4 3 2 1 0JPEGDecodeHorizontalPixel SizeBit 15JPEGDecodeHorizontalPixel SizeBit 14JPEGDecodeHorizontalPixel SizeBit 13JPEGDecodeHorizontalPixel SizeBit 12JPEGDecodeHorizontalPixel SizeBit 11JPEGDecodeHorizontalPixel SizeBit 10JPEGDecodeHorizontalPixel SizeBit 9JPEGDecodeHorizontalPixel SizeBit 8Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateREG[3D9h] Bits 7-0,REG[3D8h] Bits 7-0JPEG Decode Horizontal Pixel Size bits [15:0]These bits specify the horizontal image size during JPEG decode process.JPEG Decode Vertical Pixel Size Register 0REG[3DCh]Bit 7 6 5 4 3 2 1 0JPEGDecodeVerticalPixel SizeBit 7JPEGDecodeVerticalPixel SizeBit 6JPEGDecodeVerticalPixel SizeBit 5JPEGDecodeVerticalPixel SizeBit 4JPEGDecodeVerticalPixel SizeBit 3JPEGDecodeVerticalPixel SizeBit 2JPEGDecodeVerticalPixel SizeBit 1JPEGDecodeVerticalPixel SizeBit 0Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateJPEG Decode Vertical Pixel Size Register 1REG[3DDh]Bit 7 6 5 4 3 2 1 0JPEGDecodeVerticalPixel SizeBit 15JPEGDecodeVerticalPixel SizeBit 14JPEGDecodeVerticalPixel SizeBit 13JPEGDecodeVerticalPixel SizeBit 12JPEGDecodeVerticalPixel SizeBit 11JPEGDecodeVerticalPixel SizeBit 10JPEGDecodeVerticalPixel SizeBit 9JPEGDecodeVerticalPixel SizeBit 8Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateREG[3DDh] Bits 7-0,REG[3DCh] Bits 7-0JPEG Decode Vertical Pixel Size bits [15:0]These bits specify the vertical image size during JPEG decode process.SSD1926Application NoteRev 1.0 P 139/140 Jul 2009 Solomon Systech

JPEG Operation Mode Setting RegisterREG[400h]Bit 7 6 5 4 3 2 1 0Reserved Reserved MJPEG Reserved Reserved Reserved Reserved ReservedModeType RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0Bits 7-6Bit 5Bits 4, 3, 1, 0Bit 2Reserved bitsThese bits should be programmed by 0.MJPEG modeThis bit determines if Motion JPEG mode is used for decode process.When this bit = 1, Motion JPEG mode is used.When this bit = 0, Still JPEG mode is used.Reserved bitsThis bit should be programmed by 0.Reserved bitThis bit should be programmed by 1.JPEG Operation Mode Setting RegisterREG[401h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved YUVDecodeFormatBit 1YUVDecodeFormatBit 0Type RW RW RW RW RW RW RO ROResetstate0 0 0 0 0 0 0 0Bits 7-2Reserved bitsThese bits should be programmed by 0.Bits 1-0 YUV Decode Format bits [1:0]These bits indicate the YUV format of the data being decoded.Table 2-33: YUV Format SelectionREG[401h] bits 1-0 YUV Format00 4:4:401 4:2:210 4:2:011 4:1:1JPEG Command Setting RegisterREG[402h]Bit 7 6 5 4 3 2 1 0JPEGCodecSWResetReserved Reserved Reserved Reserved Reserved Reserved JPEGOperationStartType WO RW RW RW RW RW RW WOReset 0 0 0 0 0 0 0 0stateBit 7JPEG Codec Software ResetThis bit initiates a software reset of the JPEG Codec. The JPEG Codec registers(REG[400h]-[9A2h]) are not affected.When a 1 is written to this bit, the JPEG Codec is reset.When a 0 is written to this bit, there is no hardware effect.Solomon Systech Jul 2009 P 140/141 Rev 1.0SSD1926Application Note

Bits 6-1Bit 0Reserved bitsThese bits should be programmed by 0.JPEG Operation StartThis bit is used to begin a JPEG operation.When a 1 is written to this bit, the JPEG operation is started.When a 0 is written to this bit, there is no hardware effect.JPEG Operation Status RegisterREG[404h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved JPEGOperationStatusType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Bits 7-1Bit 0Reserved bitJPEG Operation StatusThis bit indicates the state of the JPEG codec.When this bit = 1, the JPEG codec is busy (decode operation is in progress).When this bit = 0, the JPEG codec is idle.JPEG Decode Quantization Table Number RegisterREG[407h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Color 3QTableSelectColor 2QTableSelectType RW RW RW RW RW RO RO ROReset 0 0 0 0 0 0 0 0stateColor 1QTableSelectBit 7-3Bit 2Bit 1Bit 0Reserved bitsThese bits should be programmed by 0.Color 3 QTable SelectThis bit indicates the Quantization Table used by Color 3.Color 2 QTable SelectThis bit indicates the Quantization Table used by Color 2.Color 1 QTable SelectThis bit indicates the Quantization Table used by Color 1.JPEG Decode Huffman Table RegisterREG[408h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Color 3 ACHTableSelectColor 3 DCHTableSelectColor 2 ACHTableSelectColor 2 DCHTableSelectColor 1 ACHTableSelectType RW RW RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateColor 1 DCHTableSelectBit 7-6Bit 5Bit 4Reserved bitsThese bits should be programmed by 0.Color 3 AC HTable SelectThis bit indicated the AC Huffman Table used by Color 3.Color 3 DC HTable SelectThis bit indicated the DC Huffman Table used by Color 3.SSD1926Application NoteRev 1.0 P 141/142 Jul 2009 Solomon Systech

Bit 3Bit 2Bit 1Bit 0Color 2 AC HTable SelectThis bit indicated the AC Huffman Table used by Color 2.Color 2 DC HTable SelectThis bit indicated the DC Huffman Table used by Color 2.Color 1 AC HTable SelectThis bit indicated the AC Huffman Table used by Color 1.Color 1 DC HTable SelectThis bit indicated the DC Huffman Table used by Color 1.JPEG Decode DRI Setting Register 0REG[40Ah]Bit 7 6 5 4 3 2 1 0JPEGDecodeDRI Settingbit 7JPEGDecodeDRI Settingbit 6JPEGDecodeDRI Settingbit 5JPEGDecodeDRI Settingbit 4JPEGDecodeDRI Settingbit 3JPEGDecodeDRI Settingbit 2JPEGDecodeDRI Settingbit 1Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateJPEG Decode DRI Setting Register 1REG[40Bh]Bit 7 6 5 4 3 2 1 0JPEGDecodeDRI Settingbit 15JPEGDecodeDRI Settingbit 14JPEGDecodeDRI Settingbit 13JPEGDecodeDRI Settingbit 12JPEGDecodeDRI Settingbit 11JPEGDecodeDRI Settingbit 10JPEGDecodeDRI Settingbit 9Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateJPEGDecodeDRI Settingbit 0JPEGDecodeDRI Settingbit 8REG [40Bh] bits 7-0,REG [40Ah] bits 7-0JPEG Decode DRI Setting bits [15:0]These bits indicate DRI Setting used for the JPEG decode process.JPEG Line Buffer Start Address Register 0REG[410h]Bit 7 6 5 4 3 2 1 0JPEG LineBuffer StartAddress Bit7JPEG LineBuffer StartAddress Bit6JPEG LineBuffer StartAddress Bit5JPEG LineBuffer StartAddress Bit4JPEG LineBuffer StartAddress Bit3JPEG LineBuffer StartAddress Bit2JPEG LineBuffer StartAddress Bit1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateJPEG Line Buffer Start Address Register 1REG[411h]Bit 7 6 5 4 3 2 1 0JPEG LineBuffer StartAddress Bit15JPEG LineBuffer StartAddress Bit14JPEG LineBuffer StartAddress Bit13JPEG LineBuffer StartAddress Bit12JPEG LineBuffer StartAddress Bit11JPEG LineBuffer StartAddress Bit10JPEG LineBuffer StartAddress Bit90JPEG LineBuffer StartAddress Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateSolomon Systech Jul 2009 P 142/143 Rev 1.0SSD1926Application Note

JPEG Line Buffer Start Address Register 2REG[412h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved JPEG LineBuffer StartAddress Bit17Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateJPEG LineBuffer StartAddress Bit16REG[412h] Bits 1-0,REG[411h] Bits 7-0,REG[410h] Bits 7-0REG[412h] Bits 7-2JPEG Line Buffer Start Address bits [17:0]Bit 0 must be program as 0.These bits define the start address for the JPEG Line Buffer.Reserved bitsThese bits should be programmed by 0.JPEG FIFO Start Address Register 0REG[414h]Bit 7 6 5 4 3 2 1 0JPEG FIFOStartAddress Bit7JPEG FIFOStartAddress Bit6JPEG FIFOStartAddress Bit5JPEG FIFOStartAddress Bit4JPEG FIFOStartAddress Bit3JPEG FIFOStartAddress Bit2JPEG FIFOStartAddress Bit1Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateJPEG FIFO Start Address Register 1REG[415h]Bit 7 6 5 4 3 2 1 0JPEG FIFOStartAddress Bit15JPEG FIFOStartAddress Bit14JPEG FIFOStartAddress Bit13JPEG FIFOStartAddress Bit12JPEG FIFOStartAddress Bit11JPEG FIFOStartAddress Bit10JPEG FIFOStartAddress Bit90JPEG FIFOStartAddress Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateJPEG FIFO Start Address Register 2REG[416h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved JPEG FIFOStartAddress Bit17JPEG FIFOStartAddress Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[416h] Bits 1-0,REG[415h] Bits 7-0,REG[414h] Bits 7-0REG[416h] Bits 7-2JPEG FIFO Start Address bits [17:0]Bit 0 must be program as 0These bits define the start address for the JPEG FIFO.Reserved bitsThese bits should be programmed by 0.SSD1926Application NoteRev 1.0 P 143/144 Jul 2009 Solomon Systech

JPEG DNL Value Setting Register 0REG[418h]Bit 7 6 5 4 3 2 1 0DNL ValueBit 7DNL ValueBit 6DNL ValueBit 5DNL ValueBit 4DNL ValueBit 3DNL ValueBit 2DNL ValueBit 1DNL ValueBit 0Type RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0JPEG DNL Value Setting Register 1REG[419h]Bit 7 6 5 4 3 2 1 0DNL ValueBit 15DNL ValueBit 14DNL ValueBit 13DNL ValueBit 12DNL ValueBit 11DNL ValueBit 10DNL ValueBit 9DNL ValueBit 8Type RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[419h] Bits 7-0,REG[418h] Bits 7-0DNL Value bits [15:0]These bits are read-only and indicate the DNL value.JPEG RST Marker Operation Setting RegisterREG[41Ch]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved RSTMarkerOperationSelect Bit 1RSTMarkerOperationSelect Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBits 7-2Reserved bitsThese bits should be programmed by 0.Bit 1-0 RST Marker Operation Select bits [1:0]These bits select the RST Marker Operation.Table 2-34: RST Marker SelectionREG[41Ch] bits 1-0RST Marker Operation00 Error detection and data revise function is turned offThis option should only be used when it is certain that the JPEG file tobe decoded is correct and has no errors. If there is an error in the file,no error detection will take place and the decode process will not finishcorrectly.01 Error detection onWhen an error is detected during the decode process, the decodeprocess finishes and the JPEG interrupt is asserted (REG[48h] bit 2 =1, to determine the exact nature of the error see REG[382h]). Becausethe decode process finished before normal completion, all data can notbe displayed. If the JPEG file is to be decoded again with the DataRevise function on, a software reset is required (see REG[402h] bit 7).10 Data revise function onWhen an error is detected during the decode process, data isskipped/added automatically and the decode process continuesnormally to the end of file. After the decode process finishes, a datarevise interrupt is asserted. Because the decode process is finishedcompletely, the next JPEG file can be decoded immediately.11 ReservedSolomon Systech Jul 2009 P 144/145 Rev 1.0SSD1926Application Note

JPEG RST Marker Operation Status RegisterREG[41Eh]Bit 7 6 5 4 3 2 1 0Revise JPEG Error JPEG Error JPEG Error JPEG Error Reserved Reserved ReservedCode Status Bit 3 Status Bit 2 Status Bit 1 Status Bit 0Type RO RO RO RO RO RW RW RWResetstate0 0 0 0 0 0 0 0Bit 7Revise CodeThis bit indicates whether a revise operation has been done.When this bit = 1, a revise operation was done.When this bit = 0, a revise operation was not done.Bits 6-3 JPEG Error Status [3:0]For the JPEG decode process, these bits indicate the type of JPEG error. If these bits return0000, no error has occurred.Table 2-35: JPEG Error StatusREG[41Eh] bits 6-3JPEG Error Status0000 No error0001 – 1010 Reserved1011 Restart interval error1100 Image size error1101 - 1111 ReservedBits 2-0Reserved bitsThese bits should be programmed by 0.2.19 MMC/SD/SDIO RegistersThe detailed description for registers of SDHC module (REG[1001h-11FFh]) were referred to Part A2, SDHost Controller Standard Specification i .The detailed description for the SDHC was referred to Part 1, Physical Layer Specification ii .Notei Part A2, SD Host Controller Standard Specification, Version 1.0, February 2004ii Part 1, Physical Layer Specification, Version 1.01SD_CLK Divider RegisterREG[1001h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved SD_CLKDivisorType RO RO RO RO RO RW RW RWResetstate0 0 0 0 0 0 0 1REG[1001h] Bits 7-1Reserved bitsREG[1001h] Bit 0SD_CLK Divisor bitThis bit divides the MCLK by 2 for SD_CLK. It is enabled by default.Bit 0 = 1 : SD_CLK = MCLK / 2Bit 0 = 0 : SD_CLK = MCLK.The SD_CLK output will be further divides by REG[112Dh].SSD1926Application NoteRev 1.0 P 145/146 Jul 2009 Solomon Systech

DMA System Address Register 0REG[1100h]Bit 7 6 5 4 3 2 1 0DMAAddress Bit7DMAAddress Bit6DMAAddress Bit5DMAAddress Bit4DMAAddress Bit3DMAAddress Bit2DMAAddress Bit1DMAAddress Bit0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDMA System Address Register 1REG[1101h]Bit 7 6 5 4 3 2 1 0DMAAddress Bit15DMAAddress Bit14DMAAddress Bit13DMAAddress Bit12DMAAddress Bit11DMAAddress Bit10DMAAddress Bit9DMAAddress Bit8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDMA System Address Register 2REG[1102h]Bit 7 6 5 4 3 2 1 0DMAAddress Bit23DMAAddress Bit22DMAAddress Bit21DMAAddress Bit20DMAAddress Bit19DMAAddress Bit18DMAAddress Bit17DMAAddress Bit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateDMA System Address Register 3REG[1103h]Bit 7 6 5 4 3 2 1 0DMAAddress Bit31DMAAddress Bit30DMAAddress Bit29DMAAddress Bit28DMAAddress Bit27DMAAddress Bit26DMAAddress Bit25DMAAddress Bit24Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[1100h] Bits 7-0,REG[1101h] Bits 7-0,REG[1102h] Bits 7-0,REG[1103h] Bits 7-0DMA System Address bits [31:0]This register contains the system memory address for a DMA transfer. Bits [31:16] are reservedand should programmed as ‘0’.When the Host Controller stops a DMA transfer, this register shall point to the system addressof the next contiguous data position. It can be accessed only if no transaction is executing (i.e.,after a transaction has stopped). Read operations during transfers may return an invalid value.The Host Driver shall initialize this register before starting a DMA transaction.After DMA has stopped, the next system address of the next contiguous data position can beread from this register.The DMA transfer waits at the every boundary specified by the Host DMA BufferBoundary in the Block Size register. The Host Controller generates DMA Interrupt to requestthe Host Driver to update this register. The Host Driver set the next system address of the nextdata position to this register. When the most upper byte of this register (REG[1103h]) iswritten, the Host Controller restart the DMA transfer.When restarting DMA by the Resume command or by setting Continue Request in the BlockGap Control register, the Host Controller shall start at the next contiguous address stored herein the System Address register.Solomon Systech Jul 2009 P 146/147 Rev 1.0SSD1926Application Note

Block size Register 0REG[1104h]Bit 7 6 5 4 3 2 1 0TransferBlock SizeBit 7TransferBlock SizeBit 6TransferBlock SizeBit 5TransferBlock SizeBit 4TransferBlock SizeBit 3TransferBlock SizeBit 2TransferBlock SizeBit 1TransferBlock SizeBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBlock size Register1REG[1105h]Bit 7 6 5 4 3 2 1 0ReservedDMABufferBoundaryBit 2DMABufferBoundaryBit 1DMABufferBoundaryBit 0TransferBlock SizeBit 11TransferBlock SizeBit 10TransferBlock SizeBit 9TransferBlock SizeBit 8Type RO RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[1105h] Bit 7 Reserved bitREG[1105h] Bits 6-4 Host DMA Buffer Boundary bits [2:0]The large contiguous memory space may not be available in the virtual memory system. Toperform long DMA transfer, System Address register shall be updated at every system memoryboundary during DMA transfer.These bits specify the size of contiguous buffer in the system memory in terms of bytegranularity. This requires the Host Controller to break the last access according to the left overcount of bytes.The DMA transfer shall wait at the every boundary specified by these fields and the HostController generates the DMA Interrupt to request the Host Driver to update the SystemAddress register.In case of this register is set to 0 (buffer size = 4K bytes), lower 12-bit of byte address pointsdata in the contiguous buffer and the upper 20-bit points the location of the buffer in the systemmemory. The DMA transfer stops when the Host Controller detects carry out of the addressfrom bit 11 to 12.These bits shall be supported when the DMA Support in the Capabilities register is set to 1and this function is active when the DMA Enable in the Transfer Mode register is set to 1.000b001b010b011b100b101b110b111b4K bytes (Detects A11 carry out)8K bytes (Detects A12 carry out)16K Bytes (Detects A13 carry out)32K Bytes (Detects A14 carry out)64K bytes (Detects A15 carry out)128K Bytes (Detects A16 carry out)256K Bytes (Detects A17 carry out)512K Bytes (Detects A18 carry out)SSD1926Application NoteRev 1.0 P 147/148 Jul 2009 Solomon Systech

REG[1104h] Bits 7-0,REG[1105h] Bits 3-0Transfer Block Size bits [11:0]This register specifies the block size for block data transfers for CMD17, CMD18, CMD24,CMD25, and CMD53 in terms of byte granularity. This requires the Host Controller to breakthe last access according to the left over count of bytes. Values ranging from 1 up to themaximum buffer size can be set (Refer to SD Specification [i] ‘Determining Buffer blocklength’). It can be accessed only if no transaction is executing (i.e., after a transaction hasstopped). Read operations during transfers may return an invalid value, and write operationsshall be ignored.0800h 2048 Bytes…0200h 512 Bytes01FFh 511 Bytes…0004h 4 Bytes0003h 3 Bytes0002h 2 Bytes0001h 1 Byte0000h No data transferBlock Count Register 0REG[1106h]Bit 7 6 5 4 3 2 1 0BlockCount Bit 7BlockCount Bit 6BlockCount Bit 5BlockCount Bit 4BlockCount Bit 3BlockCount Bit 2BlockCount Bit 1BlockCount Bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateBlock Count Register 1REG[1107h]Bit 7 6 5 4 3 2 1 0BlockCount Bit15BlockCount Bit14BlockCount Bit13BlockCount Bit12BlockCount Bit11BlockCount Bit10BlockCount Bit 9BlockCount Bit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[1106h] Bits 7-0,REG[1107h] Bits 7-0Block Count bits [15:0]This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 andis valid only for multiple block transfers. The Host Driver shall set this register to a valuebetween 1 and the maximum block count. The Host Controller decrements the block count aftereach block transfer and stops when the count reaches zero. Setting the block count to 0 resultsin no data blocks being transferred.This register should be accessed only when no transaction is executing (i.e., after transactionsare stopped). During data transfer, read operations on this register may return an invalid valueand write operations are ignored.When saving transfer context as a result of a Suspend command, the number of blocks yet to betransferred can be determined by reading this register. When restoring transfer context prior toissuing a Resume command, the Host Driver shall restore the previously saved block count.FFFFh 65535 blocks… …0002h 2 blocks0001h 1 block0000h Stop CountSolomon Systech Jul 2009 P 148/149 Rev 1.0SSD1926Application Note

Argument Register 0REG[1108h]Bit 7 6 5 4 3 2 1 0ArgumentBit 7ArgumentBit 6ArgumentBit 5ArgumentBit 4ArgumentBit 3ArgumentBit 2ArgumentBit 1ArgumentBit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateArgument Register 1REG[1109h]Bit 7 6 5 4 3 2 1 0ArgumentBit 15ArgumentBit 14ArgumentBit 13ArgumentBit 12ArgumentBit 11ArgumentBit 10ArgumentBit 9ArgumentBit 8Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateArgument Register 2REG[110Ah]Bit 7 6 5 4 3 2 1 0ArgumentBit 23ArgumentBit 22ArgumentBit 21ArgumentBit 20ArgumentBit 19ArgumentBit 18ArgumentBit 17ArgumentBit16Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateArgument Register 3REG[110Bh]Bit 7 6 5 4 3 2 1 0ArgumentBit 31ArgumentBit 30ArgumentBit 29ArgumentBit 28ArgumentBit 27ArgumentBit 26ArgumentBit 25ArgumentBit 24Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[1108h] Bits 7-0,REG[1109h] Bits 7-0,REG[110Ah] Bits 7-0,REG[110Bh] Bits 7-0Argument bits [31:0]This register contains the SD Command Argument.The SD Command Argument is specified as bit39-8 of Command-Format in the SD MemoryPhysical Layer Specification.Transfer Mode Register 0REG[110Ch]Bit 7 6 5 4 3 2 1 0Reserved Reserved Multi /SingleBlockSelectDataTransferDirectionSelectReservedAutoCMD12EnableBlockCountEnableDMAEnableType RO RO RW RW RO RW RW RWReset 0 0 0 0 0 0 0 0stateTransfer Mode Register 1REG[110Dh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0SSD1926Application NoteRev 1.0 P 149/150 Jul 2009 Solomon Systech

REG[110Ch] Bits 7,6,3REG[110Dh] Bits 7:0REG[110Ch] Bit 5REG[110Ch] Bit 4REG[110Ch] Bit 2REG[110Ch] Bit 1REG[110Ch] Bit 0Transfer Mode bits [15:0]This register is used to control the operation of data transfers. The Host Driver shall set thisregister before issuing a command which transfers data (see Data Present Select in theCommand register), or before issuing a Resume command. The Host Driver shall save the valueof this register when the data transfer is suspended (as a result of a Suspend command) andrestore it before issuing a Resume command. To prevent data loss, the Host Controller shallimplement write protection for this register during data transactions. Writes to this register shallbe ignored when the Command Inhibit (DAT) in the Present State register is 1.Reserved bitsMulti / Single Block SelectThis bit enables multiple block DATA line data transfers. For any other commands, this bitshall be set to 0. If this bit is 0, it is not necessary to set the Block Count register. (Refer toTable 1-45)1 Multiple Block0 Single BlockData Transfer Direction SelectThis bit defines the direction of DAT line data transfers. The bit is set to 1 by the Host Driver totransfer data from the SD card to the SD Host Controller and it is set to 0 for all othercommands.1 Read (Card to Host)0 Write (Host to Card)Auto CMD12 EnableMultiple block transfers for memory require CMD12 to stop the transaction. When this bit is setto 1, the Host Controller shall issue CMD12 automatically when last block transfer iscompleted. The Host Driver shall not set this bit to issue commands that do not require CMD12to stop data transfer. In particular, secure commands defined in the SD Specification [FileSecurity] do not require CMD12.1 Enable0 DisableBlock Count EnableThis bit is used to enable the Block Count register, which is only relevant for multiple blocktransfers. When this bit is 0, the Block Count register is disabled, which is useful in executingan infinite transfer. (Refer to Table 1-45)1 Enable0 DisableDMA EnableThis bit enables DMA functionality as described in SD Specification [i] ‘Supporting DMA’.DMA can be enabled only if it is supported as indicated in the DMA Support in theCapabilities register. If DMA is not supported, this bit is meaningless and shall always read 0.If this bit is set to 1, a DMA operation shall begin when the Host Driver writes to the upper byteof Command register REG[110Fh].1 Enable0 DisableTable 2-36 shows the summary of how register settings determine types of data transfer.Table 2-36: Determination of Transfer TypeMulti/Single Block Select Block Count Enable Block Count Function0 Don’t care Don’t care Single Transfer1 0 Don’t care Infinite Transfer1 1 Not Zero Multiple Transfer1 1 Zero Stop Multiple TransferSolomon Systech Jul 2009 P 150/151 Rev 1.0SSD1926Application Note

Command Register 0REG[110Eh]Bit 7 6 5 4 3 2 1 0CommandType Bit 1CommandType Bit 0DataPresentSelectCommandIndexCheckEnableCommandCRC CheckEnableReservedResponseType SelectBit 1ResponseType SelectBit 0Type RW RW RW RW RW RO RW RWReset 0 0 0 0 0 0 0 0stateCommand Register 1REG[110Fh]Bit 7 6 5 4 3 2 1 0Reserved Reserved CommandIndex Bit 5CommandIndex Bit 4CommandIndex Bit 3CommandIndex Bit 2CommandIndex Bit 1CommandIndex Bit 0Type RO RO RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[110Eh] Bit 2,REG[110Fh] Bits 7-6Command bits [15:0]The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD)bit in the Present State register before writing to this register. Writing to the upper byte of thisregister triggers SD command generation. The Host Driver has the responsibility to write thisregister because the Host Controller does not protect for writing when Command Inhibit(CMD) is set.Reserved bitsREG[110Fh] Bits 5-0 Command Index bits [5:0]These bits shall be set to the command number (CMD0-63, ACMD0-63) that is specified in bits45-40 of the Command-Format in the SD Memory Card Physical Layer Specification and SDIOCard Specification.REG[110Eh] Bits 7-6 Command Type bits [1:0]There are three types of special commands: Suspend, Resume and Abort. These bits shall be setto 00b for all other commands.(1) Suspend CommandIf the Suspend command succeeds, the Host Controller shall assume the SD Bus has beenreleased and that it is possible to issue the next command which uses the DAT line. The HostController shall de-assert Read Wait for read transactions and stop checking busy for writetransactions. The interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, theHost Controller shall maintain its current state, and the Host Driver shall restart the transfer bysetting Continue Request in the Block Gap Control register. (Refer to SD Specification [i]‘Suspend Sequence’)(2) Resume CommandThe Host Driver re-starts starts the data transfer by restoring the registers in the range of 000-00Dh. (Refer to SD Specification [i] ‘Suspend and Resume mechanism’ for the register map.)The Host Controller shall check for busy before starting write transfers.(3) Abort CommandIf this command is set when executing a read transfer, the Host Controller shall stop reads to thebuffer. If this command is set when executing a write transfer, the Host Controller shall stopdriving the DATA line. After issuing the Abort command, the Host Driver should issue asoftware reset. (Refer to SD Specification [i] ‘Abort Transaction’)11b Abort CMD12, CMD52 for writing “I/O Abort” inCCCR10b Resume CMD52 for writing “Function Select” in CCCR01b Suspend CMD52 for writing “Bus Suspend” in CCCR00b Normal Other commandsSSD1926Application NoteRev 1.0 P 151/152 Jul 2009 Solomon Systech

REG[110Eh] Bit 5REG[110Eh] Bit 4REG[110Eh] Bit 3Data Present SelectThis bit is set to 1 to indicate that data is present and shall be transferred using the DATA line.It is set to 0 for the following:(1) Commands using only CMD line (ex. CMD52).(2) Commands with no data transfer but using busy signal on SD_DATA[0] line (R1b or R5bex. CMD38)(3) Resume command1 Data Present0 No Data PresentCommand Index Check EnableIf this bit is set to 1, the Host Controller shall check the Index field in the response to see if ithas the same value as the command index. If it is not, it is reported as a Command Index Error.If this bit is set to 0, the Index field is not checked.1 Enable0 DisableCommand CRC Check EnableIf this bit is set to 1, the Host Controller shall check the CRC field in the response. If an error isdetected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is notchecked. The number of bits checked by the CRC field value changes according to the length ofthe response. (Refer to D01-00 and Table 2-38 below.)1 Enable0 DisableREG[110Eh] Bits 1-0 Response Type Select bits [1:0]Table 2-37: Command Register00 No Response01 Response Length 13610 Response Length 4811 Response Length 48 check Busy after responseThese bits determine Response types.Note(1)In the SDIO specification, response type notation of R5b is not defined. R5 includes R5b inthe SDIO specification. But R5b is defined in this specification to specify the Host Controllershall check busy after receiving response. For example, usually CMD52 is used as R5 but I/Oabort command shall be used as R5b.Implementation Note(1)The CRC field for R3 and R4 is expected to be all “1” bits. The CRC check should bedisabled for these response types.Table 2-38: Relation Between Parameters and the Name of Response TypeResponse Type Index Check Enable CRC Check Enable Name of Response Type00 0 0 No Response01 0 1 R210 0 0 R3, R410 1 1 R1, R6, R511 1 1 R1b, R5bSolomon Systech Jul 2009 P 152/153 Rev 1.0SSD1926Application Note

Response Register 15-0REG[1110h]-[111Fh]Bit 7 6 5 4 3 2 1 0ResponseBitResponseBitResponseBitResponseBitResponseBitResponseBitResponseBitResponseBitType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[1110h] Bits 7-0 toREG[111Fh] Bits 7-0Response bits [127:0]This register is used to store responses from SD cards.The Table 2-39 describes the mapping of command responses from the SD Bus to this registerfor each response type. In the table, R[] refers to a bit range within the response data astransmitted on the SD Bus, REP[] refers to a bit range within the Response register.The Response Field indicates bit positions of “Responses” defined in the SD Specification [ii].The Table 2-39 shows that most responses with a length of 48 (R[47:0]) have 32 bits of theresponse data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b(Auto CMD12 responses) have response data bits R[39:8] stored in the Response register atREP[127:96]. Responses with length 136 (R[135:0]) have 120 bits of the response data(R[127:8]) stored in the Response register at REP[119:0].To be able to read the response status efficiently, the Host Controller only stores part of theresponse data in the Response register. This enables the Host Driver to efficiently read 32 bitsof response data in one read cycle on a 32-bit bus system. Parts of the response, the Index fieldand the CRC, are checked by the Host Controller (as specified by the Command Index CheckEnable and the Command CRC Check Enable bits in the CommandRegister REG[110Eh-110Fh]) and generate an error interrupt if an error is detected. The bitrange for the CRC check depends on the response length. If the response length is 48, the HostController shall check R[47:1], and if the response length is 136 the Host Controller shall checkR[119:1].Since the Host Controller may have a multiple block data DAT line transfer executingconcurrently with a CMD_wo_DAT command, the Host Controller stores the Auto CMD12response in the upper bits (REP[127:96]) of the Response register. The CMD_wo_DATresponse is stored in REP[31:0]. This allows the Host Controller to avoid overwriting the AutoCMD12 response with the CMD_wo_DAT and vice versa.When the Host Controller modifies part of the Response register, as shown in the Table 2-39, itshall preserve the unmodified bits.Table 2-39: Response Bit Definition for Each Response TypeKind of Response Meaning of Response Response Field Response RegisterR1, R1b (normal response) Card Status R [39:8] REP [31:0]R1b (Auto CMD12 Card Status for Auto R [39:8] REP [127:96]response)CMD12R2 (CID, CSD register) CID or CSD reg. incl. R [127:8] REP [119:0]R3 (OCR register) OCR register for memory R [39:8] REP [31:0]R4 (OCR register) OCR register for I/O etc R [39:8] REP [31:0]R5,R5b SDIO response R [39:8] REP [31:0]R6 (Published RCAresponse)New published RCA[31:16]etcR [39:8] REP [31:0]SSD1926Application NoteRev 1.0 P 153/154 Jul 2009 Solomon Systech

Data Port Register 0REG[1120h]Bit 7 6 5 4 3 2 1 0Data PortBit 7Data PortBit 6Data PortBit 5Data PortBit 4Data PortBit 3Data PortBit 2Data PortBit 1Data PortBit 0Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateData Port Register 1REG[1121h]Bit 7 6 5 4 3 2 1 0Data PortBit 15Data PortBit 14Data PortBit 13Data PortBit 12Data PortBit 11Data PortBit 10Data PortBit 9Data PortBit 8Type RO RO RO RO RO RO RO RORese 0 0 0 0 0 0 0 0tstateData Port Register 2REG[1122h]Bit 7 6 5 4 3 2 1 0Data PortBit 23Data PortBit 22Data PortBit 21Data PortBit 20Data PortBit 19Data PortBit 18Data PortBit 17Data PortBit 16Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateData Port Register 3REG[1123h]Bit 7 6 5 4 3 2 1 0Data PortBit 31Data PortBit 30Data PortBit 29Data PortBit 28Data PortBit 27Data PortBit 26Data PortBit 25Data PortBit 24Type RW RW RW RW RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[1120h] Bits 7-0,REG[1121h] Bits 7-0,REG[1122h] Bits 7-0,REG[1123h] Bits 7-0Data Port bits [31:0]The Data Port Register shall be accessible via the MCU interface in 8-bit read and write modesonly.Present State Register 0REG[1124h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved DATA LineActiveCommandInhibit(DAT)CommandInhibit(CMD)Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0statePresent State Register 1REG[1125h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved BufferReadEnableBufferWriteEnableReadTransferActiveWriteTransferActiveType RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateSolomon Systech Jul 2009 P 154/155 Rev 1.0SSD1926Application Note

Present State Register 2REG[1126h]Bit 7 6 5 4 3 2 1 0DATA[3:0]Line SignalLevel Bit 3DATA[3:0]Line SignalLevel Bit 2DATA[3:0]Line SignalLevel Bit 1DATA[3:0]Line SignalLevel Bit 0WriteProtectSwitch PinLevelCard DetectPin LevelCard StateStableCardInsertedType RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0statePresent State Register 3REG[1127h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved CMD LineSingleLevelType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Present State bits [31:0]The Host Driver can get status of the Host Controller from this 32-bit read only register.REG[1124h] Bits 7-3,REG[1125h] Bits 7-4,REG[1127h] Bits 7-1REG[1127h] Bit 0REG[1126h] Bits 7-4REG[1126h] Bit 3REG[1126h] Bit 2REG[1126h] Bit 1Reserved bitsCMD Line Signal LevelThis status is used to check the SD_CMD line level to recover from errors, and for debugging.DATA[3:0] Line Signal LevelThis status is used to check the DATA line level to recover from errors, and for debugging.This is especially useful in detecting the busy signal level from SD_DATA[0]Bit 7 SD_DATA[3]Bit 6 SD_DATA[2]Bit 5 SD_DATA[1]Bit 4 SD_DATA[0]Write Protect Switch Pin LevelThe Write Protect Switch is supported for memory and combo cards.This bit reflects the SD_WP pin1 Write Enabled (SD_WP = 1)0 Write Disabled (SD_WP = 0)Card Detect Pin LevelThis bit reflects the inverse value of the SD_CD pin. Debouncing is not performed on this bit.This bit may be valid when Card State Stable is set to 1, but it is not guaranteed because ofpropagation delay. Use of this bit is limited to testing since it must be debounced by software1 Card present (SD_CD = 0)0 No card present (SD_CD = 1)Card State StableThis bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to1, it means the Card Detect Pin Level is stable. No Card state can be detected by this bit is setto 1 and Card Inserted is set to 0. The Software Reset For All in the Software Reset registershall not affect this bit.1 No Card or Inserted0 Reset or DebouncingSSD1926Application NoteRev 1.0 P 155/156 Jul 2009 Solomon Systech

REG[1126h] Bit 0REG[1125h] Bit 3REG[1125h] Bit 2REG[1125h] Bit 1Card InsertedThis bit indicates whether a card has been inserted. The Host Controller shall debounce thissignal so that the Host Driver will not need to wait for it to stabilize. Changing from 0 to 1generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from1 to 0 generates a Card Removal interrupt in the Normal Interrupt Status register. TheSoftware Reset For All in the Software Reset register shall not affect this bit.If a card is removed while its power is on and its clock is oscillating, the Host Controller shallclear SD Bus Power in the Power Control register (REG[1129h]) and SD Clock Enable in theClock Control register (REG[112Ch]). In addition, the Host Driver should clear the HostController by the Software Reset For All in Software Reset register. The card detect is activeregardless of the SD Bus Power.1 Card Inserted0 Reset or Debouncing or No CardImplementation Note: The Host Controller starts in “Reset” state at power on and changes tothe “Debouncing” state once the debouncing clock is valid. In the “Debouncing” state, if theHost Controller detects that the signal (SD_CD) is stable during the debounce period, the stateshall change to “Card Inserted” or “No Card”. If the card is removed while in the “CardInserted” state, it will immediately change to the “Debouncing” state. Since the card detectsignal is then not stable, the Host Controller will change to the “Debouncing” state.Buffer Read EnableThis status is used for non-DMA read transfers.The Host Controller may implement multiple buffers to transfer data efficiently. This read onlyflag indicates that valid data exists in the host side buffer status. If this bit is 1, readable dataexists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read fromthe buffer. A change of this bit from 0 to 1 occurs when block data is ready in the buffer andgenerates the Buffer Read Ready interrupt.1 Read enable0 Read disableBuffer Write EnableThis status is used for non-DMA write transfers.The Host Controller can implement multiple buffers to transfer data efficiently. This read onlyflag indicates if space is available for write data. If this bit is 1, data can be written to the buffer.A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A changeof this bit from 0 to 1 occurs when top of block data can be written to the buffer and generatesthe Buffer Write Ready interrupt.1 Write enable0 Write disableRead Transfer ActiveThis status is used for detecting completion of a read transfer. Refer to SD specification [i]‘Read transaction wait / continue timing’ for sequence details.This bit is set to 1 for either of the following conditions:(1) After the end bit of the read command.(2) When writing a 1 to Continue Request in the Block Gap Control register to restart a readtransfer.This bit is cleared to 0 for either of the following conditions::(1) When the last data block as specified by block length is transferred to the System.(2) When all valid data blocks have been transferred to the System and no currentblock transfers are being sent as a result of the Stop At Block Gap Request being set to 1.A Transfer Complete interrupt is generated when this bit changes to 0.1 Transferring data0 No valid dataSolomon Systech Jul 2009 P 156/157 Rev 1.0SSD1926Application Note

REG[1125h] Bit 0REG[1124h] Bit 2Write Transfer ActiveThis status indicates a write transfer is active. If this bit is 0, it means no valid write data existsin the Host Controller. Refer to SD Specification [i] ‘Write transaction wait / continue timing’for more details on the sequence of events.This bit is set in either of the following cases:(1) After the end bit of the write command.(2) When writing a 1 to Continue Request in the Block Gap Control register to restart a writetransfer.This bit is cleared in either of the following cases:(1) After getting the CRC status of the last data block as specified by the transfer count(Single and Multiple)(2) After getting the CRC status of any block where data transmission is about to be stopped bya Stop At Block Gap Request.During a write transaction, a Block Gap Event interrupt is generated when this bit is changedto 0, as result of the Stop At Block Gap Request being set. This status is useful for the HostDriver in determining when to issue commands during write busy.1 Transferring data0 No valid dataDATA Line ActiveThis bit indicates whether one of the DATA line on SD Bus is in use.(a) In the case of read transactionsThis status indicates if a read transfer is executing on the SD Bus. Changes in this value from 1to 0 between data blocks generates a Block Gap Event interrupt in the Normal Interrupt Statusregister. Refer to SD Specification [i] ‘Read transaction wait/continue timing’ for details ontiming.This bit shall be set in either of the following cases:(1) After the end bit of the read command.(2) When writing a 1 to Continue Request in the Block Gap Control register torestart a read transfer.This bit shall be cleared in either of the following cases:(1) When the end bit of the last data block is sent from the SD Bus to the HostController.(2) When beginning a wait read transfer at a stop at the block gap initiated by a Stop At BlockGap Request.The Host Controller shall wait at the next block gap by driving Read Wait at the start of theinterrupt cycle. If the Read Wait signal is already driven (data buffer cannot receive data), theHost Controller can wait for current block gap by continuing to drive the Read Wait signal. It isnecessary to support Read Wait in order to use the suspend / resume function.(b) In the case of write transactionsThis status indicates that a write transfer is executing on the SD Bus. Changes in thisvalue from 1 to 0 generate a Transfer Complete interrupt in the Normal Interrupt Statusregister. Refer to SD Specification [i] ‘Write transaction wait/continue timing’ for sequencedetails.This bit shall be set in either of the following cases:(1) After the end bit of the write command.(2) When writing to 1 to Continue Request in the Block Gap Control register to continue awrite transfer.This bit shall be cleared in either of the following cases:(1) When the SD card releases write busy of the last data block the Host Controller shall alsodetect if output is not busy. If SD card does not drive busy signal for 8SD Clocks, the Host Controller shall consider the card drive “Not Busy”.(2) When the SD card releases write busy prior to waiting for write transfer as a result of a StopAt Block Gap Request.1 DATA Line Active0 DATA Line InactiveSSD1926Application NoteRev 1.0 P 157/158 Jul 2009 Solomon Systech

REG[1124h] Bit 1REG[1124h] Bit 0Command Inhibit (DAT)This status bit is generated if either the DATA Line Active or the Read Transfer Active is setto 1. If this bit is 0, it indicates the Host Controller can issue the next SD Command.Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type).Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal Interrupt Statusregister.Note(1)The SD Host Driver can save registers in the range of 000-00Dh for a suspend transactionafter this bit has changed from 1 to 0.1 Cannot issue command which uses the DATA line0 Can issue command which uses the DATA lineCommand Inhibit (CMD)If this bit is 0, it indicates the CMD line is not in use and the Host Controller can issue a SDCommand using the CMD line.This bit is set immediately after the Command register (00Fh) is written. This bit is clearedwhen the command response is received. Even if the Command Inhibit (DAT) is set to 1,Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0generates a Command Complete interrupt in the Normal Interrupt Status register. If the HostController cannot issue the command because of a command conflict error (Refer to CommandCRC Error (REG[1132h]) or because of Command Not Issued By Auto CMD12 Error(REG[113Ch]), this bit shall remain 1 and the Command Complete is not set.Status issuing Auto CMD12 is not read from this bit.1 Cannot issue command0 Can issue command using only CMD lineImplementation Note(1)The Host Driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for SDIO) when the DATA lines arebusy during data transfer. These commands can be issued when Command Inhibit (CMD) is set to zero.Other commands shall be issued when Command Inhibit (DAT) is set to zero. Possible changes to the SDPhysical Specification may add other commands to this list in the future.Implementation Note(1)Some fields defined in the Present State Register change values asynchronous to the system clock. TheSystem reads these statuses through the System Bus Interface and it may require data stable period during bus cycle. TheHost Controller should sample and hold values during reads from this register according to the timing required by theSystem Bus Interface specification.Figure 2-35 to Figure 2-37 show the timing of setting and clearing the Command Inhibit (DAT) and theCommand Inhibit (CMD).Figure 2-35: Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transferSolomon Systech Jul 2009 P 158/159 Rev 1.0SSD1926Application Note

Figure 2-36: Timing of Command Inhibit (DAT) for the case of response with busyFigure 2-37: Timing of Command Inhibit (CMD) for the case of no response commandHost Control RegisterREG[1128h]Bit 7 6 5 4 3 2 1 0ReservedBitReservedBitReservedBitReservedBitReservedBitReservedBitDataTransferWidthLEDControlType RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateREG[1128h] Bits 7-2Reserved bitsREG[1128h] Bit 1REG[1128h] Bit 0Data Transfer Width bitThis bit selects the data width of the Host Controller. The Host Driver shall set it to match thedata width of the SD card.1 4 bit mode0 1 bit modeLED Control bitThis bit is used to caution the user not to remove the card while the SD card is being accessed.If the software is going to issue multiple SD commands, this bit can be set during all thesetransactions. It is not necessary to change for each transaction.If this bit = 1, LED onIf this bit = 0, LED offSSD1926Application NoteRev 1.0 P 159/160 Jul 2009 Solomon Systech

Power Control RegisterREG[1129h]Bit 7 6 5 4 3 2 1 0ReservedBitReservedBitReservedBitReservedBitSD BusVoltageSelect Bit 2SD BusVoltageSelect Bit 1SD BusVoltageSelect Bit 0SD BusPower BitType RO RO RO RO RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[1129h] Bits 7-4Reserved bitsREG[1129h] Bits 3-1 SD Bus Voltage bits [2:0]By setting these bits, the Host Driver selects the voltage level for the SD card. Before settingthis register, the Host Driver shall check the Voltage Support bits in the Capabilities register.If an unsupported voltage is selected, the Host System shall not supply SD Bus voltage.SD Bus Voltage bits [2:0] SD Bus Voltage111 3.3V110-000 ReservedREG[1129h] Bit 0 SD Bus Power bitBefore setting this bit, the SD Host Driver shall set SD Bus Voltage Select. If the HostController detects the No Card state, this bit shall be cleared.If this bit = 1, Power onIf this bit = 0, Power offImplementation Note(1)Basically, the Host Driver has responsibility to supply SD Bus voltage by SD Bus Power, according to SD card OCRand supply voltage capabilities depend on the Host System.If the Host Driver selects an unsupported voltage in the SD Bus Voltage Select field, the Host Controller may ignorewrites to SD Bus Power and keep its value at zero.Implementation Note(1)The Host System shall not supply SD Bus power when SD Bus Power is set to 0 and can supply SD Bus power whenSD Bus Power is set to 1 depending on the system conditions (ex. Left of the battery).Reserved RegisterREG[112Ah]Bit 7 6 5 4 3 2 1 0ReservedBitReservedBitReservedBitReservedBitReservedBitReservedBitReservedBitReservedBitType RO RO RO RO RW RW RW RWResetstate0 0 0 0 0 0 0 0REG[112Ah] Bits 7-0Reserved bitsWake Up Control RegisterREG[112Bh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved WakeEventEnable onSD CardRemovalWakeEventEnable onSD CardInsertionWakeEventEnable onSD CardInterruptType RO RO RO RO RO RW RW RWReset 0 0 0 0 0 0 0 0stateSolomon Systech Jul 2009 P 160/161 Rev 1.0SSD1926Application Note

REG[112Bh] Bits 7-3Reserved bitREG[112Bh] Bit 2REG[112Bh] Bit 1REG[112Bh] Bit 0Wake Event Enable on SD Card Removal bitThis bit enables wakeup event via Card Removal assertion in the Normal Interrupt Statusregister.1 Enable0 DisableWake Event Enable on SD Card Insertion bitThis bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Statusregister.1 Enable0 DisableWake Event Enable on SD Card interrupt bitThis bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Statusregister.1 Enable0 DisableClock Control Register 0REG[112Ch]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved SD ClockEnableInternalClockStableInternalClockenableType RO RO RO RO RO RW RO RWReset 0 0 0 0 0 0 0 0stateClock Control Register 1REG[112Dh]Bit 7 6 5 4 3 2 1 0SDCLKFrequencySelect bit 7SDCLKFrequencySelect bit 6SDCLKFrequencySelect bit 5SDCLKFrequencySelect bit 4SDCLKFrequencySelect bit 3SDCLKFrequencySelect bit 2SDCLKFrequencySelect bit 1SDCLKFrequencySelect bit 0Type RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[112Dh] Bits 7-0 SDCLK Frequency Select bits [7:0]At the initialization of the Host Controller, the Host Driver shall set the SDCLK FrequencySelect.This register is used to select the frequency of SD_CLK pin. The frequency is notprogrammed directly; rather this register holds the divisor of the MCLK Frequency. Only thefollowing settings are allowed.80h MCLK divided by 25640h MCLK divided by 12820h MCLK divided by 6410h MCLK divided by 3208h MCLK divided by 1604h MCLK divided by 802h MCLK divided by 401h MCLK divided by 200h MCLK (10MHz-63MHz)Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, themost significant bit is used as the divisor.According to the SD Physical Specification Version 1.01 and the SDIO Card SpecificationVersion 1.0, maximum SD Clock frequency is 25MHz, and shall never exceed this limit.SSD1926Application NoteRev 1.0 P 161/162 Jul 2009 Solomon Systech

Note : The SD_CLK will default divided by 2 with REG[1001h] bit 0 = 1.The frequency of SDCLK is set by the following formula:SDCLK Frequency = MCLK / divisorREG[112Ch] Bits 7-3REG[112Ch] Bit 2REG[112Ch] Bit 1REG[112Ch] Bit 0Thus, choose the smallest possible divisor which results in a clock frequency that is less than orequal to the target frequency.For example, if the MCLK has the value 33MHz, and the target frequency is 25MHz, thenchoosing the divisor value of 01h will yield 16.5MHz (if REG[1001h] bit 0 = 0), which is thenearest frequency less than or equal to the target.Reserved bitsSD Clock EnableThe Host Controller shall stop SD_CLK when writing this bit to 0. SDCLK Frequency Selectcan be changed when this bit is 0. Then, the Host Controller shall maintain the same clockfrequency until SDCLK is stopped (Stop at SD_CLK=0). If the Host Controller detects the NoCard state, this bit shall be cleared.1 Enable0 DisableInternal Clock StableThis bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in thisregister to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.Note: This is useful when using PLL for a clock oscillator that requires setup time.1 Ready0 Not ReadyInternal Clock EnableThis bit is set to 0 when the Host Driver is not using the Host Controller or the HostController awaits a wakeup interrupt. The Host Controller should stop its internal clock to govery low power state. Still, registers shall be able to be read and written. Clock starts to oscillatewhen this bit is set to 1. When clock oscillation is stable, the Host Controller shall set InternalClock Stable in this register to 1. This bit shall not affect card detection.1 Oscillate0 StopTimeout Control RegisterREG[112Eh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved TimeoutControl Bit3TimeoutControl Bit2TimeoutControl Bit1TimeoutControl Bit0Type RO RO RO RO RW RW RW RWReset 0 0 0 0 0 0 0 0stateREG[112Eh] Bits 7-4 Reserved bitsThese bits should be programmed by 0.REG[112Eh] Bits 3-0 Timeout Control bits [3:0]At the initialization of the Host Controller, the Host Driver shall set the Data Timeout CounterValue according to the Capabilities register.This value determines the interval by which DATA line timeouts are detected. Refer to theData Timeout Error in the Error Interrupt Status register for information on factors thatdictate timeout generation. Timeout clock frequency will be generated by dividing the baseclock MCLK value by this value. When setting this register, prevent inadvertent timeout eventsby clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enableregister)1111 Reserved1110 MCLK x 2 27…..0001 MCLK x 2 140000 MCLK x 2 13Solomon Systech Jul 2009 P 162/162 Rev 1.0SSD1926Application Note

Software Reset RegisterREG[112Fh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved SoftwareReset forDATA LineSoftwareReset forCMD LineSoftwareReset for allType RO RO RO RO RO RWAC RWAC RWACReset 0 0 0 0 0 0 0 0stateREG[112Fh] Bits 7-3Reserved bitsREG[112Fh] Bit 2REG[112Fh] Bit 1REG[112Fh] Bit 0Software reset bitsA reset pulse is generated when writing 1 to each bit of this register. After completing the reset,the Host Controller shall clear each bit. Because it takes some time to complete software reset,the SD Host Driver shall confirm that these bits are 0.Software Reset for DATA LineOnly part of data circuit is reset. DMA circuit is also reset.The following registers and bits are cleared by this bit:Buffer Data Port registerBuffer is cleared and initialized.Present State registerBuffer Read EnableBuffer Write EnableRead Transfer ActiveWrite Transfer ActiveDATA Line ActiveCommand Inhibit (DAT)Block Gap Control registerContinue RequestStop At Block Gap RequestNormal Interrupt Status registerBuffer Read ReadyBuffer Write ReadyDMA InterruptBlock Gap EventTransfer Complete1 Reset0 WorkSoftware Reset For CMD LineOnly part of command circuit is reset.The following registers and bits are cleared by this bit:Present State registerCommand Inhibit (CMD)Normal Interrupt Status registerCommand Complete1 Reset0 WorkSoftware Reset For AllThis reset affects the entire Host Controller except for the card detection circuit. Register bits oftype ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the Host Driver shallset this bit to 1 to reset the Host Controller. The Host Controller shall reset this bit to 0 whencapabilities registers are valid and the Host Driver can read them.Additional use of Software Reset For All may not affect the value of the Capabilitiesregisters. If this bit is set to 1, the SD card shall reset itself and must be reinitialized by the HostDriver.1 Reset0 WorkSSD1926Application NoteRev 1.0 P 163/164 Jul 2009 Solomon Systech

Normal Interrupt Status Register 0REG[1130h]Bit 7 6 5 4 3 2 1 0CardRemovalCardInsertionBufferRead ReadyBufferWriteReadyDMAInterruptBlock GapEventTransferCompleteCommandCompleteType RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1CReset 0 0 0 0 0 0 0 0stateNormal Interrupt Status Register 1REG[1131h]Bit 7 6 5 4 3 2 1 0ErrorInterruptReserved Reserved Reserved Reserved Reserved Reserved CardInterruptType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[1131h] Bit 7REG[1131h] Bits 6-1REG[1131h] Bit 0REG[1130h] Bit 7Normal Interrupt Status bits [15:0]The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt SignalEnable does not affect these reads. An interrupt is generated when the Normal Interrupt SignalEnable is enabled and at least one of the status bits is set to 1. For all bits except CardInterrupt and Error Interrupt, writing 1 to a bit clears it; writing to 0 keeps the bitunchanged. More than one status can be cleared with a single register write. The CardInterrupt is cleared when the card stops asserting the interrupt; that is, when the Card Driverservices the interrupt condition.Error InterruptIf any of the bits in the Error Interrupt Status register are set, then this bit is set. Therefore theHost Driver can efficiently test for an error by checking this bit first. This bit is read only.1 Error0 No ErrorReserved bitsCard InterruptWriting this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor.In 1-bit mode, the Host Controller shall detect the Card Interrupt without SD Clock to supportwakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so thereare some sample delays between the interrupt signal from the SD card and the interrupt to theHost System. It is necessary to define how to handle this delay.When this status has been set and the Host Driver needs to start this interrupt service, CardInterrupt Status Enable in the Normal Interrupt Status Enable register shall be set to 0 inorder to clear the card interrupt statuses latched in the Host Controller and to stop driving theinterrupt signal to the Host System. After completion of the card interrupt service (It shouldreset interrupt factors in the SD card and the interrupt signal may not be asserted), set CardInterrupt Status Enable to 1 and start sampling the interrupt signal again.1 Generate Card Interrupt0 No Card InterruptCard RemovalThis status is set if the Card Inserted in the Present State register changes from 1 to 0.When the Host Driver writes this bit to 1 to clear this status, the status of the Card Inserted inthe Present State register should be confirmed. Because the card detect state may possibly bechanged when the Host Driver clear this bit and interrupt event may not be generated1 Card removed0 Card state stable or DebouncingSolomon Systech Jul 2009 P 164/165 Rev 1.0SSD1926Application Note

REG[1130h] Bit 6REG[1130h] Bit 5REG[1130h] Bit 4REG[1130h] Bit 3REG[1130h] Bit 2REG[1130h] Bit 1Card InsertionThis status is set if the Card Inserted in the Present State register changes from 0 to 1.When the Host Driver writes this bit to 1 to clear this status, the status of the Card Inserted inthe Present State register should be confirmed. Because the card detect state may possibly bechanged when the Host Driver clear this bit and interrupt event may not be generated.1 Card inserted0 Card state stable or DebouncingBuffer Read ReadyThis status is set if the Buffer Read Enable changes from 0 to 1. Refer to the Buffer ReadEnable in the Present State register.1 Ready to read buffer0 Not ready to read bufferBuffer Write ReadyThis status is set if the Buffer Write Enable changes from 0 to 1. Refer to the Buffer WriteEnable in the Present State register.1 Ready to write buffer0 Not ready to write bufferDMA InterruptThis status is set if the Host Controller detects the Host DMA Buffer boundary during transfer.Refer to the Host DMA Buffer Boundary in the Block Size register.Other DMA interrupt factors may be added in the future. This interrupt shall not be generatedafter the Transfer Complete.1 DMA Interrupt is generated0 No DMA InterruptBlock Gap EventIf the Stop At Block Gap Request in the Block Gap Control register is set, this bit is set whenboth a read / write transaction is stopped at a block gap. If Stop At Block Gap Request is notset to 1, this bit is not set to 1.(1) In the case of a Read TransactionThis bit is set at the falling edge of the DATA Line Active Status (When the transaction isstopped at SD Bus timing. The Read Wait must be supported in order to use this function. Referto SD Specification [i] ‘Read transaction wait / continue timing’ about the detail timing.(2) Case of Write TransactionThis bit is set at the falling edge of Write Transfer Active Status (After getting CRC status atSD Bus timing). Refer to SD Specification [i] ‘Write transaction wait / continue timing’ formore details on the sequence of events.1 Transaction stopped at block gap0 No Block Gap EventTransfer CompleteThis bit is set when a read / write transfer is completed.(1) In the case of a Read TransactionThis bit is set at the falling edge of Read Transfer Active Status. There are two cases in whichthis interrupt is generated. The first is when a data transfer iscompleted as specified by data length (After the last data has been read to theHost System). The second is when data has stopped at the block gap andcompleted the data transfer by setting the Stop At Block Gap Request in theBlock Gap Control register (After valid data has been read to the Host System).Refer to Section 3.10.3 of [i] for more details on the sequence of events.(2) In the case of a Write TransactionThis bit is set at the falling edge of the DATA Line Active Status. There are two cases in whichthis interrupt is generated. The first is when the last data is written to the SD card as specifiedby data length and the busy signal released. The second is when data transfers are stopped at theblock gap by setting Stop At Block Gap Request in the Block Gap Control register and datatransfers completed. (After valid data is written to the SD card and the busy signal released).SSD1926Application NoteRev 1.0 P 165/166 Jul 2009 Solomon Systech

Refer to SD Specification [i] ‘Write transaction wait / continue timing’ for more details on thesequence of events.The table below shows that Transfer Complete has higher priority than Data Timeout Error.If both bits are set to 1, the data transfer can be considered complete.Relation between Transfer Complete and Data Timeout ErrorTransfer Complete Data Timeout Error Meaning of the status0 0 Interrupted by another factor0 1 Timeout occur duringtransfer1 Don’t Care Data transfer complete1 Data transfer complete0 No transfer completeREG[1130h] Bit 0Command CompleteThis bit is set when get the end bit of the command response. (Except Auto CMD12)Refer to Command Inhibit (CMD) in the Present State register.The table below shows that Command Timeout Error has higher priority than CommandComplete. If both bits are set to 1, it can be considered that the response was not receivedcorrectly.Command Complete Command Timeout Error Meanin of the status0 0 Interrupted by another factorDon’t Care 1 Response not receivedwithin 64 SDCLK cycles.1 0 Response received1 Command complete0 No command completeError Interrupt Status Register 0REG[1132h]Bit 7 6 5 4 3 2 1 0Currentlimit ErrorData EndBit ErrorData CRCErrorDataTimeoutErrorCommandIndex ErrorCommandEnd bitErrorCommandCRC ErrorCommandTimeoutErrorType RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1CResetstate0 0 0 0 0 0 0 0Error Interrupt Status Register 1REG[1133h]Bit 7 6 5 4 3 2 1 0Reserved Block SizeBitData LineConflict BitResponseDirectionBit ErrorReserved Reserved Reserved AutoCMD12ErrorType RO RW1C RW1C RW1C RO RO RO RW1CResetstate0 0 0 0 0 0 0 0Signals defined in this register can be enabled by the Error Interrupt Status Enable register, butnot by the Error Interrupt Signal Enable register. The interrupt is generated when the ErrorInterrupt Signal Enable is enabled and at least one of the statuses is set to 1. Writing to 1 clearsthe bit and writing to 0 keeps the bit unchanged. More than one status can be cleared at the oneregister write.Solomon Systech Jul 2009 P 166/166 Rev 1.0SSD1926Application Note

REG[1133h] Bits 7, 3-1Reserved bitREG[1133h] Bit 6REG[1133h] Bit 5REG[1133h] Bit 4REG[1133h] Bit 0REG[1132h] Bit 7REG[1132h] Bit 6REG[1132h] Bit 5REG[1132h] Bit 4REG[1132h] Bit 3REG[1132h] Bit 2Block Size Error BitThis bit indicates that a Block Size limit error was detected. A Block Size limit error is detectedwhen the programmed Block Size for a read or write transaction is set to 0 or greater than 2048.This bit is not set when the corresponding status enable bit is not enabled.Data Line ConflictThis bit indicates that a DATA Line Conflict was detected on SD_DATA0 or additionally onSD_DATA1-3 when the 4-bit Transfer Mode is selected. This bit is not set when thecorresponding status enable bit is not enabled.Response Direction Bit ErrorThis bit indicates that the Card-to-Host Transmitter bit was not set to ‘0’. This bit is not setwhen the corresponding status enable bit is not enabled.Auto CMD12 ErrorOccurs when detecting that one of the bits in Auto CMD12 Error Status register has changedfrom 0 to 1. This bit is set to 1,not only when the errors in Auto CMD12 occur but also whenAuto CMD12 is not executed due to the previous command error.1 Error0 No ErrorCurrent Limit ErrorBy setting the SD Bus Power bit in the Power Control register, the Host Controller is requestedto supply power for the SD Bus. If the Host Controller supports the Current Limit function, itcan be protected from an illegal card by stopping power supply to the card in which case this bitindicates a failure status. Reading 1 means the Host Controller is not supplying power to SDcard due to some failure. Reading 0 means that the Host Controller is supplying power and noerror has occurred. The Host Controller may require some sampling time to detect the currentlimit. If the Host Controller does not support this function, this bit shall always be set to 0.1 Power failed0 No ErrorData End Bit ErrorOccurs either when detecting 0 at the end bit position of read data which uses the DATA line orat the end bit position of the CRC Status.1 Error0 No ErrorData CRC ErrorOccurs when detecting CRC error when transferring read data which uses the DATA line orwhen detecting the Write CRC status having a value of other than "010".1 Error0 No ErrorData Timeout ErrorOccurs when detecting one of following timeout conditions.(1) Busy timeout for R1b,R5b type(2) Busy timeout after Write CRC status(3) Write CRC Status timeout(4) Read Data timeout.1 Time out0 No ErrorCommand Index ErrorOccurs if a Command Index error occurs in the command response.1 Error0 No ErrorCommand End Bit ErrorOccurs when detecting that the end bit of a command response is 0.1 End Bit Error Generated0 No ErrorSSD1926Application NoteRev 1.0 P 167/168 Jul 2009 Solomon Systech

REG[1132h] Bit 1REG[1132h] Bit 0Command CRC ErrorCommand CRC Error is generated in two cases.(1) If a response is returned and the Command Timeout Error is set to 0 (indicating notimeout), this bit is set to 1 when detecting a CRC error in the command response.(2) The Host Controller detects a CMD line conflict by monitoring the CMD line when acommand is issued. If the Host Controller drives the CMD line to 1 level, but detects 0 level onthe CMD line at the next SDCLK edge, then the Host Controller shall abort the command (Stopdriving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 todistinguish CMD line conflict (Refer to Table 1-50).1 CRC Error Generated0 No ErrorCommand Timeout ErrorOccurs only if no response is returned within 64 SDCLK cycles from the end bit of thecommand. If the Host Controller detects a CMD line conflict, in which case Command CRCError shall also be set as shown in Table 2-40, this bit shall be set without waiting for 64SDCLK cycles because the command will be aborted by the Host Controller.1 Time out0 No ErrorThe relation between Command CRC Error and Command Timeout Error is shown in Table 2-40.Table 2-40: The relation between Command CRC Error and Command Timeout ErrorCommand CRC Error Command Timeout Error Kinds of error0 0 No Error0 1 Response Timeout Error1 0 Response CRC Error1 1 CMD line conflictNormal Interrupt Status Enable Register 0REG[1134h]Bit 7 6 5 4 3 2 1 0CardRemovalStatusEnableCardInsertionStatusEnableBufferRead ReadyStatusEnableBufferWriteReadyStatusEnableDMAInterruptStatusEnableBlock GapEventStatusEnableTransferCompleteStatusEnableCommandCompleteStatusEnableType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateNormal Interrupt Status Enable Register 1REG[1135h]Bit 7 6 5 4 3 2 1 00 Reserved Reserved Reserved Reserved Reserved Reserved CardInterruptStatusEnableType RO RO RO RO RO RO RO RWResetstate0 0 0 0 0 0 0 0REG[1135h] Bits 7-1 This bit should be readback as 0.REG[1135h] Bits 6-1Reserved bitSolomon Systech Jul 2009 P 168/169 Rev 1.0SSD1926Application Note

REG[1135h] Bit 0REG[1134h] Bit 7REG[1134h] Bit 6REG[1134h] Bit 5REG[1134h] Bit 4REG[1134h] Bit 3REG[1134h] Bit 2REG[1134h] Bit 1REG[1134h] Bit 0Card Interrupt Status EnableIf this bit is set to 0, the Host Controller shall clear interrupt request to the System. The CardInterrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1.The Host Driver should clear the Card Interrupt Status Enable before servicing the CardInterrupt and should set this bit again after all interrupt requests from the card are cleared toprevent inadvertent interrupts.1 Enabled0 MaskedCard Removal Status Enable1 Enabled0 MaskedCard Insertion Status Enable1 Enabled0 MaskedBuffer Read Ready Status Enable1 Enabled0 MaskedBuffer Write Ready Status Enable1 Enabled0 MaskedDMA Interrupt Status Enable1 Enabled0 MaskedBlock Gap Event Status Enable1 Enabled0 MaskedTransfer Complete Status Enable1 Enabled0 MaskedCommand Complete Status Enable1 Enabled0 MaskedImplementation Note(1)The Host Controller may sample the card interrupt signal during interrupt period and may hold its value in the flipflop.If the Card Interrupt Status Enable is set to 0, the Host Controller shall clear all internal signals regarding CardInterrupt.Error Interrupt Status Enable Register 0REG[1136h]Bit 7 6 5 4 3 2 1 0CurrentLimit ErrorStatusEnableData EndBit ErrorStatusEnableData CRCError StatusEnableDataTimeoutError StatusEnableCommandIndex ErrorStatusEnableCommandEnd BitError StatusEnableCommandCRC ErrorStatusEnableCommandTimeoutError StatusEnableType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateError Interrupt Status Enable Register 1REG[1137h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved AutoCMD12Error StatusEnableType RO RO RO RO RO RO RO RWResetstate0 0 0 0 0 0 0 0SSD1926Application NoteRev 1.0 P 169/170 Jul 2009 Solomon Systech

REG[1137h] Bits 7-1Reserved bitsREG[1137h] Bit 0REG[1136h] Bit 7REG[1136h] Bit 6REG[1136h] Bit 5REG[1136h] Bit 4REG[1136h] Bit 3REG[1136h] Bit 2REG[1136h] Bit 1REG[1136h] Bit 0Auto CMDI2 Error Status Enable1 Enabled0 MaskedCurrent Limit Error Status Enable1 Enabled0 MaskedData End Bit Error Status Enable1 Enabled0 MaskedData CRC Error Status Enable1 Enabledo MaskedData Timeout Error Status Enable1 Enabled0 MaskedCommand Index Error Status Enable1 Enabled0 MaskedCommand End Bit Error Status Enable1 Enabled0 MaskedCommand CRC Error Status Enable1 Enabled0 MaskedCommand Timeout Error Status Enable1 Enabled0 MaskedImplementation Note(1)To detect SD_CMD line conflict, the Host Driver must set Status Enable and Command CRC Error Status Enable to1.Normal Interrupt Signal Enable Register 0REG[1138h]Bit 7 6 5 4 3 2 1 0CardRemovalSignalEnableCardInsertionSignalEnableBufferRead ReadySignalEnableBufferWriteReadySignalEnableDMAInterruptSignalEnableBlock GapEventSignalEnableTransferCompleteSignalEnableCommandCompleteSignalEnableType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateNormal Interrupt Signal Enable Register 1REG[1139h]Bit 7 6 5 4 3 2 1 00 Reserved Reserved Reserved Reserved Reserved Reserved CardInterruptSignalEnableType RO RO RO RO RO RO RO RWResetstate0 0 0 0 0 0 0 0This register is used to select which interrupt status is indicated to the Host System as theinterrupt. These status bits all share the same bit interrupt line. Setting any of these bits to 1enables interrupt generation.Solomon Systech Jul 2009 P 170/171 Rev 1.0SSD1926Application Note

REG[1139h] Bit 7 This bit should be readback as 0.REG[1139h] Bit 6-1REG[1139h] Bit 0REG[1138h] Bit 7REG[1138h] Bit 6REG[1138h] Bit 5REG[1138h] Bit 4REG[1138h] Bit 3REG[1138h] Bit 2REG[1138h] Bit 1REG[1138h] Bit 0Reserved bitsCard Interrupt Signal Enable1 Enabled0 MaskedCard Removal Signal Enable1 Enabled0 MaskedCard Insertion Signal Enable1 Enabled0 MaskedBuffer Read Ready Signal Enable1 Enabled0 MaskedBuffer Write Ready Signal Enable1 Enabled0 MaskedDMA Interrupt Signal Enable1 Enabled0 MaskedBlock Gap Event Signal Enable1 Enabled0 MaskedTransfer Complete Signal Enable1 Enabled0 MaskedCommand Complete Signal Enable1 Enabled0 MaskedError Interrupt Signal Enable Register 0REG[113Ah]Bit 7 6 5 4 3 2 1 0CurrentLimit ErrorSignalEnableData EndBit ErrorSignalEnableData CRCErrorSignalEnableDataTimeoutErrorSignalEnableCommandIndex ErrorSignalEnableCommandEnd BitErrorSignalEnableCommandCRC ErrorSignalEnableCommandTimeoutErrorSignalEnableType RW RW RW RW RW RW RW RWReset 0 0 0 0 0 0 0 0stateError Interrupt Signal Enable Register 1REG[113Bh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved AutoCMD12ErrorSignalEnableType RO RO RO RO RO RO RO RWResetstate0 0 0 0 0 0 0 0This register is used to select which interrupt status is notified to the Host System as theinterrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1enables interrupt generation.SSD1926Application NoteRev 1.0 P 171/172 Jul 2009 Solomon Systech

REG[113Bh] Bits 7-1Reserved bitsREG[113Bh] Bit 0REG[113Ah] Bit 7REG[113Ah] Bit 6REG[113Ah] Bit 5REG[113Ah] Bit 4REG[113Ah] Bit 3REG[113Ah] Bit 2REG[113Ah] Bit 1REG[113Ah] Bit 0Auto CMDI2 Error Signal Enable1 Enabled0 MaskedCurrent Limit Error Signal Enable1 Enabled0 MaskedData End Bit Error Signal Enable1 Enabled0 MaskedData CRC Error Signal Enable1 Enabled0 MaskedData Timeout Error Signal Enable1 Enabled0 MaskedCommand Index Error Signal Enable1 Enabled0 MaskedCommand End Bit Error Signal Enable1 Enabled0 MaskedCommand CRC Error Signal Enable1 Enabled0 MaskedCommand Timeout Error Signal Enable1 Enabled0 MaskedAuto CMD12 Error Status Register 0REG[113Ch]Bit 7 6 5 4 3 2 1 0CommandNot Issuedby AutoCMD12ErrorReserved Reserved AutoCMD12Index ErrorAutoCMD12End BitErrorAutoCMD12CRC ErrorAutoCMD12TimeoutErrorAutoCMD12 notexecutedType RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateAuto CMD12 Error Status Register 1REG[113Dh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[113Dh] Bits 7-0REG[113Ch] Bit 7When Auto CMDI2 Error Status is set, the Host Driver shall check this register to identify whatkind of errorAuto CMD12 indicated. This register is valid only when the Auto CMDI2 Error isset.Reserved bitsCommand Not Issued By Auto CMDI2 ErrorSetting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error(D04-D01) in this register.1 Not Issued0 No errorSolomon Systech Jul 2009 P 172/173 Rev 1.0SSD1926Application Note

REG[113Ch] Bits 6-5REG[113Ch] Bit 4REG[113Ch] Bit 3REG[113Ch] Bit 2REG[113Ch] Bit 1REG[113Ch] Bit 0Reserved bitsAuto CMDI2 Index ErrorOccurs if the Command Index error occurs in response to a command.1 Error0 No errorAuto CMDI2 End Bit ErrorOccurs when detecting that the end bit of command response is 0.1 End Bit Error Generated0 No errorAuto CMDI2 CRC ErrorOccurs when detecting a CRC error in the command response.1 CRC Error Generated0 No errorAuto CMDI2 Timeout ErrorOccurs if no response is returned within 64 SDCLK cycles from the end bit of command.If this bit is set to 1, the other error status bits (D04-D02) are meaningless.1 Time out0 No errorAuto CMDI2 Not ExecutedIf memory multiple block data transfer is not started due to command error, this bit is not setbecause it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controllercannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. Ifthis bit is set to 1, other error status bits (D04-D01) are meaningless.1 Not executed0 ExecutedThe relation between Auto CMDI2 CRC Error and Auto CMDI2 Timeout Error is shown in Table 2-41.Table 2-41: The relation between Command CRC Error and Command Timeout Error for Auto CMDI2Auto CMDI2 CRC Error Auto CMDI2 Timeout Error Kinds of error0 0 No Error0 1 Response Timeout Error1 0 Response CRC Error1 1 CMD line conflictThe timing of changing Auto CMDI2 Error Status can be classified in three scenarios:(1) When the Host Controller is going to issue Auto CMD12Set D00 to 1 if Auto CMD12 cannot be issued due to an error in the previous command.Set D00 to 0 if Auto CMD12 is issued.(2) At the end bit of an Auto CMD12 responseCheck received responses by checking the error bits D0l, D02, D03 and D04.Set to 1 if error is detected.Set to 0 if error is not detected.(3) Before reading the Auto CMD12 Error Status bit D07Set D07 to 1 if there is a command cannot be issuedSet D07 to 0 if there is no command to issueTiming of generating the Auto CMDI2 Error and writing to the Command register are asynchronous. ThenD07 shall be sampled when driver never writing to the Command register. So just before reading the AutoCMDI2 Error Status register is good timing to set the D07 status bit.An Auto CMD12 Error Interrupt is generated when one of the error bits D00 to D04 is set to 1. The Command NotIssued By Auto CMDI2 Error does not generate an interrupt.SSD1926Application NoteRev 1.0 P 173/174 Jul 2009 Solomon Systech

Reserved RegisterREG[113Eh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Reserved RegisterREG[113Fh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[113Eh] Bits 7-0,REG[113Fh] Bits 7-0Reserved bitsCapabilities Register 0REG[1140h]Bit 7 6 5 4 3 2 1 0Timeoutclock unitReservedTimeoutclockfrequency 5Timeoutclockfrequency 4Timeoutclockfrequency 3Timeoutclockfrequency 2Timeoutclockfrequency 1Timeoutclockfrequency 0Type RO RO RO RO RO RO RO ROReset 1 0 0 0 0 0 0 0stateCapabilities Register 1REG[1141h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Base clockFreq for SDClock 5Base clockFreq for SDClock 4Base clockFreq for SDClock 3Base clockFreq for SDClock 2Base clockFreq for SDClock 1Base clockFreq for SDClock 0Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateCapabilities Register 2REG[1142h]Bit 7 6 5 4 3 2 1 0Suspend /ResumesupportDMAsupportHigh speedsupportReserved Reserved Reserved Max blocklength 1Max blocklength 0Type RO RO RO RO RO RO RO ROReset 0 1 0 0 0 0 0 1stateCapabilities Register 3REG[1143h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3.3V VoltagesupportType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 1Solomon Systech Jul 2009 P 174/175 Rev 1.0SSD1926Application Note

Capabilities Register 4REG[1144h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Capabilities Register 5REG[1145h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Capabilities Register 6REG[1146h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Capabilities Register 7REG[1147h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[1143h] Bits 7-1This register provides the Host Driver with information specific to the Host Controllerimplementation. The Host Controller may implement these values as fixed or loaded from flashmemory during power on initialization. Refer to Software Reset For All in the Software Resetregister for loading from flash memory and completion timing control.Reserved bitsREG[1143h] Bit 0 Voltage Support 3.3V1 3.3V Supported0 3.3V Not SupportedREG[1142h] Bit 7 Suspend/Resume SupportThis bit indicates whether the Host Controller supports Suspend / Resume functionality. If thisbit is 0, the Suspend and Resume mechanism (Refer to SD Specification [i] ‘Suspend andResume mechanism’) are not supported and the Host Driver shall not issue either Suspend orResume commands.1 Supported0 Not supportedREG[1142h] Bit 6 DMA SupportThis bit indicates whether the Host Controller is capable of using DMA to transfer data betweensystem memory and the Host Controller directly.1 DMA Supported0 DMA not supportedREG[1142h] Bit 5 High Speed SupportThis bit indicates whether the Host Controller and the Host System support High Speed modeand they can supply SD Clock frequency from 25MHz to 50MHz.1 High Speed Supported0 High Speed not supportedREG[1142h] Bits 4-2 Reserved bitsSSD1926Application NoteRev 1.0 P 175/176 Jul 2009 Solomon Systech

REG[1142h] Bits 1-0 Max Block Length bits [1:0]This value indicates the maximum block size that the Host Driver can read and write to thebuffer in the Host Controller. The buffer shall transfer this block size without wait cycles.Block sizes can be defined as indicated below.00/10/11 Reserved01 1024REG[1141h] Bits 7-6Reserved bitsREG[1141h] Bits 5-0 Base Clock Frequency for SD Clock bits [5:0]This value indicates the base (maximum) clock frequency for the SD Clock. Unit values are1MHz. If the real frequency is 16.5MHz, the lager value shall be set 01 0001b (17MHz)because the Host Driver use this value to calculate the clock divider value (Refer to theSDCLK Frequency Select in the Clock Control register.) and it shall not exceed upper limit ofthe SD Clock frequency. The supported clock range is 10MHz to 63MHz. If these bits are all 0,the Host System has to get information via another method.REG[1140h] Bit 7REG[1140h] Bit 6Not 0 Reserved0 Get information via another methodTimeout Clock unitThis bit shows the unit of base clock frequency used to detect Data Timeout Error.0 kHz1 MHzReserved bitREG[1140h] Bits 5-0 Timeout clock Frequency bits [5:0]This bit shows the base clock frequency used to detect Data Timeout Error.The Timeout Clock Unit defines the unit of this fields value.Timeout Clock Unit =0 [KHz] unit: 1KHz to 63KHzTimeout Clock Unit =1 [MHz] unit: 1MHz to 63MHzNot 0 1KHz to 63KHz or 1MHz to 63MHzREG[1144h] Bits 7-0REG[1145h] Bits 7-0REG[1146h] Bits 7-0REG[1147h] Bits 7-00 Get information via another methodReserved bitsMaximum Current Capabilities Register 0REG[1148h]Bit 7 6 5 4 3 2 1 0Maximumcurrent for3.3V bit 7Maximumcurrent for3.3V bit 6Maximumcurrent for3.3V bit 5Maximumcurrent for3.3V bit 4Maximumcurrent for3.3V bit 3Maximumcurrent for3.3V bit 2Maximumcurrent for3.3V bit 1Maximumcurrent for3.3V bit 0Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateMaximum Current Capabilities Register 1REG[1149h]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Solomon Systech Jul 2009 P 176/177 Rev 1.0SSD1926Application Note

Maximum Current Capabilities Register 2REG[114Ah]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Maximum Current Capabilities Register 3REG[114Bh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Maximum Current Capabilities Register 4REG[114Ch]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Maximum Current Capabilities Register 5REG[114Dh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Maximum Current Capabilities Register 6REG[114Eh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0Maximum Current Capabilities Register 7REG[114Fh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[1149h-114Fh]Bits 7-0Reserved bitsREG[1148H] BITS 7-0 Maximum Current for 3.3V bits [7:0]SSD1926Application NoteRev 1.0 P 177/178 Jul 2009 Solomon Systech

Slot Interrupt Register 0REG[11FCh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved Slot 0InterruptstatusType RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateSlot Interrupt Register 1REG[11FDh]Bit 7 6 5 4 3 2 1 0Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedType RO RO RO RO RO RO RO ROResetstate0 0 0 0 0 0 0 0REG[11FDh] Bits 7-0REG[11FCh] Bits 7-6REG[11FCh] Bit 0Reserved bitsSlot Interrupt bitThe Host Controller supports only 1 slot.This status bits indicate the logical OR of Interrupt Signal and Wakeup Signal for each slot. Amaximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, theHost Driver can know which interrupt is generated by reading these status bits.By a power on reset or by setting Software Reset For All, the interrupt signal shall be deassertedand this status shall read 00h.Host Controller Version Register 0REG[11FEh]Bit 7 6 5 4 3 2 1 0Specification versionnumber bit7Specification versionnumber bit6Specification versionnumber bit5Specification versionnumber bit4Specification versionnumber bit3Specification versionnumber bit2Specification versionnumber bit1Specification versionnumber bit0Type RO RO RO RO RO RO RO ROReset 0 0 0 0 0 0 0 0stateHost Controller Version Register 1REG[11FFh]Bit 7 6 5 4 3 2 1 0Vendorversionnumber bit7Vendorversionnumber bit6Vendorversionnumber bit5Vendorversionnumber bit4Vendorversionnumber bit3Vendorversionnumber bit2Vendorversionnumber bit1Vendorversionnumber bit0Type RO RO RO RO RO RO RO ROReset 0 0 0 1 0 0 0 0stateREG[11FFh] Bits 7-0, Vendor version bits [7:0]The Vendor Version Number field is implementation specific and shall be 2 BCD fields. Thevalue of the Vendor Version Number shall be set to 0x10 to indicate Version 1.0 of the HostController design.REG[11FEh] Bits 7-0, Specification version bits [7:0]The Specification Version Number shall be set to 8’ b0 to indicate SD Host Specification, V1.0.Solomon Systech Jul 2009 P 178/179 Rev 1.0SSD1926Application Note

Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume anyliability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including withoutlimitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters,including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not conveyany license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for useas components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for anyother application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify andhold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with suchunintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of thepart.http://www.solomon-systech.comSSD1926Application NoteRev 1.0 P 179/180 Jul 2009 Solomon Systech