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Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

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Chapter 2: <strong>Pinout</strong> TablesRTable 2-6: FF1152 Package — FX40, FX60, <strong>and</strong> FX100 Devices (Continued)BankPin DescriptionPinNumber1 IO_L5P_D23_LC_1 E181 IO_L5N_D22_LC_1 E171 IO_L6P_D21_LC_1 F151 IO_L6N_D20_LC_1 F141 IO_L7P_D19_LC_1 E161 IO_L7N_D18_LC_1 F161 IO_L8P_D17_CC_LC_1 F131 IO_L8N_D16_CC_LC_1 G13No Connects inFX60 DevicesNo Connects inFX40 Devices2 IO_L1P_D15_CC_LC_2 AH222 IO_L1N_D14_CC_LC_2 AJ222 IO_L2P_D13_LC_2 AK182 IO_L2N_D12_LC_2 AK172 IO_L3P_D11_LC_2 AG222 IO_L3N_D10_LC_2 AG212 IO_L4P_D9_LC_2 AH172 IO_L4N_D8_VREF_LC_2 AJ172 IO_L5P_D7_LC_2 AJ212 IO_L5N_D6_LC_2 AJ202 IO_L6P_D5_LC_2 AJ192 IO_L6N_D4_LC_2 AK192 IO_L7P_D3_LC_2 AG202 IO_L7N_D2_LC_2 AH202 IO_L8P_D1_LC_2 AH192 IO_L8N_D0_LC_2 AH183 IO_L1P_GC_CC_LC_3 H173 IO_L1N_GC_CC_LC_3 J173 IO_L2P_GC_VRN_LC_3 K163 IO_L2N_GC_VRP_LC_3 L163 IO_L3P_GC_LC_3 K183 IO_L3N_GC_LC_3 K173 IO_L4P_GC_LC_3 J163 IO_L4N_GC_VREF_LC_3 J153 IO_L5P_GC_LC_3 K193 IO_L5N_GC_LC_3 J19124 www.xilinx.com <strong>Virtex</strong>-4 <strong>FPGA</strong> <strong>Packaging</strong> <strong>and</strong> <strong>Pinout</strong> <strong>Specification</strong><strong>UG075</strong> (v3.3) September 19, 2008

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