SH564128FH8N0QHSCR - Itautec

SH564128FH8N0QHSCRApril 11, 2011Device Timing Parameters by Speed BinDDR3-1333ParameterSymbolUnits NotesMinMaxClock TimingMinimum clock cycle time (DLL off mode) t CK(DLL_OFF) 8 - t CK 6Average clock period t CK(avg) Refer to Speed Bin on page 33. psAverage high pulse width t CH(avg) 0.47 0.53 t CK(avg)Average low pulse width t CL(avg) 0.47 0.53 t CK(avg)Absolute clock period t CK(abs)t CK(avg)min +t JIT(per)mint CK(avg)max +t JIT(per)maxpsAbsolute clock high pulse width t CH(abs) 0.43 - t CK(avg) 25Absolute clock low pulse width t CL(abs) 0.43 - t CK(avg) 26Clock period jitter t JIT(per) -80 80 psClock period jitter during DLL locking period t JIT(per, lck) -70 70 psCycle to cycle period jitter t JIT(CC) 160 psCycle to cycle period jitter during DLL lockingperiodt JIT(CC, lck) 140 psCumulative error across 2 cycles t ERR(2per) -118 118 psCumulative error across 3 cycles t ERR(3per) -140 140 psCumulative error across 4 cycles t ERR(4per) -155 155 psCumulative error across 5 cycles t ERR(5per) -168 168 psCumulative error across 6 cycles t ERR(6per) -177 177 psCumulative error across 7 cycles t ERR(7per) -186 186 psCumulative error across 8 cycles t ERR(8per) -193 193 psCumulative error across 9 cycles t ERR(9per) -200 200 psCumulative error across 10 cycles t ERR(10per) -205 205 psCumulative error across 11 cycles t ERR(11per) -210 210 psCumulative error across 12 cycles t ERR(12per) -215 215 psps 24Cumulative error across n = 13-50 cycles t ERR(nper)t JIT(per)mint ERR(nper)max = (1 + 0.68ln(n)) *t ERR(nper)min = (1 + 0.68ln(n)) *t JIT(per)maxCorporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.comEurope: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-399290335