VLSI System Design using CADENCE - VIT University

About VIT UniversityFounded in 1984 as Vellore Engineering College, theinstitute was declared a University in recognition of its academicexcellence by the Ministry of Human Resources Development,Government of India in 2001. The University has since grown byleaps and bounds – establishing excellent infrastructure spreadover an impeccacably clean and green 360 acre campus - on wayto fulfill the vision of the founder and Chancellor Dr. G.Viswanathan to make it truly world class. VIT today comprisesof six constituent Schools and interdisciplinary Centers offeringundergraduate, graduate, post graduate and research programsupto PhD level. In the last seven years, VIT had more than 100visiting professors, some of them staying 6 to 12 weeks foroffering accelerated courses as well as participating inWorkshops and Seminars for the benefit of students of VIT andalso the industry around.About the School of Electronics EngineeringThe School offers B.Tech [ECE] and five M.Techprograms. Facilities for research leading to Ph.D. are available inmany emerging areas. A major emphasis in both theundergraduate and post graduate program is teaching andlearning process. School is actively involved in R&D activitiesand has sponsored projects from various agencies like DST,ISRO (RESPOND), and BRNS etc. It has MOU’s with industrieslike Cadence, Altera and other reputed institution and R&Dorganization of our country and other parts of the world.About VLSI design LabThe VLSI Design Laboratory is equipped with‣ Cadence ToolsCadence RTL CompilerCadence NC SimCadence SOC Encounter‣ Altera DE3 BoardQuartus- IIThis lab is being utilized by Engineers from VLSI,Embedded, Sensors and Mechatronics divisions forinnovations in their Academic as well as Research projects.Who Can Attend?‣ Faculty from Institution who are teaching VLSIDESIGN‣ Research Scholars‣ Students – Graduates and post GraduatesCourse Duration:3 Days – 21, 22, 23 February 2013.Last date for Registration:On or before : 15-02-13Date of confirmation : 17-02-13Course description:Functional VerificationPrototyping the design using FPGARTL SynthesisPhysical DesignFloor PlanPlace and routeDRC and LVSParasitic ExtractionTools: Cadence EDA, ALTERACourse Fee:For Faculty/R&D organizationRs. 5000/- [course fee + accommodation]Rs. 4000/- [course fee only]For Students\Research ScholarRs. 4500/- [course fee + accommodation]Rs. 3500/- [course fee only]Note: DD should be taken in favour of “VIT University”payable at Vellore.No. of participants restricted to 30 only.VLSI System Design FlowModeling of Combinational and sequential circuitsusing Verilog HDL

Registration FormName : ....................................................................Department: ……………………………………………Organization :………………………………………………Experience: …………..……………………………Address for Correspondence:................................................................................................................................................................................................................................................................................................Email: ................................................................................................Phone: ...............................................................................................Accommodation Required Yes NoDemand Draft Details:Faculty /Research Scholar StudentCourse coordinators and Resource Persons:For further details contactMr.R. Sakthivel , Assistant Professor (SG)Email: rsakthivel@vit.ac.incontact No: 09994627570Mr. Ravi.S, Assistant Professor (Sr)Email: msravi@vit.ac.inContact NO: 09790155650Mr. Jagannadha Naidu K, Assistant ProfessorEmail : jagannadhanaidu.k@vit.ac.inContact No: 09943062343Registration form and DD send to:Prof.R.Sakthivel,Assistant Prof (SG)-VLSI Division,School of Electronics EngineeringVIT UniversityVellore – 632014. TNVITU N I V E R S I T Y(Estd. u/s 3 of UGC Act 1956)Vellore – 632014, Tamilnadu.Indiawww.vit.ac.inHands on TrainingInVLSI SYSTEM DESIGNUSING CADENCE(RTL to GDSII)(21, 22, 23 February 2013)ByVLSI DIVISIONSchool of Electronics EngineeringVIT UniversityAmountDD No.Bank: …………………………………….: …………………………………….: …………………………….……….Dated : …………………………….……….Signature: ……………………..……….(Use Photocopy of the above form, if required)VIT: A place to learn; A chance to grow