CS5531/32/33/34 - Eshop-Rychle.cz

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CS5531/32/33/34+3 V10 ΩAnalogSupply 0.1 µF 0.1 µF5 15VA+ VD+1AIN1+9OptionalOSC2Clock2SourceAIN1-310 4.9152 MHzC1OSC1-3 VAnalogSupply2.5VColdJunction22 nF4 CS5532C218VREF+ CS17VREF-SDI20 AIN2+ SDO19 AIN2-7 SCLKA08 A1VA - DGND61614131211SerialDataInterfaceFigure 24. CS5532 Configured for Thermocouple MeasurementV+ V+V 1V 2VV2 1(a)(b)Figure 25. Bridge with Series Resistors44 DS289PP5
CS5531/32/33/342.12. Getting StartedThis A/D converter has several features. From asoftware programmer’s prospective, what shouldbe done first? To begin, a 4.9152 MHz or 4.096MHz crystal takes approximately 20 ms to start. Toaccommodate for this, it is recommended that asoftware delay of approximately 20 ms start theprocessor’s ADC initialization code. Next, sincethe CS5531/32/33/34 do not provide a power-onresetfunction, the user must first initialize the ADCto a known state. This is accomplished by resettingthe ADC’s serial port with the Serial Port Initializationsequence. This sequence resets the serial portto the command mode and is accomplished bytransmitting 15 SYNC1 command bytes (0xFFhexadecimal), followed by one SYNC0 command(0xFE hexadecimal). Once the serial port of theADC is in the command mode, the user must resetall the internal logic by performing a system resetsequence (see 2.3.2 System Reset Sequence). Thenext action is to initialize the voltage referencemode. The voltage reference select (VRS) bit in theconfiguration register must be set based upon themagnitude of the reference voltage between theVREF+ and the VREF- pins.After this, the channel-setup registers (CSRs) shouldbe initialized, as these registers determine how calibrationsand conversions will be performed. Oncethe CSRs are initialized, the user has three options incalibrating the ADC: 1) don’t calibrate and use thedefault settings; 2) perform self or system calibrations;or 3) upload previously saved calibration resultsto the offset and gain registers. At this point,the ADC is ready to perform conversions.2.13. PCB LayoutFor optimal performance, the CS5531/32/33/34should be placed entirely over an analog groundplane. All grounded pins on the ADC, including theDGND pin, should be connected to the analogground plane that runs beneath the chip. In a splitplanesystem, place the analog-digital plane splitimmediately adjacent to the digital portion of thechip.Note:See the CDB5531/32/33/34 data sheet forsuggested layout details and ApplicationsNote 18 for more detailed layout guidelines.Before layout, please call for our FreeSchematic Review Service.DS289PP5 45
Page 1 and 2: CS5531/32/33/3416-Bit and 24-Bit AD
Page 3 and 4: CS5531/32/33/342.3.8. Filter Rate S
Page 5 and 6: CS5531/32/33/341. CHARACTERISTICS A
Page 7 and 8: CS5531/32/33/34ANALOG CHARACTERISTI
Page 9 and 10: TYPICAL RMS NOISE (nV), CS5532/34-B
Page 11 and 12: CS5531/32/33/34DYNAMIC CHARACTERIST
Page 13 and 14: CS5531/32/33/34CSSDISCLKt3MSB MSB-1
Page 15 and 16: CS5531/32/33/34-40°C to +85°C (MC
Page 17 and 18: CS5531/32/33/34Using the single con
Page 19 and 20: CS5531/32/33/342.2.2. Command Regis
Page 21 and 22: CS5531/32/33/34READ/WRITE INDIVIDUA
Page 23 and 24: CS5531/32/33/34PERFORM CALIBRATIOND
Page 25 and 26: CS5531/32/33/342.2.5. Reading/Writi
Page 27 and 28: CS5531/32/33/34φ1 Fineφ1 FineVREF
Page 29 and 30: CS5531/32/33/34Filter Rate Select,
Page 31 and 32: CS5531/32/33/34U/B (Unipolar / Bipo
Page 33 and 34: CS5531/32/33/342.5.4. Performing Ca
Page 35 and 36: CS5531/32/33/34sult in the loss of
Page 37 and 38: CS5531/32/33/34FRS (WR3-WR0)Clock C
Page 39 and 40: CS5531/32/33/34Unipolar InputVoltag
Page 41 and 42: CS5531/32/33/342.10. Clock Generato
Page 43: CS5531/32/33/34+2.5 V+3 V ~ +5 VAna
Page 47 and 48: CS5531/32/33/34SDI - Serial Data In
Page 49 and 50: CS5531/32/33/346. PACKAGE DRAWINGSN
Page 51: • Notes •

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