CS5531/32/33/34 - Eshop-Rychle.cz

CS5531/32/33/34initialized, all the Setups point to their defaultsettings irrespective of the conversion orcalibration mode (i.e conversions can beperformed, but only physical channel 1 will beconverted). Further note that filterconvolutions are reset (i.e. flushed) ifconsecutive conversions are performed ontwo different physical channels. Ifconsecutive conversions are performed onthe same physical channel, the filter is notreset. This allows the ADCs to more quicklysettle full scale step inputs.2.7. Using Multiple ADCs SynchronouslySome applications require synchronous data outputsfrom multiple ADCs converting different analogchannels. Multiple CS5531/32/33/34 parts canbe synchronized in a single system by using the followingguidelines:1) All of the ADCs in the system must be operatedfrom the same oscillator source.2) All of the ADCs in the system must share commonSCLK and SDI lines.3) A software reset must be performed at the sametime for all of the ADCs after system power-up (byselecting all of the ADCs using their respective CSpins, and writing the reset sequence to all parts, usingSDI and SCLK).4) A start conversion command must be sent to alloftheADCsinthesystematthesametime.The±8 clock cycles of ambiguity for the first conversion(or for a single conversion) will be the same for allADCs, provided that they were all reset at the sametime.5) Conversions can be obtained by monitoringSDO on only one ADC, (bring CS high for all butone part) and reading the data out of each part individually,before the next conversion data words areready.An example of a synchronous system using twoCS5532 parts is shown in Figure 15.CS5532SDOSDISCLKCSOSC2CS5532SDOSDISCLKCSOSC2µCCLOCKSOURCEFigure 15. Synchronizing Multiple ADCs2.8. Conversion Output CodingThe CS5531/32/33/34 output 16-bit (CS5531/33)and 24-bit (CS5532/34) data conversion words. Toread a conversion word the user must read the conversiondata register. The conversion data registeris 32 bits long and outputs the conversions MSBfirst. The last byte of the conversion data registercontains data monitoring flags. The channel indicator(CI) bits keep track of which physical channelwas converted and the overrange flag (OF) monitorsto determine if a valid conversion was performed.Refer to the Conversion Data OutputDescriptions section for more details.The CS5531/32/33/34 output data conversions inbinary format when operating in unipolar mode andin two's complement when operating in bipolarmode. Tables 4 and 5 show the code mapping forboth unipolar and bipolar mode. VFS in the tablesrefers to the positive full-scale voltage range of theconverter in the specified gain range, and -VFS refersto the negative full-scale voltage range of theconverter. The total differential input range (betweenAIN+ and AIN-) is from 0 to VFS in unipolarmode, and from -VFS to VFS in bipolar mode.38 DS289PP5