CS5531/32/33/34 - Eshop-Rychle.cz

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CS5531/32/33/342.5.6. System CalibrationFor the system calibration functions, the user mustsupply the converters calibration signals which representground and full scale. When a system offset calibrationis performed, a ground referenced signalmust be applied to the converters. Figure 13 illustratessystem offset calibration.As shown in Figure 14, the user must input a signalrepresenting the positive full scale point to performa system gain calibration. In either case, the calibrationsignals must be within the specified calibrationlimits for each specific calibration step (referto the System Calibration Specifications).2.5.7. Calibration TipsCalibration steps are performed at the output wordrate selected by the WR2-WR0 bits of the channelsetup registers. Due to limited register lengths inthe faster word-rate filters (240 Sps and higher),channels that are used in these rates should also becalibrated in one of these word rates, and channelsused in the lower word rates (120 Sps and lower)should be calibrated at one of these lower rates.Since higher word rates result in conversion wordswith more peak-to-peak noise, calibration shouldbe performed at the lowest possible output wordrate for maximum accuracy. For the 7.5 Sps to 120Sps word rate settings, calibrations can be performedat 7.5 Sps, and for 240 Sps and higher, calibrationcan be performed at 240 Sps. To minimizedigital noise near the device, the user should waitfor each calibration step to be completed beforereading or writing to the serial port. Reading thecalibration registers and averaging multiple calibrationstogether can produce a more accurate calibrationresult. Note that accessing the ADC’sserial port before a calibration has finished may re-AIN+S1OPENS2CLOSED+-1X GAIN+-Reference + -AIN-AIN+AIN-VREF+VREF-+-XGAINOPENOPENCLOSEDCLOSED+-Figure 11. Self Calibration of OffsetFigure 12. Self Calibration of GainExternalConnections0V + -AIN++XGAIN+Full Scale + -ExternalConnectionsAIN++XGAIN+CM + ---CM + -AIN-AIN---Figure 13. System Calibration of OffsetFigure 14. System Calibration of Gain34 DS289PP5
CS5531/32/33/34sult in the loss of synchronization between the microcontrollerand the ADC, and may prematurelyhalt the calibration cycle.For maximum accuracy, calibrations should be performedfor both offset and gain (selected by changingthe G2-G0 bits of the channel-setup registers).Note that only one gain range can be calibrated perphysical channel when the OGS bit in the ConfigurationRegister is set to ‘0’. Multiple gain rangescan be calibrated for a single channel by manipulatingthe OGS bit and the OG1-OG0 bits of the selectedSetup (see Section 2.3.7 for more details). Iffactory calibration of the user’s system is performedusing the system calibration capabilities ofthe CS5531/32/33/34, the offset and gain registercontents can be read by the system microcontrollerand recorded in non-volatile memory. These samecalibration words can then be uploaded into the offsetand gain registers of the converter when poweris first applied to the system, or when the gain rangeis changed.When the device is used without calibration, theuncalibrated gain accuracy is about ±1 percent andthe gain tracking from range (2X to 64X) to rangeis approximately ±0.3 percent.Note that the gain from the offset register to theoutput is 1.83007966 decimal, not 1. If a user wantsto adjust the calibration coefficients externally,they will need to divide the information to be writtento the offset register by the scale factor of1.83007966. (This discussion assumes that the gainregister is 1.000...000 decimal. The offset registeris also multiplied by the gain register before beingapplied to the output conversion words).2.5.8. Limitations in Calibration RangeSystem calibration can be limited by signal headroomin the analog signal path inside the chip asdiscussed under the Analog Input section of thisdata sheet. For gain calibration, the full scale inputsignal can be reduced to 3% of the nominal fullscalevalue. At this point, the gain register is approximatelyequal to 33.33 (decimal). While thegain register can hold numbers all the way up to 64-2 -24 , gain register settings above a decimal valueof 40 should not be used. With the converter’s intrinsicgain error, this minimum full scale input signalmay be higher or lower. In defining theminimum Full Scale Calibration Range (FSCR)under Analog Characteristics, margin is retained toaccommodate the intrinsic gain error. Inversely, theinput full scale signal can be increased to a point inwhich the modulator reaches its 1’s density limit of86 percent, which under nominal conditions occurswhen the full scale input signal is 1.1 times thenominal full scale value. With the chip’s intrinsicgain error, this maximum full scale input signalmaybe higher or lower. In defining the maximumFSCR, margin is again incorporated to accommodatethe intrinsic gain error.2.6. Performing ConversionsThe CS5531/32/33/34 offers two distinctly differentconversion modes. The three sections that followdetail the differences and provide examplesillustrating how to use the conversion modes withthe channel-setup registers.2.6.1. Single Conversion ModeBased on the information provided in the channelsetupregisters (CSRs), after the user transmits theconversion command, a single, fully-settled conversionis performed. The command byte includesa pointer address to the Setup register to be usedduring the conversion. Once transmitted, the serialport enters data mode where it waits until the conversionis complete. When the conversion data isavailable, SDO falls to logic 0. Forty SCLKs arethen needed to read the conversion data word. Thefirst 8 SCLKs are used to clear the SDO flag. Duringthe first 8 SCLKs, SDI must be logic 0. The last32 SCLKs are needed to read the conversion result.Note that the user is forced to read the conversionin single conversion mode as SDO will remain lowDS289PP5 35
Page 1 and 2: CS5531/32/33/3416-Bit and 24-Bit AD
Page 3 and 4: CS5531/32/33/342.3.8. Filter Rate S
Page 5 and 6: CS5531/32/33/341. CHARACTERISTICS A
Page 7 and 8: CS5531/32/33/34ANALOG CHARACTERISTI
Page 9 and 10: TYPICAL RMS NOISE (nV), CS5532/34-B
Page 11 and 12: CS5531/32/33/34DYNAMIC CHARACTERIST
Page 13 and 14: CS5531/32/33/34CSSDISCLKt3MSB MSB-1
Page 15 and 16: CS5531/32/33/34-40°C to +85°C (MC
Page 17 and 18: CS5531/32/33/34Using the single con
Page 19 and 20: CS5531/32/33/342.2.2. Command Regis
Page 21 and 22: CS5531/32/33/34READ/WRITE INDIVIDUA
Page 23 and 24: CS5531/32/33/34PERFORM CALIBRATIOND
Page 25 and 26: CS5531/32/33/342.2.5. Reading/Writi
Page 27 and 28: CS5531/32/33/34φ1 Fineφ1 FineVREF
Page 29 and 30: CS5531/32/33/34Filter Rate Select,
Page 31 and 32: CS5531/32/33/34U/B (Unipolar / Bipo
Page 33: CS5531/32/33/342.5.4. Performing Ca
Page 37 and 38: CS5531/32/33/34FRS (WR3-WR0)Clock C
Page 39 and 40: CS5531/32/33/34Unipolar InputVoltag
Page 41 and 42: CS5531/32/33/342.10. Clock Generato
Page 43 and 44: CS5531/32/33/34+2.5 V+3 V ~ +5 VAna
Page 45 and 46: CS5531/32/33/342.12. Getting Starte
Page 47 and 48: CS5531/32/33/34SDI - Serial Data In
Page 49 and 50: CS5531/32/33/346. PACKAGE DRAWINGSN
Page 51: • Notes •

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