Non-Conductive Epoxy Filled Vias in PCB's Provides New ... - SMTA

Non-Conductive Epoxy FilledVias in PCB’s Provides NewProduct OfferingsPresented by:- David Hoover – MultekSr. Field Applications Engineer06-10-04

Why Hole Filling?

Via in Pad Benefits1. Provides a flat coplanar surface. (For component attachment)2. More traces on PCB escaping devices through rout channels.(Results in less lyrs / potential lower costs)3. Increased component density. (Due to absence of periphery vias)4. Potential EMI / SI benefits. (Lower Inductance due to no dogbonepads with traces.)5. Thermal dissipation. (Either at lead connections or underdevices – heat pipes)6. No via (Soldermask) plugging required at the component locations.(Filled Vias seal off the possibility of solutions wicking up from the bottomside. This also provides a flatter soldermask / pad surface which will yieldgreater feature resolution during stencil paste printing for assembly)

Non-Conductive Filled Vias(Grid Array Package Benefits)Added Rout Channelson Outerlayer(underneath device)Extra Cost Considerations• Hole filling - (materials)• Planarization – (Mechanical Equipment & Process Time)• Copper Capping (Additional Drilling and Copper Plating)

Hole Plugging – Overview of the ProcessVIP Process flowNC drillingPasteThrough hole platingPHP selective hole pluggingBack-up boardSolder maskPolishingTo Solder Mask processCopper plating on surfaceCopper plating on surfaceImaging

Planarization Equipment - Prototype

Hole Plugging - ApplicationsHole plugging forinner processStandard Hole Plug- Increased buried via reliability- Customer requirementHole plugging forouter processVia in Pad- Allow uvia stack over the BVH- Allow via in SMT, size reductionLimitations- Aspect Ratio- Filler Particle Size- Production Quantities

Cross Section PhotosAfter Planarization

Cross Section PhotosFilled Blind Vias 1-2

Cross Section PhotosFilled Blind Vias 1-3

Non-Conductive Filled Vias – ObjectivesThe process developed was able to: Fill the holes to have a better topography Fill the holes to have a “stacked via” design Prove out structures with Reliability TestingA New Challenge was Identified Fill holes with an aspect ratio up to 15:1 andminimum diameter of 0.25mm (10 mil)(Current Process is for low volume – R and D)

Depression

Hole Plugging (epoxy filling through hole)- DimpleUneven surface in the capped via23um25umDimple = 25um (

Depression 350x

3D Mapping of the Pad Geometry's1.701.200.700.20-0.30-0.80(Mils)1.20-1.700.70-1.200.20-0.70-0.30-0.20-0.80--0.30-1.30--0.80-1.80--1.30-1.30BJ-1.80AU4943373125191372ANAE

Top View of Larger Size Pads and HolesCould be used for Larger Feature Components• Socketed BGAs and LGAs• Surface Mounted High Speed Connectors• Can help fill Via Holes where Solder Volume Wicking is an issue.

Cross Section PhotosFilled Vias in larger PTHs

Bubble Example

Cross Section PhotosReliability TestsAfter Soldershock(6 X @ 288’C)

IST Results – (Reliability Tests)PTH performance all 6 headsPTH performance all 6 headschange in mohms12011511010510095908580757065605550454035302520151050-5-10-151 13 25 37 49 61 73 85 97 109 121 133 145 157 169 181 193 205 217 229 241 253 265 277 289 301 313 325# of Cycles741-1-1741-1-2741-1-3741-1-4741-1-5741-1-6change in mohms12011511010510095908580757065605550454035302520151050-5-10-151 10 19 28 37 46 55 64 73 82 91 100 109 118 127 136 145 154 163 172 181 190 199 208 217 226 235 244 253# of Cycles741-1-1741-1-2741-1-3741-1-4741-1-5741-1-6IST Coupons Without Filled ViasIST Coupons With Filled ViasThis IST testing suggests that that the Filling of the Vias with Non-Conductive Epoxyproduces results that meet (or exceed) the results of standard PTH technology.

SummaryProcess acceptable up to 15:1 AR(Prototype Small R & D Volume Quantities)Scalability possibilitiesProcess suitable for LGA, Socketed BGA, orSurface Mounted Connector TechnologiesNon-Conductive Filled Via Technology meetscurrent Industry Reliability RequirementsImportant Things to Note (Differences in Appearance)Small bubbles sometimes presentSmall depressions sometimes present

Future Activities(My Wishlist)• Increased Demand for VIP Technology due to High Speed Requirements(Low Lead inductance)• Increased Demand for VIP Technology due to increased Routability(Finer Pitch Components drives the Density Up requiring more Metal Fanout Design Channels)• Thermal Dissipation Possibilities(Copper Plating Thickness, Connection to Planes, MLF Devices)• NC Dispensing(Precise Application of the Inks / Media)• Full PTH Sealing for Assembly Reliability(Sealing of the Via in Pads stops the solder Volume from wicking away from the Solder Joints)