Power Grid Analysis in VLSI Designs - SERC

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• Maximum current surge that will happen given the number of switches.• Delay impact of consecutive switches while they turned on.• IR drop across switch network5.2.2.1 Algorithm for Power Switch Network Analysis:Initialize load voltage to zero and current charging to Zero.{For each, infinitesimal small times period, predict the current based on thevoltage at lumped load from IV table of the switch type.Identify the actual current based on the number of switches turned on at theparticular instance of time.Track the current at VDD i.e. if the new current is greater than old one, assignmaximum surge current to new current.Calculate the rise in voltage in the infinitesimal small time based on equation(3).Continue till either all the switches are turned on or the desired voltage level isreached.}Print maximum surge current and voltage level reached after turning on some specificswitches as required by user.98
Above algorithm is developed for the case where the delay between 2 consecutive switches insequential switch network is same. However, it is possible to extend for different delay scenario.In this case, we need to use timing information from Static Timing Analysis or simulations.5.2.2.2 Algorithm for Static IR drop analysis across power switches:{Read switch characterization data – for static IR drop, read ON Channelresistance (RON)Determine total number of switches required to reach desired voltage level –desired voltage level is specified by user – by “Algorithm for power SwitchNetwork Analysis”Effective resistance of the switches predicted above (N) is: RON/NCompute power consumption of switched off or virtual power network usingany methods described in this work (can be outside this work also!)Compute average current consumption of the virtual power network. Iavg =Pavg/VDDStatic IR drop across switch network is: Iavg*RON/N.}5.3 Results and AnalysisTraditional approach to study above would be full-fledged SPICE simulation that includesvirtual power network and switch network where each switch is turned on after some delay.Note that here we are talking about thousands of switches in switch network and about million99
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
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Figure 1.6 Total power break up int
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CMOSDieAcronym for Complimentary Me
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2 Toggle Activity Estimation2.1 Ove
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For large T, D(x) becomes time inva
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done hierarchically or there is reu
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A Sample SDC file with above comman
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Some of the care needs to be taken
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Figure 2.5 Timing Arcs in extracted
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3 Power Estimation3.1 OverviewAccur
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In this work, above power component
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on the required accuracy, different
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Based on power sensitivity and tool
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Page 51 and 52: 3.4.3 Interconnect setupAll the cir
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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