Power Grid Analysis in VLSI Designs - SERC

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Note that the 1 stcharacterization – IV characterization – that we did also is resistancecharacterization. This resistance varies for different value of voltages across switch so it is alsocalled non-linear resistance characterization.5.2.2 Current or Switch PredictionCurrent prediction is done based on simplified extracted model of block under consideration asFigure 5.6. The switch network is modeled along with its detailed connectivity and timingwhereas the logic connected to virtual domain is modeled as capacitive load. Current throughswitch is predicted in infinitesimal small time duration. The CV characteristic is applied hereas below:Current(I) =dq/dt OR dq = I dtBut dq = C * dvHence dv = I * dt / C……1……2……3VDDSwitchNetworkVoutExtractedTotal CloadFigure 5.6 Analysis model of Virtual Power NetworkEquation 3 forms the basis of Algorithm 1 described in next section. The delay between twoconsecutive switches is used to predict the charge being supplied by the switch to virtual power96
network domain. The IV table of the switch is used to predict current by further dividing delayinto infinitesimal small time duration as shown in Figure 5.7. Based on the initial voltage andcharge supplied, the voltage has been derived when the next switch just starts turning on. Thisprocess continues till either all switches are turned on or the specified voltage level is reached.Further, the same method continues if all the switches are turned on but voltage value is lowerthan the ideal voltage value (VDD golden) to predict the maximum surge in current. Predictednumber of switches is used to predict static IR drop across switch network as explained inAlgorithm 2. This is another important parameter that will not be discussed further in thischapter.Figure 5.7 Infinitesimal Time Division for Current PredictionParameters those can be analyzed through this setup include:• Total number of switches required reaching a required voltage value.• Alternatively, voltage value that can be reached with given number of switches.97
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
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Figure 1.6 Total power break up int
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CMOSDieAcronym for Complimentary Me
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2 Toggle Activity Estimation2.1 Ove
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For large T, D(x) becomes time inva
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done hierarchically or there is reu
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A Sample SDC file with above comman
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Some of the care needs to be taken
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Figure 2.5 Timing Arcs in extracted
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3 Power Estimation3.1 OverviewAccur
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In this work, above power component
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on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
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Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
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Page 102 and 103: Vdesired (mV)Actual#SwitchesSwitche
Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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