Power Grid Analysis in VLSI Designs - SERC

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power network start getting charged. Loads include interconnect capacitances, gatecapacitances as well as the circuit diffusion/diode caps. The amount of current being sunk bythese caps depends on the ability of switch network to provide charge in a given time. Due tofast current need of the virtual power domain, there is L*di/dt noise being injected into circuitthat can affect normal functioning of the golden power domain. Note that despite of capacitiveload dominating, the peak current is still limited by saturation current of switch causing currentprofile we got in Figure 5.3.5.2 Switch Network AnalysisSwitch Network Analysis (SNA) early in design-planning includes decision of switch networktopology, identification of switches to be used, total system timings for turning on/off powerdomains as well as total power supply noise contribution by a switch network. Sequentialconfiguration allows configuring delay such that the peak current at any point of time can becontrolled to meet the specification of system noise and hence the tradeoff between the totaltime systems requires to on/off virtual network and the noise criteria. This information shouldgo to the placement and routing tools for physical design. Further, switch network contributioncomes from maximum current surge it causes and the point of optimization there is totalnumber of switches of each type in the network and delay.Following assumptions are made to keep the analysis simple but in reality the solution can beextended to handle them.• Delay between two consecutive switches is same.• 2 types of switches exist in the network.94
• Voltage at any node in virtual power network is of the same value at any time instantduring power ON if there is zero static IR drop.• Switch Network is sequential. Parallel configuration essentially means a BIG switch -all transistors forming a BIG switch with characteristic lumped to a single MOS.High-level flow for the analysis is shown in block diagram Figure 5.5.Switch IVCharacterizationCurrent prediction thatcharges capacitive loadDetermination ofrequired parametersFigure 5.5 Schematic Switch network Analysis Flow5.2.1 Switch CharacterizationSwitch IV Characterization includes current being sourced through switch for different voltagesbetween golden and virtual power port of switch. This is achieved using transient SPICEsimulation of the switch. The data is stored in value-pair (voltage-current) format for furtherprocessing.Switch characterization also involves switch ON resistance measurement. This is resistance thatswitches offer during normal functionality i.e. when switches are turned ON and virtual powernetwork is connected to golden power network. This is measured by putting 10mV batteryacross switch and measuring current. This resistance value is later used for average IR dropanalysis across switch.95
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
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Figure 1.6 Total power break up int
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CMOSDieAcronym for Complimentary Me
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2 Toggle Activity Estimation2.1 Ove
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For large T, D(x) becomes time inva
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done hierarchically or there is reu
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A Sample SDC file with above comman
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Some of the care needs to be taken
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Figure 2.5 Timing Arcs in extracted
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3 Power Estimation3.1 OverviewAccur
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In this work, above power component
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Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
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Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
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Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
Page 96 and 97: Note that the 1 stcharacterization
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Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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