Power Grid Analysis in VLSI Designs - SERC

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5 Power Up AnalysisOne of the popular techniques to reduce leakage is to use gated power supply. [74, 79, 80].Shekhar [74] has highlighted a technique called ‘sleep transistor’ and challenges associatedwith that. This technique proposes to gate power supply using a high threshold transistor whennot required as shown in Figure 5.1. The ‘sleep transistor’ also known as ‘power switch’ turnsoff power supply when a portion of chip is idle and thus saving leakage current. Apart fromdesign challenges, the technique has additional Design Analysis challenges as mentioned below.Figure 5.1 Gated Power Supply ([74])1. When Power Supply turns on from off state, a huge capacitive load gets chargedcausing a huge surge in current causing Power Supply Noise (PSN). This can couplewith signal lines causing state change or delay change. It can also remain within supply89
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
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Figure 1.6 Total power break up int
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CMOSDieAcronym for Complimentary Me
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2 Toggle Activity Estimation2.1 Ove
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For large T, D(x) becomes time inva
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done hierarchically or there is reu
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A Sample SDC file with above comman
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Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 91 and 92: number of optimal switches meeting
Page 93 and 94: • Switch network consists of one
Page 95 and 96: • Voltage at any node in virtual
Page 97 and 98: network domain. The IV table of the
Page 99 and 100: Above algorithm is developed for th
Page 101 and 102: SPICE accuracy data while keeping s
Page 103 and 104: No. of switches Simulation Time (in
Page 105 and 106: 6 Conclusion6.1 SummaryPower Grid a
Page 107 and 108: decoupling capacitors - intrinsic d
Page 109 and 110: 7 References1. Semiconductor Indust
Page 111 and 112: 41. Bai, G.; Bobba, S.; Hajji, I.N,
Page 113 and 114: 85. Fei Li; Lei He; Saluja, K.K.;
Page 115 and 116: Appendix A Sample SDC filecreate_cl
Page 117 and 118: *RES0 PREZ PREZ:0 0.11 DTP10J_0:PRE
Page 119 and 120: Appendix D Current Characterization
Page 121: Figure 6 1GHz Transformation for 1M
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