Power Grid Analysis in VLSI Designs - SERC

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500 MHz 0.00168113 0.0016 0.0009410 0.00086539 0.00192531 0.0018Table 4.1 Comparison of Peak power Dissipation4.5.2 Peak Dynamic IR Drop ResultsFor determining peak Dynamic IR drop, initially three circuits were used.• 100 Inverter Chain – It is a chain of 100 inverters with the output of the previousinverter acting as the input of the next. Delay of the chain is higher than the frequencyof operation.• 32 Bit Shift Register – This 32-bit shift register is series/parallel shift register.Depending upon the input and selection criteria, the input is shifted in series or parallelmanner.• 16 Bit Adder – This is 16-bit binary adder. ‘Carry Forward’ logic is used for addition.Following points are taken into account while generating the net lists for these circuits.• Package RLC is added to each power pad.• Ideal voltage source is attached to each power pad.• Uniform mesh structure is used and all leaf cells are placed randomly on to it.• Reduced interconnect network was used using driving point admittance estimation forpower as well as signal lines.• No existing decoupling capacitors were estimated.The peak Dynamic IR drop data is obtained using Average Activity approach, Timing Windowapproach and SPICE simulation. The data obtained is shown in Table 4.2.84
Circuit%Drop inaverage activity%Drop in TimingWindow ApproachSPICE%Drop100 Inverter Chain 1.65 6 132 Bit Shift Register 17.5 40 1216 Bit Adder 31 NA 19.16Table 4.2 Comparison of percentage peak instantaneous IR dropIt is clear that the accuracy of the Average Activity method is better than Timing Windowmethod. To check the performance of this approach, Average Activity method was applied to afew industry standard circuits. Table 4.3 below shows the comparison of the maximumDynamic IR Drop in a circuit using average switching activity and Power Mill. Power Mill is aSPICE based transient analysis tool offered by Synopsys. It is now called Nano Sim.circuit %V Drop using avg activity %Vdrop in Power Mill %Errors27 4.5 5.8 -22.4138s344 6.3 6.6 -4.54545s349 6.2 7.5 -17.3333s444 8.6 13.3 -35.3383s1238 13.4 13.3 0.75188s298 12.5 15 -16.6667Table 4.3 Comparison of percentage peak IR drop on ISCAS89 circuits85
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
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Figure 1.6 Total power break up int
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CMOSDieAcronym for Complimentary Me
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2 Toggle Activity Estimation2.1 Ove
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For large T, D(x) becomes time inva
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done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
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Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
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Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
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Page 96 and 97: Note that the 1 stcharacterization
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Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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