Power Grid Analysis in VLSI Designs - SERC

500 MHz 0.00168113 0.0016 0.0009410 0.00086539 0.00192531 0.0018Table 4.1 Comparison of Peak power Dissipation4.5.2 Peak Dynamic IR Drop ResultsFor determining peak Dynamic IR drop, initially three circuits were used.• 100 Inverter Chain – It is a chain of 100 inverters with the output of the previousinverter acting as the input of the next. Delay of the chain is higher than the frequencyof operation.• 32 Bit Shift Register – This 32-bit shift register is series/parallel shift register.Depending upon the input and selection criteria, the input is shifted in series or parallelmanner.• 16 Bit Adder – This is 16-bit binary adder. ‘Carry Forward’ logic is used for addition.Following points are taken into account while generating the net lists for these circuits.• Package RLC is added to each power pad.• Ideal voltage source is attached to each power pad.• Uniform mesh structure is used and all leaf cells are placed randomly on to it.• Reduced interconnect network was used using driving point admittance estimation forpower as well as signal lines.• No existing decoupling capacitors were estimated.The peak Dynamic IR drop data is obtained using Average Activity approach, Timing Windowapproach and SPICE simulation. The data obtained is shown in Table 4.2.84