Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
Based on the generated current signatures, a new PG network is created. After this, all themacro instances are replaced with the corresponding current signatures. In our analysis, wetook a PG network with uniform Power Grid and ideal GND. We did not do any actual powerrouting but attached the current sources randomly. This is compared with actual spice circuitsfor all macros in the same PG network at the same locations.4.4.3 SPICE SimulationNow, each cell is replaced by current source driven by its corresponding PWL data. Package R,L & C is attached to the top-level power pins. SPICE simulation is performed. The voltage ateach node of the power mesh is punched. The IR drop for each cell is calculated using aCODAC (Characterization & Optimization of Digital & Analog Circuits) program (TI InternalProgram), which subtracts power supply from the minimum voltage obtained at each node togive the Peak Dynamic IR Drop at that node. This is done for all the nodes of the circuit. Thesame CODAC program can be used to calculate the Average Dynamic IR Drop at each node ofthe circuit.4.5 Validation and ResultsIn this work, we have done following simplifications:• Modeled power grid by creating an nxm mesh. The resistance of each arm in mesh wasderived from Ohm/um number. We also assumed 2 such arms in parallel to comprehendmulti-layer chip scenario.• Matrix solver was not developed as part of this work. Instead, we used SPICEsimulators available.82
We executed the flow as explained in previous section. Instead of 1MHz, we used 10MHz forcharacterization. This is to reduce the amount of data. We still did 13.33GHz sampling of celldata.4.5.1 Peak Power ResultsThree small circuits were studied to stabilize the above approach. These three circuits are –• TWOAND :- The circuit consist of two AND gate one after the another.• ANDOR :- The circuit consists of one AND gate followed by one OR gate.• 2AND-1OR :- This circuit has two AND gate at the first level. The outputs of theseAND gates are given to an OR gate whose output is the final output.The peak power data is obtained for three small circuits using the approach described in thereport and using SPICE simulation. The data obtained using average switching activityapproach and SPICE for 100 Mega Hz and 500 Mega Hz input frequency is given below inTable 4.1.PEAK POER (Watts)FREEQUNCYTWOAND AND-OR 2AND-1ORSpiceOurApproachSPICEOurApproachSPICEOurApproach100 MHz0.00168170.0016 0.0009409 0.0008421 0.0019253 0.001983
- Page 31 and 32: done hierarchically or there is reu
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- Page 37 and 38: Figure 2.5 Timing Arcs in extracted
- Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
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- Page 51 and 52: 3.4.3 Interconnect setupAll the cir
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- Page 55 and 56: Design TFC + Power Compiler Runtime
- Page 57 and 58: Design Name CLK Power Total Power %
- Page 59 and 60: DesignNamePowerCompilerProposedAppr
- Page 61 and 62: We can approximate the average powe
- Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
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- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
- Page 75 and 76: Characterized data was transformed
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- Page 79 and 80: of any node. Alternatively frequenc
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- Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
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- Page 96 and 97: Note that the 1 stcharacterization
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- Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
- Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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- Page 116 and 117: Appendix B Sample SPEF Format*SPEF
- Page 118 and 119: Appendix C Power Waveforms Analysis
- Page 120 and 121: Appendix E Waveform transformation
We executed the flow as expla<strong>in</strong>ed <strong>in</strong> previous section. Instead of 1MHz, we used 10MHz forcharacterization. This is to reduce the amount of data. We still did 13.33GHz sampl<strong>in</strong>g of celldata.4.5.1 Peak <strong>Power</strong> ResultsThree small circuits were studied to stabilize the above approach. These three circuits are –• TWOAND :- The circuit consist of two AND gate one after the another.• ANDOR :- The circuit consists of one AND gate followed by one OR gate.• 2AND-1OR :- This circuit has two AND gate at the first level. The outputs of theseAND gates are given to an OR gate whose output is the f<strong>in</strong>al output.The peak power data is obta<strong>in</strong>ed for three small circuits us<strong>in</strong>g the approach described <strong>in</strong> thereport and us<strong>in</strong>g SPICE simulation. The data obta<strong>in</strong>ed us<strong>in</strong>g average switch<strong>in</strong>g activityapproach and SPICE for 100 Mega Hz and 500 Mega Hz <strong>in</strong>put frequency is given below <strong>in</strong>Table 4.1.PEAK POER (Watts)FREEQUNCYTWOAND AND-OR 2AND-1ORSpiceOurApproachSPICEOurApproachSPICEOurApproach100 MHz0.00168170.0016 0.0009409 0.0008421 0.0019253 0.001983
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