Power Grid Analysis in VLSI Designs - SERC

Based on the generated current signatures, a new PG network is created. After this, all themacro instances are replaced with the corresponding current signatures. In our analysis, wetook a PG network with uniform Power Grid and ideal GND. We did not do any actual powerrouting but attached the current sources randomly. This is compared with actual spice circuitsfor all macros in the same PG network at the same locations.4.4.3 SPICE SimulationNow, each cell is replaced by current source driven by its corresponding PWL data. Package R,L & C is attached to the top-level power pins. SPICE simulation is performed. The voltage ateach node of the power mesh is punched. The IR drop for each cell is calculated using aCODAC (Characterization & Optimization of Digital & Analog Circuits) program (TI InternalProgram), which subtracts power supply from the minimum voltage obtained at each node togive the Peak Dynamic IR Drop at that node. This is done for all the nodes of the circuit. Thesame CODAC program can be used to calculate the Average Dynamic IR Drop at each node ofthe circuit.4.5 Validation and ResultsIn this work, we have done following simplifications:• Modeled power grid by creating an nxm mesh. The resistance of each arm in mesh wasderived from Ohm/um number. We also assumed 2 such arms in parallel to comprehendmulti-layer chip scenario.• Matrix solver was not developed as part of this work. Instead, we used SPICEsimulators available.82