Power Grid Analysis in VLSI Designs - SERC

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In our work, we have computed resistances and capacitors based on technology data for 130nmnode. A sample program was written to realize the mesh structure as shown in Figure 4.10 forVDD network and VSS was taken as ideal ground. This is not an issue since we can lump allthe VSS network elements to VDD network. After determining Power Grid Current Waveform,we solved the network through SPICE simulations.4.3.1 Power Grid Current Waveform ModelingPower Grid Current waveform modeling involves following steps:1. Compute Toggle frequency for each of the instance in design as proposed in Chapter 2.2. Using the current characterized data for the cell, transform the current data at the abovecomputed toggle frequency.3. Compute the input arrival for each of the instance in design. This is done using StaticTiming Analysis. Compute the shift required in current waveform with reference toclock edge. For simplicity, we have assumed 0 skew for clock network.4. Hook up the current sources and solve the PG network.5. Determine the PG model simulation time.There are explained further below.1 Read the characterized data.74
Characterized data was transformed from time domain to frequency domain. Thesampling is done at fixed frequency (much higher than common design frequencyvalues) – 1000/75 ~ 13.33 GHz and [t, i(t)] are stored.I(t) = i(0)d(0) + i(0+Ts)d(0+Ts) + i(0+2*Ts)d(0+2*Ts) + … N SamplesWhere,‘Ts’ is sampling frequency – in this case 13.33 GHzi(t) is current value at time ‘t’d(t) = 1 when t=n*Ts else 0. n ranges from 1,…,NFor computation efficiency N may be chosen as power of 2… N = 2 ** n (n is integer)Now, the Fourier transform of the samples have been performed:I[k] = i[n]*2 Model the current waveform for each Boolean gate at computed toggle frequency.• A compression factor (M) is defined to meet the targeted frequency of the cell underconsideration.M = targeted frequency/cell characterized frequency (10MHz in this work)• Transformation allows preserving base of the current transients. This would not havebeen possible in a time domain while we scale frequency. Hence, the need of frequencydomain transformation. Appendix E shows the waveform generated after transformationfrom 1 MHz waveform. As it can be seen, 1GHz waveform is not per expectation. Thisis not an issue since apart from clock cells, other cells are not expected to switch at 175
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
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Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
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Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73: Each such armRepresents resistance
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
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Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
Page 94 and 95: power network start getting charged
Page 96 and 97: Note that the 1 stcharacterization
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Page 100 and 101: gates in the virtual network or mor
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Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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