Power Grid Analysis in VLSI Designs - SERC

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Cell SPICE DeckSPICE simulation@ 10 MHzPerl Processing toSample VDD currentsFigure 4.9 Cell Characterization FlowUsing the above methodology, we characterized all the cells which were being instantiated inISCAS89 circuits.4.3 Power Grid network modelingThis section describes the Power Grid network building using the cell characterization data.Power Grid offers resistance, capacitance as well as inductance to the switching logic. Figure4.10 shows schematic of typical power grid. [45] The power & ground supply pins are modeledas ideal voltage sources. The methodology however vastly varies in terms of current sourcemodeling and capacitance estimation [50 51 52 53]. This work also focuses on current sourcemodeling which is described in next sub section.72
Each such armRepresents resistance…Figure 4.10 Power Grid ModelingOnce, the power grid is determined along with capacitance and current source distribution, itcan be realized as matrix data structure and can be solved for computing voltages at desirednodes – specifically the nodes where cell components are connected as below.V * Y = IWhere V is voltage value at each node, Y is admittance or resistance of PG segment, I iscurrent that we have characterized.OR v(t) = Z * i(t) ( Z = R – jW for power network )V(w) = z(w) * i(w)73
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
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• Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
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Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71: 3. The temporal correlation between
Page 75 and 76: Characterized data was transformed
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Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
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Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
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Page 96 and 97: Note that the 1 stcharacterization
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Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
Page 120 and 121: Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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