Power Grid Analysis in VLSI Designs - SERC

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characterization and use them appropriately during use. (Figure 4.3) In our case, wecapture rise and fall transition together and use them for analysis, making proposedapproach direction independent. Figure 4.8 State Dependency on cell switchingFigure 4.8 State Dependency on cell switchingWe also established few corollaries those will be used later in discussion.1. Slew impacts the short circuit current of the device. For multi-stage block, slew impacts1 st stage the most and the overall current waveform is unaffected due to this change.The impact varies from lo to hi when the design stages are decreasing.2. Glitches or hazardous transitions can contribute to peak current need of the circuit.Modeling glitches in non-SPICE analysis is not trivial. It is desired that glitches arereduced by robust design practices. In this work, it is assumed that there are no glitchesin the design.70
3. The temporal correlation between different inputs influences the characterization data alot. This is due to simultaneous switching. We have used the least affecting combinationi.e. 0 skew between multiple inputs in our analysis – this is worst case also. (Figure 4.8)4.2.2 Current Characterization FlowCurrent Source generation involves time variant current waveform determination for each cell.This is current waveform as it is seen at VDD pin of cell when the cell output is rising or falling.The flow is shown in Figure 4.9. Sample SPICE deck is shown in Appendix D. PERL Programthat takes input from SPICE simulation has following options available. In our case, we tooklast option with 75ps as sampling interval.1. full – Whole current data available in the punch file is given as output in two columnformat, first column giving the simulation time and the second column giving thecurrent value corresponding to each simulation time instance.2. fixed – The total simulation time is divided into 8192 points and the current value atthese 8192 time-values is obtained either directly, if available or by interpolation.3. Interval filtered – An interval in picoseconds is specified and according to that, theprogram obtains the time-values for which the data is expected. Again, the current datacorresponding to these time-values is obtained directly, if available or by interpolation.71
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
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AbstractPower has become an importa
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1 Introduction1.1 MotivationVLSI in
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Further, Figure 1.3 shows that ther
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proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69: Figure 4.6 Load vs. peak power for
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
Page 94 and 95: power network start getting charged
Page 96 and 97: Note that the 1 stcharacterization
Page 98 and 99: • Maximum current surge that will
Page 100 and 101: gates in the virtual network or mor
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Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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Page 110 and 111: 21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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Page 116 and 117: Appendix B Sample SPEF Format*SPEF
Page 118 and 119: Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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