Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
Output isrising. There isnotablesymmetry forrise/fall. Thishelps us tocharacterizeonly onecurrent and dothe analysis atPower/Groundnetwork.Output isrising. Thisalignment ispreserved forbetter resultsduring currentwaveformgeneration.Same is truefor Outputfalling.Figure 4.3 Inverter waveforms measured at different nodes66
In this work, we have maintained temporal relation ship between Power and Ground currentwaveforms and decoupled the simulations i.e. they are simulated separately and IR drop resultsare merged.We performed simulations and arrived at following conclusions.• The shape of the current waveform remains the same if the patterns used are sameacross different frequencies. Note here that the overall simulation time decreases whenfrequency increases for a same set of patterns. This is not a surprise as the load beingcharged and discharged is same during each transition for the same slew and for thesame set of patterns. In case of CMOS gate, shape of current waveform remains samefor very high frequencies (period ~= 3 times of 0-100% slew). (Appendix C)• The slew or transition time (used interchangeably) plays a big role for peak powerdetermination of cells. When the slew decreases, the width of the current spikedecreases with increase in peak. Figure 4.4 and Figure 4.5 shows the peak powervariation for different input transition times. Note the variation of ~2x for inverter and~1.5x for 2 input NAND gate.67
- Page 15 and 16: Further, Figure 1.3 shows that ther
- Page 17 and 18: proposed in a few papers. In this t
- Page 19 and 20: • Degradation in switching speeds
- Page 21 and 22: Second, today’s design has huge P
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- Page 25 and 26: CMOSDieAcronym for Complimentary Me
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- Page 29 and 30: For large T, D(x) becomes time inva
- Page 31 and 32: done hierarchically or there is reu
- Page 33 and 34: A Sample SDC file with above comman
- Page 35 and 36: Some of the care needs to be taken
- Page 37 and 38: Figure 2.5 Timing Arcs in extracted
- Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
- Page 41 and 42: In this work, above power component
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- Page 45 and 46: Based on power sensitivity and tool
- Page 47 and 48: with SPICE. Power Mill is dynamic s
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- Page 51 and 52: 3.4.3 Interconnect setupAll the cir
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- Page 57 and 58: Design Name CLK Power Total Power %
- Page 59 and 60: DesignNamePowerCompilerProposedAppr
- Page 61 and 62: We can approximate the average powe
- Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
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- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
- Page 75 and 76: Characterized data was transformed
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- Page 112 and 113: 62. H. Mehta, R.M.Owens, M.J.Irwin,
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In this work, we have ma<strong>in</strong>ta<strong>in</strong>ed temporal relation ship between <strong>Power</strong> and Ground currentwaveforms and decoupled the simulations i.e. they are simulated separately and IR drop resultsare merged.We performed simulations and arrived at follow<strong>in</strong>g conclusions.• The shape of the current waveform rema<strong>in</strong>s the same if the patterns used are sameacross different frequencies. Note here that the overall simulation time decreases whenfrequency <strong>in</strong>creases for a same set of patterns. This is not a surprise as the load be<strong>in</strong>gcharged and discharged is same dur<strong>in</strong>g each transition for the same slew and for thesame set of patterns. In case of CMOS gate, shape of current waveform rema<strong>in</strong>s samefor very high frequencies (period ~= 3 times of 0-100% slew). (Appendix C)• The slew or transition time (used <strong>in</strong>terchangeably) plays a big role for peak powerdeterm<strong>in</strong>ation of cells. When the slew decreases, the width of the current spikedecreases with <strong>in</strong>crease <strong>in</strong> peak. Figure 4.4 and Figure 4.5 shows the peak powervariation for different <strong>in</strong>put transition times. Note the variation of ~2x for <strong>in</strong>verter and~1.5x for 2 <strong>in</strong>put NAND gate.67
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