Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
Output isrising. There isnotablesymmetry forrise/fall. Thishelps us tocharacterizeonly onecurrent and dothe analysis atPower/Groundnetwork.Output isrising. Thisalignment ispreserved forbetter resultsduring currentwaveformgeneration.Same is truefor Outputfalling.Figure 4.3 Inverter waveforms measured at different nodes66
In this work, we have maintained temporal relation ship between Power and Ground currentwaveforms and decoupled the simulations i.e. they are simulated separately and IR drop resultsare merged.We performed simulations and arrived at following conclusions.• The shape of the current waveform remains the same if the patterns used are sameacross different frequencies. Note here that the overall simulation time decreases whenfrequency increases for a same set of patterns. This is not a surprise as the load beingcharged and discharged is same during each transition for the same slew and for thesame set of patterns. In case of CMOS gate, shape of current waveform remains samefor very high frequencies (period ~= 3 times of 0-100% slew). (Appendix C)• The slew or transition time (used interchangeably) plays a big role for peak powerdetermination of cells. When the slew decreases, the width of the current spikedecreases with increase in peak. Figure 4.4 and Figure 4.5 shows the peak powervariation for different input transition times. Note the variation of ~2x for inverter and~1.5x for 2 input NAND gate.67
- Page 15 and 16: Further, Figure 1.3 shows that ther
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Output isris<strong>in</strong>g. There isnotablesymmetry forrise/fall. Thishelps us tocharacterizeonly onecurrent and dothe analysis at<strong>Power</strong>/Groundnetwork.Output isris<strong>in</strong>g. Thisalignment ispreserved forbetter resultsdur<strong>in</strong>g currentwaveformgeneration.Same is truefor Outputfall<strong>in</strong>g.Figure 4.3 Inverter waveforms measured at different nodes66