Power Grid Analysis in VLSI Designs - SERC

Most popular technique to control this IR drop is to insert decoupling capacitors in the design.Figure 4.2 shows electrical representation of inductance and dynamic switching of cell thatcauses Power supply noise and decoupling capacitors that helps in meeting this instantaneousneed.V ddV ssL pdV dd PinC pdRpdI ddR ndL V ss Pinps R ps C psI ssV dd NetC ndV ss NetCellC decapR nsC nsFigure 4.2 Schematic circuit for instantaneous voltage drop analysisThis work focuses on computing instantaneous IR drop (deltaV) or actual voltage (Vdd-deltaV)at Cell’s Power/Ground ports. Vdd is ideal voltage source here and constant over time. Herealso our approach is focused on cell based designs. Next section explains the cellcharacterization and modeling needed for block level analysis. Using this characterization, webuild a power grid network that can be simulated. This is discussed in section 5.3. Section 5.4explains the prototype flow we developed and chapter ends with validation results andconclusion.4.2 Cell CharacterizationDefinition: Cell characterization is a process through which data is prepared forevery cell for usage in the design.Process involves SPICEcharacterization as well as post processing of data. The process needs64