Power Grid Analysis in VLSI Designs - SERC

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DesignNamePowerCompilerProposedApproachPrimePowerPowerMill%newpower/powercompiler%powercompiler/PowerMill%newapproach/PowerMill%primepower/PowerMills13207 2572 1718 1436 1418.89 -33.2 81.27 21.08 1.21s15850 2640.3 1971.3 1400 1361.52 -25.34 93.92 44.79 2.83s15850_1 3272.6 2630.3 1539 1945.25 -19.63 68.24 35.22 -20.88s38417 7654.6 4659.3 4352 4688.74 -39.13 63.26 -0.63 -7.18s35932 17606 9654 6789 8513.75 -45.17 106.79 13.39 -20.26s38584_1 12031.7 8339.6 5630 6738.36 -30.69 78.56 23.76 -16.45s38584 10951.4 8057.2 4261 6235.13 -26.43 75.64 29.22 -31.66Table 3.5 Power Estimation across various tools3.6 Power estimation applicationsOnce the power estimation has been done, the data can be used in a post-processing step toinvestigate various circuit properties. Note that some of them are applications of average togglecalculation method we described above.3.6.1 Average power/ground bus currentsConsider the problem of computing the average current in the power or ground bus branches.This can be solved using toggle densities and average power consumption for each library cell.60
We can approximate the average power for each cell based on toggle densities and approximatepower or ground network as distributed or lumped R and C. SPICE simulating this powernetwork, one can estimate average power/ground bus currents. [31]3.6.2 Average power dissipationAs a direct consequence of the power estimation described above, it should be clear that theanalysis gives overall average power dissipation, summing over all circuit nodes.3.6.3 Electro migration failuresElectro migration [93][94] is a major reliability problem caused by the transport of atoms in ametal line due to electron flow. Under persistent current stress, this can cause deformations ofthe metal, leading to either short or open circuits. The electro migration failure depends onaverage and root mean square – RMS current densities in metal leads. The average current ineach metal lead can be estimated by the method described in this chapter and thus potentialelectro migration current can be addressed either in power network or signal lead.3.6.4 Power RoutingIt has been noticed that inaccurate power estimation normally is the root cause of ‘over design’of power network. By estimating accurate power number, it is possible to have dense powergrid on a block and light power grid on some other block and thus reducing the overall IR dropproblem also.61
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Power Grid Analysis in VLSI Designs
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4.4.1 Timing Information Generation
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Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59: DesignNamePowerCompilerProposedAppr
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
Page 94 and 95: power network start getting charged
Page 96 and 97: Note that the 1 stcharacterization
Page 98 and 99: • Maximum current surge that will
Page 100 and 101: gates in the virtual network or mor
Page 102 and 103: Vdesired (mV)Actual#SwitchesSwitche
Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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114
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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