Power Grid Analysis in VLSI Designs - SERC

More documents

Recommendations

Info

4.4.1 Timing Information Generation ................................................................................................................ 804.4.2 Power Grid Generator............................................................................................................................. 804.4.3 SPICE Simulation................................................................................................................................... 824.5 Validation and Results....................................................................................................................824.5.1 Peak Power Results ............................................................................................................................... 834.5.2 Peak Dynamic IR Drop Results ............................................................................................................... 844.6 Summary.........................................................................................................................................875 Power Up Analysis........................................................................................................895.1 Switched PG Networks...................................................................................................................915.2 Switch Network Analysis.................................................................................................................945.2.1 Switch Characterization .......................................................................................................................... 955.2.2 Current or Switch Prediction.................................................................................................................... 965.3 Results and Analysis.......................................................................................................................995.4 Summary.......................................................................................................................................1046 Conclusion...................................................................................................................1056.1 Summary.......................................................................................................................................1056.2 Scope of Future Work...................................................................................................................1067 References...................................................................................................................109Appendix A Sample SDC file...............................................................................................115Appendix B Sample SPEF Format......................................................................................116Appendix C Power Waveforms Analysis...........................................................................118Appendix D Current Characterization – sample spice deck ...........................................119Appendix E Waveform transformation example...............................................................1206
Table of FiguresFigure 1.1 Power Dissipation in CMOS designs ......................................................................................13Figure 1.2 Power Density trend in CMOS designs...................................................................................14Figure 1.3 Leakage and Dynamic Power Dissipation [2].........................................................................15Figure 1.4 Schematic of Power Grid in CMOS designs...........................................................................18Figure 1.5 Normalized delay and normalized delay to voltage ratio........................................................21Figure 1.6 Total power break up into leakage and active........................................................................23Figure 2.1 Schematic of logic circuit 1......................................................................................................31Figure 2.2 Schematic of Logic Circuit 2....................................................................................................32Figure 2.3 Gated clock example ...............................................................................................................34Figure 2.4 Gate Level Netlist for 'simple' design......................................................................................36Figure 2.5 Timing Arcs in extracted model of 'simple' design..................................................................37Figure 3.1 Venn diagram of Power Components.....................................................................................40Figure 3.2 Power Estimation in Design Stages........................................................................................45Figure 3.3 Power Estimation Validation Flow...........................................................................................49Figure 3.4 Legends for Validation Flow....................................................................................................49Figure 4.1 Voltage over time representation at an internal design node ................................................63Figure 4.2 Schematic circuit for instantaneous voltage drop analysis ....................................................64Figure 4.3 Inverter waveforms measured at different nodes...................................................................66Figure 4.4 transition time vs. peak power for Inverter..............................................................................68Figure 4.5 Transition time vs. peak power for nand gate.........................................................................68Figure 4.6 Load vs. peak power for AND gate.........................................................................................69Figure 4.7 Load vs. Peak power for OR gate...........................................................................................69Figure 4.8 State Dependency on cell switching .......................................................................................70Figure 4.9 Cell Characterization Flow.......................................................................................................72Figure 4.10 Power Grid Modeling.............................................................................................................73Figure 4.11 Peak IR drop Computation Flow...........................................................................................79Figure 4.12 Prime Time flow for arrival time computation .......................................................................80Figure 4.13 Power Grid Generation Flow.................................................................................................81Figure 4.14 PSN waveform of Proposed Method.....................................................................................86Figure 4.15 PSN Reference Waveform....................................................................................................86Figure 5.1 Gated Power Supply ([74]) ......................................................................................................89Figure 5.2 Layout of 1M gate with switch network...................................................................................92Figure 5.3 Current Glitch and Voltage Ramp at arbitrary switch output..................................................92Figure 5.4 Typical PG network with Power Switches...............................................................................93Figure 5.5 Schematic Switch network Analysis Flow...............................................................................95Figure 5.6 Analysis model of Virtual Power Network...............................................................................96Figure 5.7 Infinitesimal Time Division for Current Prediction...................................................................97Figure 5.8 Reduced Switch Network for validation ................................................................................100Figure 5.9 Voltage Ramp up over Time for various nodes ....................................................................103Figure 5.10 Current comparison over time.............................................................................................103Figure 1 1MHz, Peak: 838.9 uW.............................................................................................................118Figure 2 100MHz, Peak: 840.7 uW.........................................................................................................1187
Page 1: Power Grid Analysis in VLSI Designs
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58:
Design Name CLK Power Total Power %
Page 59 and 60:
DesignNamePowerCompilerProposedAppr
Page 61 and 62:
We can approximate the average powe
Page 63 and 64:
4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66:
to be absolutely in complete alignm
Page 67 and 68:
In this work, we have maintained te
Page 69 and 70:
Figure 4.6 Load vs. peak power for
Page 71 and 72:
3. The temporal correlation between
Page 73 and 74:
Each such armRepresents resistance
Page 75 and 76:
Characterized data was transformed
Page 77 and 78:
Do timing analysis and based on inp
Page 79 and 80:
of any node. Alternatively frequenc
Page 81 and 82:
Cell Char @ fix frequency(10MHz in
Page 83 and 84:
We executed the flow as explained i
Page 85 and 86:
Circuit%Drop inaverage activity%Dro
Page 87:
4.6 SummaryWe proposed novel PG net
Page 90 and 91:
network but causing huge dynamic IR
Page 92 and 93:
Power SwitchFigure 5.2 Layout of 1M
Page 94 and 95:
power network start getting charged
Page 96 and 97:
Note that the 1 stcharacterization
Page 98 and 99:
• Maximum current surge that will
Page 100 and 101:
gates in the virtual network or mor
Page 102 and 103:
Vdesired (mV)Actual#SwitchesSwitche
Page 104 and 105:
5.4 SummaryThere are various techni
Page 106 and 107:
5. Power Up analysis for MTCMOS bas
Page 108 and 109:
108
Page 110 and 111:
21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113:
62. H. Mehta, R.M.Owens, M.J.Irwin,
Page 114 and 115:
114
Page 116 and 117:
Appendix B Sample SPEF Format*SPEF
Page 118 and 119:
Appendix C Power Waveforms Analysis
Page 120 and 121:
Appendix E Waveform transformation
show all

Power Grid Analysis in VLSI Designs - SERC

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?