Power Grid Analysis in VLSI Designs - SERC

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DesignNamePowerCompilerProposedApproachPrimePowerPowerMill%newpower/powercompiler%powercompiler/PowerMill%newapproach/PowerMill%primepower/PowerMills4 3.72 3.35 2.93 2.79 -9.95 33.43 20.16 4.95s5 2.49 1.34 0.47 1.72 -46.12 44.66 -22.05 -72.61s27 12.69 10.91 10.03 9.36 -14.01 35.54 16.55 7.14s208_1 44.91 30.43 22.4 29.03 -32.25 54.7 4.81 -22.84s298 67.33 54.12 40.05 41.42 -19.62 62.57 30.67 -3.31s344 85.24 61.11 56.55 65.7 -28.31 29.74 -6.99 -13.93s349 86.48 61.14 56.66 65.86 -29.3 31.31 -7.16 -13.97s382 83.57 91.73 52.75 53.15 9.76 57.25 72.6 -0.75s386 75.15 32.28 42.78 48.46 -57.05 55.07 -33.4 -11.73s400 83.96 94.51 52.77 53.3 12.58 57.51 77.32 -1s420_1 70.19 53.75 45.6 44.12 -23.43 59.11 21.83 3.37s444 83.79 84.83 52.9 53.64 1.24 56.22 58.15 -1.38s510 64.68 29.43 18.23 47.43 -54.51 36.36 -37.96 -61.57s526n 85.2 85.94 53.54 53.89 0.87 58.1 59.48 -0.65s526 85.41 85.89 53.67 54.08 0.57 57.93 58.83 -0.7558
DesignNamePowerCompilerProposedApproachPrimePowerPowerMill%newpower/powercompiler%powercompiler/PowerMill%newapproach/PowerMill%primepower/PowerMills641 159.77 117.38 72.37 93.34 -26.53 71.17 25.76 -22.46s713 162.62 123.07 74.51 96.57 -24.32 68.41 27.44 -22.84s820 119.02 72.29 47.96 73 -39.27 63.04 -0.98 -34.3s832 119.18 72.5 48.03 73.34 -39.17 62.51 -1.14 -34.51s838_1 126.27 99.96 93.41 75.78 -20.84 66.63 31.91 23.27s953 159.75 102.37 85.98 88.5 -35.92 80.51 15.67 -2.85s1494 187.71 158.7 98.28 136.47 -15.45 37.54 16.29 -27.99s1488 203.99 158.24 98.16 135.83 -22.42 50.18 16.5 -27.73s1423 406.56 356.1 244.9 278.03 -12.41 46.23 28.08 -11.92s1238 302.45 150.51 128.2 151.55 -50.24 99.57 -0.69 -15.41s1196 296.7 151.17 126.5 151.13 -49.05 96.33 0.03 -16.3s5378 1041.2 751.75 584.3 688.62 -27.8 51.2 9.17 -15.15s9234_1 1480.6 891.59 704.7 812.36 -39.78 82.26 9.75 -13.25s9234 1300.4 632.35 508.2 472.82 -51.37 175.03 33.74 7.48s13207_1 2853 1908.3 1533 1677.46 -33.11 70.08 13.76 -8.6159
Page 1:
Power Grid Analysis in VLSI Designs
Page 6 and 7:
4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57: Design Name CLK Power Total Power %
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
Page 94 and 95: power network start getting charged
Page 96 and 97: Note that the 1 stcharacterization
Page 98 and 99: • Maximum current surge that will
Page 100 and 101: gates in the virtual network or mor
Page 102 and 103: Vdesired (mV)Actual#SwitchesSwitche
Page 104 and 105: 5.4 SummaryThere are various techni
Page 106 and 107: 5. Power Up analysis for MTCMOS bas
Page 108 and 109:
108
Page 110 and 111:
21. F.N. Najm, R.Burch, P. Yang, an
Page 112 and 113:
62. H. Mehta, R.M.Owens, M.J.Irwin,
Page 114 and 115:
114
Page 116 and 117:
Appendix B Sample SPEF Format*SPEF
Page 118 and 119:
Appendix C Power Waveforms Analysis
Page 120 and 121:
Appendix E Waveform transformation
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