Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
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DesignNameIN OUT Flops Boolean(gates+<strong>in</strong>v)s713 35 23 19 139+254s820 18 19 5 256+33s832 18 19 5 262+25s838_1 34 1 32 288+158s9234 19 22 228 2027+3570s9234_1 36 39 211 2027+3570s953 16 23 29 311+84Table 3.2 ISCAS89 circuit descriptionDesign TFC + <strong>Power</strong> Compiler Runtimes (<strong>in</strong> mts) <strong>Power</strong>Mill runtime (CPUHr)S13207 3 23S13207_1 3 24S15850 3 25S15850_1 3 26S35932 6 25054