Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
DesignNameIN OUT Flops Boolean(gates+<strong>in</strong>v)s111 8 1 0 8s1196 14 14 18 388+141s1238 14 14 18 428+80s13207 31 121 669 2573+5378s13207_1 62 152 638 2573+5378s1423 17 5 74 490+167s1488 8 19 6 550+103s1494 8 19 6 558+89s15850 14 87 597 3448+6324s15850_1 77 150 534 3448+6324s208_1 10 1 8 66+38s27 4 1 3 8+2s298 3 6 14 75+44s344 9 11 15 101+59s349 9 11 15 104+5752