Power Grid Analysis in VLSI Designs - SERC

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3.4.1 Netlist Setup:Standard industry benchmark circuits – ISCAS89 are used for the validation. The circuits’complexity ranges from 14 gates to 22000 gates. The detail statistics of the circuit is mentionedin Table 2. [71]To make the validation complete, two single cell circuits are added for ‘micro’ level validation.ISCAS89 benchmark circuits were mapped to 130nm technology for analysis. Note that there isno optimization or synthesis being used while mapping the circuits to 130nm technologyhowever predetermined set of cells was used. They are,• 2,3,4 inputs AND/NAND gates• 2,3,4 inputs OR and NOR gates• Buffers and inverters• 2,3 inputs ex-or and ex-nor gates• Flops3.4.2 Vector GenerationRandom vectors were generated for all the ISCAS89 circuits. The numbers of vectors werebased on circuit complexity and number of gates. They vary from 4 vectors to 38000 vectorsapproximately. The same set of vectors is used for logic simulation and SPICE simulation aswell as derivation of switching activity and static probabilities for Input Pins.50
3.4.3 Interconnect setupAll the circuits can be estimated as synthesized Verilog netlist and hence the parasiticinformation was not available. To make comparison more realistic, no load modes were used inpower compiler and in SPICE simulation. The logic simulation was based on SDF generatedfrom Synopsys.3.5 Validation and ResultsThe complete data from different tools are shown in Table 3.5. Table 3.2 describes circuits usedfor benchmarking. Table 3.3 compares run time between dynamic method and modified togglecomputation method for some of the big design blocks. Table 3.4 shows power estimation forclock network vs. total power estimation. All the power data is dynamic power in uW.• The power numbers mainly reflect the cell internal power and switching power only dueto gate input capacitances as no interconnects were assumed.• All the experiments are done at nominal operating point i.e. normal process, 25 Ctemperatures and 1.2 voltage (nominal voltage).• Clock network power is 50% of total dynamic power but this is not true in all cases.• Run time reduction from static approach is more than 1000 times.• Prime Power reported power is optimistic in many cases to PowerMill. This is not inour expectation and we are looking into it.• TFC is within 30% of PowerMill reported power. However there are certain exceptionswhere it reports 30% optimistic power or >50% pessimistic power.• Power Compiler is >50% pessimistic in most of the cases.51
Page 1: Power Grid Analysis in VLSI Designs
Page 6 and 7: 4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
Page 94 and 95: power network start getting charged
Page 96 and 97: Note that the 1 stcharacterization
Page 98 and 99: • Maximum current surge that will
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gates in the virtual network or mor
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Vdesired (mV)Actual#SwitchesSwitche
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5.4 SummaryThere are various techni
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5. Power Up analysis for MTCMOS bas
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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