Power Grid Analysis in VLSI Designs - SERC

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1. Temperature dependency of power. Power consumption in CMOS depends on mobilityfactors, threshold voltage and doping concentrations. These factors are temperaturedependent. Hence power also varies according to variation in temperature.2. Voltage dependency of power. Voltage dependency of power is well known.(P=C*V*V*f). This is true for CMOS technology also. If we model, the CMOScomponent as a capacitor, it is clear that power varies based on the variation on supplyvoltage.3. Power increases with increase in frequency of operation. In fact, many designs now aday have different modes of operation. A high frequency mode when the device isoperational and a low frequency mode when the device is in standby mode. The impactof frequency on power estimation is already being discussed in previous section.4. Now a day, most of the designs have a significant chunk of flops or registers. Accordingto one statistics, around 40-50% logic of the design contains flops. If all the flops areclocked throughout the operation, clock network consumes almost 50% of total power.It is sometimes helpful to analyze power consumption on clock network. This workanalyzes clock power contribution to total power.5. Process corner also impacts the currents and power consumption. This is especially truefor leakage power. A typical VLSI process has leakage power variation of order of 4-6from worst process to best process.44
Based on power sensitivity and tool study analysis in this section, we propose a powerestimation flow in typical design cycle as shown in Figure 3.2 below. Note that the poweranalysis varies from RTL design to pre layout netlist to post layout netlist.Power Estimation(spreadsheet)ArchitectureForward SAIF*Or FrequencyConstraintsRTLToggle FrequencyCalculatorUnplaced NetlistPlaced NetlistDetailed Route OverLogic SimulationPIF FileGenerationPower Estimationin PowerCompiler (wireload, global SPEF,Detailed SPEF)RC RC SPICE NetlistNanoSimPrimePowerRecommendedLeast Preferred* SAIF - Switching Activity File based approachFigure 3.2 Power Estimation in Design Stages3.3 Power analysis Tools3.3.1 Power Compiler: [67]Formerly known as Design Power, power compiler is currently most widely used Synopsys tool.Power compiler, typically being used during synthesis, does power optimization as well aspower estimation. This tool has static algorithms for calculating switching activity at various45
Page 1: Power Grid Analysis in VLSI Designs
Page 6 and 7: 4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43: on the required accuracy, different
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
Page 92 and 93: Power SwitchFigure 5.2 Layout of 1M
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power network start getting charged
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Note that the 1 stcharacterization
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• Maximum current surge that will
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gates in the virtual network or mor
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Vdesired (mV)Actual#SwitchesSwitche
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5.4 SummaryThere are various techni
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5. Power Up analysis for MTCMOS bas
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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