Power Grid Analysis in VLSI Designs - SERC

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3.2 Current approaches to Power AnalysisCell based power estimation consists of cell characterization and logic simulation or activityestimation. The characterization phase entails a set of electrical simulations of each library cellfor all possible input transitions and for a wide range of fanin and fanout conditions. Timingand power information obtained in this way is used to construct lookup tables for the basiclibrary elements [46][69].Summing the leakage power of the design’s constituent library cells derives the total leakagepower of a circuit:P leakageTotal = ∑∀ Cell (i)PCellLeaka ge(i) (3)Where P cellLeakage(I) is the leakage power dissipation of each cell. Technology library developersannotate the library cells with the approximate total leakage power dissipated by each cell.There is usually a single static power number per library cell but sometimes leakage power candepend on the logical condition of the cell. In this case, the library cell is annotated with a statedependent static power.A cell’s internal power is the sum of the internal power of all of the cell’s inputs and outputs asmodeled in the technology library:∑P = Ei * A(i) * f ( i)(4)Internal∀Pin(i)Where Ei is the internal energy of each pin. In practice, the internal energy if a pin ischaracterized in the technology library and can be accessed by simple table look-up. Depending42
on the required accuracy, different look-up tables can be provided by the library designers asexplained in Table 3.1.Lookup TablePinDirectionIndicesInput/OutputInput Transition OR Output load capacitanceOutputInput transition and output load capacitanceOnedimensionalTwodimensionalThreedimensionalOutputInput transition and output load capacitance of the two outputsthat have equal or opposite logic valuesTable 3.1 Power Modeling for CMOS gatesThe switching power is calculated in the following way:∑Pswitching = ( VDD^2) * ( Cload(i)* A(i) * f ( i))(5)∀CellWhere Cload(i) is the capacitive load of net i. Without any physical information, the loadcapacitance Cload(i) is calculated using the wire load model of the net and the fanout of thedriving pin. Usually, this approach achieves relative accuracy.Apart from the approaches mentioned above, the following factors are also important foraccurate power estimation.43
Page 1: Power Grid Analysis in VLSI Designs
Page 6 and 7: 4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29 and 30: For large T, D(x) becomes time inva
Page 31 and 32: done hierarchically or there is reu
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41: In this work, above power component
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
Page 81 and 82: Cell Char @ fix frequency(10MHz in
Page 83 and 84: We executed the flow as explained i
Page 85 and 86: Circuit%Drop inaverage activity%Dro
Page 87: 4.6 SummaryWe proposed novel PG net
Page 90 and 91: network but causing huge dynamic IR
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Power SwitchFigure 5.2 Layout of 1M
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power network start getting charged
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Note that the 1 stcharacterization
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• Maximum current surge that will
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gates in the virtual network or mor
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Vdesired (mV)Actual#SwitchesSwitche
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5.4 SummaryThere are various techni
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5. Power Up analysis for MTCMOS bas
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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