Power Grid Analysis in VLSI Designs - SERC

3 Power Estimation3.1 OverviewAccurate Power Estimates are necessary at various stages of the design in order to make correctarchitectural, implementation and cost tradeoffs.[61] Architectural level tradeoffs are higherlevel and involves software or instruction level power modeling or high level activity numbersfor different blocks to do implementation tradeoffs. Many times weighted averages are used toidentify best cost options [62-65]. Once the design gets converted to structural net list andPhysical Design starts, Power Estimation mainly drives package design, PG network designand lower level power minimization. In this case, power dissipation is described as below.P = (A*C*V^2*f) + (τ*A*V*Ishort) + (V*Ileak)WhereA = activity factorthis specifies the amount of switching at various internalnodes of design. Note that ‘f’ is clock frequency which is readily available formost designs. Activity factor specifies about how much a node toggles per ‘f’transitions of clock. The activity factor can be derived from simulation patternsof the logic.C = capacitanceInterconnect load capacitance or wire capacitanceV = dynamic voltagevoltage at which the logic operatesf = frequencyclock frequency at which the logic operates39