Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
2.5 SummaryIn this work, we address real issues being faced by large designs. Automatic toggle generationeases usability as well as improves accuracy. Hierarchical analysis helps in hierarchical designwhich is common methodology to handle design complexity.38
3 Power Estimation3.1 OverviewAccurate Power Estimates are necessary at various stages of the design in order to make correctarchitectural, implementation and cost tradeoffs.[61] Architectural level tradeoffs are higherlevel and involves software or instruction level power modeling or high level activity numbersfor different blocks to do implementation tradeoffs. Many times weighted averages are used toidentify best cost options [62-65]. Once the design gets converted to structural net list andPhysical Design starts, Power Estimation mainly drives package design, PG network designand lower level power minimization. In this case, power dissipation is described as below.P = (A*C*V^2*f) + (τ*A*V*Ishort) + (V*Ileak)WhereA = activity factorthis specifies the amount of switching at various internalnodes of design. Note that ‘f’ is clock frequency which is readily available formost designs. Activity factor specifies about how much a node toggles per ‘f’transitions of clock. The activity factor can be derived from simulation patternsof the logic.C = capacitanceInterconnect load capacitance or wire capacitanceV = dynamic voltagevoltage at which the logic operatesf = frequencyclock frequency at which the logic operates39
- Page 1: Power Grid Analysis in VLSI Designs
- Page 6 and 7: 4.4.1 Timing Information Generation
- Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
- Page 11 and 12: AbstractPower has become an importa
- Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
- Page 15 and 16: Further, Figure 1.3 shows that ther
- Page 17 and 18: proposed in a few papers. In this t
- Page 19 and 20: • Degradation in switching speeds
- Page 21 and 22: Second, today’s design has huge P
- Page 23 and 24: Figure 1.6 Total power break up int
- Page 25 and 26: CMOSDieAcronym for Complimentary Me
- Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
- Page 29 and 30: For large T, D(x) becomes time inva
- Page 31 and 32: done hierarchically or there is reu
- Page 33 and 34: A Sample SDC file with above comman
- Page 35 and 36: Some of the care needs to be taken
- Page 37: Figure 2.5 Timing Arcs in extracted
- Page 41 and 42: In this work, above power component
- Page 43 and 44: on the required accuracy, different
- Page 45 and 46: Based on power sensitivity and tool
- Page 47 and 48: with SPICE. Power Mill is dynamic s
- Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
- Page 51 and 52: 3.4.3 Interconnect setupAll the cir
- Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
- Page 55 and 56: Design TFC + Power Compiler Runtime
- Page 57 and 58: Design Name CLK Power Total Power %
- Page 59 and 60: DesignNamePowerCompilerProposedAppr
- Page 61 and 62: We can approximate the average powe
- Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
- Page 65 and 66: to be absolutely in complete alignm
- Page 67 and 68: In this work, we have maintained te
- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
- Page 75 and 76: Characterized data was transformed
- Page 77 and 78: Do timing analysis and based on inp
- Page 79 and 80: of any node. Alternatively frequenc
- Page 81 and 82: Cell Char @ fix frequency(10MHz in
- Page 83 and 84: We executed the flow as explained i
- Page 85 and 86: Circuit%Drop inaverage activity%Dro
- Page 87: 4.6 SummaryWe proposed novel PG net
2.5 SummaryIn this work, we address real issues be<strong>in</strong>g faced by large designs. Automatic toggle generationeases usability as well as improves accuracy. Hierarchical analysis helps <strong>in</strong> hierarchical designwhich is common methodology to handle design complexity.38
Change language