Power Grid Analysis in VLSI Designs - SERC

Figure 2.5 Timing Arcs in extracted model of 'simple' designThere are combinational archs from i3 to out2 and i1 to out2. Hence, output toggle rate at out2will be controlled by the same clock as i3 or i1. In this case, we assign maximum of i3 or i1toggle rate at output pin. The other timing arch is clk2->out1. In this case, out1 will be assignedaverage switching activity of clk2.Thus using timing model information, we generate output toggle rates of memories, complexhard macros or blocks.2.4 Validation and ResultsAbove changes were incorporated into executable code and applied to ISCAS89 circuits. Theresults were compared through power estimation as discussed in next chapter.37