Power Grid Analysis in VLSI Designs - SERC
Power Grid Analysis in VLSI Designs - SERC Power Grid Analysis in VLSI Designs - SERC
4 Complex loop handlingThese were handled by breaking the loops. We broke the loop at the 1 st point where wefound the loop forming.5 Unconnected inputs going into logicThis was handled by reverse tracking the first sequential cell encountered in thetransitive fan out of unconnected inputs. This algorithm gives the clock controlling thetoggle rate down the line.If the unconnected inputs are clocks, we assigned the worst toggle rate of the blockitself.6 Gated clocks or generated clocksGated clock is a clock signal that can be modified by logic within the design, such as aclock that can be turned off to save power. Schematic of gated clock is shown in Figure2.3.Figure 2.3 Gated clock exampleWe made the gated elements transparent for toggle propagation. A clock gating cell ishandled like a buffer.7 Design Constraints – Guidelines to do realistic usable toggle activity estimation34
Some of the care needs to be taken despite of all the above solutions. For example,toggle estimation must be done based on the targeted application. This drives certaininputs used in 1-6 above. In the implementation, we kept certain hooks to give controlto the user.2.3.2 Hierarchical Modeling1. Huge portion of the design is occupied by memories however memory output switchingactivity calculation is not straight forward2. Complex functionalities: Hard macros3. Multi-million gates cannot afford to have flat analysis due to cycle time and inherentlimitations of probabilistic approaches. We needed to devise a method to do hierarchicalanalysis by modeling sub-blocks and using them as a black box.We used the timing modeling approach to handle (1), (2), (3).All standard library components are presently modeled in liberty file. [69] Static timinganalysis tools can generate similar liberty file for blocks after completing the analysis. [25]This file has following information,• Input pin 2 output pin timing arch• Setup and Hold constraints for the data input and clock input• Output timing with respect to either input pin or related clockWe derive output toggle frequency f(out) as below.35
- Page 1: Power Grid Analysis in VLSI Designs
- Page 6 and 7: 4.4.1 Timing Information Generation
- Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
- Page 11 and 12: AbstractPower has become an importa
- Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
- Page 15 and 16: Further, Figure 1.3 shows that ther
- Page 17 and 18: proposed in a few papers. In this t
- Page 19 and 20: • Degradation in switching speeds
- Page 21 and 22: Second, today’s design has huge P
- Page 23 and 24: Figure 1.6 Total power break up int
- Page 25 and 26: CMOSDieAcronym for Complimentary Me
- Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
- Page 29 and 30: For large T, D(x) becomes time inva
- Page 31 and 32: done hierarchically or there is reu
- Page 33: A Sample SDC file with above comman
- Page 37 and 38: Figure 2.5 Timing Arcs in extracted
- Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
- Page 41 and 42: In this work, above power component
- Page 43 and 44: on the required accuracy, different
- Page 45 and 46: Based on power sensitivity and tool
- Page 47 and 48: with SPICE. Power Mill is dynamic s
- Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
- Page 51 and 52: 3.4.3 Interconnect setupAll the cir
- Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
- Page 55 and 56: Design TFC + Power Compiler Runtime
- Page 57 and 58: Design Name CLK Power Total Power %
- Page 59 and 60: DesignNamePowerCompilerProposedAppr
- Page 61 and 62: We can approximate the average powe
- Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
- Page 65 and 66: to be absolutely in complete alignm
- Page 67 and 68: In this work, we have maintained te
- Page 69 and 70: Figure 4.6 Load vs. peak power for
- Page 71 and 72: 3. The temporal correlation between
- Page 73 and 74: Each such armRepresents resistance
- Page 75 and 76: Characterized data was transformed
- Page 77 and 78: Do timing analysis and based on inp
- Page 79 and 80: of any node. Alternatively frequenc
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4 Complex loop handl<strong>in</strong>gThese were handled by break<strong>in</strong>g the loops. We broke the loop at the 1 st po<strong>in</strong>t where wefound the loop form<strong>in</strong>g.5 Unconnected <strong>in</strong>puts go<strong>in</strong>g <strong>in</strong>to logicThis was handled by reverse track<strong>in</strong>g the first sequential cell encountered <strong>in</strong> thetransitive fan out of unconnected <strong>in</strong>puts. This algorithm gives the clock controll<strong>in</strong>g thetoggle rate down the l<strong>in</strong>e.If the unconnected <strong>in</strong>puts are clocks, we assigned the worst toggle rate of the blockitself.6 Gated clocks or generated clocksGated clock is a clock signal that can be modified by logic with<strong>in</strong> the design, such as aclock that can be turned off to save power. Schematic of gated clock is shown <strong>in</strong> Figure2.3.Figure 2.3 Gated clock exampleWe made the gated elements transparent for toggle propagation. A clock gat<strong>in</strong>g cell ishandled like a buffer.7 Design Constra<strong>in</strong>ts – Guidel<strong>in</strong>es to do realistic usable toggle activity estimation34
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