Power Grid Analysis in VLSI Designs - SERC

A Sample SDC file with above command is shown in Appendix A. Note that SDC fileis collection of commands in tcl format so we have shown the commands which areprimarily required.2 Sequential element modeling (e.g. flip-flops, latches)Sequential elements do not directly switch arbitrarily when the input switches. Hence,we can not apply the formula as mentioned in equation (1,2).We used following formula to compute toggle frequency at the output of sequentialcells. Note that we are referring latches and basic flip-flops as part of sequential cellsand not the complex macros. They are dealt separately.Qout = min(DataInput, clock/2)The upper bounding of clock/2 is required since we identified certain cases where DataInput toggles more than clock/2. This is explained below. For the cases, where datainput is not toggling more than clock/2, output can not toggle more than Data Input.Above equation takes care of these facts.3 Some Boolean gates were not taking care realistic scenarios: exor/exnor gates, muxEquation (1,2) can compute higher toggle rate than clock toggle rate. This can go evenhigher than clock toggle rate if there are more such gates in transitive fan out. We foundthat this is not the case on actual designs and in many cases, this was not intendedbehavior. We exceptionally identified such cells and clipped their toggle rate to half ofthe clock toggle rate.In similar fashion, we exceptionally identified mux cells and assigned the output togglerate to maximum toggle rate of all inputs.33