Power Grid Analysis in VLSI Designs - SERC

Figure 2.2 Schematic of Logic Circuit 2In case of above, Input Clk or D going to block can be primary inputs. Unless user givestoggle rate, it is highly difficult to compute the same. We used static timing analysis[24][25] specifications to derive these inputs. They are,Input Delay Specification – A constraint that specifies the minimum or maximumamount of delay from a clock edge to the arrival of a signal at aspecified input port. Input delay specification is with respect to a clockthat triggers events on that signal.Clock specification – specifies the characteristics of a clock, including the clockname, source period and waveform.Mode Specifications – specifies the constant values applied on certain port or pinsto drive timing analysis in a specific mode. This means that these pinsor ports are not toggling during the analysis. It also specifies theconstant value to which the port or pin is tied to.For clock inputs, we used the toggle rate specified as per the clock specification.For non-clock inputs, we used the clock specified on the Input Delay specification.For constant ports, we used 0 toggle rate and static probability based on constant valuetied i.e. if it is constant 0, static probability is 0 else it is 1.32