Power Grid Analysis in VLSI Designs - SERC

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dydx=y⊕yx = 1 x = 0(1)It was shown in [5] that, if the inputs x I to boolean logic are (spatially) independent, then thedensity of its output y is given by:ndyD( y)= ∑ P() D(xi)(2)dxii=1In (2), it is assumed that all inputs are independent. This can lead to inaccuracy where primaryinputs will be diverging and than reconverging to primary outputs – they are not really spatiallyindependent. However, at a block, the primary inputs can be considered pretty muchindependent and hence the above approach can be modeled more accurately if the wholeblock’s boolean difference is computed.Given the signal probability and toggle density values at the primary inputs of a logic circuit, asingle pass over the circuit, using (2), gives the density at every node. Note that apart fromestimating toggle densities at the output node, we also need to calculate output signalprobabilities to do toggle density estimation of subsequent circuit logic. This is simple for twoinput AND gate.P(Y) = P(A)*P(B)orP(Y) = 1 – P(A)P(B) for NAND gate.2.3 Multi-million gate solutionWhen we apply the above approach, it gives good results for designs which are small and canbe analyzed flat and dominated by combinational logic. Beside, it is always not possible to runflat due to other logistic concerns like blocks are designed first or rest of the design is being30
done hierarchically or there is reusable IPs in design which do not have net list. The approachdescribed in previous section was extended to handle such requirements.We also came across several issues while applying this approach to some large designs [>5Mgates] and implementing tool – Toggle Frequency Calculator. In this section, we will discusssolutions those addresses each of the problem in detail.2.3.1 Deriving automatic toggle frequency values1 Primary Input HandlingThe toggle rate at Primary Input is not known. Since they are driven externally, there isno easy way to predict toggle rate for the same. The same is true for primary inputsignal probability. Consider the following Figure 2.1 and Figure 2.2.Figure 2.1 Schematic of logic circuit 131
Page 1: Power Grid Analysis in VLSI Designs
Page 6 and 7: 4.4.1 Timing Information Generation
Page 8 and 9: Figure 3 1GHz, Peak: 838.2 uW......
Page 11 and 12: AbstractPower has become an importa
Page 13 and 14: 1 Introduction1.1 MotivationVLSI in
Page 15 and 16: Further, Figure 1.3 shows that ther
Page 17 and 18: proposed in a few papers. In this t
Page 19 and 20: • Degradation in switching speeds
Page 21 and 22: Second, today’s design has huge P
Page 23 and 24: Figure 1.6 Total power break up int
Page 25 and 26: CMOSDieAcronym for Complimentary Me
Page 27 and 28: 2 Toggle Activity Estimation2.1 Ove
Page 29: For large T, D(x) becomes time inva
Page 33 and 34: A Sample SDC file with above comman
Page 35 and 36: Some of the care needs to be taken
Page 37 and 38: Figure 2.5 Timing Arcs in extracted
Page 39 and 40: 3 Power Estimation3.1 OverviewAccur
Page 41 and 42: In this work, above power component
Page 43 and 44: on the required accuracy, different
Page 45 and 46: Based on power sensitivity and tool
Page 47 and 48: with SPICE. Power Mill is dynamic s
Page 49 and 50: DREPGENDREPFILE+ DATAGENFUNCTDLRAND
Page 51 and 52: 3.4.3 Interconnect setupAll the cir
Page 53 and 54: DesignNameIN OUT Flops Boolean(gate
Page 55 and 56: Design TFC + Power Compiler Runtime
Page 57 and 58: Design Name CLK Power Total Power %
Page 59 and 60: DesignNamePowerCompilerProposedAppr
Page 61 and 62: We can approximate the average powe
Page 63 and 64: 4 Power Supply Noise Analysis4.1 Ov
Page 65 and 66: to be absolutely in complete alignm
Page 67 and 68: In this work, we have maintained te
Page 69 and 70: Figure 4.6 Load vs. peak power for
Page 71 and 72: 3. The temporal correlation between
Page 73 and 74: Each such armRepresents resistance
Page 75 and 76: Characterized data was transformed
Page 77 and 78: Do timing analysis and based on inp
Page 79 and 80: of any node. Alternatively frequenc
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Cell Char @ fix frequency(10MHz in
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We executed the flow as explained i
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Circuit%Drop inaverage activity%Dro
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4.6 SummaryWe proposed novel PG net
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network but causing huge dynamic IR
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Power SwitchFigure 5.2 Layout of 1M
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power network start getting charged
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Note that the 1 stcharacterization
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• Maximum current surge that will
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gates in the virtual network or mor
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Vdesired (mV)Actual#SwitchesSwitche
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5.4 SummaryThere are various techni
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5. Power Up analysis for MTCMOS bas
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108
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21. F.N. Najm, R.Burch, P. Yang, an
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62. H. Mehta, R.M.Owens, M.J.Irwin,
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Appendix B Sample SPEF Format*SPEF
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Appendix C Power Waveforms Analysis
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Appendix E Waveform transformation
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Power Grid Analysis in VLSI Designs - SERC

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